A method for simulating gate tunneling current under total dose

Abstract

The present invention discloses a gate tunneling current simulation method under the action of total dose, comprising the following steps: step 10, performing three-dimensional device structure modeling on a SOI NMOS device; step 20, modifying a gate dielectric material parameter file of the SOI NMOS three-dimensional device structure model to activate a Radiation model and set an irradiation bias state of the model; step 30, setting an irradiation dose rate and a plurality of different irradiation times, performing irradiation total dose simulation on the SOI NMOS three-dimensional device structure model, and extracting a threshold voltage V corresponding to different irradiation doses. th ; Step 40, the threshold voltage V th The gate tunneling current characteristics under the total dose effect are obtained by inputting the empirical formula of the gate tunneling current for simulation. The present invention obtains the device threshold voltage by changing with time under different bias states and different irradiation doses, and then substitutes the changed threshold voltage into the empirical formula of the gate tunneling current for simulation, so as to accurately obtain the gate tunneling current under different total irradiation doses.

Description

Technical Field

[0001] The invention belongs to the technical field of power semiconductor devices, and in particular relates to a gate tunneling current simulation method under the action of total dose. Background Art

[0002] With the rapid development of semiconductor integrated circuit technology, in order to meet the requirements of integrated circuits for higher integration, faster transmission speed, lower cost and lower power consumption, the characteristic size of devices is constantly decreasing. Semiconductor technology with complementary CMOS as the core has now entered the nanometer scale, where the thickness of the gate oxide layer is several nanometers, resulting in an increase in the probability of carriers in the channel inversion layer tunneling through the gate oxide layer. The increase in gate tunneling current has caused a series of problems: reduced reliability, increased static power consumption, etc. Therefore, more and more attention has been paid to the research on gate tunneling current.

[0003] Silicon-on-insulator (SOI) technology has been a hot topic in the field of integrated circuits since the end of the last century. With the rapid development and in-depth research of SOI process technology, SOI technology has gradually matured. Due to its dielectric isolation layer structure, SOI technology completely isolates the active area and substrate of MOS devices. Compared with conventional bulk silicon devices, SOI devices effectively eliminate latch-up effects, reduce parasitic capacitance, and improve signal transmission speed. Due to the wide application of SOI devices in space and military fields, they are easily affected by high-energy particles in space, such as x-rays and gamma rays. Due to the existence of the dielectric isolation layer, the radiation degradation of SOI devices with the same process is more complicated than that of bulk silicon devices, and the total dose radiation resistance of SOI devices is worse than that of bulk silicon devices. As the characteristic size of SOI devices enters the deep submicron level, the gradually thinning gate oxide thickness makes its sensitivity to the total dose effect decrease. However, when the gate dielectric is reduced to below 2nm, the gate tunneling current increases exponentially with the reduction of the gate dielectric thickness. The gate tunneling current is an important parameter indicator of device degradation under total dose radiation conditions.

[0004] At present, the gate current of SOI devices under total dose conditions is mostly tested based on experiments. The irradiation experimental test is a considerable waste of manpower, material and financial resources. Gate current simulation is mostly done through numerical modeling and does not involve the total dose effect of irradiation. The existing TCAD total dose effect simulation is to add fixed positive charges to the gate oxide layer to simulate the accumulation of positive charges in the gate oxide layer under TID irradiation. However, this method cannot reflect the changes of the device over time under different bias states and different irradiation doses, and cannot accurately derive the electrical characteristics of the device. Summary of the invention

[0005] In order to solve the above problems existing in the prior art, the present invention provides a gate tunneling current simulation method under the action of total dose. The technical problem to be solved by the present invention is achieved by the following technical solutions:

[0006] A gate tunneling current simulation method under total dose, comprising the following steps:

[0007] Step 10, performing three-dimensional device structure modeling on the SOI NMOS device based on TCAD Sentaurus to generate a three-dimensional device structure model of SOINMOS;

[0008] Step 20, modifying the gate dielectric material parameter file of the SOI NMOS three-dimensional device structure model through Sentaurus to add and activate the Radiation model in the Physics part of Sdevice, and setting the radiation bias state of the SOI NMOS three-dimensional device structure model;

[0009] Step 30, setting the irradiation dose rate and a plurality of different irradiation times, performing irradiation total dose simulation on the SOI NMOS three-dimensional device structure model, and extracting the threshold voltage V corresponding to different irradiation doses. th ;

[0010] Step 40, the threshold voltage V th The empirical formula of gate tunneling current is input for simulation and the gate tunneling current characteristics under the total dose effect are obtained.

[0011] In one embodiment of the present invention, the modifying of the gate dielectric material parameter file of the SOI NMOS three-dimensional device structure model by Sentaurus includes: replacing the identifier of the gate dielectric material with the identifier of the oxide semiconductor material by Sentaurus, and replacing the parameter file of the oxide semiconductor material with the parameter file of the gate dielectric material.

[0012] In one embodiment of the present invention, the gate tunneling current empirical formula is:

[0013] Where Ig is the gate tunneling current, W is the device gate width, and L is the device gate length. C(V g ,V ox ,t ox ,φ beff ) is the model correction factor, TWKB is the tunneling probability of electrons passing through the gate dielectric to reach the gate electrode. ε ox is the relative dielectric constant of the gate dielectric, t ox is the gate dielectric thickness, φ b is the initial barrier height between the gate dielectric and silicon, φ b0 is the potential barrier height between Si and SiO2, φbeff is the effective barrier height between the gate dielectric and silicon, V ox is the voltage on the gate dielectric, V ox =V g -V th , V g is the voltage applied to the gate, V th is the device threshold voltage, N is the gate interface carrier concentration, m ox is the effective mass of the electron, E ox is the electric field applied on the gate, h is Planck's constant, q is the charge of the elementary charge, and α is the fitting coefficient.

[0014] In one embodiment of the present invention, the bias state includes: an ON state, an OFF state or a transmission state.

[0015] In one embodiment of the present invention, the threshold voltage V corresponding to different radiation doses is extracted. th Extraction based on Inspect.

[0016] In one embodiment of the present invention, the simulation is performed by Matlab in step 40.

[0017] Beneficial effects of the present invention:

[0018] The present invention obtains the relationship between the device threshold voltage and the radiation dose by changing the device threshold voltage with time under different bias states and different radiation doses, and then substitutes the changed threshold voltage into the empirical formula of the gate tunneling current. The gate tunneling current under the total radiation dose is simulated by Matlab, so that the gate tunneling current under different total radiation doses can be accurately obtained.

[0019] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 It is a schematic diagram of the structure of Sentaurus software used in a gate tunneling current simulation method under the total dose provided by an embodiment of the present invention;

[0021] Figure 2 It is a flow chart of a gate tunneling current simulation method under the total dose provided by an embodiment of the present invention;

[0022] Figure 3a It is a schematic diagram of a three-dimensional SOI NMOS device structure model provided by an embodiment of the present invention;

[0023] Figure 3b is a grid distribution diagram of a SOI NMOS three-dimensional device structure model provided by an embodiment of the present invention;

[0024] Figure 4 A diagram of the threshold voltage simulation result under the total dose effect in the ON state of a SOI NMOS three-dimensional device structure model provided by an embodiment of the present invention;

[0025] Figure 5a The embodiment of the present invention provides a method for analyzing the TWKB tunneling rate of a SOI NMOS three-dimensional device structure model under different total radiation doses in the ON state with respect to the gate voltage V g Change simulation result diagram;

[0026] Figure 5b The embodiment of the present invention provides a simulation result diagram of gate tunneling current variation under different total radiation doses in the ON state of a SOI NMOS three-dimensional device structure model. DETAILED DESCRIPTION

[0027] The present invention is further described in detail below with reference to specific embodiments, but the embodiments of the present invention are not limited thereto.

[0028] Reference Figure 1 , Figure 1 The Sentaurus software used in the simulation of the present invention mainly includes four tools: SDE, Sdevice, Sentaurus Visual and Inspect, wherein SDE is used to construct the device structure, set the doping information and the grid information; Sdevice is used to calculate the grid and solve the semiconductor equation, and includes six parts, namely File-defining the input and output files, Physics-defining the physical model used in the simulation, Plot-saving the variable information after the solution, Math-controlling the numerical calculation during the simulation, Electrode-defining the device structure electrode and setting the bias state and Solve-solving the Poisson equation; Sentaurus Visual is used to view the structure and physical parameters of the device after simulation; Inspect is used to view the electrical characteristics of the device after simulation and extract the device parameters.

[0029] See also Figure 2 , a gate tunneling current simulation method under total dose, comprising the following steps:

[0030] Step 10: Perform three-dimensional device structure modeling on the SOI NMOS device based on TCAD Sentaurus to generate a three-dimensional device structure model of SOINMOS. Figure 3a It is a schematic diagram of the SOI NMOS three-dimensional device structure model. Figure 3b It is a grid distribution diagram of the SOI NMOS three-dimensional device structure model. The structure of the SOI NMOS three-dimensional device structure model is substrate, buried oxide layer and body region from bottom to top. Above the body region are source region, channel and drain region respectively, and above the channel is the gate.

[0031] Step 20, modify the gate dielectric material parameter file of the SOI NMOS three-dimensional device structure model through Sentaurus, add and activate the Radiation model in the Physics part of Sdevice, and set the irradiation bias state of the SOI NMOS three-dimensional device structure model. Specifically, before performing the TID irradiation total dose simulation, it is necessary to modify the gate dielectric material file in the SOI NMOS three-dimensional device structure model in the Sentaurus software. The specific modification process is: replace all gate dielectric material (SiO2) identifiers with oxide semiconductor material identifiers, copy the gate dielectric material (SiO2) parameter file to the oxide semiconductor material parameter file, delete the original new oxide semiconductor material parameter file, and add and activate the Radiation model in the Physics (physical model) part of Sdevice. In the Electrode (electrode) part of Sdevice, the bias states of the gate, drain, source and substrate during the device total dose simulation are set. The device bias states are ON state (open state), OFF state (closed state) and Transport (transmission state). In this embodiment, the ON state is adopted, and the initial state of the device electrode is: V g =V D =V S =V sub =0V, the device electrode bias state during irradiation is set to: V g =1.2V, V D =V S =V sub =0V, after irradiation, the device bias state is set to V D =0.1V, V S =V sub =0V, V g Sweep from 0 to 1.2V. Where V D is the drain voltage, V S is the source voltage, V sub is the substrate voltage.

[0032] Step 30, setting the irradiation dose rate and a plurality of different irradiation times, performing irradiation total dose simulation on the SOI NMOS three-dimensional device structure model, and extracting the threshold voltage V corresponding to different irradiation doses. thSpecifically, the irradiation dose rate and irradiation time can be set arbitrarily. Preferably, the irradiation dose rate is set to 100rad(SiO2) / s, and the irradiation time is set to 500s, 3000s, 5000s and 10000s, respectively, that is, the corresponding irradiation doses are 50krad(SiO2) / s, 300krad(SiO2) / s, 500krad(SiO2) / s and 1000krad(SiO2) / s, respectively. The ID-VG characteristics of the SOI NMOS three-dimensional device structure model are simulated, and the threshold voltage V corresponding to different irradiation doses is extracted by Inspect in Sentaurus software. th , threshold voltage V th As the radiation dose changes Figure 4 shown.

[0033] Step 40, the threshold voltage V th The empirical formula of gate tunneling current is input for simulation and the gate tunneling current characteristics under the total dose effect are obtained.

[0034] Specifically, the gate tunneling current empirical formula of the SOI NMOS three-dimensional device structure model is modeled based on Matlab (matrix & laboratory, matrix laboratory) software. The gate tunneling current empirical formula is: The threshold voltage V under the total irradiation dose is extracted th Import the established gate tunneling current empirical formula and simulate it through Matlab to obtain the TWKB tunneling probability with gate voltage V g Changes in gate tunneling current under changes in total dose, such as Figure 5a and Figure 5b shown.

[0035] Where Ig is the gate tunneling current, W is the device gate width, and L is the device gate length. C(V g ,V ox ,t ox ,φ beff ) is the model correction factor, TWKB is the tunneling probability of electrons passing through the gate dielectric to reach the gate electrode. ε ox is the relative dielectric constant of the gate dielectric, t ox is the gate dielectric thickness, φ b is the initial barrier height between the gate dielectric and silicon, φ b0 is the potential barrier height between Si and SiO2, φ beff is the effective barrier height between the gate dielectric and silicon, V ox is the voltage on the gate dielectric, V ox =V g -Vth , V g is the voltage applied to the gate, V th is the device threshold voltage, N is the gate interface carrier concentration, m ox is the effective mass of the electron, E ox is the electric field applied on the gate, h is Planck's constant, q is the charge of the elementary charge, and α is the fitting coefficient.

[0036] The devices in the OFF state and the Transport state can be simulated according to the above steps 10 to 40.

[0037] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

[0038] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0039] In the present invention, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0040] In the present invention, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may include that the first and second features are in direct contact, or may include that the first and second features are not in direct contact but are in contact through another feature between them. Moreover, a first feature being "above", "above" and "above" a second feature includes that the first feature is directly above and obliquely above the second feature, or simply indicates that the first feature is higher in level than the second feature. A first feature being "below", "below" and "below" a second feature includes that the first feature is directly below and obliquely below the second feature, or simply indicates that the first feature is lower in level than the second feature.

[0041] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine different embodiments or examples described in this specification.

[0042] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the protection scope of the present invention.

Claims

1. A gate tunneling current simulation method under total dose, characterized in that: The following steps are involved: Step 10, performing three-dimensional device structure modeling on the SOI NMOS device based on TCAD Sentaurus to generate a three-dimensional device structure model of SOINMOS; Step 20, modifying the gate dielectric material parameter file of the SOI NMOS three-dimensional device structure model through Sentaurus to add and activate the Radiation model in the Physics part of Sdevice, and setting the radiation bias state of the SOI NMOS three-dimensional device structure model; Step 30, setting the irradiation dose rate and a plurality of different irradiation times, performing irradiation total dose simulation on the SOI NMOS three-dimensional device structure model, and extracting the threshold voltage V corresponding to different irradiation doses. th ; Step 40, the threshold voltage V th Input the empirical formula of gate tunneling current to perform simulation and obtain the gate tunneling current characteristics under the total dose effect; The gate tunneling current empirical formula is: Where Ig is the gate tunneling current, W is the device gate width, and L is the device gate length. is the model correction factor; TWKB is the tunneling probability of electrons passing through the gate dielectric to reach the gate electrode. ε ox is the relative dielectric constant of the gate dielectric, t ox is the gate dielectric thickness, is the initial barrier height between the gate dielectric and silicon, is the barrier height between Si and SiO2, is the effective barrier height between the gate dielectric and silicon, V ox is the voltage on the gate dielectric, V ox =V g -V th , V g is the voltage applied to the gate, V th is the device threshold voltage, N is the gate interface carrier concentration, m ox is the effective mass of the electron, E ox is the electric field applied on the gate, h is Planck's constant, q is the charge of the elementary charge, and α is the fitting coefficient.

2. The gate tunneling current simulation method under total dose according to claim 1, characterized in that: The modifying of the gate dielectric material parameter file of the SOI NMOS three-dimensional device structure model by using Sentaurus includes: replacing the identifier of the gate dielectric material with the identifier of the oxide semiconductor material by using Sentaurus, and replacing the parameter file of the oxide semiconductor material with the parameter file of the gate dielectric material.

3. The gate tunneling current simulation method under total dose according to claim 1, characterized in that: The bias state includes: an ON state, an OFF state or a transmission state.

4. The gate tunneling current simulation method under total dose according to claim 1, characterized in that: The threshold voltage V corresponding to different irradiation doses is extracted. th Extraction based on Inspect.

5. The gate tunneling current simulation method under total dose according to claim 1, characterized in that: In the step 40, simulation is performed by Matlab.

Images