A Low-Noise Wideband Millimeter-Wave Frequency Source Based on Multi-Phase Injection Locking

Abstract

The present invention provides a low-noise broadband millimeter-wave frequency source based on multi-phase injection locking, which includes a multi-phase clock generation module and a multi-phase injection-locked frequency multiplier module; the differential input end of the multi-phase clock generation module is connected to the injection voltage signal of an external signal source; the multi-phase clock generation module is used to generate a plurality of voltage signals with different phases from the injection voltage signal of the external signal source and output them to the multi-phase injection-locked frequency multiplier module; the multi-phase injection-locked frequency multiplier module includes a resonant cavity, and the resonant cavity includes a in-phase coupling transformer, a in-phase coupling transformer and an anti-phase coupling transformer. The plurality of voltage signals with different phases are respectively converted into current signals and then divided into two groups of injection signal sources. The two groups of injection signal sources are respectively injected into the in-phase coupling transformer and the in-phase coupling transformer and then output through the reverse coupling transformer. This millimeter-wave frequency source can reduce harmonic spurs in the entire frequency band and improve the power of the output signal.

Description

Technical Field

[0001] The present invention belongs to the field of electronic technology and relates to a low-noise broadband millimeter-wave frequency source based on multi-phase injection locking. Background Art

[0002] Millimeter-wave 5G wireless communication has gradually become a research and application hotspot. The 5G communication frequency bands include 24.75–27.5 GHz, 27.5–28.35 GHz, 37–38.6 GHz, 38.6–40 GHz, and 37–42.5 GHz. It is extremely challenging to generate clock signals with an ultra-wide frequency range using a local oscillator (LO) in the 5G frequency bands. At the same time, the higher data transmission rate requires more complex modulation methods, which also pose higher requirements for the phase noise of the local oscillator (LO). In addition, multi-input and multi-output systems and phased array transceivers also make the distribution of the local oscillator (LO) source difficult, and the local oscillator (LO) signal is required to have the characteristics of low power consumption and high efficiency.

[0003] Using a frequency multiplier to generate a high-frequency local oscillator (LO) source is a better way and has many advantages. First, applying a frequency multiplier to generate a high-frequency LO does not require a voltage-controlled oscillator operating at a higher frequency. Due to the low Q values of the tuning capacitor arrays and variable capacitors in high-frequency voltage-controlled oscillators, the phase noise of high-frequency voltage-controlled oscillators is poor, the frequency tuning range is small, and the power consumption is large. Second, by distributing frequency multipliers near the mixers in each channel, it is easier to distribute the generated local oscillator (LO) signals. Compared with traditional frequency multipliers, injection-locked frequency multipliers are commonly used frequency multiplication methods due to their low power consumption and low phase noise characteristics. The key to designing a high-performance injection-locked frequency multiplier is to enable the frequency source to have a wide frequency tuning range, high output power, and low harmonic spurs under limited power consumption.

[0004] In order to improve the frequency locking range of an injection-locked frequency multiplier, there have been some related research works. These include connecting a resistor in series in the resonator to increase the frequency locking range by reducing the Q value of the resonator. However, its frequency locking range is still limited, the output signal power is low, and the harmonic spurs are large. Another method is to add a calibration circuit in the resonator of the frequency multiplier to adjust the capacitance value of the resonator so that the resonance frequency changes synchronously with the injection signal frequency, thereby increasing the frequency locking range of the frequency multiplier. However, this method increases the complexity of the circuit design, and the injection-locked frequency range still cannot cover all communication protocols in the 5G band, and the phase noise deteriorates severely at the edge of the frequency locking range. Further research shows that increasing the order of the resonator of the frequency multiplier makes the frequency multiplier unstable in a large frequency range, so as to facilitate locking in a wider frequency range, which is an effective way to increase the frequency locking range. However, due to the widened frequency band, the output signal power obtained at each frequency point in the frequency band will decrease. The recent research amplifies the current of the injection signal through a transformer and combines it with a high-order resonator, which can increase the locking range of the frequency multiplier again, but the power of the output signal is still limited, and the harmonic spurs are large. Due to the limited output signal power of traditional frequency sources, in order to increase the output signal power, a power amplifier is usually cascaded at the output end, which significantly increases the overall power consumption of the frequency source. Summary of the Invention

[0005] The object of the present invention is to overcome the above-mentioned disadvantages of the prior art and propose a low-noise broadband millimeter-wave frequency source based on multi-phase injection locking. This millimeter-wave frequency source can reduce harmonic spurs in the entire frequency band and increase the power of the output signal.

[0006] The present invention is realized through the following technical solutions:

[0007] A low-noise broadband millimeter-wave frequency source based on multi-phase injection locking, comprising a multi-phase clock generation module and a multi-phase injection-locked frequency multiplier module;

[0008] The differential input end of the multi-phase clock generation module is connected to the injection voltage signal of an external signal source; the multi-phase clock generation module is used to generate voltage signals with multiple different phases from the injection voltage signal of the external signal source and output them to the multi-phase injection-locked frequency multiplier module;

[0009] The multi-phase injection-locked frequency multiplier module includes a resonator, and the resonator includes a in-phase coupling transformer, a in-phase coupling transformer, and an anti-phase coupling transformer. Voltage signals with multiple different phases are respectively converted into current signals and then divided into two groups of injection signal sources. The two groups of injection signal sources are respectively injected into the in-phase coupling transformer and the in-phase coupling transformer and then output through the reverse coupling transformer.

[0010] Preferably, the resonant cavity includes a first inductor, a second inductor, a third inductor, a fourth inductor, a fifth inductor, a sixth inductor, a fourth capacitor, a fifth capacitor, a sixth capacitor, a seventh capacitor, and an eighth capacitor; the first inductor and the fourth inductor form a in-phase coupling transformer, the second inductor and the third inductor form a in-phase coupling transformer, and the fifth inductor and the sixth inductor form a reverse coupling transformer; the multi-phase injection-locked frequency multiplier module includes a first carrier signal output terminal and a second carrier signal output terminal;

[0011] Wherein, a set of injection signal sources is connected to one end of the seventh capacitor and the fourth inductor, and another injection signal source is connected to one end of the sixth capacitor and the third inductor; one end of the eighth capacitor is connected to one end of the sixth inductor and the second carrier signal output terminal, the other end of the eighth capacitor is connected to one end of the fifth inductor and the first carrier signal output terminal, the other end of the fifth inductor is connected to one end of the fourth capacitor and one end of the first inductor, the other end of the sixth inductor is connected to one end of the fifth capacitor and one end of the second inductor, and the other ends of the first inductor, the second inductor, the third inductor, the fourth inductor, the fourth capacitor, the fifth capacitor, the sixth capacitor, and the seventh capacitor are all connected to the power supply voltage.

[0012] Further, the multi-phase injection-locked frequency multiplier module further includes: a first input terminal, a second input terminal, a third input terminal, a fourth input terminal, a fifth input terminal, a sixth input terminal, a thirty-first NMOS transistor, a thirty-second NMOS transistor, a thirty-third NMOS transistor, a thirty-fourth NMOS transistor, a thirty-fifth NMOS transistor, a thirty-sixth NMOS transistor, a thirty-seventh NMOS transistor, a thirty-eighth NMOS transistor, a thirty-ninth NMOS transistor, a fortieth NMOS transistor, a forty-first NMOS transistor, and a forty-second NMOS transistor;

[0013] The multi-phase clock generation module generates six voltage signals V inj,0 、V inj,60 、V inj,120 、V inj,180 、V inj,240 and V inj,300, are respectively connected to the first input terminal, the second input terminal, the third input terminal, the fourth input terminal, the fifth input terminal and the sixth input terminal; the source of the thirty-first NMOS transistor is grounded, the gate of the thirty-first NMOS transistor is connected to the first input terminal, the drain of the thirty-first NMOS transistor is connected to the source of the thirty-fourth NMOS transistor, the source of the thirty-second NMOS transistor is grounded, the gate of the thirty-second NMOS transistor is connected to the third input terminal, the drain of the thirty-second NMOS transistor is connected to the source of the thirty-fifth NMOS transistor, the source of the thirty-third NMOS transistor is grounded, the gate of the thirty-third NMOS transistor is connected to the fifth input terminal, the drain of the thirty-third NMOS transistor is connected to the source of the thirty-sixth NMOS transistor, the source of the thirty-seventh NMOS transistor is grounded, the gate of the thirty-seventh NMOS transistor is connected to the second input terminal, the drain of the thirty-seventh NMOS transistor is connected to the source of the fortieth NMOS transistor, the source of the thirty-eighth NMOS transistor is grounded, the gate of the thirty-eighth NMOS transistor is connected to the fourth input terminal, the drain of the thirty-eighth NMOS transistor is connected to the source of the forty-first NMOS transistor, the source of the thirty-ninth NMOS transistor is grounded, the gate of the thirty-ninth NMOS transistor is connected to the sixth input terminal, the drain of the thirty-ninth NMOS transistor is connected to the source of the forty-second NMOS transistor, the drains of the thirty-fourth NMOS transistor, the thirty-fifth NMOS transistor and the thirty-sixth NMOS transistor are all connected to one end of the fourth inductor and one end of the seventh capacitor, the drains of the fortieth NMOS transistor, the forty-first NMOS transistor and the forty-second NMOS transistor are all connected to one end of the third inductor and one end of the sixth capacitor, and the gates of the thirty-fourth NMOS transistor, the thirty-fifth NMOS transistor, the thirty-sixth NMOS transistor, the fortieth NMOS transistor, the forty-first NMOS transistor and the forty-second NMOS transistor are all connected to the bias voltage input terminal.

[0014] Further, the multi-phase injection-locked frequency multiplier module further includes a twenty-ninth NMOS transistor and a thirtieth NMOS transistor; the source of the twenty-ninth NMOS transistor is grounded, the gate of the twenty-ninth NMOS transistor is connected to the drain of the thirtieth NMOS transistor, the second carrier signal output terminal, one end of the eighth capacitor and one end of the sixth inductor, the drain of the twenty-ninth NMOS transistor is respectively connected to the gate of the thirtieth NMOS transistor, the first carrier signal output terminal, the other end of the eighth capacitor and one end of the fifth inductor, and the source of the thirtieth NMOS transistor is grounded.

[0015] Preferably, the multi-phase clock generation module includes: a first differential input terminal, a second differential input terminal, a first exclusive-OR gate, a second exclusive-OR gate, a current mirror, a first low-pass filter, a second low-pass filter, an operational amplifier, an injection-locked ring oscillator, a third resistor, and a fourth resistor; the injection-locked ring oscillator includes a third differential input terminal and a fourth differential input terminal, and a first single-phase output terminal, a second single-phase output terminal, a third single-phase output terminal, a fourth single-phase output terminal, a fifth single-phase output terminal, and a sixth single-phase output terminal that output to the multi-phase injection-locked frequency multiplier module;

[0016] The first differential input terminal and the second differential input terminal are respectively connected to the first differential output port and the second differential output port of an external signal source; one end of the third resistor is connected to the first differential input terminal, and the other end is connected to the first output terminal of the current mirror and the third differential input terminal; one end of the fourth resistor is connected to the second differential input terminal, and the other end is connected to the second output terminal of the current mirror and the fourth differential input terminal;

[0017] The output terminal of the first low-pass filter is connected to the positive terminal of the operational amplifier, the input terminal of the first low-pass filter is connected to the output terminal of the first exclusive-OR gate, and the two input terminals of the first exclusive-OR gate are respectively connected to the first single-phase output terminal and the second single-phase output terminal; the output terminal of the second low-pass filter is connected to the negative terminal of the operational amplifier, the input terminal of the second low-pass filter is connected to the output terminal of the second exclusive-OR gate, and the two input terminals of the second exclusive-OR gate are respectively connected to the third single-phase output terminal and the fourth single-phase output terminal; the output terminal of the operational amplifier is connected to the input terminal of the current mirror.

[0018] Further, the first low-pass filter includes a first capacitor and a first resistor; one end of the first capacitor is grounded, the other end of the first capacitor is connected to the positive terminal of the operational amplifier and one end of the first resistor, and the other end of the first resistor is connected to the output terminal of the first exclusive-OR gate;

[0019] The second low-pass filter includes a second capacitor and a second resistor; one end of the second capacitor is grounded, the other end of the second capacitor is connected to the negative terminal of the operational amplifier and one end of the second resistor, and the other end of the second resistor is connected to the output terminal of the second exclusive-OR gate.

[0020] Further, the current mirror includes a first NMOS transistor, a second NMOS transistor, a third PMOS transistor, and a fourth PMOS transistor; the source of the first NMOS transistor is grounded, the gate of the first NMOS transistor is connected to the gate of the second NMOS transistor, the drain of the first NMOS transistor is connected to the drain of the third PMOS transistor, the drain of the first NMOS transistor is connected to the gate, the source of the second NMOS transistor is grounded, the drain of the second NMOS transistor is connected to the drain of the fourth PMOS transistor, the source of the third PMOS transistor is connected to a high power supply voltage, the gate of the third PMOS transistor is connected to the output terminal of the operational amplifier, the source of the fourth PMOS transistor is connected to the high power supply voltage, the drain of the fourth PMOS transistor is connected to the gate, the other end of the third resistor is connected to the gate of the fourth PMOS transistor, and the other end of the fourth resistor is connected to the gate of the second NMOS transistor.

[0021] Further, the multi-phase clock generation module further includes a third capacitor, one end of the third capacitor is connected to the output terminal of the operational amplifier, and the other end of the third capacitor is grounded.

[0022] Further, the multi-phase clock generation module further includes a first buffer output, a second buffer output, a third buffer output, a fourth buffer output, a fifth buffer output, a sixth buffer output, a seventh buffer output, an eighth buffer output, a ninth buffer output, a tenth buffer output, an eleventh buffer output, and a twelfth buffer output;

[0023] The first single-phase output terminal is connected to the input terminals of the first buffer output and the seventh buffer output, the second single-phase output terminal is connected to the input terminals of the second buffer output and the eighth buffer output, the third single-phase output terminal is connected to the input terminals of the third buffer output and the ninth buffer output, the fourth single-phase output terminal is connected to the input terminals of the fourth buffer output and the tenth buffer output, the fifth single-phase output terminal is connected to the input terminals of the fifth buffer output and the eleventh buffer output, the sixth single-phase output terminal is connected to the input terminals of the sixth buffer output and the twelfth buffer output, the output terminals of the first buffer output and the second buffer output are respectively connected to the two input terminals of the first exclusive-OR gate, the output terminals of the third buffer output and the fourth buffer output are respectively connected to the two input terminals of the second exclusive-OR gate, the output terminal of the fifth buffer output is floating, the output terminal of the sixth buffer output is floating, and the output terminals of the seventh buffer output, the eighth buffer output, the ninth buffer output, the tenth buffer output, the eleventh buffer output, and the twelfth buffer output are respectively connected to the six input terminals of the multi-phase injection-locked frequency multiplier module in one-to-one correspondence.

[0024] Further, the injection-locked ring oscillator further includes a first inverter, a second inverter, a third inverter, a fourth inverter, a fifth inverter, a sixth inverter, a fifth NMOS transistor, a sixth NMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, an eleventh PMOS transistor, a twelfth PMOS transistor, a thirteenth NMOS transistor, a fourteenth NMOS transistor, a fifteenth PMOS transistor, a sixteenth PMOS transistor, a seventeenth NMOS transistor, an eighteenth NMOS transistor, a nineteenth PMOS transistor, a twentieth PMOS transistor, a twenty-first NMOS transistor, a twenty-second NMOS transistor, a twenty-third PMOS transistor, a twenty-fourth PMOS transistor, a twenty-fifth NMOS transistor, a twenty-sixth NMOS transistor, a twenty-seventh PMOS transistor, and a twenty-eighth PMOS transistor;

[0025] The source of the fifth NMOS transistor is grounded. The drain of the fifth NMOS transistor is connected to the source of the sixth NMOS transistor. The drain of the sixth NMOS transistor is connected to the drain of the seventh PMOS transistor, the output terminal of the first inverter, the input terminal of the second inverter, and the first single-phase output terminal. The gate of the sixth NMOS transistor is connected to the gate of the seventh PMOS transistor and the drain of the fourteenth NMOS transistor. The source of the seventh PMOS transistor is connected to the drain of the eighth PMOS transistor. The source of the eighth PMOS transistor is connected to the high power supply voltage. The source of the ninth NMOS transistor is grounded. The drain of the ninth NMOS transistor is connected to the source of the tenth NMOS transistor. The gate of the tenth NMOS transistor is connected to the gate of the eleventh PMOS transistor and the drain of the sixth NMOS transistor. The drain of the tenth NMOS transistor is connected to the drain of the eleventh PMOS transistor, the output terminal of the third inverter, the input terminal of the fourth inverter, and the fifth single-phase output terminal. The source of the eleventh PMOS transistor is connected to the drain of the twelfth PMOS transistor. The source of the twelfth PMOS transistor is connected to the high power supply voltage. The source of the thirteenth NMOS transistor is grounded. The drain of the thirteenth NMOS transistor is connected to the source of the fourteenth NMOS transistor. The drain of the fourteenth NMOS transistor is connected to the drain of the fifteenth PMOS transistor, the output terminal of the fifth inverter, the input terminal of the sixth inverter, and the third single-phase output terminal. The gate of the fourteenth NMOS transistor is connected to the gate of the fifteenth PMOS transistor and the drain of the tenth NMOS transistor. The source of the fifteenth PMOS transistor is connected to the drain of the sixteenth PMOS transistor. The source of the sixteenth PMOS transistor is connected to the high power supply voltage. The source of the seventeenth NMOS transistor is grounded. The drain of the seventeenth NMOS transistor is connected to the source of the eighteenth NMOS transistor. The gate of the eighteenth NMOS transistor is connected to the gate of the nineteenth PMOS transistor and the drain of the twenty-sixth NMOS transistor. The drain of the eighteenth NMOS transistor is connected to the drain of the nineteenth PMOS transistor, the input terminal of the first inverter, the output terminal of the second inverter, and the fourth single-phase output terminal. The source of the nineteenth PMOS transistor is connected to the drain of the twentieth PMOS transistor. The source of the twentieth PMOS transistor is connected to the high power supply voltage. The source of the twenty-first NMOS transistor is grounded. The drain of the twenty-first NMOS transistor is connected to the source of the twenty-second NMOS transistor. The gate of the twenty-second NMOS transistor is connected to the gate of the twenty-third PMOS transistor and the drain of the eighteenth NMOS transistor. The drain of the twenty-second NMOS transistor is connected to the drain of the twenty-third PMOS transistor, the input terminal of the third inverter, the output terminal of the fourth inverter, and the second single-phase output terminal. The source of the twenty-third PMOS transistor is connected to the drain of the twenty-fourth PMOS transistor. The source of the twenty-fourth PMOS transistor is connected to the high power supply voltage. The source of the twenty-fifth NMOS transistor is grounded. The drain of the twenty-fifth NMOS transistor is connected to the source of the twenty-sixth NMOS transistor. The gate of the twenty-sixth NMOS transistor is connected to the gate of the twenty-seventh PMOS transistor and the drain of the twenty-second NMOS transistor.The drain of the twenty-sixth NMOS transistor is connected to the drain of the twenty-seventh PMOS transistor, the input terminal of the fifth inverter, the output terminal of the sixth inverter, and the sixth single-phase output terminal. The source of the twenty-seventh PMOS transistor is connected to the drain of the twenty-eighth PMOS transistor. The source of the twenty-eighth PMOS transistor is connected to the high power supply voltage. The gates of the fifth NMOS transistor, the ninth NMOS transistor, the thirteenth NMOS transistor, the seventeenth NMOS transistor, the twenty-first NMOS transistor, and the twenty-fifth NMOS transistor are all connected to the fourth differential input terminal. The gates of the eighth PMOS transistor, the twelfth PMOS transistor, the sixteenth PMOS transistor, the twentieth PMOS transistor, the twenty-fourth PMOS transistor, and the twenty-eighth PMOS transistor are all connected to the third differential input terminal.

[0026] Compared with the prior art, the present invention has the following beneficial effects:

[0027] In the present invention, a reverse-coupled transformer is added to the resonant cavity of the multi-phase injection-locked frequency multiplier module to increase the input impedance of the resonant cavity within the working range, thereby effectively improving the output signal power of the millimeter-wave frequency source. The high-precision clock signal required by the multi-phase injection-locked frequency multiplier module in the present invention is provided by the multi-phase clock generation module. The clock signal is reasonably distributed and injected into the resonant cavity of the multi-phase injection-locked frequency multiplier module. The multi-phase injection-locked frequency multiplier module converts the injected voltage signals with multiple different phases into current signals and reasonably superimposes them, so that the fundamental wave and the second harmonic current components cancel each other out, and the third harmonic current is superimposed and enhanced, reducing the harmonic spurs of the millimeter-wave frequency source within the full frequency band.

[0028] Furthermore, due to the increase in the total bandwidth of the microprocessor, there is a greater demand for large-scale parallel low-power links with high data rates, which poses strict requirements for the generation and distribution of on-chip clocks. In the past, in order to reduce power consumption, area, and jitter, injection-locked ring oscillators were mainly used to generate the required clock signals. However, the traditional single-point injection method results in a small frequency locking range of the ring oscillator, which cannot meet the requirements of broadband applications. Moreover, when the frequency of the injection signal differs significantly from the intrinsic frequency of the ring oscillator, there are large phase errors in the multi-phase signals generated by the ring oscillator, making it no longer suitable for circuits with high requirements for clock accuracy. Existing research has proposed adding frequency tracking technology to regulate the control voltage of the ring oscillator, making the frequency of the injection signal the same as the intrinsic frequency of the ring oscillator, greatly improving the frequency locking range of the injection-locked ring oscillator and reducing the phase error between clocks. However, the existing technologies can mainly calibrate orthogonal clock circuits, and the calibration of clock circuits with arbitrary phases has not been given. To solve this problem, the present invention forms a frequency locking loop by an injection-locked ring oscillator, a first exclusive-OR gate, a second exclusive-OR gate, a first low-pass filter, a second low-pass filter, an operational amplifier, and a current mirror. During specific operations, an injection signal with low jitter and high output swing provided by an external instrument is input into the injection-locked ring oscillator. The injection-locked ring oscillator uses the frequency locking loop to calibrate the output signal frequency of the ring oscillator in real time, making the intrinsic signal frequency of the injection-locked ring oscillator consistent with the injection signal frequency. On the one hand, the frequency locking range of the injection-locked ring oscillator is improved, and on the other hand, the phase error between adjacent clock signals is effectively reduced. Since the present invention adopts a multi-node injection locking method for the ring oscillator, when there is no frequency locking loop, the frequency locking range of the injection-locked ring oscillator is already large. Therefore, the phase noise of the output signal can track the phase noise of the injection signal to a farther frequency offset, further reducing the jitter of the clock signal generated by the injection-locked ring oscillator. The high-precision clock signal generation circuit proposed by the present invention can be extended to the generation of clock signals with arbitrary phases. Description of the Drawings

[0029] Figure 1 is a schematic structural diagram of the present invention;

[0030] Figure 2 is a schematic diagram of the principle of the multi-phase clock generation module in the present invention;

[0031] Figure 3 is a schematic diagram of the principle of the injection-locked ring oscillator in the present invention;

[0032] Figure 4 is a schematic diagram of the principle of the multi-phase injection-locked frequency multiplier module in the present invention;

[0033] Figure 5 is a schematic diagram of the current vector injected into the tripler in the present invention. Detailed Embodiments

[0034] To further understand the present invention, the present invention will be described below in conjunction with embodiments. These descriptions are only to further explain the features and advantages of the present invention and are not intended to limit the claims of the present invention.

[0035] Reference Figure 1 , the low-noise broadband millimeter-wave frequency source based on multi-phase injection locking according to the present invention includes a bias voltage input terminal, a first carrier signal output terminal, a second carrier signal output terminal, an external signal source, a multi-phase clock generation module, and a multi-phase injection locking frequency multiplier module;

[0036] The first differential output port V INJ,P and the second differential output port V INJ,N of the external signal source are connected to the differential input terminals of the multi-phase clock generation module. The first output terminal V inj,0 , the second output terminal V inj,60 , the third output terminal V inj,120 , the fourth output terminal V inj,180 , the fifth output terminal V inj,240 and the sixth output terminal V inj,300 of the multi-phase clock generation module are respectively connected to the first input terminal V inj,0 , the second input terminal V inj,60 , the third input terminal V inj,120 , the fourth input terminal V inj,180 , the fifth input terminal V inj,240 and the sixth input terminal V inj,300 of the multi-phase injection locking frequency multiplier module. The single-ended input terminal of the multi-phase injection locking frequency multiplier module is connected to the bias voltage input terminal V B . The differential output terminals of the multi-phase injection locking frequency multiplier module are respectively connected to the first carrier signal output terminal OUTP and the second carrier signal output terminal OUTN.

[0037] Reference Figure 2 , the multi-phase clock generation module includes a first differential input terminal V INJ,P and a second differential input terminal V INJ,N , a first output terminal V inj,0 , a second output terminal V inj,60 , a third output terminal V inj,120 , a fourth output terminal V inj,180 , a fifth output terminal V inj,240 , a sixth output terminal V inj,300, the first exclusive-OR gate XOR1, the second exclusive-OR gate XOR2, a current mirror, the first low-pass filter 1, the second low-pass filter 2, an operational amplifier, an injection-locked ring oscillator, the third capacitor C3, the third resistor R3, the fourth resistor R4, the first buffer output b0, the second buffer output b1, the third buffer output b2, the fourth buffer output b3, the fifth buffer output b4, the sixth buffer output b5, the seventh buffer output b6, the eighth buffer output b7, the ninth buffer output b8, the tenth buffer output b9, the eleventh buffer output b 10 , the twelfth buffer output b 11 .

[0038] Among them, the current mirror includes the first NMOS transistor M1, the second NMOS transistor M2, the third PMOS transistor M3, and the fourth PMOS transistor M4.

[0039] The source of the first NMOS transistor M1 is grounded. The gate of the first NMOS transistor M1 is connected to the gate of the second NMOS transistor M2. The drain of the first NMOS transistor M1 is connected to the drain of the third PMOS transistor M3. The drain of the first NMOS transistor M1 is connected to its gate. The source of the second NMOS transistor M2 is grounded. The drain of the second NMOS transistor M2 is connected to the drain of the fourth PMOS transistor M4. The source of the third PMOS transistor M3 is connected to the high power supply voltage VDDH. The gate of the third PMOS transistor M3 is connected to the output terminal V of the operational amplifier ctrl and one end of the third capacitor C3. The other end of the third capacitor C3 is grounded. The source of the fourth PMOS transistor M4 is connected to the high power supply voltage VDDH. The drain of the fourth PMOS transistor M4 is connected to its gate. One end of the third resistor R3 is connected to the first differential input terminal V INJ,P , and the other end is connected to the gate of the fourth PMOS transistor M4 and the third differential input terminal V of the injection-locked ring oscillator IP . One end of the fourth resistor R4 is connected to the second differential input terminal V INJ,N , and the other end is connected to the gate of the second NMOS transistor M2 and the fourth differential input terminal V of the injection-locked ring oscillator IN .

[0040] The first low-pass filter 1 includes the first capacitor C1 and the first resistor R1. One end of the first capacitor C1 is grounded. The other end of the first capacitor C1 is connected to the positive terminal of the operational amplifier and one end of the first resistor R1. The other end of the first resistor R1 is connected to the output terminal of the first exclusive-OR gate XOR1. The two input terminals of the first exclusive-OR gate XOR1 are respectively connected to the output terminals of the first buffer output b0 and the second buffer output b1.

[0041] The second low-pass filter 2 includes a second capacitor C2 and a second resistor R2; one end of the second capacitor C2 is grounded, the other end of the second capacitor C2 is connected to the negative terminal of the operational amplifier and one end of the second resistor R2, the other end of the second resistor R2 is connected to the output terminal of the second exclusive-OR gate XOR2, and the two input terminals of the second exclusive-OR gate XOR2 are respectively connected to the output terminals of the third buffer b2 and the fourth buffer b3.

[0042] The first single-phase output terminal CKR_0 of the injection-locked ring oscillator is connected to the input terminals of the first buffer b0 and the seventh buffer b6, the second single-phase output terminal CKR_60 of the injection-locked ring oscillator is connected to the input terminals of the second buffer b1 and the eighth buffer b7, the third single-phase output terminal CKR_120 of the injection-locked ring oscillator is connected to the input terminals of the third buffer b2 and the ninth buffer b8, the fourth single-phase output terminal CKR_180 of the injection-locked ring oscillator is connected to the input terminals of the fourth buffer b3 and the tenth buffer b9, the fifth single-phase output terminal CKR_240 of the injection-locked ring oscillator is connected to the input terminals of the fifth buffer b4 and the eleventh buffer b 10 The input terminal of, the sixth single-phase output terminal CKR_300 of the injection-locked ring oscillator is connected to the input terminals of the sixth buffer b5 and the twelfth buffer b 11 The output terminal of the fifth buffer b4 is floating, the output terminal of the sixth buffer b5 is floating, the output terminal of the seventh buffer b6 is connected to the first output terminal V of the multi-phase clock generation module inj,0 is connected, the output terminal of the eighth buffer b7 is connected to the second output terminal V inj,60 is connected, the output terminal of the ninth buffer b8 is connected to the third output terminal V inj,120 is connected, the output terminal of the tenth buffer b9 is connected to the fourth output terminal V inj,180 is connected, the output terminal of the eleventh buffer b 10 is connected to the fifth output terminal V inj,240 is connected, the output terminal of the twelfth buffer b 11 is connected to the sixth output terminal V inj,300 is connected.

[0043] In the locked state, the output signal frequency of the injection-locked ring oscillator is the same as that of the external signal source, and the information of the self-oscillation frequency of the ring oscillator is lost. There is a large phase error between adjacent clock signals. The four adjacent output signals of the injection-locked ring oscillator after passing through the buffer are sequentially passed through the first and second exclusive-OR gates. The first low-pass filter 1 takes the mean value of the output signal of the first exclusive-OR gate, and the second low-pass filter 2 takes the mean value of the output signal of the second exclusive-OR gate. When the phase differences between the signals CKO_0 and CKO_60 and the signals CKO_120 and CKO_180 are different, the mean values of the outputs of the first low-pass filter 1 and the second low-pass filter 2 are different. At this time, the operational amplifier charges and discharges the third capacitor C3, changing the output voltage V ctrl , and the change of the output voltage V ctrl is fed back into the injection-locked ring oscillator through the current mirror, adjusting the magnitude of the current injected into the injection-locked ring oscillator, thereby changing the output signal frequency of the injection-locked ring oscillator, making the intrinsic output signal frequency of the injection-locked ring oscillator the same as the injection signal frequency of the external signal source. When the feedback system makes the phase differences between the signals CKO_0 and CKO_60 and the signals CKO_120 and CKO_180 the same, the output voltage V ctrl remains unchanged. At this time, the multi-phase clock module generates an output signal with higher phase accuracy.

[0044] Reference Figure 3 , the injection-locked ring oscillator includes a third differential input terminal V IP , a fourth differential input terminal V IN , a first single-phase output terminal CKR_0, a second single-phase output terminal CKR_60, a third single-phase output terminal CKR_120, a fourth single-phase output terminal CKR_180, a fifth single-phase output terminal CKR_240, a sixth single-phase output terminal CKR_300, a first inverter Lat1, a second inverter Lat2, a third inverter Lat3, a fourth inverter Lat4, a fifth inverter Lat5, a sixth inverter Lat6, a fifth NMOS transistor M5, a sixth NMOS transistor M6, a seventh PMOS transistor M7, an eighth PMOS transistor M8, a ninth NMOS transistor M9, a tenth NMOS transistor M 10 , an eleventh PMOS transistor M 11 , a twelfth PMOS transistor M 12 , a thirteenth NMOS transistor M 13 , a fourteenth NMOS transistor M 14 , a fifteenth PMOS transistor M 15 , a sixteenth PMOS transistor M 16 , a seventeenth NMOS transistor M 17 , an eighteenth NMOS transistor M 18 , a nineteenth PMOS transistor M19 and the twentieth PMOS transistor M 20 and the twenty-first NMOS transistor M 21 and the twenty-second NMOS transistor M 22 and the twenty-third PMOS transistor M 23 and the twenty-fourth PMOS transistor M 24 and the twenty-fifth NMOS transistor M 25 and the twenty-sixth NMOS transistor M 26 and the twenty-seventh PMOS transistor M 27 and the twenty-eighth PMOS transistor M 28 .

[0045] The source of the fifth NMOS transistor M5 is grounded. The drain of the fifth NMOS transistor M5 is connected to the source of the sixth NMOS transistor M6. The drain of the sixth NMOS transistor M6 is connected to the drain of the seventh PMOS transistor M7, the output terminal of the first inverter Lat1, the input terminal of the second inverter Lat2, and the first single-phase output terminal CKR_0. The gate of the sixth NMOS transistor M6 is connected to the gate of the seventh PMOS transistor M7 and the drain of the fourteenth NMOS transistor M 14 . The source of the seventh PMOS transistor M7 is connected to the drain of the eighth PMOS transistor M8. The source of the eighth PMOS transistor M8 is connected to the high power supply voltage VDDH. The source of the ninth NMOS transistor M9 is grounded. The drain of the ninth NMOS transistor M9 is connected to the source of the tenth NMOS transistor M 10 . The gate of the tenth NMOS transistor M 10 is connected to the gate of the eleventh PMOS transistor M 11 and the gate of the sixth NMOS transistor M6 and the drain of the sixth NMOS transistor M6. The drain of the tenth NMOS transistor M 10 is connected to the drain of the eleventh PMOS transistor M 11 , the output terminal of the third inverter Lat3, the input terminal of the fourth inverter Lat4, and the fifth single-phase output terminal CKR_240. The source of the eleventh PMOS transistor M 11 is connected to the drain of the twelfth PMOS transistor M 12 . The source of the twelfth PMOS transistor M 12 is connected to the high power supply voltage VDDH. The source of the thirteenth NMOS transistor M 13 is grounded. The drain of the thirteenth NMOS transistor M 13 is connected to the source of the fourteenth NMOS transistor M 14 . The drain of the fourteenth NMOS transistor M 14 is connected to the drain of the fifteenth PMOS transistor M 15 , the output terminal of the fifth inverter Lat5, the input terminal of the sixth inverter Lat6, and the third single-phase output terminal CKR_120. The fourteenth NMOS transistor M 14and the gate of the fifteenth PMOS transistor M 15 and the gate of the tenth NMOS transistor M 10 are connected to the drain of the fifteenth PMOS transistor M 15 The source of the fifteenth PMOS transistor M is connected to the drain of the sixteenth PMOS transistor M 16 The source of the sixteenth PMOS transistor M is connected to the drain of the sixteenth PMOS transistor M 16 The source of the sixteenth PMOS transistor M is connected to the high power supply voltage VDDH, and the source of the seventeenth NMOS transistor M 17 is grounded. The drain of the seventeenth NMOS transistor M 17 is connected to the source of the eighteenth NMOS transistor M 18 The source of the eighteenth NMOS transistor M 18 The gate of the eighteenth NMOS transistor M is connected to the gate of the nineteenth PMOS transistor M 19 and the gate of the twenty-sixth NMOS transistor M 26 are connected to the drain of the eighteenth NMOS transistor M 18 The drain of the eighteenth NMOS transistor M is connected to the drain of the nineteenth PMOS transistor M 19 The drain, the input terminal of the first inverter Lat1, the output terminal of the second inverter Lat2, and the fourth single-phase output terminal CKR_180 are connected. The source of the nineteenth PMOS transistor M 19 is connected to the drain of the twentieth PMOS transistor M 20 The source of the twentieth PMOS transistor M 20 is connected to the high power supply voltage VDDH. The source of the twenty-first NMOS transistor M 21 is grounded. The drain of the twenty-first NMOS transistor M 21 is connected to the source of the twenty-second NMOS transistor M 22 The source of the twenty-second NMOS transistor M 22 The gate of the twenty-second NMOS transistor M is connected to the gate of the twenty-third PMOS transistor M 23 and the gate of the eighteenth NMOS transistor M 18 are connected to the drain of the eighteenth NMOS transistor M 22 The drain of the twenty-second NMOS transistor M is connected to the drain of the twenty-third PMOS transistor M 23 The drain, the input terminal of the third inverter Lat3, the output terminal of the fourth inverter Lat4, and the second single-phase output terminal CKR_60 are connected. The source of the twenty-third PMOS transistor M 23 is connected to the drain of the twenty-fourth PMOS transistor M 24 The source of the twenty-fourth PMOS transistor M 24 is connected to the high power supply voltage VDDH. The source of the twenty-fifth NMOS transistor M 25 is grounded. The drain of the twenty-fifth NMOS transistor M 25 is connected to the source of the twenty-sixth NMOS transistor M 26 The source of the twenty-sixth NMOS transistor M 26 The gate of the twenty-sixth NMOS transistor M is connected to the gate of the twenty-seventh PMOS transistor M27 and the gate of the twenty-second NMOS transistor M 22 are connected to the drain of the twenty-sixth NMOS transistor M 26 is connected to the drain of the twenty-seventh PMOS transistor M 27 is connected to the drain of the twenty-seventh PMOS transistor M, the input terminal of the fifth inverter Lat5, the output terminal of the sixth inverter Lat6, and the sixth single-phase output terminal CKR_300. The source of the twenty-seventh PMOS transistor M 27 is connected to the drain of the twenty-eighth PMOS transistor M 28 is connected to the drain of the twenty-eighth PMOS transistor M 28 is connected to the high power supply voltage VDDH. The gates of the fifth NMOS transistor M5, the ninth NMOS transistor M9, the thirteenth NMOS transistor M 13 are connected to the gate of the seventeenth NMOS transistor M 17 are connected to the gate of the twenty-first NMOS transistor M 21 are connected to the gate of the twenty-fifth NMOS transistor M 25 are all connected to the fourth differential input terminal V IN The gates of the eighth PMOS transistor M8, the twelfth PMOS transistor M 12 are connected to the gate of the sixteenth PMOS transistor M 16 are connected to the gate of the twentieth PMOS transistor M 20 are connected to the gate of the twenty-fourth PMOS transistor M 24 are connected to the gate of the twenty-eighth PMOS transistor M 28 are all connected to the third differential input terminal V IP is connected.

[0046] When the third differential input terminal V IP and the fourth differential input terminal V IN are biased at reasonable DC values, the ring oscillator will generate clock signals with six equal phase differences under the condition of satisfying the Barkhausen criterion. When the DC values of the two differential input terminals change, the power consumption of the ring oscillator changes accordingly. The output clock frequency of the ring oscillator is in the same direction as the change in power consumption. When AC signal values are injected into the two differential input terminals, the larger the injection signal swing and the closer the frequency is to the intrinsic output signal frequency of the ring oscillator, the easier it is to lock. In the locked state, the output signal frequency of the ring oscillator is the same as the frequency of the injection source. At this time, the output noise of the injection-locked ring oscillator is mainly determined by the injection signal source.

[0047] Reference Figure 4 , the multi-phase injection-locked frequency multiplier module includes a first input terminal V inj,0 , a second input terminal V inj,60 , a third input terminal V inj,120 , a fourth input terminal V inj,180 , a fifth input terminal V inj,240, the sixth input terminal V inj,300 , the bias voltage input terminal V B , the first carrier signal output terminal OUTP, the second carrier signal output terminal OUTN, the twenty-ninth NMOS transistor M 29 , the thirtieth NMOS transistor M 30 , the thirty-first NMOS transistor M 31 , the thirty-second NMOS transistor M 32 , the thirty-third NMOS transistor M 33 , the thirty-fourth NMOS transistor M 34 , the thirty-fifth NMOS transistor M 35 , the thirty-sixth NMOS transistor M 36 , the thirty-seventh NMOS transistor M 37 , the thirty-eighth NMOS transistor M 38 , the thirty-ninth NMOS transistor M 39 , the fortieth NMOS transistor M 40 , the forty-first NMOS transistor M 41 , the forty-second NMOS transistor M 42 , the first inductor L1, the second inductor L2, the third inductor L3, the fourth inductor L4, the fifth inductor L5, the sixth inductor L6, the fourth capacitor C4, the fifth capacitor C5, the sixth capacitor C6, the seventh capacitor C7 and the eighth capacitor C8.

[0048] Among them, the source of the twenty-ninth NMOS transistor M 29 is grounded. The gate of the twenty-ninth NMOS transistor M 29 is connected to the drain of the thirtieth NMOS transistor M 30 , the second carrier signal output terminal OUTN, one end of the eighth capacitor C8 and one end of the sixth inductor L6. The drain of the twenty-ninth NMOS transistor M 29 is respectively connected to the gate of the thirtieth NMOS transistor M 30 , the first carrier signal output terminal OUTP, the other end of the eighth capacitor C8 and one end of the fifth inductor L5. The source of the thirtieth NMOS transistor M 30 is grounded. The source of the thirty-first NMOS transistor M 31 is grounded. The gate of the thirty-first NMOS transistor M 31 is connected to the first input terminal V inj,0 . The drain of the thirty-first NMOS transistor M 31 is connected to the source of the thirty-fourth NMOS transistor M 34 . The source of the thirty-second NMOS transistor M 32 is grounded. The gate of the thirty-second NMOS transistor M 32 is connected to the third input terminal V inj,120 . The drain of the thirty-second NMOS transistor M 32The drain of and the thirty-fifth NMOS transistor M 35 The source of are connected, and the thirty-third NMOS transistor M 33 The source of is grounded, and the thirty-third NMOS transistor M 33 The gate of and the fifth input terminal V inj,240 Are connected, and the thirty-third NMOS transistor M 33 The drain of and the thirty-sixth NMOS transistor M 36 The source of are connected, and the thirty-seventh NMOS transistor M 37 The source of is grounded, and the thirty-seventh NMOS transistor M 37 The gate of and the second input terminal V inj,60 Are connected, and the thirty-seventh NMOS transistor M 37 The drain of and the fortieth NMOS transistor M 40 The source of are connected, and the thirty-eighth NMOS transistor M 38 The source of is grounded, and the thirty-eighth NMOS transistor M 38 The gate of and the fourth input terminal V inj,180 Are connected, and the thirty-eighth NMOS transistor M 38 The drain of and the forty-first NMOS transistor M 41 The source of are connected, and the thirty-ninth NMOS transistor M 39 The source of is grounded, and the thirty-ninth NMOS transistor M 39 The gate of and the sixth input terminal V inj,300 Are connected, and the thirty-ninth NMOS transistor M 39 The drain of and the forty-second NMOS transistor M 42 The source of are connected, and the thirty-fourth NMOS transistor M 34 The drain of, the thirty-fifth NMOS transistor M 35 The drain of and the thirty-sixth NMOS transistor M 36 The drains of are all connected to one end of the fourth inductor L4 and one end of the seventh capacitor C7. The drain of the fortieth NMOS transistor M 40 The drain of, the forty-first NMOS transistor M 41 The drain of and the forty-second NMOS transistor M 42 The drains of are all connected to one end of the third inductor L3 and one end of the sixth capacitor C6. The gate of the thirty-fourth NMOS transistor M 34 The gate of, the thirty-fifth NMOS transistor M 35 The gate of, the thirty-sixth NMOS transistor M 36 The gate of, the fortieth NMOS transistor M 40 The gate of, the forty-first NMOS transistor M 41 The gate of and the forty-second NMOS transistor M 42 The gates of are all connected to the bias voltage input terminal V Bare connected. The other end of the fifth inductor L5, one end of the fourth capacitor C4, and one end of the first inductor L1 are connected. The other end of the sixth inductor L6, one end of the fifth capacitor C5, and one end of the second inductor L2 are connected. The other ends of the first inductor L1, the second inductor L2, the third inductor L3, the fourth inductor L4, the fourth capacitor C4, the fifth capacitor C5, the sixth capacitor C6, and the seventh capacitor C7 are all connected to the power supply voltage VDD.

[0049] The first inductor and the fourth inductor form a in-phase coupling transformer 1 with a coupling coefficient of K1. The second inductor and the third inductor form a in-phase coupling transformer 2 with a coupling coefficient of K2. The fifth inductor and the sixth inductor form an anti-phase coupling transformer 3 with a coupling coefficient of K3. The fourth capacitor C4, the fifth capacitor C5, the sixth capacitor C6, the seventh capacitor C7, the eighth capacitor C8, the in-phase coupling transformer 1, the in-phase coupling transformer 2, and the anti-phase coupling transformer 3 form the resonant cavity of the tripler. Since the order of this resonant cavity is relatively high, it is unstable in a relatively large frequency range, which is convenient for locking. And by adding the anti-phase coupling transformer 3 to the traditional structure, the output impedance of the resonant cavity in the unstable range is improved. The voltage signals V inj,0 、V inj,120 、V inj,240 、V inj,60 、V inj,180 and V inj,300 are sequentially applied to the gates of the thirty-first NMOS transistor M 31 , the thirty-second NMOS transistor M 32 , the thirty-third NMOS transistor M 33 , the thirty-seventh NMOS transistor M 37 , the thirty-eighth NMOS transistor M 38 , and the thirty-ninth NMOS transistor M 39 respectively, and are converted into current signals I inj,0 , I inj,120 , I inj,240 , I inj,60 , I inj,180 , and I inj,300 which are injected into the resonant cavity of the tripler. Among them, I inj,0 , I inj,120 , and I inj,240 form a group of injection signal sources, and I inj,60 , I inj,180 , and I inj,300 form another group of injection signal sources. As shown in Figure 5 , at this time, the fundamental wave and the second harmonic components of the current injected into the resonant cavity cancel each other out, and the third harmonic current is superimposed and enhanced, making the frequency multiplier better locked at three times the input signal frequency.

Claims

1. A low-noise broadband millimeter-wave frequency source based on multi-phase injection locking, characterized in that It includes a multi-phase clock generation module and a multi-phase injection-locked frequency multiplier module; The differential input terminal of the multi-phase clock generation module is connected to the injection voltage signal of an external signal source; the multi-phase clock generation module is used to generate a plurality of voltage signals with different phases from the injection voltage signal of the external signal source and output them to the multi-phase injection-locked frequency multiplier module; The multi-phase injection-locked frequency multiplier module includes a resonant cavity, and the resonant cavity includes a in-phase coupling transformer (1), a in-phase coupling transformer (2), and an anti-phase coupling transformer (3). A plurality of voltage signals with different phases are respectively converted into current signals and then divided into two groups of injection signal sources. The two groups of injection signal sources are respectively injected into the in-phase coupling transformer (1) and the in-phase coupling transformer (2) and then output through the reverse coupling transformer (3); The resonant cavity includes a first inductor (L1), a second inductor (L2), a third inductor (L3), a fourth inductor (L4), a fifth inductor (L5), a sixth inductor (L6), a fourth capacitor (C4), a fifth capacitor (C5), a sixth capacitor (C6), a seventh capacitor (C7), and an eighth capacitor (C8); the first inductor (L1) and the fourth inductor (L4) form the in-phase coupling transformer (1), the second inductor (L2) and the third inductor (L3) form the in-phase coupling transformer (2), and the fifth inductor (L5) and the sixth inductor (L6) form the anti-phase coupling transformer (3); the multi-phase injection-locked frequency multiplier module includes a first carrier signal output terminal (OUTP) and a second carrier signal output terminal (OUTN); Among them, one group of injection signal sources is connected to one end of the seventh capacitor (C7) and the fourth inductor (L4), and the other injection signal source is connected to one end of the sixth capacitor (C6) and the third inductor (L3); one end of the eighth capacitor (C8) is connected to one end of the sixth inductor (L6) and the second carrier signal output terminal (OUTN), the other end of the eighth capacitor (C8) is connected to one end of the fifth inductor (L5) and the first carrier signal output terminal (OUTP), the other end of the fifth inductor (L5) is connected to one end of the fourth capacitor (C4) and one end of the first inductor (L1), the other end of the sixth inductor (L6) is connected to one end of the fifth capacitor (C5) and one end of the second inductor (L2), and the other ends of the first inductor (L1), the second inductor (L2), the third inductor (L3), the fourth inductor (L4), the fourth capacitor (C4), the fifth capacitor (C5), the sixth capacitor (C6), and the seventh capacitor (C7) are all connected to the power supply voltage (VDD); The multi-phase injection-locked frequency multiplier module further includes: a first input terminal (V inj,0 ), a second input terminal (V inj,60 ), a third input terminal (V inj,120 ), a fourth input terminal (V inj,180 ), a fifth input terminal (V inj,240 ), a sixth input terminal (V inj,300 ), a thirty-first NMOS transistor (M 31 ), a thirty-second NMOS transistor (M 32 ), a thirty-third NMOS transistor (M 33 ), a thirty-fourth NMOS transistor (M 34 ), a thirty-fifth NMOS transistor (M 35 ), a thirty-sixth NMOS transistor (M 36 ), a thirty-seventh NMOS transistor (M 37 ), a thirty-eighth NMOS transistor (M 38 ), a thirty-ninth NMOS transistor (M 39 ), a fortieth NMOS transistor (M 40 ), a forty-first NMOS transistor (M 41 ), and a forty-second NMOS transistor (M 42 ); The multi-phase clock generation module generates six voltage signals V with different phases from the injection voltage signal of the external signal source inj,0 , V inj,60 , V inj,120 , V inj,180 , V inj,240 and V inj,300 , and connect them to the first input terminal (V inj,0 ), the second input terminal (V inj,60 ), the third input terminal (V inj,120 ), the fourth input terminal (V inj,180 ), the fifth input terminal (V inj,240 ) and the sixth input terminal (V inj,300 ); the source of the thirty-first NMOS transistor (M 31 ) is grounded, the gate of the thirty-first NMOS transistor (M 31 ) is connected to the first input terminal (V inj,0 ), the drain of the thirty-first NMOS transistor (M 31 ) is connected to the source of the thirty-fourth NMOS transistor (M 34 ), the source of the thirty-second NMOS transistor (M 32 ) is grounded, the gate of the thirty-second NMOS transistor (M 32 ) is connected to the third input terminal (V inj,120 ), the drain of the thirty-second NMOS transistor (M 32 ) is connected to the source of the thirty-fifth NMOS transistor (M 35 ), the source of the thirty-third NMOS transistor (M 33 ) is grounded, the gate of the thirty-third NMOS transistor (M 33 ) is connected to the fifth input terminal (V inj,240 ), the drain of the thirty-third NMOS transistor (M 33 ) is connected to the source of the thirty-sixth NMOS transistor (M 36 ), the source of the thirty-seventh NMOS transistor (M 37 ) is grounded, the gate of the thirty-seventh NMOS transistor (M 37 ) is connected to the second input terminal (V inj,60 ), the drain of the thirty-seventh NMOS transistor (M 37 ) is connected to the source of the fortieth NMOS transistor (M 40 ), the source of the thirty-eighth NMOS transistor (M 38 ) is grounded, the gate of the thirty-eighth NMOS transistor (M 38 ) is connected to the fourth input terminal (V inj,180 ), the drain of the thirty-eighth NMOS transistor (M 38 ) is connected to the source of the forty-first NMOS transistor (M 41 )is connected to the source of the thirty-ninth NMOS transistor (M 39 )has its source grounded, and the thirty-ninth NMOS transistor (M 39 )has its gate connected to the sixth input terminal (V inj,300 ), and the drain of the thirty-ninth NMOS transistor (M 39 )is connected to the source of the forty-second NMOS transistor (M 42 ). The drain of the thirty-fourth NMOS transistor (M 34 ), the drain of the thirty-fifth NMOS transistor (M 35 ), and the drain of the thirty-sixth NMOS transistor (M 36 )are all connected to one end of the fourth inductor (L4) and one end of the seventh capacitor (C7). The drain of the fortieth NMOS transistor (M 40 ), the drain of the forty-first NMOS transistor (M 41 ), and the drain of the forty-second NMOS transistor (M 42 )are all connected to one end of the third inductor (L3) and one end of the sixth capacitor (C6). The gates of the thirty-fourth NMOS transistor (M 34 ), the thirty-fifth NMOS transistor (M 35 ), the thirty-sixth NMOS transistor (M 36 ), the fortieth NMOS transistor (M 40 ), the forty-first NMOS transistor (M 41 ), and the forty-second NMOS transistor (M 42 )are all connected to the bias voltage input terminal (V B ); The multi-phase clock generation module includes: a first differential input terminal (V INJ,P ), a second differential input terminal (V INJ,N ), a first exclusive-OR gate (XOR1), a second exclusive-OR gate (XOR2), a current mirror, a first low-pass filter (1), a second low-pass filter (2), an operational amplifier, an injection-locked ring oscillator, a third resistor (R3), and a fourth resistor (R4); the injection-locked ring oscillator includes a third differential input terminal (V IP ), and a fourth differential input terminal (V IN ), and a first single-phase output terminal (CKR_0), a second single-phase output terminal (CKR_60), a third single-phase output terminal (CKR_120), a fourth single-phase output terminal (CKR_180), a fifth single-phase output terminal (CKR_240), and a sixth single-phase output terminal (CKR_300) that output to a multi-phase injection-locked frequency multiplier module; The first differential input terminal (V INJ,P ), and the second differential input terminal (V INJ,N ) are respectively connected to the first differential output port (V INJ,P ) and the second differential output port (V INJ,N ) of an external signal source; one end of a third resistor (R3) is connected to the first differential input terminal (V INJ,P ), and the other end is connected to the first output terminal of the current mirror and the third differential input terminal (V IP ); one end of a fourth resistor (R4) is connected to the second differential input terminal (V INJ,N ), and the other end is connected to the second output terminal of the current mirror and the fourth differential input terminal (V IN ); The output terminal of the first low-pass filter (1) is connected to the positive terminal of the operational amplifier. The input terminal of the first low-pass filter (1) is connected to the output terminal of the first exclusive-OR gate (XOR1). The two input terminals of the first exclusive-OR gate (XOR1) are respectively connected to the first single-phase output terminal (CKR_0) and the second single-phase output terminal (CKR_60). The output terminal of the second low-pass filter (2) is connected to the negative terminal of the operational amplifier. The input terminal of the second low-pass filter (2) is connected to the output terminal of the second exclusive-OR gate (XOR2). The two input terminals of the second exclusive-OR gate (XOR2) are respectively connected to the third single-phase output terminal (CKR_120) and the fourth single-phase output terminal (CKR_180). The output terminal (V ctrl ) of the operational amplifier is connected to the input terminal of the current mirror.

2. The low-noise broadband millimeter-wave frequency source based on multi-phase injection locking according to claim 1, wherein The multi-phase injection-locked frequency multiplier module further includes a twenty-ninth NMOS transistor (M 29 ), and a thirtieth NMOS transistor (M 30 ); the source of the twenty-ninth NMOS transistor (M 29 ) is grounded, the gate of the twenty-ninth NMOS transistor (M 29 ) is connected to the drain of the thirtieth NMOS transistor (M 30 ), one end of the second carrier signal output terminal (OUTN), one end of the eighth capacitor (C8), and one end of the sixth inductor (L6), the drain of the twenty-ninth NMOS transistor (M 29 ) is respectively connected to the gate of the thirtieth NMOS transistor (M 30 ), the first carrier signal output terminal (OUTP), the other end of the eighth capacitor (C8), and one end of the fifth inductor (L5), and the source of the thirtieth NMOS transistor (M 30 ) is grounded.

3. The low-noise broadband millimeter-wave frequency source based on multi-phase injection locking according to claim 1, characterized in that The first low-pass filter (1) includes a first capacitor (C1) and a first resistor (R1); one end of the first capacitor (C1) is grounded, the other end of the first capacitor (C1) is connected to the positive terminal of the operational amplifier and one end of the first resistor (R1), and the other end of the first resistor (R1) is connected to the output terminal of the first exclusive-OR gate (XOR1); The second low-pass filter (2) includes a second capacitor (C2) and a second resistor (R2); one end of the second capacitor (C2) is grounded, the other end of the second capacitor (C2) is connected to the negative terminal of the operational amplifier and one end of the second resistor (R2), and the other end of the second resistor (R2) is connected to the output terminal of the second exclusive-OR gate (XOR2).

4. The low-noise broadband millimeter-wave frequency source based on multi-phase injection locking according to claim 1, characterized in that The current mirror includes a first NMOS transistor (M1), a second NMOS transistor (M2), a third PMOS transistor (M3), and a fourth PMOS transistor (M4); the source of the first NMOS transistor (M1) is grounded, the gate of the first NMOS transistor (M1) is connected to the gate of the second NMOS transistor (M2), the drain of the first NMOS transistor (M1) is connected to the drain of the third PMOS transistor (M3), the drain of the first NMOS transistor (M1) is connected to its gate, the source of the second NMOS transistor (M2) is grounded, the drain of the second NMOS transistor (M2) is connected to the drain of the fourth PMOS transistor (M4), the source of the third PMOS transistor (M3) is connected to the high power supply voltage (VDDH), the gate of the third PMOS transistor (M3) is connected to the output terminal of the operational amplifier (V ctrl ), the source of the fourth PMOS transistor (M4) is connected to the high power supply voltage (VDDH), the drain of the fourth PMOS transistor (M4) is connected to its gate, the other end of the third resistor (R3) is connected to the gate of the fourth PMOS transistor (M4), and the other end of the fourth resistor (R4) is connected to the gate of the second NMOS transistor (M2).

5. The low-noise broadband millimeter-wave frequency source based on multi-phase injection locking according to claim 1, characterized in that The multi-phase clock generation module further includes a third capacitor (C3). One end of the third capacitor (C3) is connected to the output terminal (V ctrl ) of the operational amplifier, and the other end of the third capacitor (C3) is grounded.

6. The low-noise broadband millimeter-wave frequency source based on multi-phase injection locking according to claim 1, wherein The multi-phase clock generation module further includes a first buffer output (b0), a second buffer output (b1), a third buffer output (b2), a fourth buffer output (b3), a fifth buffer output (b4), a sixth buffer output (b5), a seventh buffer output (b6), an eighth buffer output (b7), a ninth buffer output (b8), a tenth buffer output (b9), an eleventh buffer output (b 10 ), and a twelfth buffer output (b 11 ); The first single-phase output terminal (CKR_0) is connected to the input terminals of the first buffer output (b0) and the seventh buffer output (b6). The second single-phase output terminal (CKR_60) is connected to the input terminals of the second buffer output (b1) and the eighth buffer output (b7). The third single-phase output terminal (CKR_120) is connected to the input terminals of the third buffer output (b2) and the ninth buffer output (b8). The fourth single-phase output terminal (CKR_180) is connected to the input terminals of the fourth buffer output (b3) and the tenth buffer output (b9). The fifth single-phase output terminal (CKR_240) is connected to the input terminals of the fifth buffer output (b4) and the eleventh buffer output (b 10 ). The sixth single-phase output terminal (CKR_300) is connected to the input terminals of the sixth buffer output (b5) and the twelfth buffer output (b 11 ). The output terminals of the first buffer output (b0) and the second buffer output (b1) are respectively connected to the two input terminals of the first exclusive-OR gate (XOR1). The output terminals of the third buffer output (b2) and the fourth buffer output (b3) are respectively connected to the two input terminals of the second exclusive-OR gate (XOR2). The output terminal of the fifth buffer output (b4) is floating. The output terminal of the sixth buffer output (b5) is floating. The output terminals of the seventh buffer output (b6), the eighth buffer output (b7), the ninth buffer output (b8), the tenth buffer output (b9), the eleventh buffer output (b 10 ), and the output terminal of the twelfth buffer output (b 11 ) are correspondingly connected to the six input terminals of the multi-phase injection-locked frequency multiplier module.

7. The low-noise broadband millimeter-wave frequency source based on multi-phase injection locking according to claim 1, wherein The described injection-locked ring oscillator further includes a first inverter (Lat1), a second inverter (Lat2), a third inverter (Lat3), a fourth inverter (Lat4), a fifth inverter (Lat5), a sixth inverter (Lat6), a fifth NMOS transistor (M5), a sixth NMOS transistor (M6), a seventh PMOS transistor (M7), an eighth PMOS transistor (M8), a ninth NMOS transistor (M9), a tenth NMOS transistor (M 10 ), an eleventh PMOS transistor (M 11 ), a twelfth PMOS transistor (M 12 ), a thirteenth NMOS transistor (M 13 ), a fourteenth NMOS transistor (M 14 ), a fifteenth PMOS transistor (M 15 ), a sixteenth PMOS transistor (M 16 ), a seventeenth NMOS transistor (M 17 ), an eighteenth NMOS transistor (M 18 ), a nineteenth PMOS transistor (M 19 ), a twentieth PMOS transistor (M 20 ), a twenty-first NMOS transistor (M 21 ), a twenty-second NMOS transistor (M 22 ), a twenty-third PMOS transistor (M 23 ), a twenty-fourth PMOS transistor (M 24 ), a twenty-fifth NMOS transistor (M 25 ), a twenty-sixth NMOS transistor (M 26 ), a twenty-seventh PMOS transistor (M 27 ), a twenty-eighth PMOS transistor (M 28 ); The source of the fifth NMOS transistor (M5) is grounded. The drain of the fifth NMOS transistor (M5) is connected to the source of the sixth NMOS transistor (M6). The drain of the sixth NMOS transistor (M6) is connected to the drain of the seventh PMOS transistor (M7), the output terminal of the first inverter (Lat1), the input terminal of the second inverter (Lat2), and the first single-phase output terminal (CKR_0). The gate of the sixth NMOS transistor (M6) is connected to the gate of the seventh PMOS transistor (M7) and the drain of the fourteenth NMOS transistor (M 14 ). The source of the seventh PMOS transistor (M7) is connected to the drain of the eighth PMOS transistor (M8). The source of the eighth PMOS transistor (M8) is connected to the high power supply voltage (VDDH). The source of the ninth NMOS transistor (M9) is grounded. The drain of the ninth NMOS transistor (M9) is connected to the source of the tenth NMOS transistor (M 10 ). The gate of the tenth NMOS transistor (M 10 is connected to the gate of the eleventh PMOS transistor (M 11 and the drain of the sixth NMOS transistor (M6). The drain of the tenth NMOS transistor (M 10 is connected to the drain of the eleventh PMOS transistor (M 11 ), the output terminal of the third inverter (Lat3), the input terminal of the fourth inverter (Lat4), and the fifth single-phase output terminal (CKR_240). The source of the eleventh PMOS transistor (M 11 is connected to the drain of the twelfth PMOS transistor (M 12 ). The source of the twelfth PMOS transistor (M 12 is connected to the high power supply voltage (VDDH). The source of the thirteenth NMOS transistor (M 13 is grounded. The drain of the thirteenth NMOS transistor (M 13 is connected to the source of the fourteenth NMOS transistor (M 14 ). The drain of the fourteenth NMOS transistor (M 14 is connected to the drain of the fifteenth PMOS transistor (M 15 ), the output terminal of the fifth inverter (Lat5), the input terminal of the sixth inverter (Lat6), and the third single-phase output terminal (CKR_120). The gate of the fourteenth NMOS transistor (M 14 is connected to the gate of the fifteenth PMOS transistor (M 15 and the drain of the tenth NMOS transistor (M 10 ). The source of the fifteenth PMOS transistor (M 15 is connected to the drain of the sixteenth PMOS transistor (M 16 ). The source of the sixteenth PMOS transistor (M 16 is connected to the high power supply voltage (VDDH). The source of the seventeenth NMOS transistor (M 17 The source of the seventeenth NMOS transistor (M 17 is grounded, and the drain of the seventeenth NMOS transistor (M 18 is connected to the source of the eighteenth NMOS transistor (M 18 ), and the gate of the eighteenth NMOS transistor (M 19 is connected to the gate of the nineteenth PMOS transistor (M 26 and the drain of the twenty-sixth NMOS transistor (M 18 ), and the drain of the eighteenth NMOS transistor (M 19 is connected to the drain of the nineteenth PMOS transistor (M 19 ), the input terminal of the first inverter (Lat1), the output terminal of the second inverter (Lat2), and the fourth single-phase output terminal (CKR_180). The source of the nineteenth PMOS transistor (M 20 is connected to the drain of the twentieth PMOS transistor (M 20 ), the source of the twentieth PMOS transistor (M 21 is connected to the high power supply voltage (VDDH), the source of the twenty-first NMOS transistor (M 21 is grounded, the drain of the twenty-first NMOS transistor (M 22 is connected to the source of the twenty-second NMOS transistor (M 22 ), the gate of the twenty-second NMOS transistor (M 23 is connected to the gate of the twenty-third PMOS transistor (M 18 and the drain of the eighteenth NMOS transistor (M 22 ), the drain of the twenty-second NMOS transistor (M 23 is connected to the drain of the twenty-third PMOS transistor (M 23 ), the input terminal of the third inverter (Lat3), the output terminal of the fourth inverter (Lat4), and the second single-phase output terminal (CKR_60). The source of the twenty-third PMOS transistor (M 24 is connected to the drain of the twenty-fourth PMOS transistor (M 24 ), the source of the twenty-fourth PMOS transistor (M 25 is connected to the high power supply voltage (VDDH), the source of the twenty-fifth NMOS transistor (M 25 is grounded, the drain of the twenty-fifth NMOS transistor (M 26 is connected to the source of the twenty-sixth NMOS transistor (M 26 ), the gate of the twenty-sixth NMOS transistor (M 27 is connected to the gate of the twenty-seventh PMOS transistor (M 22 and the drain of the twenty-second NMOS transistor (M 26 ), and the drain of the twenty-sixth NMOS transistor (M 27 The drain of (), the input terminal of the fifth inverter (Lat5), the output terminal of the sixth inverter (Lat6), and the sixth single-phase output terminal (CKR_300) are connected. The source of the twenty-seventh PMOS transistor (M 27 is connected to the source of the twenty-eighth PMOS transistor (M 28 ), and the drain of the twenty-eighth PMOS transistor (M 28 is connected to the high power supply voltage (VDDH). The gates of the fifth NMOS transistor (M5), the ninth NMOS transistor (M9), the thirteenth NMOS transistor (M 13 ), the seventeenth NMOS transistor (M 17 ), the twenty-first NMOS transistor (M 21 ), and the twenty-fifth NMOS transistor (M 25 ) are all connected to the fourth differential input terminal (V IN ). The gates of the eighth PMOS transistor (M8), the twelfth PMOS transistor (M 12 ), the sixteenth PMOS transistor (M 16 ), the twentieth PMOS transistor (M 20 ), the twenty-fourth PMOS transistor (M 24 ), and the twenty-eighth PMOS transistor (M 28 ) are all connected to the third differential input terminal (V IP ).

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