A new low-power high-image-rejection active CMOS complex filter circuit

Abstract

The application discloses a novel low-power high-image-rejection active CMOS complex filter circuit, comprising a notch filter circuit, a biquadratic low-pass filter circuit, a linear frequency shift circuit, an I-channel differential input voltage end, an I-channel differential output end, a Q-channel differential input voltage end and a Q-channel differential output end, and the complex notch filter technology is introduced on the basis of the complex band-pass filter, so that the effects of notch filtering at the image signal frequency point and band-pass filtering at the useful signal frequency point are realized; compared with the existing complex band-pass filter, the application has the frequency selection ability at the useful signal frequency point and can have a good image rejection effect under a single-stage circuit structure without increasing the circuit area and power consumption, so that the multi-stage cascade form is avoided, and the total power consumption and area loss of the circuit are greatly reduced, and the quadrature mismatch problem is also avoided. In addition, the complex filter can also be used in other low intermediate frequency receivers, and is suitable for a wide range of applications.

Description

Technical Field

[0001] This invention belongs to the field of radio frequency receiver technology, specifically relating to a novel low-power high image rejection active CMOS complex filter circuit. Background Technology

[0002] Currently, there are three main architectures used in RF receiver chips: superheterodyne, zero-IF, and low-IF. Superheterodyne cannot be fully integrated onto the chip, typically requiring off-chip filters and consuming significant power, making it unsuitable for miniaturized, low-power applications. Zero-IF architecture can be used for miniaturized applications, but suffers from DC offset and low linearity, making it unsuitable for systems with high linearity requirements. Low-IF architecture can also be used for miniaturized applications and offers good system performance in terms of power consumption and linearity, making it more suitable for RF receiver chips compared to the other two architectures.

[0003] Image rejection filters play a crucial role in low-IF RF receivers by suppressing image signals and improving the signal-to-noise ratio. Image rejection filters are generally divided into passive and active types, with active image rejection filters being more widely used due to their advantages such as low power consumption, small area, and high image rejection. In related technologies, most circuit designs employ active image rejection filters, such as complex notch filters or complex bandpass filters. However, complex notch filters cannot provide bandpass filtering at the desired signal frequency, thus requiring cascaded bandpass filters. While complex bandpass filters can provide bandpass filtering at the desired signal frequency, achieving good image rejection still requires a cascaded structure, which leads to problems such as high power consumption, large area loss, and orthogonal mismatch resulting in deteriorated image rejection. Summary of the Invention

[0004] To address the aforementioned problems in the prior art, this invention provides a novel low-power, high image rejection active CMOS complex filter circuit. The technical problem to be solved by this invention is achieved through the following technical solution:

[0005] This invention provides a novel low-power, high-image-suppression active CMOS complex filter circuit, comprising: a notch filter circuit, a dual second-order low-pass filter circuit, a linear frequency shift circuit, an I-path differential input voltage terminal, an I-path differential output terminal, a Q-path differential input voltage terminal, and a Q-path differential output terminal. The dual second-order low-pass filter circuit includes an I-path dual second-order low-pass filter circuit and a Q-path dual second-order low-pass filter circuit.

[0006] The differential input voltage terminal of the notch filter circuit is connected to the differential input voltage terminal of the I-path and the differential input voltage terminal of the Q-path, respectively. The differential current output terminal of the I-path of the notch filter circuit is connected in phase with the differential input current terminal of the I-path dual second-order low-pass filter circuit. The differential current output terminal of the Q-path of the notch filter circuit is connected in reverse phase with the differential input current terminal of the Q-path dual second-order low-pass filter circuit.

[0007] Both the I-path dual second-order low-pass filter circuit and the Q-path dual second-order low-pass filter circuit include a first node and a second node, and both the first node and the second node are connected to the linear frequency shift circuit; the differential output terminals of the dual second-order low-pass filter circuits are the I-path differential output terminal and the Q-path differential output terminal.

[0008] In one embodiment of the present invention, the I-path differential input voltage terminal includes an input voltage terminal V. II_P and input voltage terminal V II_N The Q-path differential input voltage terminal includes an input voltage terminal V. IQ_P and input voltage terminal V IQ_N ;

[0009] The input voltage terminal V II_P The phase of the input voltage terminal V II_N The phase difference is 180°, and the input voltage terminal V IQ_P The phase of the input voltage terminal V IQ_N The phase difference is 180°, and the input voltage terminal V II_P The phase of the input voltage terminal V IQ_P The phase difference is 90°, and the input voltage terminal V II_N The phase of the input voltage terminal V IQ_N The phase difference is 90°.

[0010] In one embodiment of the present invention, the notch filter circuit further includes: a high-pass low-pass transconductance stage, an I-path differential current output terminal, and a Q-path differential current output terminal, wherein the high-pass low-pass transconductance stage includes an I-path high-pass low-pass transconductance stage and a Q-path high-pass low-pass transconductance stage; wherein...

[0011] The differential input voltage terminal of the high-pass low-pass transconductance stage includes a differential voltage positive input terminal +V and a differential voltage negative input terminal -V. The differential input voltage terminal of the I-path high-pass low-pass transconductance stage is connected to the I-path differential input voltage terminal, and the differential input voltage terminal of the Q-path high-pass low-pass transconductance stage is connected to the Q-path differential input voltage terminal.

[0012] The differential current output terminal of the high-pass and low-pass transconductance stage includes a high-pass differential current positive output terminal +I. HHigh-pass differential current negative output terminal -I H Low-pass differential current positive output terminal +I L and low-pass differential current negative output terminal -I L The low-pass differential current positive output terminal +I of the I-path high-pass and low-pass transconductance stage L The high-pass differential current negative output terminal -I of the Q-path high-pass low-pass transconductance stage H The circuit is connected via a first preset node, which serves as the positive terminal of the differential current output of the I-path; the low-pass differential current negative output terminal of the high-pass and low-pass transconductance stages of the I-path is I... L The positive output terminal of the high-pass differential current of the Q-path high-pass and low-pass transconductance stage is +I. H The circuit is connected via a second preset node, which serves as the negative terminal of the differential current output of the I-path; the high-pass differential current positive output terminal of the high-pass and low-pass transconductance stages of the I-path is +I. H The low-pass differential current positive output terminal +I of the Q-path high-pass and low-pass transconductance stage is connected to the aforementioned Q-path. L The connection is made through a third preset node, which serves as the positive terminal of the differential current output of the Q-path; the negative terminal of the high-pass differential current of the I-path high-pass and low-pass transconductance stage is -I. H The low-pass differential current negative output terminal -I of the Q-path high-pass and low-pass transconductance stage. L The connection is made through a fourth preset node, which serves as the negative terminal of the differential current output terminal of the Q-path.

[0013] In one embodiment of the present invention, the I-channel dual second-order low-pass filter circuit includes: transconductors OTA1, OTA2, OTA3, and load capacitor C. L1 C L2 C L3 C L4 I-path differential input current terminal and I-path differential output voltage terminal;

[0014] The differential input current terminals of the I-path are connected in phase with the input terminals of OTA1 and OTA3, respectively. The output terminal of OTA1 is connected in reverse phase with the input terminal of OTA2, the output terminal of OTA2 is connected in phase with the input terminal of OTA1, and the output terminal of OTA3 is connected in reverse phase with the input terminal of OTA3. The second node of the I-path dual second-order low-pass filter circuit is the differential output voltage terminal of the I-path. L1 C L2 The upper electrode is connected to the first node of the I-channel dual second-order low-pass filter circuit, and the lower electrode is grounded; C L3 C L4 The upper electrode is connected to the second node of the I-channel dual second-order low-pass filter circuit, and the lower electrode is grounded.

[0015] In one embodiment of the present invention, the Q-path dual second-order low-pass filter circuit includes: transconductors OTA6, OTA7, and OTA8, and a load capacitor C. L5 C L6 C L7 C L8 Q-path differential input current terminal and Q-path differential output voltage terminal;

[0016] The differential input current terminals of the Q-path are connected in phase with the input terminals of OTA6 and OTA8, respectively. The output terminal of OTA6 is connected in reverse phase with the input terminal of OTA7, the output terminal of OTA7 is connected in phase with the input terminal of OTA6, and the output terminal of OTA8 is connected in reverse phase with the input terminal of OTA8. The second node of the dual second-order low-pass filter circuit of the Q-path is the differential output voltage terminal of the Q-path; C L5 C L6 The upper electrode is connected to the first node of the Q-path dual second-order low-pass filter circuit, and the lower electrode is grounded; C L7 C L8 The upper electrode is connected to the second node of the Q-path dual second-order low-pass filter circuit, and the lower electrode is grounded.

[0017] In one embodiment of the present invention, the phase of the Q-path differential input current terminal is 90° out of phase with the phase of the I-path differential input current terminal.

[0018] In one embodiment of the present invention, the linear frequency shift circuit includes transconductors OTA4, OTA5, OTA9, and OTA1. 10 ;

[0019] Specifically, the differential input terminal of OTA4 is connected in phase with the first node of the I-channel dual second-order low-pass filter circuit and in reverse phase with the differential output terminal of OTA9. The differential output terminal of OTA4 is connected in phase with the first node of the Q-channel dual second-order low-pass filter circuit and the differential input terminal of OTA9. The differential input terminal of OTA5 is connected in phase with the second node of the I-channel dual second-order low-pass filter circuit and the differential output terminal of OTA9. 10 The differential output terminals are connected in reverse phase; the differential output terminals of OTA5 are respectively connected to the second node of the Q-path dual second-order low-pass filter circuit and OTA. 10 The differential input terminals are connected in phase.

[0020] In one embodiment of the present invention, the I-channel high-pass and low-pass transconductance stage includes transistors: M1, M2, M3, M4, M5, M6, M7, M8, M9, M1... 10 M 11 M 12 M 13 M 14M 15 and M 16 Load capacitance: C H1 C H2 I-path differential input voltage terminal, I-path differential current output terminal, bias voltage input terminal V B V b and power supply voltage V DD ;in,

[0021] The gates of M1, M3, and M6 are connected to the positive terminal of the differential input voltage terminal of the I-path; the gates of M2, M4, and M5 are connected to the negative terminal of the differential input voltage terminal of the I-path; M7, M8, M9, and M 10 M 11 and M 12 The gate is connected to the bias voltage input terminal V. B M 13 M 14 M 15 and M 16 The gate is connected to the bias voltage input terminal V. b The source of M1 is connected to the drain of M7 and the C1 electrode, respectively. H1 The upper plate of M2 is connected, and the source of M2 is connected to the drain of M8 and the C plate. H1 The lower plate is connected, and the source of M3 is connected to the drain of M9 and the C plate, respectively. H2 The upper plate of M4 is connected, and the source of M4 is connected to M5 respectively. 10 The drain and C H2 The lower electrode is connected, and the source of M5 is connected to the source of M6 and M... 11 M 12 Drain connection; M7, M8, M9, M 10 M 11 and M 12 The source is grounded, M 13 M 14 M 15 and M 16 The source of the power supply voltage V DD Connections: The drain of M3 is connected to the drain of M5, and the drain of M4 is connected to the drain of M6; M 13 The drain of M is connected to the positive terminal of the differential current output terminal of the I-path of the notch filter circuit. 14 The drain of M is connected to the negative terminal of the differential current output terminal of the I-path of the notch filter circuit. 15 The drain of M is connected to the positive terminal of the Q-path differential current output terminal of the notch filter circuit. 16 The drain of the filter is connected to the negative terminal of the Q-path differential current output terminal of the notch filter circuit.

[0022] In one embodiment of the present invention, transconductors OTA1, OTA2, OTA3, OTA4, OTA5, OTA6, OTA7, OTA8, OTA9, and OTA 10 The structures are the same.

[0023] In one embodiment of the present invention, OTA1 includes a transistor: M 17 M 18 M 19 M 20 and M 21 First differential input voltage terminal, first differential current output terminal, bias voltage input terminal V′ B V′ b and power supply voltage V DD ;in,

[0024] M 17 The gate of M is connected to the positive terminal of the first differential input voltage terminal. 18 The gate of M is connected to the negative terminal of the first differential input voltage terminal; 19 M 20 The gate and the bias voltage input terminal V′ b Connection, M 21 The gate and the bias voltage input terminal V′ B Connection, M 17 The source poles are respectively with M 18 The source and M 21 Drain connection; M 19 M 20 The source of the power supply voltage V DD Connection, M 21 The source is grounded, M 17 The drain is connected to M through the fifth preset node. 19 The drain of the first differential current output terminal, the fifth preset node, serves as the negative terminal -I. O M 18 The drain is connected to M through the sixth preset node. 20 The drain of the first differential current output terminal, the sixth preset node, serves as the positive terminal +I. O .

[0025] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0026] This invention provides a novel low-power, high-image-suppression active CMOS complex filter circuit, comprising: a notch filter circuit, a dual second-order low-pass filter circuit, a linear frequency shift circuit, an I-path differential input voltage terminal, an I-path differential output terminal, a Q-path differential input voltage terminal, and a Q-path differential output terminal. By introducing complex notch filtering technology into the existing complex bandpass filter, it achieves the effect of notching at the image signal frequency and bandpassing at the useful signal frequency. Compared with the complex bandpass filters in the prior art, this invention, without increasing the circuit area and power consumption, has both the ability to select frequencies at the useful signal frequency and a good image suppression effect in a single-stage circuit structure, avoiding the multi-stage cascaded form, thereby greatly reducing the total power consumption and area loss of the circuit, and also avoiding the problem of quadrature mismatch.

[0027] Furthermore, the complex filter proposed in this invention can also be used in other low-IF receivers, making it widely applicable.

[0028] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0029] Figure 1 This is a schematic diagram of the structure of an active CMOS complex bandpass filter circuit in the prior art;

[0030] Figure 2 This is a schematic diagram of a novel low-power high image suppression active CMOS complex filter circuit provided in an embodiment of the present invention;

[0031] Figure 3 This is a circuit diagram of a high-pass and low-pass transconductance stage in a novel low-power high image suppression active CMOS complex filter circuit provided in this embodiment of the invention;

[0032] Figure 4 This is a circuit diagram of the transconductor OTA1 in the novel low-power high image rejection active CMOS complex filter circuit provided in this embodiment of the invention;

[0033] Figure 5 This is a schematic diagram illustrating the theoretical analysis results of the novel low-power high image suppression active CMOS complex filter circuit provided in this embodiment of the invention. Detailed Implementation

[0034] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0035] Figure 1 This is a schematic diagram of an existing active CMOS complex bandpass filter circuit. Please refer to [link / reference]. Figure 1Complex bandpass filters first convert the input voltage signal into a current signal through a transconductor, and then use a bandpass filter circuit to achieve image filtering. However, the image rejection of existing complex filters is relatively low, so multiple stages are usually cascaded to improve image rejection. This process increases the power consumption and area of ​​the complex filter; in addition, there is the problem of quadrature mismatch, which further weakens the image rejection effect.

[0036] In view of this, the present invention provides a novel low-power, high image suppression active CMOS complex filter circuit.

[0037] Figure 2 This is a schematic diagram of a novel low-power, high image suppression active CMOS complex filter circuit provided in an embodiment of the present invention. Figure 2 As shown, this embodiment of the invention provides a novel low-power, high image rejection active CMOS complex filter circuit, comprising: a notch filter circuit, a dual second-order low-pass filter circuit, a linear frequency shift circuit, an I-path differential input voltage terminal, an I-path differential output terminal, a Q-path differential input voltage terminal, and a Q-path differential output terminal. The dual second-order low-pass filter circuit includes: an I-path dual second-order low-pass filter circuit and a Q-path dual second-order low-pass filter circuit; wherein,

[0038] The differential input voltage terminals of the notch filter circuit are connected to the differential input voltage terminals of the I-path and the Q-path respectively. The differential current output terminal of the I-path of the notch filter circuit is connected in phase with the differential input current terminal of the I-path dual second-order low-pass filter circuit. The differential current output terminal of the Q-path of the notch filter circuit is connected in reverse phase with the differential input current terminal of the Q-path dual second-order low-pass filter circuit.

[0039] Both the I-path dual second-order low-pass filter circuit and the Q-path dual second-order low-pass filter circuit include a first node and a second node. The first node N1 and the second node N2 are both connected to the linear frequency shift circuit. The differential output terminals of the dual second-order low-pass filter circuit are the I-path differential output terminal and the Q-path differential output terminal.

[0040] Optionally, the I-path differential input voltage terminal includes an input voltage terminal V. II_P and input voltage terminal V II_N The Q-path differential input voltage terminal includes the input voltage terminal V. IQ_P and input voltage terminal V IQ_N ;

[0041] Input voltage terminal V II_P The phase of the input voltage terminal V II_N The phase difference is 180°, and the input voltage terminal V IQ_P The phase of the input voltage terminal V IQ_N The phase difference is 180°, and the input voltage terminal V II_PThe phase of the input voltage terminal V IQ_P The phase difference is 90°, and the input voltage terminal V II_N The phase of the input voltage terminal V IQ_N The phase difference is 90°.

[0042] Optionally, the I-path dual second-order low-pass filter circuit includes: transconductors OTA1, OTA2, OTA3, and load capacitor C. L1 C L2 C L3 C L4 I-path differential input current terminal and I-path differential output voltage terminal;

[0043] The differential input current terminals of the I-path are connected in phase with the input terminals of OTA1 and OTA3, respectively. The output terminal of OTA1 is connected out of phase with the input terminal of OTA2, the output terminal of OTA2 is connected in phase with the input terminal of OTA1, and the output terminal of OTA3 is connected out of phase with the input terminal of OTA3. The second node N2 of the I-path dual second-order low-pass filter circuit is the differential output voltage terminal of the I-path. L1 C L2 The upper electrode is connected to the first node N1 of the I-path dual second-order low-pass filter circuit, and the lower electrode is grounded; C L3 C L4 The upper electrode is connected to the second node N2 of the I-channel dual second-order low-pass filter circuit, and the lower electrode is grounded.

[0044] It should be noted that in this embodiment, the input terminal of the transconductor OTA1 is denoted as the first node of the I-path dual second-order low-pass filter circuit, and the output terminal of the transconductor OTA1 is denoted as the second node of the I-path dual second-order low-pass filter circuit.

[0045] Optionally, the Q-path dual second-order low-pass filter circuit includes: transconductors OTA6, OTA7, and OTA8, and load capacitor C. L5 C L6 C L7 C L8 Q-path differential input current terminal and Q-path differential output voltage terminal;

[0046] The differential input current terminals of the Q-path are connected in phase with the input terminals of OTA6 and OTA8, respectively. The output terminal of OTA6 is connected out of phase with the input terminal of OTA7, the output terminal of OTA7 is connected in phase with the input terminal of OTA6, and the output terminal of OTA8 is connected out of phase with the input terminal of OTA8. The second node N2 of the Q-path dual second-order low-pass filter circuit is the differential output voltage terminal of the Q-path. L5 C L6 The upper electrode is connected to the first node N1 of the Q-path dual second-order low-pass filter circuit, and the lower electrode is grounded; C L7 CL8 The upper electrode is connected to the second node N2 of the Q-path dual second-order low-pass filter circuit, and the lower electrode is grounded.

[0047] It should be noted that in this embodiment, the phase of the differential input current terminal of the Q-path is 90° different from the phase of the differential input current terminal of the I-path. The input terminal of the transconductor OTA6 is denoted as the first node of the Q-path dual second-order low-pass filter circuit, and the output terminal of the transconductor OTA6 is denoted as the second node of the Q-path dual second-order low-pass filter circuit.

[0048] Figure 3 This is a circuit diagram of a high-pass and low-pass transconductance stage in a novel low-power, high image suppression active CMOS complex filter circuit provided in this embodiment of the invention. Please refer to... Figure 2-3 The notch filter circuit also includes: a high-pass and a low-pass transconductance stage g. mHL I-path differential current output terminal and Q-path differential current output terminal, high-pass low-pass transconductance stage g mHL This includes I-channel high-pass and low-pass transconductance stages and Q-channel high-pass and low-pass transconductance stages; among which,

[0049] The differential input voltage terminals of the high-pass and low-pass transconductance stages include the differential voltage positive input terminal +V. I and differential voltage negative input terminal -V I The differential input voltage terminal of the I-path high-pass low-pass transconductance stage is connected to the differential input voltage terminal of the I-path, and the differential input voltage terminal of the Q-path high-pass low-pass transconductance stage is connected to the differential input voltage terminal of the Q-path.

[0050] The differential current output terminals of the high-pass and low-pass transconductance stages include the high-pass differential current positive output terminal +I. H High-pass differential current negative output terminal -I H Low-pass differential current positive output terminal +I L and low-pass differential current negative output terminal -I L The positive output terminal of the low-pass differential current of the I-path high-pass and low-pass transconductance stage is +I. L The high-pass differential current negative output terminal -I of the Q-path high-pass and low-pass transconductance stage H The first preset node is connected and serves as the positive terminal of the differential current output terminal of the I-path; the low-pass differential current negative output terminal of the high-pass and low-pass transconductance stages of the I-path is I... L The high-pass differential current positive output terminal +I of the Q-path high-pass and low-pass transconductance stage H The second preset node is connected and serves as the negative terminal of the differential current output of the I-path; the positive terminal of the high-pass differential current of the I-path high-pass and low-pass transconductance stage is +I. H The low-pass differential current positive output terminal +I of the Q-path high-pass and low-pass transconductance stage LThe third preset node is connected and serves as the positive terminal of the differential current output of the Q-path; the high-pass differential current negative output terminal of the I-path high-pass and low-pass transconductance stage is I. H The low-pass differential current negative output terminal -I of the Q-path high-pass and low-pass transconductance stage L The connection is made through the fourth preset node, which serves as the negative terminal of the Q-path differential current output.

[0051] like Figure 3 As shown, the I-channel high-pass and low-pass transconductance stages include transistors: M1, M2, M3, M4, M5, M6, M7, M8, M9, M... 10 M 11 M 12 M 13 M 14 M 15 and M 16 Load capacitance: C H1 C H2 I-path differential input voltage terminal, I-path differential current output terminal, bias voltage input terminal V B V b and power supply voltage V DD ;in,

[0052] The gates of M1, M3, and M6 are connected to the positive terminal of the differential input voltage terminal of the I-path; the gates of M2, M4, and M5 are connected to the negative terminal of the differential input voltage terminal of the I-path; M7, M8, M9, and M 10 M 11 and M 12 The gate is connected to the bias voltage input terminal V. B M 13 M 14 M 15 and M 16 The gate is connected to the bias voltage input terminal V. b The source of M1 is connected to the drain of M7 and the C1 electrode, respectively. H1 The upper plate of M2 is connected, and the source of M2 is connected to the drain of M8 and the C plate. H1 The lower plate is connected, and the source of M3 is connected to the drain of M9 and the C plate, respectively. H2 The upper plate of M4 is connected, and the source of M4 is connected to M5 respectively. 10 The drain and C H2 The lower electrode is connected, and the source of M5 is connected to the source of M6 and M... 11 M 12 Drain connection; M7, M8, M9, M 10 M 11 and M 12 The source is grounded, M 13 M 14 M 15 and M16 The source and power supply voltage V DD Connections: The drain of M3 is connected to the drain of M5, and the drain of M4 is connected to the drain of M6; M 13 The drain of M is connected to the positive terminal of the differential current output terminal of the I-path of the notch filter circuit. 14 The drain of M is connected to the negative terminal of the differential current output terminal of the I-path of the notch filter circuit. 15 The drain of M is connected to the positive terminal of the Q-path differential current output of the notch filter circuit. 16 The drain of the filter is connected to the negative terminal of the Q-path differential current output of the notch filter circuit.

[0053] It should be understood that the drain output of M1 and M2 is a high-pass differential current -I H and+I H M5's drain output low-pass differential current +I L The drain output of M6 has a low-pass differential current -I L .

[0054] Furthermore, in the novel low-power high image suppression active CMOS complex filter circuit provided by this invention, the Q-path high-pass and low-pass transconductance stage structures are the same, so they will not be described again here.

[0055] Please continue reading Figure 2 The linear frequency shift circuit includes transconductors OTA4, OTA5, OTA9, and OTA2. 10 ;

[0056] Specifically, the differential input terminal of OTA4 is connected in phase with the first node N1 of the I-channel dual second-order low-pass filter circuit and in phase with the differential output terminal of OTA9. The differential output terminal of OTA4 is connected in phase with the first node N1 of the Q-channel dual second-order low-pass filter circuit and the differential input terminal of OTA9. The differential input terminal of OTA5 is connected in phase with the second node N2 of the I-channel dual second-order low-pass filter circuit and in phase with the differential output terminal of OTA9. 10 The differential output terminals are connected in reverse; the differential output terminals of OTA5 are respectively connected to the second node N2 of the Q-path dual second-order low-pass filter circuit and OTA. 10 The differential input terminals are connected in phase.

[0057] Figure 4 This is a circuit diagram of the transconductor OTA1 in a novel low-power, high image suppression active CMOS complex filter circuit provided in an embodiment of the present invention. Figure 4 As shown, OTA1 includes transistors: M 17 M 18 M 19 M 20 and M 21First differential input voltage terminal, first differential current output terminal, bias voltage input terminal V′ B V′ b and power supply voltage V DD ;in,

[0058] M 17 The gate of M is connected to the positive terminal of the first differential input voltage terminal. 18 The gate of M is connected to the negative terminal of the first differential input voltage terminal; 19 M 20 The gate and the bias voltage input terminal V′ b Connection, M 21 The gate and the bias voltage input terminal V′ B Connection, M 17 The source poles are respectively with M 18 The source and M 21 Drain connection; M 19 M 20 The source of the power supply voltage VD D Connection, M 21 The source is grounded, M 17 The drain is connected to M through the fifth preset node. 19 The drain of the first differential current output terminal, the fifth preset node, serves as the negative terminal -I. O M 18 The drain is connected to M through the sixth preset node. 20 The drain of the first differential current output terminal, the sixth preset node, serves as the positive terminal +I. O .

[0059] It should be noted that in this embodiment, transconductors OTA2, OTA3, OTA4, OTA5, OTA6, OTA7, OTA8, OTA9 and OTA 10 All of them have the same structure as the transconductor OTA1, so they will not be described in detail here.

[0060] Furthermore, the transfer function of the complex filter implementing the present invention can be expressed as:

[0061]

[0062] in,

[0063] Specifically, the transfer function can be viewed as the product of two terms: the first term represents the transfer function of the complex notch filter, and the second term represents the transfer function of the complex bandpass filter. In the first term, A... L A H and ω L ω HThese are the gain and pole frequencies of the first-order low-pass filter and the first-order high-pass filter, respectively. In a low-IF receiver, the image signal and the useful signal are downconverted by a quadrature local oscillator into two signals with the same frequency but opposite sequences: a positive frequency signal and a negative frequency signal. The image signal and the useful signal are displayed as differential and quadrature phase signals. From the transfer function, we know that the useful negative frequency signal (s=-jω) p The frequency falls within the passband of the notch filter, while the positive frequency (s=jω) p The image signal is suppressed. If the gain and pole frequencies of the low-pass and high-pass filters are perfectly matched, the useful signal and the image signal are suppressed at ω. p The gains at the locations are respectively And 0, meaning the notch filter circuit completely rejects the image signal. In the latter term, is a typical second-order low-pass filter that is first shifted to the right by ωI in the complex frequency domain. F The second-order low-pass filter is obtained by inverting the input. It is frequency-shifted ω to the right in the complex frequency domain. IF A bandpass filter is obtained with a center frequency of ω. IF Thus, the useful signal with positive frequency (s=jω) p The frequency falls within the passband of the bandpass filter, while the negative frequency (s=-jω) p The image signal is suppressed. From the above analysis, it can be seen that the notch filter circuit and the bandpass filter circuit have different passbands, located at the negative frequency and the positive frequency respectively. Therefore, by inverting the input of the bandpass filter circuit, the useful signal falls within the passbands of both filter circuits, while the image signal is always suppressed. If ω L ω H and ω IF A perfect match, meaning they are completely identical, results in the best image suppression effect, where the complex filter completely rejects the image signal.

[0064] Figure 5 This is a schematic diagram illustrating the theoretical analysis results of the novel low-power, high image suppression active CMOS complex filter circuit provided in this embodiment of the invention. Please refer to... Figure 5 The image suppression effect of the filter circuit provided by the present invention is significantly improved compared with the traditional complex bandpass filter.

[0065] As can be seen from the above embodiments, the beneficial effects of the present invention are as follows:

[0066] This invention provides a novel low-power, high-image-suppression active CMOS complex filter circuit, comprising: a notch filter circuit, a dual second-order low-pass filter circuit, a linear frequency shift circuit, an I-path differential input voltage terminal, an I-path differential output terminal, a Q-path differential input voltage terminal, and a Q-path differential output terminal. By introducing complex notch filtering technology into the existing complex bandpass filter, it achieves the effect of notching at the image signal frequency and bandpassing at the useful signal frequency. Compared with the complex bandpass filters in the prior art, this invention, without increasing the circuit area and power consumption, has both the ability to select frequencies at the useful signal frequency and a good image suppression effect in a single-stage circuit structure, avoiding the multi-stage cascaded form, thereby greatly reducing the total power consumption and area loss of the circuit, and also avoiding the problem of quadrature mismatch.

[0067] Furthermore, the complex filter proposed in this invention can also be used in other low-IF receivers, making it widely applicable.

[0068] In the description of this invention, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0069] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. In addition, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0070] Although this application has been described herein in conjunction with various embodiments, those skilled in the art, by reviewing the accompanying drawings, disclosure, and appended claims, will understand and implement other variations of the disclosed embodiments in carrying out the claimed application. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude a plurality. A single processor or other unit can implement several functions listed in the claims. While different dependent claims may recite certain measures, this does not mean that these measures cannot be combined to produce good results.

[0071] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A novel low-power, high image rejection active CMOS complex filter circuit, characterized in that, include: The system comprises a notch filter circuit, a dual second-order low-pass filter circuit, a linear frequency shift circuit, an I-path differential input voltage terminal, an I-path differential output terminal, a Q-path differential input voltage terminal, and a Q-path differential output terminal. The dual second-order low-pass filter circuit includes an I-path dual second-order low-pass filter circuit and a Q-path dual second-order low-pass filter circuit. The differential input voltage terminal of the notch filter circuit is connected to the differential input voltage terminal of the I-path and the differential input voltage terminal of the Q-path, respectively. The differential current output terminal of the I-path of the notch filter circuit is connected in phase with the differential input current terminal of the I-path dual second-order low-pass filter circuit. The differential current output terminal of the Q-path of the notch filter circuit is connected in reverse phase with the differential input current terminal of the Q-path dual second-order low-pass filter circuit. Both the I-path dual second-order low-pass filter circuit and the Q-path dual second-order low-pass filter circuit include a first node and a second node, and both the first node and the second node are connected to the linear frequency shift circuit; the differential output terminals of the dual second-order low-pass filter circuits are the I-path differential output terminal and the Q-path differential output terminal; The notch filter circuit includes: a high-pass and low-pass transconductance stage, an I-path differential current output terminal, and a Q-path differential current output terminal. The high-pass and low-pass transconductance stage includes an I-path high-pass and low-pass transconductance stage and a Q-path high-pass and low-pass transconductance stage. The differential input voltage terminals of the high-pass and low-pass transconductance stages include a differential voltage positive input terminal. and differential voltage negative input terminal The differential input voltage terminal of the I-path high-pass low-pass transconductance stage is connected to the differential input voltage terminal of the I-path, and the differential input voltage terminal of the Q-path high-pass low-pass transconductance stage is connected to the differential input voltage terminal of the Q-path. The differential current output terminal of the high-pass and low-pass transconductance stage includes a high-pass differential current positive output terminal. High-pass differential current negative output terminal Low-pass differential current positive output terminal and low-pass differential current negative output terminal The low-pass differential current positive output terminal of the I-path high-pass and low-pass transconductance stage The high-pass differential current negative output terminal of the Q-path high-pass and low-pass transconductance stage The circuit is connected via a first preset node, which serves as the positive terminal of the differential current output of the I-path; the low-pass differential current negative output terminal of the high-pass and low-pass transconductance stages of the I-path. The high-pass differential current positive output terminal of the Q-path high-pass and low-pass transconductance stage The circuit is connected via a second preset node, which serves as the negative terminal of the differential current output of the I-path; the high-pass differential current positive output terminal of the high-pass and low-pass transconductance stages of the I-path. The low-pass differential current positive output terminal of the Q-path high-pass and low-pass transconductance stage. The third preset node is connected and serves as the positive terminal of the Q-path differential current output; the high-pass differential current negative output terminal of the I-path high-pass low-pass transconductance stage. The low-pass differential current negative output terminal of the Q-path high-pass and low-pass transconductance stage The connection is made through a fourth preset node, which serves as the negative terminal of the differential current output terminal of the Q-path.

2. The novel low-power high image suppression active CMOS complex filter circuit according to claim 1, characterized in that, The I-path differential input voltage terminal includes an input voltage terminal. and input voltage terminal The Q-path differential input voltage terminal includes an input voltage terminal. and input voltage terminal ; The input voltage terminal The phase of the input voltage terminal phase difference The input voltage terminal The phase of the input voltage terminal phase difference The input voltage terminal The phase of the input voltage terminal phase difference The input voltage terminal The phase of the input voltage terminal phase difference .

3. The novel low-power high image suppression active CMOS complex filter circuit according to claim 1, characterized in that, The I-path dual second-order low-pass filter circuit includes: a transconductor , , Load capacitor , , , I-path differential input current terminal and I-path differential output voltage terminal; The differential input current terminals of the I-path are respectively connected to... input terminal and The input terminals are connected in phase. The output terminal and The input terminals are connected in reverse. The output terminal and The input terminals are connected in phase. The output terminal and The input terminals are connected in reverse, and the second node of the I-path dual second-order low-pass filter circuit is the differential output voltage terminal of the I-path. , The upper electrode is connected to the first node of the I-channel dual second-order low-pass filter circuit, and the lower electrode is grounded; , The upper electrode is connected to the second node of the I-channel dual second-order low-pass filter circuit, and the lower electrode is grounded.

4. The novel low-power high image suppression active CMOS complex filter circuit according to claim 3, characterized in that, The Q-path dual second-order low-pass filter circuit includes: a transconductor , , Load capacitor , , , Q-path differential input current terminal and Q-path differential output voltage terminal; The Q-path differential input current terminal is respectively connected to input terminal and The input terminals are connected in phase. The output terminal and The input terminals are connected in reverse. The output terminal and The input terminals are connected in phase. The output terminal and The input terminals are connected in reverse, and the second node of the Q-path dual second-order low-pass filter circuit is the differential output voltage terminal of the Q-path. , The upper electrode is connected to the first node of the Q-path dual second-order low-pass filter circuit, and the lower electrode is grounded; , The upper electrode is connected to the second node of the Q-path dual second-order low-pass filter circuit, and the lower electrode is grounded.

5. The novel low-power high image suppression active CMOS complex filter circuit according to claim 4, characterized in that, The phase difference between the Q-path differential input current terminal and the I-path differential input current terminal is... .

6. The novel low-power high image rejection active CMOS complex filter circuit according to claim 4, characterized in that, The linear frequency shift circuit includes a transconductor. , , , ; in, The differential input terminals are respectively connected in phase to the first node of the I-path dual second-order low-pass filter circuit, and to... The differential output terminals are connected in reverse. The differential output terminals are respectively connected to the first node of the Q-path dual second-order low-pass filter circuit and The differential input terminals are connected in phase. The differential input terminals are respectively connected in phase to the second node of the I-path dual second-order low-pass filter circuit, and to... The differential output terminals are connected in reverse phase; The differential output terminals are respectively connected to the second node of the Q-path dual second-order low-pass filter circuit and The differential input terminals are connected in phase.

7. The novel low-power high image suppression active CMOS complex filter circuit according to claim 1, characterized in that, The I-path high-pass and low-pass transconductance stage includes a transistor: , , , , , , , , , , , , , , and Load capacitor: , I-path differential input voltage terminal, I-path differential current output terminal, bias voltage input terminal , and power supply voltage ;in, , , The gate is connected to the positive terminal of the differential input voltage terminal of the I-path. , , The gate is connected to the negative terminal of the differential input voltage terminal of the I-path; , , , , and The gate is connected to the bias voltage input terminal. , , , and The gate is connected to the bias voltage input terminal. ; The source poles are respectively with Drain and The upper electrode plate is connected. The source poles are respectively with Drain and The lower electrode plate is connected. The source poles are respectively with Drain and The upper electrode plate is connected. The source poles are respectively with Drain and The lower electrode plate is connected. The source poles are respectively with The source pole and , Drain connection; , , , , and The source is grounded. , , and The source and the power supply voltage connect; Drain and The drain connection, Drain and Drain connection; The drain of the filter is connected to the positive terminal of the differential current output terminal of the I-path of the notch filter circuit. The drain of the filter is connected to the negative terminal of the differential current output terminal of the I-path of the notch filter circuit. The drain of the filter is connected to the positive terminal of the Q-path differential current output of the notch filter circuit. The drain of the filter is connected to the negative terminal of the Q-path differential current output terminal of the notch filter circuit.

8. The novel low-power high image suppression active CMOS complex filter circuit according to claim 6, characterized in that, transconductor , , , , , , , , , The structures are the same.

9. The novel low-power high image suppression active CMOS complex filter circuit according to claim 8, characterized in that, Including transistors: , , , and First differential input voltage terminal, first differential current output terminal, bias voltage input terminal , and power supply voltage ;in, The gate is connected to the positive terminal of the first differential input voltage terminal. The gate is connected to the negative terminal of the first differential input voltage terminal; , The gate and the bias voltage input terminal connect, The gate and the bias voltage input terminal connect, The source poles are respectively with The source pole and Drain connection; , The source and the power supply voltage connect, The source is grounded. The drain is connected to the fifth preset node. The drain of the first differential current output terminal is the fifth preset node, which serves as the negative terminal of the first differential current output terminal. ; The drain is connected to the sixth preset node. The drain of the first differential current output terminal is the sixth preset node, which serves as the positive terminal of the first differential current output terminal. .

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