Wafer level chip packaging method and chip packaging structure

Abstract

The application discloses a wafer-level chip packaging method and a packaging structure. The method comprises the following steps: providing a wafer-level substrate; forming a re-distribution layer on the upper surface of the wafer-level substrate, wherein the re-distribution layer comprises a metal layer, a passive device is arranged in the re-distribution layer, and the passive device is electrically connected with the metal layer; providing a chip, wherein the chip has a sensing area and a bonding pad electrically coupled with the sensing area; flip-chip mounting the chip on the re-distribution layer, and electrically connecting the bonding pad with the metal layer; filling plastic packaging material to package the chip and the re-distribution layer; peeling off the wafer-level substrate, and forming an external protrusion on the surface of the re-distribution layer, wherein the external protrusion is electrically connected with the metal layer; and cutting the formed wafer-level packaging structure to obtain a plurality of independent chip packaging structures. The wafer-level chip packaging method can improve the packaging efficiency and reduce the packaging volume.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor packaging, and in particular to a wafer level chip packaging method and a chip packaging structure. BACKGROUND

[0002] Wafer Level Packaging (WLP) is an advanced packaging technology that has developed rapidly in recent years due to its small size, excellent electrical performance, good heat dissipation, low cost, and other advantages. According to Verified Market Research research data, the wafer level packaging market was 48.4 billion US dollars in 2020, and is expected to reach 228.3 billion US dollars by 2028, with a compound annual growth rate of 21.4% from 2021 to 2028.

[0003] With the continuous upgrading of electronic products, emerging markets such as smart phones, 5G, and AI have higher requirements for packaging technology, making packaging technology develop towards high integration, three-dimensional, and ultra-fine pitch interconnection. Wafer level packaging technology can reduce chip size, wiring length, solder ball pitch, etc., thereby improving the integration of integrated circuits, the speed of processors, reducing power consumption, and improving reliability, which meets the development needs of electronic products that are increasingly light, thin, short, and small, and low cost.

[0004] Compared with traditional packaging, wafer level packaging has the following advantages: small packaging size, high transmission speed, high density connection, short production cycle, and low process cost.

[0005] In the prior art, when multiple filter chips are packaged with passive devices, the packaging volume of the packaged body is large, and the packaging efficiency is not high.

[0006] The information disclosed in this BACKGROUND section is only intended to increase an understanding of the general context in which the present application can be practiced. It is not admitted that this information constitutes prior art that is already known in the art. SUMMARY

[0007] The present application relates to the technical field of semiconductor packaging, and in particular to a wafer level chip packaging method and a chip packaging structure.

[0008] To achieve the above object, the embodiment of the present application provides a wafer level chip packaging method, which comprises the following steps: providing a wafer level substrate; forming a re-distribution layer on the upper surface of the wafer level substrate, wherein the re-distribution layer comprises a metal layer, a passive device is arranged in the re-distribution layer, and the passive device is electrically connected to the metal layer; providing a chip, wherein the chip has a sensing area and a bonding pad electrically coupled to the sensing area, the chip is inverted on the re-distribution layer, and the bonding pad is electrically connected to the metal layer; filling plastic packaging material to package the chip and the re-distribution layer; peeling off the wafer level substrate, and forming an external bump on the surface of the re-distribution layer, wherein the external bump is electrically connected to the metal layer; and cutting the formed wafer level packaging structure to obtain a plurality of independent chip packaging structures.

[0009] In one or more embodiments of the present application, before the step of forming the re-distribution layer on the upper surface of the wafer level substrate, the method further comprises the step of forming an adhesive layer on the upper surface of the wafer level substrate, and the re-distribution layer is formed on the surface of the adhesive layer.

[0010] In one or more embodiments of the present application, after the step of peeling off the wafer level substrate, the method further comprises the step of peeling off the adhesive layer.

[0011] In one or more embodiments of the present application, the re-distribution layer further comprises a dielectric layer, and the metal layer is formed in the dielectric layer and partially exposes the upper and lower surfaces of the dielectric layer.

[0012] In one or more embodiments of the present application, before the step of forming the re-distribution layer on the surface of the adhesive layer, the method further comprises the step of forming a passivation layer on the surface of the adhesive layer, the re-distribution layer is formed on the surface of the passivation layer, and the metal layer in the re-distribution layer partially exposes the surface of the passivation layer.

[0013] In one or more embodiments of the present application, before the step of filling the plastic packaging material to package the chip and the re-distribution layer, the method further comprises the step of laminating the chip, and forming a lamination layer on the surface of the chip and the surface of the re-distribution layer, and the plastic packaging material is filled on the surface of the lamination layer.

[0014] In one or more embodiments of the present application, before the step of inverting the chip on the re-distribution layer, the method further comprises the step of forming a metal bump electrically connected to the bonding pad on the bonding pad of the chip, and the bonding pad of the chip is electrically connected to the metal layer through the metal bump.

[0015] In one or more embodiments of the present application, the method for forming a metal bump on the pad of the chip to electrically connect the pad includes: providing a wafer-level chip, the wafer-level chip having a plurality of chips arranged in a grid, the chip having a sensing region and a pad electrically coupled to the sensing region; forming a metal bump on the pad of the chip; and cutting the wafer-level chip to obtain a single chip.

[0016] In one or more embodiments of the present application, a chip packaging structure is provided, which includes a chip, a redistribution layer, a passive device, a molding layer, and an external bump.

[0017] The chip has a first surface and a second surface arranged oppositely, the first surface of the chip has a sensing region and a pad electrically coupled to the sensing region; the redistribution layer is located on the first surface of the chip, the redistribution layer includes a metal layer, the metal layer is electrically connected to the pad; the passive device is located in the redistribution layer and is electrically connected to the metal layer; the molding layer is located on the second surface of the chip and covers the surface of the chip and the redistribution layer; and the external bump is formed on a side of the redistribution layer away from the chip and is electrically connected to the metal layer.

[0018] In one or more embodiments of the present application, the redistribution layer further includes a dielectric layer, and the metal layer is formed in the dielectric layer and partially exposes the upper and lower surfaces of the dielectric layer.

[0019] In one or more embodiments of the present application, the chip packaging structure further includes a passivation layer and a lamination layer. The passivation layer is formed on a side of the redistribution layer away from the chip and the metal layer partially exposes the surface of the passivation layer, and the external bump completely covers the metal layer exposed to the passivation layer; the lamination layer is located on the second surface of the chip and covers the surface of the chip and the redistribution layer, and the molding layer is formed on a side surface of the lamination layer away from the chip.

[0020] Compared with the prior art, the wafer-level chip packaging method of the embodiments of the present application realizes the integrated packaging of multiple chips and passive devices, has a small packaging volume, and has high packaging efficiency. BRIEF DESCRIPTION OF DRAWINGS

[0021] Figure 1 And Figure 2 is a flowchart of the wafer-level chip packaging method of the embodiments of the present application;

[0022] Figures 3-15 is a structural diagram of the wafer-level chip packaging process of the embodiments of the present application.

[0023] Figures 6a-6iis a specific formation structure diagram of a re-routed layer in a chip packaging process of a specific embodiment of the present application (from Figure 5 formation Figure 6 of the detailed steps).

[0024] Figure 16 is a chip packaging structure diagram of an embodiment of the present application. DETAILED DESCRIPTION

[0025] The specific embodiments of the present application are described in detail below with reference to the accompanying drawings, but it should be understood that the protection scope of the present application is not limited by the specific embodiments.

[0026] Unless otherwise explicitly stated, in the entire specification and claims, the term "comprise" or its variants such as "contain" or "include" and the like will be understood to encompass the stated element or components, without excluding other elements or components.

[0027] As stated in the background, the fan-out type packaging of the filter in the prior art has a large volume of the package after the integration of the passive device, and the independent packaging of a single or several filters has low packaging efficiency. In order to solve the above problems, the present application provides a wafer-level chip packaging method, which can greatly reduce the volume of the package and improve the packaging efficiency.

[0028] The specific embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0029] As shown in Figure 1 , an embodiment of the present application provides a wafer-level chip packaging method, which comprises: providing a wafer-level substrate s1; forming an adhesive layer on the upper surface of the wafer-level substrate s2; forming a passivation layer on the surface of the adhesive layer s3; forming a re-routed layer on the surface of the passivation layer s4, wherein the re-routed layer comprises a metal layer, the re-routed layer is provided with a passive device, and the passive device is electrically connected to the metal layer; providing a chip s5, wherein the chip has a sensing area and a solder pad electrically coupled to the sensing area; flip-chip bonding the chip on the re-routed layer and electrically connecting the solder pad to the metal layer s6; laminating the chip and forming a laminated layer on the surface of the chip and the surface of the re-routed layer s7; filling a plastic encapsulation material on the surface of the laminated layer s8 to encapsulate the chip and the re-routed layer; peeling off the wafer-level substrate and the adhesive layer and forming external protrusions on the surface of the re-routed layer s9, wherein the external protrusions are electrically connected to the metal layer; and cutting the formed wafer-level packaging structure s10 to obtain a plurality of independent chip packaging structures.

[0030] Further, before the step of flip-chip bonding the chip on the re-routed layer, the method further comprises the step of forming a metal bump electrically connected to the solder pad on the solder pad of the chip, and the solder pad of the chip is electrically connected to the metal layer of the re-routed layer through the metal bump. Specifically, as shown in Figure 2As shown, a wafer-level chip s51 can be provided first. The wafer-level chip has multiple chips arranged in a grid. The chip has a sensing area and a pad electrically coupled to the sensing area; a metal bump s52 is formed on the pad of the chip; and the wafer-level chip is cut to obtain a single chip s53.

[0031] Figures 3 to 15 This is a schematic diagram of the structure of the wafer-level chip packaging process of an embodiment of the present invention. Figures 3 to 15 , the wafer-level chip packaging method of the present invention is described in detail.

[0032] First, refer to Figure 3 As shown, a wafer-level substrate 10 is provided. The material of the wafer-level substrate 10 can be selected from one or more of glass, silicon, silicon oxide, metal, or ceramic. The wafer-level substrate 10 is flat, such as, but not limited to, a circular glass plate of a certain thickness. The circular glass plate has a relatively smooth surface, which makes it easier to peel in subsequent processes.

[0033] refer to Figure 4 As shown, an adhesive layer 20 is formed on the upper or lower surface of the wafer-level substrate 10. The adhesive layer 20 serves as a separation layer between the passivation layer 30 (rewiring layer 40) and the wafer-level substrate 10 in subsequent processes, and is preferably supported by an adhesive material with a smooth surface. In specific embodiments, the adhesive layer 20 can be a UV-dissolving tape, a thermal-dissolving tape, or other suitable tape material, formed by processes such as spraying, spin coating, or gluing. In subsequent processes, the adhesive layer 20 and the wafer-level substrate 10 can be easily removed from the passivation layer 30 by irradiation with UV light.

[0034] refer to Figure 5 As shown, a passivation layer 30 is formed on the surface of the adhesive layer 20. The passivation layer 30 serves to completely isolate the metal layer 41 in the redistribution layer 40 from the outside, preventing the metal layer 41 from contacting the external medium, thereby preventing the metal layer 41 from corroding.

[0035] refer to Figure 6As shown, a rewiring layer 40 is formed on the surface of the passivation layer 30, wherein the rewiring layer 40 includes a metal layer 41 and a dielectric layer 42. The metal layer 41 is formed in the dielectric layer 42 and partially exposes the upper and lower surfaces of the dielectric layer 42. Furthermore, the metal layer 41 partially extends into the passivation layer 30 and exposes the surface of the passivation layer 30 from the other side of the passivation layer 30, so as to facilitate the formation of external protrusions 70 electrically connected to the metal layer 41 on the surface of the passivation layer 30 in subsequent processes. The dielectric layer 42 can be made of epoxy resin, silicone, PI, PBO, BCB, silicon oxide, phosphosilicate glass or fluorine-containing glass. The dielectric layer 42 can be formed by spin coating, CVD, plasma-enhanced CVD and other processes. Passive devices (not shown) are also provided in the rewiring layer 40. The passive devices are completely encapsulated by the rewiring layer 40 and are electrically connected to the metal layer 41. The passive modules may include capacitors, inductors and resistors, and their specific arrangement positions may be designed according to actual needs, which is not limited in the present invention.

[0036] In one embodiment, reference Figures 6a to 6i As shown, the steps of forming the redistribution layer 40 may include: Figure 6a As shown, a first dielectric layer 421 is formed on the passivation layer 30. Figure 6b As shown, a first set of through holes 422 is opened on the first dielectric layer 421 and the passivation layer 30. The first set of through holes 422 penetrates into the adhesive layer 20 but does not penetrate the adhesive layer 20. Figure 6c As shown, a first metal layer 411 is formed in the first set of through holes 422, and the upper surface of the first metal layer 411 is flush with the upper surface of the first dielectric layer 421. Figure 6d As shown, a second dielectric layer 423 is formed on the first dielectric layer 421 and the first metal layer 411. Figure 6e As shown, a second set of through holes 424 is opened on the second dielectric layer 423, and the second set of through holes 424 exposes part or all of the first metal layer 411. Figure 6f As shown, a second metal layer 412 electrically connected to the first metal layer 411 is formed in the second set of through holes 424, and the upper surface of the second metal layer 412 is flush with the upper surface of the second dielectric layer 423. Figure 6g As shown, a third dielectric layer 425 is formed on the second dielectric layer 423 and the second metal layer 412. Figure 6h As shown, a third set of through holes 426 is opened on the third dielectric layer 425, and the third set of through holes 426 exposes part or all of the second metal layer 412. Figure 6i As shown, a third metal layer 413 electrically connected to the second metal layer 412 is formed in the third set of through holes 426 , and the upper surface of the third metal layer 413 is protruding from the upper surface of the third dielectric layer 425 to facilitate subsequent bonding and packaging processes.

[0037] In other embodiments, the re-distribution layer 40 can also be formed in other ways, such as forming the dielectric layer 42 directly, forming the via in the dielectric layer 42, and forming the metal layer 41 in the via; or forming the metal layer 41 by patterning first, and then filling the dielectric material to form the dielectric layer 42. The present application does not limit the forming method of the re-distribution layer 40.

[0038] Referring to Figures 7 to 9 As shown in FIG. 1, a wafer-level chip 100 is provided, which includes a plurality of chips 110 arranged in a matrix (grid) and a scribe lane region 120 between the chips 110. Each chip 110 has a sensing region and a pad arranged around the sensing region and coupled to the sensing region. A metal bump 111 is formed on the pad of each chip 110 and electrically connected to the pad. The wafer-level chip 100 is cut along the scribe lane region 120 to form a plurality of chips 110. The wafer-level chip 100 can be cut by using the existing cutting process, which will not be described in detail here. Figure 7 FIG. 1 is a top view of the wafer-level chip 100, Figure 8 FIG. 2 is a cross-sectional view of the plurality of chips 110 in the A-A1 direction. Each chip 110 on the wafer-level chip 100 has a sensing region and a pad arranged around the sensing region and coupled to the sensing region. A metal bump 111 is formed on the pad of each chip 110 and electrically connected to the pad. The wafer-level chip 100 is cut along the scribe lane region 120 to form a plurality of chips 110. The wafer-level chip 100 can be cut by using the existing cutting process, which will not be described in detail here.

[0039] Referring to Figure 10 As shown in FIG. 3, one or more chips 110 obtained by cutting are flipped on the re-distribution layer 40, and the metal bump 111 on the chip 110 is electrically connected to the metal layer 41 on the re-distribution layer 40. The metal bump 111 and the metal layer 41 can be bonded by using a bonding process, such as ultrasonic bonding, thermal compression bonding, or ordinary reflow soldering.

[0040] Referring to Figure 11 and Figure 12 As shown in FIG. 4, the chip 110 is laminated, and a laminated layer 50 is formed on the surface of the chip 110 and the surface of the re-distribution layer 40. The laminated chip 110 is encapsulated by filling an encapsulation material, and the encapsulation material is solidified to form an encapsulation layer 60. The encapsulation material is resin or solder resist ink material, such as epoxy resin or acrylic resin.

[0041] The encapsulation layer 60 is formed to protect the chip 110, prevent performance failure of the chip 110 caused by the influence of the external environment, prevent moisture from entering from the outside, and electrically insulate from the outside. On the other hand, the encapsulation layer 60 supports the chip 110 (the wafer-level substrate 10 will be removed later), fixes the chip 110 for subsequent circuit connection, and makes the chip less likely to be damaged after encapsulation. The encapsulation layer 60 is formed by using a molding process, which can be a transfer method or a compression method.

[0042] Referring to Figure 13 andFigure 14 The adhesive layer 20 and the wafer-level substrate 10 are peeled off. The adhesive layer 20 and the wafer-level substrate 10 can be peeled off by one or more of mechanical grinding, chemical polishing, etching, ultraviolet peeling, and mechanical peeling. In this embodiment, the wafer-level substrate 10 can be peeled off by tearing off the adhesive layer 20.

[0043] If the adhesive layer 20 is a UV-decomposable adhesive tape or a thermal-decomposable adhesive tape, the UV-decomposable adhesive tape or the thermal-decomposable adhesive tape can be made to lose adhesion by UV irradiation, so that the adhesive layer 20 and the wafer-level substrate 10 can be easily removed from the redistribution layer 40.

[0044] Referring to Figure 15 As shown in the figure, external connection protrusions 70 are formed on the surface of the redistribution layer 41, and the external connection protrusions 70 are electrically connected to the metal layer 41. The external connection protrusions 70 are used to connect to external circuits. In this embodiment, the external connection protrusions 70 are in the shape of balls, and the external connection protrusions 70 are in the structure of a ball grid array (BGA). The external connection protrusions 70 are formed by a ball mounting process. The material of the external connection protrusions 70 can be gold, tin, or a tin alloy, such as tin-silver, tin-lead, tin-silver-copper, tin-silver-zinc, tin-zinc, tin-bismuth-indium, tin-indium, tin-gold, tin-copper, tin-zinc-indium, or tin-silver-antimony.

[0045] Finally, the wafer-level packaging structure is cut to obtain a plurality of independent chip packaging structures, as shown in the figure. Figure 16 The cutting process is slicing or laser cutting. Since laser cutting has a smaller cutting width and improves the accuracy of the cutting process, the wafer-level packaging structure formed by laser cutting is used for cutting in this embodiment.

[0046] Referring to Figure 16 The present application also provides a chip packaging structure, which includes a chip 110, a passivation layer 30, a redistribution layer 40, a passive device, a lamination layer 50, a plastic encapsulation layer 60, and external connection protrusions 70.

[0047] The chip 110 has a first surface and a second surface arranged opposite to each other. The first surface of the chip 110 has a sensing region and a bonding pad coupled to the sensing region.

[0048] The redistribution layer 40 is located on the first surface of the chip 110. The redistribution layer 40 includes a metal layer 41 and a dielectric layer 42. The metal layer 41 is formed in the dielectric layer 42 and partially exposes the upper and lower surfaces of the dielectric layer 42. The metal layer 41 is electrically connected to the bonding pad. The passive device is located in the redistribution layer 40 and is electrically connected to the metal layer 41.

[0049] The passivation layer 30 is formed on a side of the redistribution layer 40 away from the chip 110 , and a portion of the metal layer 41 in the redistribution layer 40 exposes a surface of the passivation layer 30 .

[0050] The laminate layer 50 is located on the second surface of the chip 110 and covers the surface of the chip 110 and the redistribution layer 40. The molding layer 60 is formed on a surface of the laminate layer 50 away from the chip 110.

[0051] The external protrusion 70 is formed on a side of the redistribution layer 40 away from the chip 110 and is electrically connected to the metal layer 41 . The external protrusion 70 completely covers the metal layer 41 that exposes the passivation layer 30 .

[0052] Compared with the prior art, the wafer-level chip packaging method of the embodiment of the present invention realizes the integrated packaging of multiple chips and passive devices, and has a small packaging volume and high packaging efficiency.

[0053] The foregoing descriptions of specific exemplary embodiments of the present invention are for purposes of illustration and description. These descriptions are not intended to limit the invention to the precise forms disclosed, and it is apparent that many variations and modifications are possible in light of the foregoing teachings. The exemplary embodiments have been selected and described for the purpose of explaining the specific principles of the invention and their practical application, thereby enabling those skilled in the art to realize and utilize a variety of exemplary embodiments of the invention and various options and modifications. The scope of the invention is intended to be defined by the claims and their equivalents.

Claims

1. A wafer-level chip packaging method, characterized in that: include: providing a wafer-level substrate; forming a redistribution layer on the upper surface of the wafer-level substrate, wherein the redistribution layer includes a metal layer, and a passive device is disposed in the redistribution layer, wherein the passive device is electrically connected to the metal layer; Providing a chip, the chip having a sensing area and a bonding pad electrically coupled to the sensing area, flip-chipping the chip on the redistribution layer and electrically connecting the bonding pad to the metal layer; Filling the chip and the redistribution layer with a plastic encapsulation material to perform plastic encapsulation; peeling off the wafer-level substrate and forming an external protrusion on the surface of the redistribution layer, wherein the external protrusion is electrically connected to the metal layer; Cutting the formed wafer-level packaging structure to obtain multiple independent chip packaging structures; Before the step of filling the molding material to mold the chip and the rewiring layer, the method further includes: laminating the chip and forming a laminated layer on the surface of the chip and the surface of the rewiring layer, wherein the molding material is filled on the surface of the laminated layer.

2. The wafer-level chip packaging method according to claim 1, wherein: Before the step of forming a redistribution layer on the upper surface of the wafer-level substrate, the method further includes the step of forming an adhesive layer on the upper surface of the wafer-level substrate, wherein the redistribution layer is formed on the surface of the adhesive layer.

3. The wafer-level chip packaging method according to claim 2, wherein: After the step of peeling off the wafer-level substrate, the method further includes the step of peeling off the adhesive layer.

4. The wafer-level chip packaging method according to claim 2, wherein: The rewiring layer further includes a dielectric layer. The metal layer is formed in the dielectric layer and partially exposes the upper and lower surfaces of the dielectric layer.

5. The wafer-level chip packaging method according to claim 4, wherein: Before the step of forming a redistribution layer on the surface of the adhesive layer, the method further includes forming a passivation layer on the surface of the adhesive layer. The redistribution layer is formed on the surface of the passivation layer, and the metal layer in the redistribution layer partially exposes the surface of the passivation layer.

6. The wafer-level chip packaging method according to claim 1, wherein: Before the step of flipping the chip onto the rewiring layer, the method further includes forming metal bumps electrically connected to the bonding pads of the chip, wherein the bonding pads of the chip are electrically connected to the metal layer via the metal bumps.

7. The wafer-level chip packaging method according to claim 6, wherein: The metal bumps electrically connected to the bonding pads of the chip are formed on the bonding pads, including: Providing a wafer-level chip, wherein the wafer-level chip has a plurality of chips arranged in a grid, and the chip has a sensing area and a bonding pad electrically coupled to the sensing area; forming metal bumps on the bonding pads of the chip; The wafer-level chips are cut into individual chips.

8. A chip packaging structure, characterized in that: include: A chip having a first surface and a second surface opposite to each other, wherein a sensing area and a bonding pad coupled to the sensing area are formed on the first surface of the chip; a redistribution layer, located on the first surface of the chip, the redistribution layer comprising a metal layer, the metal layer being electrically connected to the bonding pad; A passive device is located in the redistribution layer and is electrically connected to the metal layer; A plastic packaging layer is located on the second surface of the chip and covers the surface of the chip and the redistribution layer; an external protrusion formed on a side of the redistribution layer away from the chip and electrically connected to the metal layer; The lamination layer is located on the second surface of the chip and covers the surface of the chip and the redistribution layer. The plastic encapsulation layer is formed on the surface of the lamination layer away from the chip.

9. The chip packaging structure according to claim 8, wherein: The rewiring layer further includes a dielectric layer. The metal layer is formed in the dielectric layer and partially exposes the upper and lower surfaces of the dielectric layer.

10. The chip packaging structure according to claim 8, wherein: Also includes: A passivation layer is formed on a side of the redistribution layer away from the chip, and a portion of the metal layer in the redistribution layer exposes a surface of the passivation layer. The circumscribed protrusion completely covers the metal layer that exposes the passivation layer.

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