Highly reliable silicon carbide mosfet device with integrated reverse sbd and method of fabrication

Abstract

The application provides a high-reliability silicon carbide MOSFET integrated with a reverse SBD and a preparation method, which comprises an N-type substrate, an N-type epitaxial layer, a P+shield region, a Schottky contact metal, a source electrode, a gate dielectric, a polysilicon gate, a P-body region, a P+contact region, an N+contact region and a drain; the silicon carbide MOSFET device provided by the application forms a P+shield region with self-regulating electric potential in the device body, protects the gate oxide layer without reducing the conduction capacity of the device, and enhances the blocking capacity of the device; when the device is short-circuited, the PN junction depletion region formed by the P+shield region and the N-type epitaxial layer clamps off the JFET region, reduces the saturation current of the device when short-circuited, and improves the short-circuit capacity of the device.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of power semiconductor devices, and particularly relates to a high-reliability silicon carbide MOSFET device integrated with a reverse SBD and a preparation method thereof. BACKGROUND

[0002] As one of the third-generation wide-bandgap semiconductor materials, silicon carbide (SiC) has advantages of a wider band gap (3 times) than silicon, a higher critical electric field (10 times), a higher carrier saturation drift velocity (2 times), a higher thermal conductivity (2.5 times), and the like, and is an excellent material for preparing high-voltage power electronic devices, and has a wide application prospect in the fields of high power, high temperature, high voltage and radiation-resistant power electronics.

[0003] MOSFET is a gate-controlled device structure most widely used in silicon carbide power devices. As a device characterized by unipolar transport working mechanism, silicon carbide MOSFET has no charge storage effect, has lower switching loss and higher frequency characteristics than bipolar devices, and at the same time, its low on-resistance and excellent high-temperature characteristics make silicon carbide MOSFET a new generation of low-loss power device with great competitiveness.

[0004] During the operation of a power electronic system, a device may be subjected to high voltage and large current at the same time due to device misopening or load failure, that is, the device is short-circuited, at which time the current through the device rapidly reaches the saturation current. When the device is short-circuited, the device will completely lose control, not only is it easy to cause secondary damage to the device itself, it is difficult to determine the direct cause of the device failure, and the continuous short-circuit state after the device failure will cause harm to the overall system. If the silicon carbide MOSFET is turned off by the protection circuit after being short-circuited, even if the device does not fail, its electrical characteristics will also be severely degraded, greatly reducing the service life and reliability of the device.

[0005] When the device is short-circuited, compared with silicon-based devices of the same order of magnitude, due to the smaller chip area and larger current density of the silicon carbide MOSFET, it is subjected to stronger electro-thermal stress in the short-circuit state. Therefore, the demand for short-circuit protection design of the silicon carbide MOSFET is more urgent. Improving the short-circuit reliability of the silicon carbide MOSFET and prolonging the short-circuit endurance time of the device are often achieved by reducing the saturation current of the device, but reducing the saturation current of the device often increases the on-resistance of the device, sacrificing the forward conduction capability of the device.

[0006] And when the device withstands voltage, there is a high peak electric field at the gate dielectric, and long-time work may cause the reliability of the gate dielectric layer to decrease. SUMMARY

[0007] The application aims to provide a high-reliability silicon carbide MOSFET device integrated with reverse SBD, by introducing a P+shield region connected with a source electrode through a Schottky contact below a gate dielectric, a potential difference between the P+shield region and the Schottky contact metal changes under the control of a drain voltage according to different working modes of the device, that is, a SBD is integrated in the device, and the P+shield region can be switched between a grounded state and a floating state under the control of the SBD, the high-reliability silicon carbide MOSFET device integrated with reverse SBD can enhance the reliability of a gate dielectric layer of the device, increase the breakdown voltage of the device, reduce the saturation current of the device when a short circuit occurs, improve the short circuit endurance time of the device, and enhance the short circuit reliability of the device without sacrificing the original MOSFET conduction capability and increasing the on-resistance of the device.

[0008] To achieve the above-mentioned application purposes, the technical solutions of the application are as follows.

[0009] The high-reliability silicon carbide MOSFET device integrated with reverse SBD comprises an N-type substrate 10, an N-type epitaxial layer 9 above the N-type substrate 10, a P+shield region 8 in the N-type epitaxial layer 9, a Schottky contact metal 3 above the P+shield region 8 and forming a Schottky contact with the P+shield region 8, a source electrode 1 above the Schottky contact metal 3, a gate dielectric 7 above the P+shield region 8 and a polysilicon gate 2 in the gate dielectric 7, a P-body region 6 above the N-type epitaxial layer 9, a P+contact region 4 and an N+contact region 5 above the P-body region 6 and forming an ohmic contact with the source electrode 1, and a drain 11 below the N-type substrate 10 and forming an ohmic contact with the N-type substrate 10, wherein the P+contact region 4 and the N+contact region 5 are located below the source electrode 1 and on both sides of the gate dielectric 7.

[0010] As a preferred mode, the source electrode 1 is T-shaped, comprising a source electrode horizontal segment above the P+contact region 4 and the N+contact region 5, and a source electrode vertical segment between the gate dielectric 7, the source electrode horizontal segment forms an ohmic contact with the P+contact region 4 and the N+contact region 5, and the source electrode vertical segment is connected with the Schottky contact metal 3.

[0011] As a preferred mode, a Schottky contact exists between the P+shield region 8 and the Schottky contact metal 3, forming a Schottky diode, and the direction of the Schottky diode is from the P+shield region 8 to the Schottky contact metal 3.

[0012] As a preferred mode, the gate dielectric 7 is SiO2 or high-K dielectric.

[0013] As a preferred mode, the respective change of the doping type in the device is a change of the doping from P-type to N-type and vice versa.

[0014] The application also provides a preparation method of the high-reliability silicon carbide MOSFET device integrated with a reverse SBD, comprising the following steps:

[0015] First step: cleaning the epitaxial wafer, implanting aluminum ions into the N-type epitaxial layer to form a P-body region with an oxide layer as an implantation barrier;

[0016] Second step: implanting nitrogen ions into the N-type epitaxial layer to form an N+ contact region with the oxide layer as an implantation barrier;

[0017] Third step: implanting aluminum ions into the N-type epitaxial layer to form a P+ contact region with the oxide layer as an implantation barrier and activating annealing;

[0018] Fourth step: etching a trench;

[0019] Fifth step: implanting aluminum ions into the bottom of the trench to form a P+ shield region with the oxide layer as an implantation barrier;

[0020] Sixth step: dry oxygen oxidation to form a gate oxide layer, annealing in a nitrogen atmosphere and patterning the gate oxide;

[0021] Seventh step: depositing polysilicon and etching the polysilicon;

[0022] Eighth step: wet oxygen oxidation to isolate the polysilicon;

[0023] Ninth step: depositing an ohmic contact metal for the source and sintering at a temperature above 700°C;

[0024] Tenth step: etching the gate oxide at the bottom of the trench;

[0025] Eleventh step: depositing a Schottky contact metal at the bottom of the trench and sintering at a temperature below 500°C;

[0026] Twelfth step: depositing and etching the source, drain and gate metal to form ohmic contact electrodes.

[0027] The application also provides a second high-reliability silicon carbide MOSFET device integrated with reverse SBD, which comprises an N-type substrate 10, an N-type epitaxial layer 9 located above the N-type substrate 10, P+shield regions 8 located on both sides of the N-type epitaxial layer 9, Schottky contact metal 3 located above the P+shield regions 8 and forming Schottky contact with the P+shield regions 8, a source electrode 1 comprising a horizontal section and vertical sections on both sides, the vertical sections of the source electrode 1 being located above the Schottky contact metal 3, the horizontal section of the source electrode 1 being located above P+contact regions 4 and N+contact regions 5, gate dielectric 7 comprising middle gate dielectric and side gate dielectric, the side gate dielectric being located above the P+shield regions 8 and on both sides of the vertical sections of the source electrode 1, the middle gate dielectric being located in the middle of the N-type epitaxial layer 9 and below the horizontal section of the source electrode 1, polycrystalline silicon gate 2 being located in the middle gate dielectric, P-body regions 6 being located above the N-type epitaxial layer 9 between the side gate dielectric and the middle gate dielectric, the P+contact regions 4 and the N+contact regions 5 being located above the P-body regions 6 and forming ohmic contact with the source electrode 1, and a drain 11 located below the N-type substrate 10 and forming ohmic contact with the N-type substrate 10.

[0028] The application also provides a third high-reliability silicon carbide MOSFET device integrated with reverse SBD, which comprises an N-type substrate 10, an N-type epitaxial layer 9 located above the N-type substrate 10, P+contact regions 4 located on the left side of the N-type epitaxial layer 9, P+shield regions 8 located on the right side of the N-type epitaxial layer 9, and gate dielectric 7 located in the middle of the N-type epitaxial layer 9, polycrystalline silicon gate 2 being located in the gate dielectric, the P+shield regions 8 being in contact with the bottom and the right side of the gate dielectric 7, N+contact regions 5 being located between the P+contact regions 4 and the gate dielectric 7, P-body regions 6 being located below the N+contact regions 5, a source electrode 1 being located above the P+contact regions 4, the N+contact regions 5, the gate dielectric 7 and the P+shield regions 8, Schottky contact metal 3 being located above the P+shield regions 8 and forming Schottky contact with the P+shield regions 8, the Schottky contact metal 3 being located below the source electrode 1.

[0029] A drain 11 is located below the N-type substrate 10 and forms ohmic contact with the N-type substrate 10.

[0030] The device material is SiC material, and can also be other semiconductor materials.

[0031] The polycrystalline silicon end of the device is the gate, the N+ substrate end is the drain, and the N+ contact regions and the P+ contact regions are the source.

[0032] The beneficial effects of the present application are: 1: when the device works in the on state, the SBD composed of the P+shield region and the Schottky contact metal is not opened due to the low potential of the P+shield region, at this time, the P+shield region is floating, and the PN junction depletion region formed by the P+shield region and the N-type epitaxial layer has little effect on the resistance of the JFET region; 2: when the device works in the blocking state, the potential of the P+shield region rises until the SBD is opened, at this time, the P+shield region is connected with the source electrode and grounded, which can effectively shield the gate oxide electric field and improve the gate oxide reliability of the silicon carbide MOSFET device; 3: when short circuit occurs, the potential of the P+shield region rises until the SBD is opened, at this time, the P+shield region is grounded, and because the temperature of the device rises rapidly when short circuit occurs, the Schottky barrier is reduced, the potential of the P+shield region is further reduced, the PN junction depletion region formed by the P+shield region and the N-type epitaxial layer is expanded, the conduction path of the current is narrowed, the short circuit current is reduced, and the short circuit reliability of the device is improved. BRIEF DESCRIPTION OF DRAWINGS

[0033] Figure 1 is a traditional trench gate silicon carbide MOSFET;

[0034] Figure 2 is a device structure schematic diagram of embodiment 1 of the present application;

[0035] Figure 3 is a schematic diagram of cleaning the epitaxial wafer, implanting aluminum ions to form a P-body region on the N-type epitaxial layer with an oxide layer as an implantation barrier in the preparation method in embodiment 1 of the present application;

[0036] Figure 4 is a schematic diagram of implanting nitrogen ions to form an N+contact region with an oxide layer as an implantation barrier in the preparation method in embodiment 1 of the present application;

[0037] Figure 5 is a schematic diagram of implanting aluminum ions to form a P+contact region and activating annealing with an oxide layer as an implantation barrier in the preparation method in embodiment 1 of the present application;

[0038] Figure 6 is a schematic diagram of etching a trench in the preparation method in embodiment 1 of the present application;

[0039] Figure 7 is a schematic diagram of implanting aluminum ions to form a P+shield region at the bottom of the trench with an oxide layer as an implantation barrier in the preparation method in embodiment 1 of the present application;

[0040] Figure 8 is a schematic diagram of dry oxygen oxidation to generate a gate oxide layer, annealing under a nitrogen atmosphere and patterning the gate oxide in the preparation method in embodiment 1 of the present application;

[0041] Figure 9 Figure 1 is a schematic diagram of depositing and etching polysilicon in the preparation method in Embodiment 1 of the present application;

[0042] Figure 10 Figure 2 is a schematic diagram of isolating polysilicon by wet oxygen oxidation in the preparation method in Embodiment 1 of the present application;

[0043] Figure 11 Figure 3 is a schematic diagram of depositing ohmic contact metal for source and high-temperature sintering in the preparation method in Embodiment 1 of the present application;

[0044] Figure 12 Figure 4 is a schematic diagram of etching gate oxide in the bottom of the trench in the preparation method in Embodiment 1 of the present application;

[0045] Figure 13 Figure 5 is a schematic diagram of depositing Schottky contact metal in the bottom of the trench and low-temperature sintering in the preparation method in Embodiment 1 of the present application;

[0046] Figure 14 Figure 6 is a schematic diagram of depositing and etching source, drain and gate metal to form ohmic contact electrodes in the preparation method in Embodiment 1 of the present application;

[0047] Figure 15 Figure 7 is a schematic diagram of the device structure in Embodiment 2 of the present application;

[0048] Figure 16 Figure 8 is a schematic diagram of the device structure in Embodiment 3 of the present application.

[0049] 1 is a source electrode, 2 is a polysilicon gate, 3 is a Schottky contact metal, 4 is a P+ contact region, 5 is an N+ contact region, 6 is a P-body region, 7 is a gate dielectric, 8 is a P+ shield region, 9 is an N-type epitaxial layer, 10 is an N-type substrate, and 11 is a drain electrode. DETAILED DESCRIPTION

[0050] The present application is described herein with reference to specific embodiments thereof which are illustrated in the attached drawings. These embodiments are described in detail and are sufficient for those skilled in the art to understand the present application. Other advantages and effects of the present application can be easily understood by those skilled in the art from the description herein. The present application can be implemented or applied in different specific embodiments, and the details in the description herein can be modified or changed based on different viewpoints and applications without departing from the spirit of the present application.

[0051] Embodiment 1

[0052] As Figure 2As shown, the high-reliability silicon carbide MOSFET device integrated with reverse SBD of the embodiment comprises an N-type substrate 10, an N-type epitaxial layer 9 above the N-type substrate 10, a P+shield region 8 in the N-type epitaxial layer 9, a Schottky contact metal 3 above the P+shield region 8 and forming a Schottky contact with the P+shield region 8, a source electrode 1 above the Schottky contact metal 3, a gate dielectric 7 above the P+shield region 8 and a polysilicon gate 2 inside the gate dielectric 7, a P-body region 6 above the N-type epitaxial layer 9, a P+contact region 4 and an N+contact region 5 above the P-body region 6 and forming an ohmic contact with the source electrode 1, a drain 11 below the N-type substrate 10 and forming an ohmic contact with the N-type substrate 10, the P+contact region 4 and the N+contact region 5 being on both sides of the gate dielectric 7 and below the source electrode 1.

[0053] The source electrode 1 is T-shaped, comprising a source electrode horizontal segment above the P+contact region 4 and the N+contact region 5, a source electrode vertical segment between the gate dielectric 7, the source electrode horizontal segment forming an ohmic contact with the P+contact region 4 and the N+contact region 5, and the source electrode vertical segment being connected with the Schottky contact metal 3.

[0054] The P+shield region 8 exists in the N-type epitaxial layer 9 below the Schottky contact metal 3 and the gate dielectric 7. A Schottky contact exists between the P+shield region 8 and the Schottky contact metal 3, forming a Schottky diode, and the direction of the Schottky diode is from the P+shield region 8 to the Schottky contact metal 3.

[0055] The working principle of the embodiment is as follows:

[0056] When the device works in an on state, the SBD between the P+shield region 8 and the Schottky contact metal is not opened, at this time the P+shield region 8 is floating, and the depletion region of the PN junction formed by the P+shield region 8 and the N-type epitaxial layer 9 has little effect on the resistance of the JFET region.

[0057] When the device works in an off state, the SBD between the P+shield region 8 and the Schottky contact metal is opened, at this time the P+shield region 8 is grounded, which plays a role in moderating the electric field borne by the gate dielectric 7 and improving the gate oxide reliability of the silicon carbide MOSFET device.

[0058] When short circuit occurs, the potential of P+shield region rises until SBD opens, at which time P+shield region is grounded, and due to the rapid rise in temperature of the device when short circuit occurs, the Schottky barrier is lowered, the potential of P+shield region is further lowered, the depletion region of the PN junction formed by P+shield region and N-type epitaxial layer is expanded, the conduction path of current is narrowed, the short circuit current is reduced, and the short circuit reliability of the device is improved.

[0059] As shown in Figures 3-14 The embodiment also provides a preparation method of the high-reliability silicon carbide MOSFET device integrated with reverse SBD, including the following steps:

[0060] First step: cleaning the epitaxial wafer, implanting aluminum ions on the N-type epitaxial layer to form a P-body region with an oxide layer as an implantation barrier;

[0061] Second step: implanting nitrogen ions to form an N+contact region with the oxide layer as an implantation barrier;

[0062] Third step: implanting aluminum ions to form a P+contact region with the oxide layer as an implantation barrier and activating annealing;

[0063] Fourth step: etching a trench;

[0064] Fifth step: implanting aluminum ions to form a P+shield region at the bottom of the trench with the oxide layer as an implantation barrier;

[0065] Sixth step: dry oxygen oxidation to generate a gate oxide layer, annealing under a nitrogen atmosphere and patterning the gate oxide;

[0066] Seventh step: depositing polysilicon and etching the polysilicon;

[0067] Eighth step: wet oxygen oxidation to isolate the polysilicon;

[0068] Ninth step: depositing an ohmic contact metal for the source and sintering at 700°C or above;

[0069] Tenth step: etching the gate oxide at the bottom of the trench;

[0070] Eleventh step: depositing a Schottky contact metal at the bottom of the trench and sintering at 500°C or below;

[0071] Twelfth step: depositing and etching the source, drain and gate metal to form an ohmic contact electrode.

[0072] Embodiment 2:

[0073] As shown in Figure 15As shown, the embodiment provides a high-reliability silicon carbide MOSFET device integrated with reverse SBD, which comprises an N-type substrate 10, an N-type epitaxial layer 9 above the N-type substrate 10, P+shield regions 8 on both sides in the N-type epitaxial layer 9, a Schottky contact metal 3 above the P+shield regions 8 and forming a Schottky contact with the P+shield regions 8, a source electrode 1 comprising a horizontal segment and vertical segments on both sides, the vertical segments of the source electrode 1 being above the Schottky contact metal 3, the horizontal segment of the source electrode 1 being above P+contact regions 4 and N+contact regions 5, a gate dielectric 7 comprising middle gate dielectric and side gate dielectric, the side gate dielectric being above the P+shield regions 8 and on both sides of the vertical segments of the source electrode 1, the middle gate dielectric being in the middle of the N-type epitaxial layer 9 and below the horizontal segment of the source electrode 1, a polysilicon gate 2 inside the middle gate dielectric, P-body regions 6 above the N-type epitaxial layer 9 between the side gate dielectric and the middle gate dielectric, the P+contact regions 4 and the N+contact regions 5 above the P-body regions 6 and forming ohmic contact with the source electrode 1, and a drain 11 below the N-type substrate 10 and forming ohmic contact with the N-type substrate 10.

[0074] The source electrode 1 is connected with the Schottky contact metal 3, the P+shield regions 8 exist in the N-type epitaxial layer 9 below the Schottky contact metal 3 and the gate dielectric 7, the Schottky contact exists between the P+shield regions 8 and the Schottky contact metal 3, forming a Schottky diode, and the direction of the Schottky diode is from the P+shield regions 8 to the Schottky contact metal 3. When the device works in the on state, the SBD between the P+shield regions 8 and the Schottky contact metal is not opened, at this time the P+shield regions 8 are floating, and the PN junction depletion region formed by the P+shield regions 8 and the N-type epitaxial layer 9 has little effect on the resistance of the JFET region; when the device works in the blocking state, the SBD between the P+shield regions 8 and the Schottky contact metal is opened, at this time the P+shield regions 8 are grounded, which plays a role in moderating the electric field borne by the gate dielectric 7 and improving the gate oxide reliability of the silicon carbide MOSFET device; when a short circuit occurs, the potential of the P+shield regions rises until the SBD is opened, at this time the P+shield regions are grounded, and because the temperature of the device rises rapidly when the short circuit occurs, the Schottky barrier is reduced, the potential of the P+shield regions will be further reduced, the PN junction depletion region formed by the P+shield regions and the N-type epitaxial layer is expanded, the conduction path of the current is narrowed, the short-circuit current is reduced, and the short-circuit reliability of the device is improved.

[0075] Compared with the embodiment 1, the embodiment does not need to adopt a split gate structure, i.e., does not need to split the polysilicon gate 2, thereby reducing the process difficulty.

[0076] Embodiment 3:

[0077] As Figure 16As shown, the embodiment provides a high-reliability silicon carbide MOSFET device integrated with a reverse SBD, which comprises an N-type substrate 10, an N-type epitaxial layer 9 located above the N-type substrate 10, a P+ contact region 4 located above the left side of the inside of the N-type epitaxial layer 9, a P+shield region 8 located above the right side of the inside of the N-type epitaxial layer 9, a gate dielectric 7 located in the middle of the N-type epitaxial layer 9, a polysilicon gate 2 located in the inside of the gate dielectric 7, the P+shield region 8 in contact with the bottom and the right side of the gate dielectric 7, an N+ contact region 5 located between the P+ contact region 4 and the gate dielectric 7, a P-body region 6 located below the N+ contact region 5, a source electrode 1 located above the P+ contact region 4, the N+ contact region 5, the gate dielectric 7 and the P+shield region 8, and a Schottky contact metal 3 located above the P+shield region 8 and forming a Schottky contact with the P+shield region 8, the Schottky contact metal 3 being located below the source electrode 1.

[0078] A drain 11 is located below the N-type substrate 10 and forms an ohmic contact with the N-type substrate 10.

[0079] The source electrode 1 is connected with the Schottky contact metal 3, and a Schottky contact exists between the P+shield region 8 and the Schottky contact metal 3, forming a Schottky diode, and the direction of the Schottky diode is from the P+shield region 8 to the Schottky contact metal 3. When the device works in a conducting state, the SBD between the P+shield region 8 and the Schottky contact metal is not opened, at this time, the P+shield region 8 is floating, and the PN junction depletion region formed by the P+shield region 8 and the N-type epitaxial layer 9 has little effect on the resistance of the JFET region; when the device works in a blocking state, the SBD between the P+shield region 8 and the Schottky contact metal is opened, at this time, the P+shield region 8 is grounded, which plays a role in moderating the electric field borne by the gate dielectric 7 and improving the gate oxide reliability of the silicon carbide MOSFET device; when a short circuit occurs, the potential of the P+shield region rises until the SBD is opened, at this time, the P+shield region is grounded, and because the temperature of the device rises rapidly when the short circuit occurs, the Schottky barrier is reduced, the potential of the P+shield region is further reduced, the PN junction depletion region formed by the P+shield region and the N-type epitaxial layer is expanded, the conduction path of the current is narrowed, the short-circuit current is reduced, and the short-circuit reliability of the device is improved.

[0080] Comparison between the embodiment and embodiment 1: the figure of the embodiment is a half cell of the device, the P-shield region 8 is formed between the two adjacent trenches, and the PN junction depletion region formed by the P-shield region 8, the P+ contact region 4 and the N-type epitaxial layer protects the oxide layer, and reduces the short-circuit peak current density.

Claims

1. A high-reliability silicon carbide MOSFET device with integrated reverse SBD, characterized in that... include: The N-type substrate (10), the N-type epitaxial layer (9) above the N-type substrate (10), the P+shield region (8) within the N-type epitaxial layer (9), the Schottky contact metal (3) above the P+shield region (8) and forming a Schottky contact with the P+shield region (8), the source electrode (1) above the Schottky contact metal (3), the gate dielectric (7) above the P+shield region (8) and the polysilicon gate (2) inside the gate dielectric (7), the P-body region (6) above the N-type epitaxial layer (9), the P+ contact region (4) and the N+ contact region (5) above the P-body region (6) and forming an ohmic contact with the source electrode (1), and the drain electrode (11) below the N-type substrate (10) and forming an ohmic contact with the N-type substrate (10), wherein the P+ contact region (4) and the N+ contact region (5) are located on both sides of the gate dielectric (7) and below the source electrode (1).

2. The high-reliability silicon carbide MOSFET device with integrated reverse SBD according to claim 1, characterized in that: The source electrode (1) is T-shaped, including a horizontal segment of the source electrode above the P+ contact area (4) and the N+ contact area (5), and a vertical segment of the source electrode between the gate dielectric (7). The horizontal segment of the source electrode (1) forms an ohmic contact with the P+ contact area (4) and the N+ contact area (5), and the vertical segment of the source electrode (1) is connected to the Schottky contact metal (3).

3. A high-reliability silicon carbide MOSFET device with integrated reverse SBD according to claim 1, characterized in that: There is a Schottky contact between the P+shield region (8) and the Schottky contact metal (3), forming a Schottky diode, and the direction of the Schottky diode is from the P+shield region (8) to the Schottky contact metal (3).

4. A high-reliability silicon carbide MOSFET device with integrated reverse SBD as described in claim 1 of any one of claims 1 to 3, characterized in that: The gate dielectric (7) is SiO2 or a high-K dielectric.

5. A high-reliability silicon carbide MOSFET device with integrated reverse SBD as described in claim 1 of any one of claims 1 to 3, characterized in that: The doping types in the device are reversed accordingly, that is, P-type doping becomes N-type doping while N-type doping becomes P-type doping.

6. A method for fabricating a high-reliability silicon carbide MOSFET device with integrated reverse SBD according to any one of claims 1 to 3, characterized in that, Includes the following steps: Step 1: Clean the epitaxial wafer, and implant aluminum ions into the N-type epitaxial layer using the oxide layer as an implantation barrier to form a P-body region; Step 2: Nitrogen ions are injected into the oxide layer as an injection barrier to form an N+ contact region; Step 3: Using the oxide layer as an injection barrier layer, aluminum ions are injected to form a P+ contact region and annealing is activated. Step 4: Etching grooves; Step 5: Using the oxide layer as an injection barrier, aluminum ions are injected at the bottom of the trench to form a P+ shield region; Step 6: Dry oxygen oxidation to generate the gate oxide layer, annealing in a nitrogen atmosphere and patterning the gate oxide; Step 7: Deposit and etch polysilicon; Step 8: Wet oxygen oxidation to isolate polycrystalline silicon; Step 9: Deposit ohmic contact metal at the source electrode and sinter at temperatures above 700°C; Step 10: Etch the gate oxide at the bottom of the trench; Step 11: Deposit Schottky contact metal at the bottom of the tank and sinter at below 500°C; Step 12: Deposit and etch the source, drain, and gate metals to form ohmic contact electrodes.

7. A high-reliability silicon carbide MOSFET device with integrated reverse SBD, characterized in that: The system includes an N-type substrate (10), an N-type epitaxial layer (9) located above the N-type substrate (10), P+ shield regions (8) on both sides of the N-type epitaxial layer (9), and a Schottky contact metal (3) forming a Schottky contact with the P+ shield regions (8) above the P+ shield regions (8). The source electrode (1) includes a horizontal segment and vertical segments on both sides. The vertical segment of the source electrode (1) is located above the Schottky contact metal (3). The horizontal segment of the source electrode (1) is located above the P+ contact region (4) and the N+ contact region (5). The gate dielectric (7) includes a middle gate dielectric and gate dielectrics on both sides. The two gate dielectrics are located above the P+shield region (8) and on both sides of the vertical segment of the source electrode (1). The middle gate dielectric is located in the middle of the N-type epitaxial layer (9) and below the horizontal segment of the source electrode (1). A polysilicon gate (2) is provided inside the middle gate dielectric. A P-body region (6), a P+ contact region (4) and an N+ contact region (5) located above the P-body region (6) and forming an ohmic contact with the source electrode (1) are provided above the N-type epitaxial layer (9) between the two gate dielectrics and the middle gate dielectric. A drain electrode (11) forming an ohmic contact with the N-type substrate (10) is provided below the N-type substrate (10).

8. A high-reliability silicon carbide MOSFET device with integrated reverse SBD, characterized in that: The structure includes an N-type substrate (10), an N-type epitaxial layer (9) located above the N-type substrate (10), a P+ contact region (4) on the upper left side of the N-type epitaxial layer (9), a P+ shield region (8) on the right side, a gate dielectric (7) in the middle, a polysilicon gate (2) inside the gate dielectric, the P+ shield region (8) in contact with the bottom and right side of the gate dielectric (7), an N+ contact region (5) between the P+ contact region (4) and the gate dielectric (7), a P-body region (6) below the N+ contact region (5), a source electrode (1) above the P+ contact region (4), the N+ contact region (5), the gate dielectric (7) and the P+ shield region (8), a Schottky contact metal (3) forming a Schottky contact with the P+ shield region (8) above the P+ shield region (8), and the Schottky contact metal (3) located below the source electrode (1). A drain (11) is provided below the N-type substrate (10) to form an ohmic contact with the N-type substrate (10).

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