ToF system

Abstract

Embodiments of the present invention relate to a ToF system. In one embodiment, a method includes: resetting respective count values ​​of a plurality of analog counters to initial count values, each analog counter in the plurality of analog counters corresponding to a histogram bin of a time-of-flight (ToF) histogram; receiving a plurality of digital addresses from a time-to-digital converter (TDC) after resetting the respective count values; during an integration period, for each received digital address, selecting an analog counter based on the received digital address and changing the respective count value of the selected one analog counter by a discrete amount toward a second count value, wherein each analog counter has a final count value at the end of the integration period; and after the integration period, determining a corresponding final bin count for each histogram bin of the ToF histogram based on the final count value of the corresponding analog counter.

Description

Technical Field

[0001] The present disclosure relates generally to electronic systems and methods, and in particular embodiments to time-of-flight (ToF) systems. Background Art

[0002] Devices for determining the distance (or range) to an object are known. One method for determining the distance to an object is called time of flight (ToF). This method involves sending a light signal toward the object and measuring the time it takes for the signal to propagate to the object and back. The time it takes for the signal to make this propagation can be calculated by measuring the time difference between the signal emanating from the light source and the signal reflected from the object and detected by a light sensor. Knowing this time difference and the speed of light allows the distance to the object to be determined.

[0003] Single-photon avalanche diodes (SPADs) can be used as detectors of reflected light. Typically, a SPAD array is provided as a sensor to detect reflected light pulses. Photons can generate carriers in the SPADs through the photoelectric effect. The photogenerated carriers can trigger an avalanche current in one or more of the SPADs in the SPAD array. The avalanche current can signal an event, i.e., a photon of light has been detected.

[0004] A time-to-digital converter (TDC) can be used to calculate the time difference between the emission time of light and the arrival time of the reflected light to obtain the distance to the object.

[0005] The detector (e.g., a SPAD array) is configured to generate many rapid readings in a short period of time. Therefore, a histogram of detected events (e.g., received photons) is typically generated, where the arrival times of the detected events are quantized in histogram bins, which can be post-processed to identify the positions / distances of multiple targets within the detector's field of view (FoV).

[0006] Direct ToF (DTOF) image sensors use ToF technology to determine the distance to an object to provide, for example, a 3D depth map. A DTOF image sensor typically includes an image capture mechanism, data converter(s), and timing generation circuitry. Summary of the Invention

[0007] According to one embodiment, a method includes resetting respective count values ​​of a plurality of analog counters to initial count values, each analog counter in the plurality of analog counters corresponding to a histogram bin of a time-of-flight (ToF) histogram. 箱); after resetting respective count values ​​of the plurality of analog counters, receiving a plurality of digital addresses from a time-to-digital converter (TDC), the TDC having an input coupled to a single photon avalanche diode (SPAD); during an integration period, for each received digital address in the plurality of digital addresses, selecting one of the plurality of analog counters based on the received digital address, and changing the respective count value of the selected one of the analog counters by a discrete amount toward a second count value, the second count value being different from the initial count value, wherein each of the analog counters has a final count value at an end of the integration period; and after the integration period, determining an associated final bin count for each histogram bin of the ToF histogram based on the final count value of the corresponding analog counter.

[0008] According to one embodiment, a time-of-flight (ToF) system includes: a plurality of single-photon avalanche diodes (SPADs), the SPADs configured to generate SPAD events; a plurality of time-to-digital converters (TDCs) coupled to the plurality of SPADs, wherein each of the plurality of TDCs is configured to generate a digital address based on the SPAD events generated by a corresponding SPAD in the plurality of SPADs; a plurality of histogram generation circuits, each of the plurality of histogram generation circuits coupled to a corresponding TDC in the plurality of TDCs, wherein each histogram generation circuit includes: an addressing logic circuit having a plurality of outputs and an input configured to receive a digital address from the corresponding TDC, and a plurality of analog counters, wherein each of the plurality of analog counters includes an input coupled to a corresponding output of the plurality of outputs of the addressing logic circuit, wherein each analog counter includes an associated storage capacitor; and an analog-to-digital converter (ADC) coupled to the plurality of analog counters, wherein: each histogram generation circuit is configured to reset a voltage of an associated storage capacitor of each analog counter to a first voltage, the addressing logic circuit being configured to, for each received digital address, select one of the plurality of analog counters based on the received digital address and assert an input of the selected one of the analog counters after resetting the plurality of analog counters during an integration period, wherein the selected one of the analog counters is configured to change a voltage of an associated storage capacitor of the selected one of the analog counters by a discrete voltage toward a second voltage when the input of the selected one of the analog counters is asserted, wherein the associated storage capacitor of each analog counter is configured to have a final voltage at an end of the integration period, and the ADC being configured to convert the final voltage of the associated storage capacitor of each analog counter into a corresponding digital count, wherein each digital count is associated with a histogram bin of a ToF histogram, and wherein the associated final bin count for each histogram bin of the ToF histogram is based on the associated digital count.

[0009] According to one embodiment, a time-of-flight (ToF) system includes: a single-photon avalanche diode (SPAD) array, the SPAD array including a pixel array, each pixel of the pixel array including a SPAD and a SPAD front-end circuit; a plurality of time-to-digital converters (TDCs) coupled to corresponding SPADs of the SPAD array, wherein each of the plurality of TDCs is configured to generate a digital address based on a SPAD event generated by the corresponding SPAD, wherein each of the digital addresses includes m bits, where m is a positive integer greater than or equal to 1; a plurality of histogram generation circuits, each of the plurality of histogram generation circuits including: an addressing logic circuit having n outputs and an input configured to receive a digital address from the corresponding TDC, and n analog counters, where n is equal to 2 m , wherein each of the n analog counters includes an input coupled to a respective one of the n outputs of the addressing logic circuit, wherein each analog counter includes an associated storage capacitor, n first logic gates, each of the n first logic gates having a first input coupled to the n outputs of the addressing logic circuit, respectively, and a pulse control circuit having an output coupled to a second input of each of the n first logic gates; and an analog-to-digital converter (ADC) coupled to the n analog counters. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] For a more complete understanding of the present invention and its advantages, reference is now made to the following description taken in conjunction with the accompanying drawings, in which:

[0011] Figure 1 A time-of-flight (ToF) imaging system according to an embodiment of the present invention is shown;

[0012] Figure 2 and Figure 3 The embodiment according to the present invention is shown Figure 1 TDC and Figure 1 The corresponding histogram generation circuit is coupled to Figure 1 Schematic diagram of a possible implementation of a SPAD array;

[0013] Figure 4 The diagram showing an embodiment of the present invention is based on Figure 1 A diagram showing a process of generating a ToF histogram by ToF measurement of a ToF imaging system;

[0014] Figure 5 shows a schematic diagram of a portion of a ToF system illustrating a histogram generation circuit according to an embodiment of the present invention;

[0015] Figure 6 and Figure 7 1 shows a flow chart of an embodiment method for generating and reading a ToF histogram according to an embodiment of the present invention;

[0016] Figure 8 The embodiment of the present invention is shown in Figure 7 A timing diagram for decrementing a simulated counter during execution of the method;

[0017] Figure 9 and Figure 10 A diagram showing an embodiment of the present invention Figure 5 Schematic diagram of a portion of a ToF system including an analog-to-digital converter (ADC);

[0018] Figure 11 The embodiment according to the present invention is shown Figure 9 A schematic diagram of a portion of an ADC;

[0019] Figure 12 The embodiment according to the present invention is shown Figure 5 Schematic diagram of an analog counter;

[0020] Figure 13 The embodiment of the present invention is shown in Figure 7 During the execution of the method Figure 12 Timing diagram of the waveform associated with the analog counter;

[0021] Figure 14 The embodiment according to the present invention is shown Figure 5 Schematic diagram of an analog counter;

[0022] Figure 15 and Figure 16 shows a diagram illustrating a portion of a ToF system according to an embodiment of the present invention;

[0023] Figure 17 A diagram showing an embodiment of the present invention Figure 16 A top view of a possible layout of a portion of a ToF system (not to scale);

[0024] Figure 18 and Figure 19 A low voltage digital signal (LVDS) latch according to an embodiment of the present invention is shown;

[0025] Figure 20A and Figure 20B 1. FIG. 1 shows a pixel as part of a SPAD array and a corresponding timing diagram according to an embodiment of the present invention, respectively;

[0026] Figure 21 shows a diagram illustrating a portion of a ToF system according to an embodiment of the present invention;

[0027] Figure 22 A diagram showing an embodiment of the present invention Figure 21 FIG. 1 is a perspective view of a possible layout of a portion of a ToF system;

[0028] Figure 23A shows a pixel according to an embodiment of the present invention;

[0029] Figure 23B A diagram showing an embodiment of the present invention is shown by Figure 23A A timing diagram of the differential signal received by the pixel;

[0030] Figure 24A shows a pixel according to an embodiment of the present invention;

[0031] Figure 24B The embodiment of the present invention shows Figure 24A Different operation modes of pixels Figure 24A the status of the switch; and

[0032] Figure 25 The embodiment according to the present invention is shown Figure 24A Self-referenced control circuit.

[0033] Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated.The figures are drawn to clearly illustrate the relevant aspects of the preferred embodiments and are not necessarily drawn to scale. DETAILED DESCRIPTION

[0034] The making and using of the disclosed embodiments are discussed in detail below. However, it should be understood that the present invention provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the invention and are not intended to limit the scope of the invention.

[0035] The following description explains various specific details to provide an in-depth understanding of several example embodiments according to this specification. These embodiments can be obtained without one or more of these specific details, or can be obtained by other methods, components, materials, etc. In other cases, known structures, materials, or operations are not shown or described in detail to avoid confusing different aspects of the embodiments. References to "embodiments" in this specification indicate that the specific configuration, structure, or feature described in connection with the embodiment is included in at least one embodiment. Therefore, phrases such as "in one embodiment" that may appear in different places in this specification do not necessarily refer to the same embodiment. In addition, specific formation methods, structures, or features can be combined in any appropriate manner in one or more embodiments.

[0036] Embodiments of the present invention will be described in a specific context, including a ToF system using a ToF histogram generation circuit based on a charge transfer amplifier (CTA) analog counter, and a SPAD array including a plurality of SPAD sensor pixels. Embodiments of the present invention can be used with other types of analog counters, other types of ToF sensors, and / or other types of ToF pixel designs. Some embodiments can be implemented in other types of applications, such as applications that can benefit from CTA-based analog counters and / or SPAD sensor pixels.

[0037] In an embodiment of the present invention, multiple analog integrators are used to determine and store histogram bin counts based on related SPAD events from one or more SPADs. Digital addressing (e.g., using a decoder) based on the output from the TDC is used to select the analog integrator (histogram bin) to be incremented. A (e.g., shared) analog-to-digital converter (ADC) is used to read the bin count from each of the analog integrators associated with the one or more SPADs. In some embodiments, the analog integrator operating as an analog counter is implemented in the pixel. In some embodiments, the analog counter is implemented with a charge transfer amplifier (CTA).

[0038] By using digital addressing, some embodiments advantageously can use analog counters to achieve histogram generation speeds similar to those achieved in implementations relying on SRAM or parallelized counters. In some embodiments, the use of analog counters can advantageously achieve lower power operation and / or a smaller area compared to implementations relying on SRAM or parallelized counters.

[0039] In some embodiments, a (e.g., shared) ADC uses a self-referencing ramp generated in cooperation with the analog integrator to determine the bin counts of the analog integrator. In some embodiments, using a self-referencing ADC can advantageously improve linearity, achieve a larger count range (e.g., by allowing a smaller step size ΔV), reduce noise, and achieve good matching between histogram bins, e.g., when compared to an implementation that does not use a self-referencing ADC.

[0040] In some embodiments, low voltage digital signal (LVDS) latches are used for clock distribution in the ToF system. In some embodiments, using LVDS latches for clock distribution advantageously allows clock propagation with low power consumption and / or zero quiescent current within the pixel.

[0041] In some embodiments, the TDC can be implemented using one or more LVDS latches. In some embodiments, the LVDS latch can simultaneously operate as a TDC and as a decoder for digital addressing of multiple analog counters and / or as a comparator for a self-referenced ADC. In some embodiments, reusing the LVDS latches to receive clock signals, perform TDC operations, digital addressing operations, and / or comparator operations for the self-referenced ADC can advantageously enable low-power and compact implementations of histogram generation and readout circuitry. In some embodiments, part or all of the histogram generation circuitry can be implemented within the pixel.

[0042] Additional advantages of some embodiments include implementing a ToF system with a smaller area and lower power ToF pixel using LVDS latches and CTA-based analog counters. Some embodiments can implement a small area and lower power pixel design in a ToF system using a large ToF sensor array (e.g., a SPAD array) such as one with more than 1 megapixel.

[0043] Optical ranging devices using ToF technology rely on detecting return signals from objects (targets) in their field of view (FoV) to determine the range of these objects from the ranging device. Figure 1 A ToF system (e.g., a DTOF system) 100 according to an embodiment of the present invention is shown. The ToF system 100 includes an illumination source 106, a SPAD array 104, a plurality of TDCs 102, a plurality of histogram generation circuits 118, a processor 110, and a timing generation circuit 108. Routing circuitry 112 couples the SPADs of the SPAD array 104 to the TDCs 102 (e.g., via metal traces and / or logic circuit(s)).

[0044] During normal operation, illumination source 106 transmits light pulses 122 toward object 116, e.g., at times controlled by timing generator circuit 108. Reflected light pulses 124 are sensed by SPAD array 104 and routed to TDC 102 by routing circuit 112. TDC 102 generates a digital representation of the time between the emission of light pulse 122 and the receipt of reflected light pulse 124. Histogram generation circuit 118 generates a ToF histogram based on the output of TDC 102. Processor 110 then processes the ToF histogram, e.g., in a known manner, to determine the distance to object 116 and / or generate a 3D depth map.

[0045] A ToF histogram can be understood as a histogram having bins corresponding to different times from the emission of a light pulse (e.g., 122). Typically, lower bins (e.g., decimal bins 1 and 2, or equivalent binary bins 00 and 01) correspond to shorter times (and therefore closer targets), while higher bins (e.g., decimal bins 9 and 10, or equivalent binary bins 1001 and 1010) correspond to longer times (and therefore farther targets). In some embodiments, a ToF histogram with multiple bins (e.g., 4, 8, 64, 128, or more bins) allows for DTOF operation, e.g., where a pulsed light source (e.g., 106) is used and the distance to the target(s) is calculated directly based on the peak(s) of the ToF histogram.

[0046] The illumination source 106 can be implemented in any manner known in the art. For example, the illumination source 106 can be implemented as a vertical cavity surface emitting laser (VCSEL). Other implementations are also possible.

[0047] Processor 110 may be implemented as a general-purpose digital signal processor (DSP), a processor or controller including, for example, a combination of circuits coupled to a memory. For example, in some embodiments, processor 110 is configured to execute instructions stored in the memory. Processor 110 may also be implemented as a custom application-specific integrated circuit (ASIC). Other implementations are also possible.

[0048] In some embodiments, the timing generation circuit 108 generates, for example, a periodic signal CLK trigger (CLK trigger ) to trigger the illumination source 106 to emit the light pulse 122. In some embodiments, the timing generation circuit 108 also provides a signal CLK indicating the emission time of the light pulse 122 to the TDC 102 采样 (CLK sample ), for example, to serve as a reference signal. In some embodiments, the signal CLK 采样 Multiple out-of-phase clock signals may be included. For example, in some embodiments, m clock signals (such as m out-of-phase differential clock signals) may be provided to TDC 102, where TDC 102 is configured to generate an m-bit digital address. In some embodiments, signal CLK 采样 The timing generation circuit 108 may be implemented in any manner known in the art.

[0049] TDC 102 generates a signal indicating a reference time (eg, a signal CLK 采样The output of the time between the SPAD event (given) and the event time (e.g., the activation time of the SPAD). In some embodiments, the TDC 102 can be implemented in any manner known in the art. For example, the TDC 102 can be implemented using multiple flip-flops that update their states based on one or more reference clocks, and the TDC 102 determines the time between the SPAD event and the reference based on the states of the flip-flops when the multiple flip-flops receive the SPAD event. In some embodiments, the TDC uses multiple out-of-phase clocks to update the states of the TDC's flip-flops. Other implementations are also possible.

[0050] The SPAD array 104 may include, for example, a plurality of pixels arranged in rows and columns, wherein each pixel includes one or more SPADs (e.g., 202, 302, 2002, respectively). Figure 2 、 Figure 3 and FIG20 ) and SPAD front-end circuits (eg, 2004, 2404, as shown in FIG20 and FIG24 , respectively). Other implementations are also possible.

[0051] As will be described in more detail later, in some embodiments, the TDC and the histogram generation circuitry may be implemented inside the pixels of the SPAD array.In some embodiments, the TDC may be part of the histogram generation circuitry.

[0052] In some embodiments, each SPAD of the SPAD array 104 is coupled to a corresponding TDC 102. In some embodiments, multiple SPADs share the same TDC 102 via, for example, an OR tree. Figure 2 and Figure 3 A schematic diagram illustrating a possible implementation of the coupling of a TDC 102 and corresponding histogram generation circuit 118 to a SPAD array 104 according to an embodiment of the present invention is shown.

[0053] like Figure 2 As shown, in some embodiments, each pixel of the SPAD array 104 includes a single SPAD 202, and each TDC 102 can be coupled to the single SPAD 202 via one or more buffers 204 (where the buffers 204 are part of the routing circuit 112). In some embodiments, one or more inverters can be used instead of or in addition to the one or more buffers 204.

[0054] like Figure 3As shown, in some embodiments, each pixel of the SPAD array 104 includes multiple SPADs 202, and each TDC 102 can be coupled to multiple SPADs 302 via an OR tree 304 (where the OR tree 304 is part of the routing circuit 112). Different numbers of SPADs can be used for each pixel of the SPAD array 104, such as 2, 4, 6, 10, 16, etc.

[0055] The histogram generation circuit 118 is configured to generate a ToF histogram based on the output of the corresponding TDC 102. For example, Figure 4 A diagram illustrating a process of generating a ToF histogram based on ToF measurements of the ToF system 100 according to an embodiment of the present invention is shown.

[0056] During normal operation, for each transmitted light pulse 122, the TDC 102 measures the transmitted light pulse 122 (eg, based on the signal CLK 采样 ) and the received reflected light pulse 124 (eg, based on the TDC input signal In 102 ) and sends a digital code Out indicating the time Δt to the histogram generation circuit 118 102 The histogram generation circuit 118 receives the digital code Out 102 And increment with digital code Out 102 Associated histogram bins. As will be described in more detail later, histogram bins and incrementing of histogram bins can be implemented using analog counters.

[0057] In some embodiments, the digital code Out 102 It can be, for example, a 7-bit word. In some embodiments, the digital code Out 102 It can be implemented with less than 7 bits (such as 6 bits, 4 bits or less), or with more than 7 bits (such as 8 bits or more). 102 Also known as digital address Out 102 .

[0058] In some embodiments, the digital code Out 102 Using binary coding, the digital code Out 102 Corresponds to the binary address of the histogram bin. For example, when the digital code Out 102 When digital code Out102 is 10, bin 2 is incremented, when digital code Out102 is 101, bin 5 is incremented, etc. Other implementations are possible.

[0059] Histogram generation can be performed on-chip (e.g., in the same integrated circuit as the image sensor (such as a SPAD array) is located), or off-chip (e.g., in a circuit external to the integrated circuit that includes the image sensor). Off-chip histogram generation can advantageously allow the use of a fast, powerful processor to generate the ToF histogram. On-chip histogram generation can advantageously avoid outputting an event signal (e.g., a SPAD event) or raw TDC data from each pixel of the image sensor (e.g., a SPAD or a group of SPADs), which can advantageously reduce the output data rate and reduce power consumption. For example, in some embodiments, the on-chip implementation of histogram generation can achieve a data compression rate that is proportional to the amount of data being generated. For example, in some embodiments, the on-chip implementation of histogram generation can achieve Num_TDC_Timestamps·TDC_bit_depth with num_bins·2 bit_depth_per_bin The data compression ratio is , where Num_TDC_Timestamps represents the number of timestamps of the TDC 102, TDC_bit_depth represents the bit depth of the TDC 102, bit_depth_per _箱 represents the bit depth of each bin of the histogram generated by the histogram generation circuit 118, num _箱s represents the number of bins of the histogram generated by the histogram generation circuit 118. For example, 1024 photons triggering an 8b TDC timestamp (for external processing) and an 8b TDC plus histogram with 256 bins (8b per bin) can result in (1024×8=)8192b transmitted at a very high frequency (when the illumination source 106 is triggered during the integration time) for external processing, compared to (256×8=)2048b of histogram for the internal on-chip histogram, which is transmitted at a lower frequency after the integration time, resulting in a compression ratio of 4 in this example. The compression ratio can be higher than 4. For example, in some embodiments, the on-chip implementation of histogram generation can achieve data compression (data output from the histogram generation circuit 118) of approximately 256 times or greater compared to outputting the raw TDC data.

[0060] In some embodiments, the SPAD array 104, routing circuit 112, TDC 102, and histogram generation circuit 118 can be implemented in the same integrated circuit (IC). In some embodiments, the same IC also includes the illumination source 106 and the timing generation circuit 108, and / or part or all of the processor 110. In some embodiments, the TDC 102 and the histogram generation circuit 118 are disposed adjacent to the SPAD array 104. In some embodiments, the ToF system can include the TDC 102 and the histogram generation circuit 118 disposed within the SPAD array. For example, in some embodiments, each pixel of the SPAD array has a corresponding TDC 102 and histogram generation circuit 118. Other implementations are also possible.

[0061] Figure 5 A schematic diagram of a portion of a ToF system 500 illustrating a histogram generation circuit 518 according to an embodiment of the present invention is shown. The ToF system 100 may be implemented as the ToF system 500. Each histogram generation circuit 118 may be implemented as the histogram generation circuit 518.

[0062] During normal operation, in response to the TDC input signal In 102 Activation (e.g., signal In 102 Pulsing), TDC102 sends digital code Out to addressing logic circuit 504 102 , and the input signal In 502 In response to receiving the digital code Out 102 , the addressing logic circuit 504 activates its n outputs with the digital code Out 102 Corresponding to an output, where the digital code Out 102 For example, in an embodiment where n is equal to 128, the digital code Out 102 With log2128=7 bits, and the digital code Out 102 Each of the possible codes activates a unique output Out 504 For example, in some embodiments, when the digital code Out 102 When equal to 0, only Out is output 504_0 Is activated when the digital code Out 102 When equal to 1, only Out is output 504_1 activated, etc.

[0063] In response to input 502 The pulse control circuit 502 activates the output Out 502 Therefore, when the output Out 502When activated, the AND gates 506 all receive 1s at their first inputs, but only one of the AND gates 506 (corresponding to the AND digital code Out 102 Corresponding output Out 504 The AND gate 506 receives a 1 in its second input. As a result, only one of the n analog counters 508 is incremented.

[0064] In some embodiments, the analog counter 508 is configured to 508 When activated, it changes (e.g., increments or decrements) the internal voltage by a quantized (e.g., fixed discrete) amount (e.g., ΔV). Thus, in some embodiments, each of the n analog counters 508 serves as a storage device for a corresponding histogram bin (of the n histogram bins), e.g., where the value is stored in the voltage of the analog counter 508 (e.g., in a capacitor).

[0065] The counts stored in the analog counters 508 can be read using an analog-to-digital converter (ADC). For example, some embodiments can use a single shared ADC 510 to read (e.g., sequentially) a voltage (e.g., the voltage of a corresponding capacitor) from each of the n analog counters 508, where the read voltage indicates the count of the corresponding histogram bin. By sharing a single ADC to measure each of the voltages from each of the n analog counters 508, some embodiments advantageously reduce or minimize measurement differences between different histogram bins (e.g., reducing errors associated with offset and fixed pattern noise of difference pixels), which can advantageously produce histogram bins of the same (or approximately the same) size compared to using multiple ADCs.

[0066] The addressing logic circuit 504 can be implemented as a conventional 1-of-n decoder, where a single "hot" output is based on the digital code Out 102 is activated, while the rest of the decoder outputs remain deactivated. For example, in the digital code Out 102 In an embodiment where the word is 7 bits, the addressing logic circuit 504 may be implemented as a 1-to-128 decoder having 128 outputs coupled to 128 AND gates 506. Other implementations are also possible.

[0067] The pulse control circuit 502 is configured to activate the output Out in synchronization with the addressing logic circuit 504. 502 For example, in some embodiments, the pulse control circuit 502 may include a delay circuit that is configured to delay the input In 502 Delay time after being activated to activate output Out 502 , so that the addressing logic circuit 504 activates the digital code Out 102Corresponding output Out 504 At the same time or shortly after, output Out 502 is activated.

[0068] In some embodiments, the pulse control circuit 502 can be implemented using an inverter chain (e.g., four inverters connected in a chain). In some embodiments, one or more inverters in the inverter chain can have a load input (e.g., via a capacitor). In some embodiments, multiple inverter chains can be connected in a chain to achieve a desired delay. Other implementations, such as using other circuits to generate the delay, can also be used to implement the pulse control circuit 502.

[0069] In some embodiments, the input 502 Based on the input 102 For example, in some embodiments, 502 Can be used with In 102 In some embodiments, the input 502 Can be based on digital output Out 102 For example, in some embodiments, 502 Can respond to digital output Out 102 In some embodiments, the input 502 The address logic circuit 504 can be used to trigger the address logic circuit 504 based on the code Out 102 To update its output Out 504 The addressing logic circuit is generated by flip-flops. Other implementations are also possible.

[0070] Figure 6 A flow chart of an embodiment method 600 for generating and reading a ToF histogram according to an embodiment of the present invention is shown. The ToF systems 100 and 500 may implement the method 600 .

[0071] During step 602, the analog counter (e.g., 506) is reset. For example, each time the corresponding input of the analog counter (e.g., In 508 ) is activated, resetting the analog counters includes setting an internal voltage used to store the count of each analog counter to a full-scale value. 508) is activated, the analog counters are incremented, resetting the analog counters includes setting an internal voltage used to store the count of each analog counter to a minimum value (e.g., 0V). In some embodiments, all n analog counters (e.g., 508) are reset simultaneously (in parallel). In some embodiments, resetting the analog counters may require 100 ns. Other durations may also be used, such as less than 100 ns (e.g., 90 ns, 50 ns, or less) or greater than 100 ns (e.g., 200 ns or greater).

[0072] In some embodiments, the controller (eg, 520) is configured to provide a signal to the analog counter to cause the analog counter to be reset. In some embodiments, the controller 520 may be implemented using logic circuits and may include, for example, a state machine.

[0073] During step 604, in a process called integration, the digital code (eg, Out 102 ) sequence to increment the histogram bins of the ToF histogram (eg, 118). For example, in some embodiments, for each received digital code Out 102 Activate n inputs In 508 A single input in 508 Each time you enter 508 When activated, the corresponding analog counter 508 changes (e.g., increases or decreases) its internal voltage by a quantized value (e.g., ΔV). In some embodiments, the integration process can last for a fixed amount of time, such as 100 ns. Longer integration times, such as 200 ns, 1 ms, or longer, or shorter integration times, such as 90 ns, 50 ns, or shorter, can also be used. In some embodiments, the integration phase occurs simultaneously for all n analog counters (e.g., 508).

[0074] After the interrogation process is complete, during step 606, the internal voltage of each analog counter is measured (e.g., sequentially), for example, by a (e.g., shared) ADC (e.g., 510), or a count associated with each internal voltage is determined. During step 608, a histogram bin count associated with each analog counter is determined based on the measured voltage or the measured count. After each analog counter (e.g., 508) has a corresponding input (e.g., In 508 ) is activated, the voltage measured by the ADC is directly related to the count of the analog counter. 508) is activated, the voltage measured by the ADC is related to the full scale minus the count of the analog counter. For example, if the input In 508 If 100 activations are required to go from the full-scale internal voltage to the minimum internal voltage, and the voltage measured by the ADC corresponds to 60 (remaining) activations, the count stored in the analog counter is 100-60=40 (because 40 activations are required to go from 100 to 60).

[0075] In some embodiments, a (e.g., shared) self-referencing ADC is used to measure the terminal count of each analog counter (e.g., during step 606) and the full-scale count of each counter. By using a self-referencing ADC, some embodiments advantageously mitigate the effects of different quantization step sizes within the same analog counter and between analog counters.

[0076] Figure 7 Flowchart of an embodiment method 700 for generating and reading a ToF histogram according to an embodiment of the present invention is shown. ToF systems 100 and 500 can implement method 700. Method 700 includes steps 602, 604, 606, 706, and 708. Steps 602, 604, and 606 can be performed in a similar manner as in method 600.

[0077] like Figure 7 As shown, after performing the signal conversion (step 606), during step 602, the analog counter is reset again. After resetting the analog counter, during step 706, a full-scale conversion is performed. For example, in some embodiments, for each analog counter 508, the input In 502 Is activated multiple times until the internal voltage of the analog counter reaches a predetermined threshold.

[0078] In some embodiments, the count associated with the signal conversion phase (e.g., step 606) of an analog counter (e.g., 508) and the count associated with the full-scale conversion phase (e.g., step 706) of the same analog counter can be used to determine the histogram bin count during step 708. For example, in some embodiments, for a decrementing analog counter (e.g., 508), the ADC (e.g., 510) can measure the remaining number of activations Cnt required to reach a predetermined minimum voltage during step 606. 剩余 (Cnt remaining ) (starting from the voltage at the end of the integration process), and the total number of activations Cnt required to reach a predetermined minimum voltage starting from the full-scale voltage can be measured during step 706 满量程 (Cnt full-scale ). In some such embodiments, the histogram bin count Cnt 箱 (Cnt bin) can be given by the following formula

[0079] Cnt 箱 =Cnt 满量程 –Cnt 剩余 (1)

[0080] In some embodiments, for an incrementing analog counter (eg, 508), the ADC (eg, 510) may measure the remaining number of activations Cnt required to reach the full-scale voltage during step 606. 剩余 (starting from the voltage at the end of the integration process), and the total number of activations Cnt required to reach the full-scale voltage starting from a predetermined minimum value can be measured during step 706 满量程 In some such embodiments, the histogram bin count Cnt 箱 It can be given by Equation 1.

[0081] Figure 8 A timing diagram illustrating decrementing an analog counter (eg, 508 ) during execution of method 700 is shown in accordance with an embodiment of the present invention. Figure 8 The internal voltage V of one of the n analog counters (eg, 508) is shown. cap Can be combined with Figure 7 To understand Figure 8 .

[0082] like Figure 8 As shown, during step 602, the internal voltage V cap Reset to full-scale voltage V FS In some embodiments, all n analog counters (e.g., 508) are reset simultaneously ( Figure 8 not shown).

[0083] During the integration phase (step 604), each time the input signal In 508 When activated, the voltage V cap Decrement quantization value (ΔV). At the end of the integration phase, the voltage V cap Equal to V sig .like Figure 8 As shown, the voltage V sig Indicated voltage V cap The number of decrements (equal to the input signal In 508 In some embodiments, for all n analog counters ( Figure 8 ), the integration phase occurs simultaneously.

[0084] During the signal conversion phase (step 606), the input signal In 508 is activated (e.g., by a state machine) until the voltage V cap Reaching the reference voltage Vref In some embodiments, V ref Equal to 0.5V. For voltage V ref Other voltages may also be used, such as higher than 0.5V (e.g., 0.55V, 0.6V, or higher) or lower than 0.5V (e.g., 0.4V or lower). A counter such as a ripple counter may be used to counter the input signal In 508 is activated so that the voltage V cap From V sig Reach V ref The number of times (Cnt 剩余 ) to count.

[0085] In some embodiments, the signal conversion phase (step 606) is performed sequentially for each analog counter 508. Thus, in some embodiments, once the count Cnt of a particular analog counter is determined, 剩余 , the signal conversion step is performed for the next counter until the count Cnt is determined for all n analog counters 剩余 .

[0086] After executing the signal conversion phase (step 606) (eg, for all analog counters), the voltage V cap is reset to the full-scale voltage V FS During the full-scale conversion phase (step 706), the input signal In 508 is activated (e.g., by a state machine) until the voltage V cap Reaching the reference voltage V ref A counter such as the same ripple counter used during the signal conversion phase (step 606) may be used to counter the input signal In 508 is activated so that the voltage V cap From V FS Reach V ref The number of times (Cnt 满量程 ) to count.

[0087] In some embodiments, the full-scale conversion phase (step 706) is performed sequentially for each analog counter 508. Thus, in some embodiments, once the count Cnt of a particular analog counter is determined, 满量程 , a full-scale step is performed for the next counter until the count Cnt is determined for all n analog counters 满量程 .

[0088] In some embodiments, the ADC 510 controls the pulse control circuit 502 and the addressing logic circuit 504 to enable a specific input signal In of a specific analog counter 508 to be 508Multiple activations during the signal conversion phase (step 606) and during the full-scale conversion phase (step 706). For example, Figure 9 A schematic diagram of a portion of a ToF system 900 illustrating an ADC 910 is shown according to an embodiment of the present invention. The ToF system 500 may be implemented as the ToF system 900. The ADC 510 may be implemented as the ADC 910. The addressing logic circuit 504 may be implemented as the addressing logic circuit 904. The pulse control circuit 502 may be implemented as the pulse control circuit 902.

[0089] Figure 9 The circuitry associated with a single analog counter 508 (e.g., counter 508_i) among the n analog counters 508 is shown, where the i-th analog counter 508 can be any of the n analog counters 508. Some of the circuitry (e.g., addressing logic circuit 904, pulse control circuit 902, pulse generator 932, controller 930, multiplexer (MUX) 940, and ripple counter 934) can be shared between all n analog counters 508. Other circuitry (e.g., AND gates 506 and 936, analog counter 508, and comparator 938) can be replicated n times for each of the n histogram bins. Other implementations are also possible. For example, in some embodiments, comparator 938 can be implemented external to ADC 910.

[0090] Can be combined Figure 8 To understand Figure 9 .

[0091] During the integration phase (604), the controller 930 causes the MUXs 924 and 926 to select the input signals In and 502 and output code Out 102 Therefore, during the integration phase (604), the analog counter 508 508_i Increments its count when activated.

[0092] In some embodiments, during the integration phase (604), the ADC 910 ignores the output Out 508_i For example, in some embodiments, the ripple counter 934 may be disabled (eg, in reset mode), or the output of the ripple counter 934 may be ignored during the integration phase (604). Other implementations are also possible.

[0093] At the beginning of the signal conversion phase (step 606), the controller 930 causes the MUXs 924 and 926 to select the output of the pulse generator 932 (Output 932 ) and output code Out 930During the signal conversion phase (step 606), when the i-th analog counter 508 is selected for signal conversion, the controller 930 causes the MUX 940 to output the signal Out 936_i Coupled to the input of the ripple counter 934 (In 934 ), so that the decoder 928 selects to activate the output Out 504_i , and reset (eg, via a reset signal Rst 934 ) ripple counter 934. After the ripple counter 934 is reset, the pulse generator 932 generates a plurality of pulses to cause the input In 508_i The corresponding multiple activations make the voltage V cap decreases until it reaches a voltage V ref As shown by AND gate 936, ripple counter 934 outputs out 932 Increase the count Cnt when pulsing 934 Once the output is 508_i becomes lower than the voltage V ref , AND gate 936 output is low, thereby freezing the state of ripple counter 934, which has a value equal to Cnt 剩余 Count Cnt 934 Count Cnt 934 (which at this moment is equal to the count Cnt remaining of the i-th analog counter 508) is transmitted to the controller 930 for further processing.

[0094] During the full-scale conversion phase (step 706), when the i-th analog counter 508 is selected for full-scale conversion, the controller 930 causes the MUX 940 to output the signal Out 936_i Coupled to the input of the ripple counter 934 (In 934 ), so that the decoder 928 selects (activates) the output Out 504_i , reset (eg, via a reset signal Rst 934 ) ripple counter 934, and reset the i-th analog counter 508. After the ripple counter 934 is reset, the pulse generator 932 generates a plurality of pulses to cause the input In 508_i The corresponding multiple activations make the voltage V cap decreases until it reaches the voltage V ref As shown by AND gate 936, ripple counter 934 outputs out 932 Increase the count Cnt when pulsing 934 Once the output is 508_i becomes lower than the voltage V ref , AND gate 936 output is low, thereby freezing the state of ripple counter 934, which has a value equal to Cnt 满量程Count Cnt 934 Count Cnt 934 (At this time, it is equal to the count Cnt of the i-th analog counter 508 满量程 ) is transmitted to the controller 930 for further processing.

[0095] In some embodiments, steps 606, 602, and 706 may be performed continuously for each analog counter 508. For example, in some embodiments, for the i-th analog counter, the controller 930 causes the MUX 940 to output the signal Out 936_i Coupled to the input of the ripple counter 934 (In 934 ) and causes decoder 928 to select and activate output Out 504_i , and the signal conversion phase (step 606 ), reset (step 602 ), and full-scale conversion phase (step 706 ) are performed before updating the states of the MUX 940 and decoder 928 to select the next analog counter 508 .

[0096] In some embodiments, a signal conversion phase (step 606 ) is performed on all n analog counters 508 before a full-scale conversion phase (step 706 ) is performed on all n analog counters 508 .

[0097] The MUX 924 is configured to select the input (eg, 1 bit) from the controller 930 between the In 502 and Out 932 MUX 926 is configured to select between Out and 102 (e.g., log2n bits) and Out 930 (eg, log2n bits). MUX 940 is configured to select from n possible Out 936 Select Out 936_i MUXes 924, 926, and 940 may be implemented in any manner known in the art.

[0098] The ripple counter 934 is configured to receive the input In 934 When activated (eg, pulsed), the internal counter (Cnt 934 ). The count of the internal counter (Cnt 934 ) is provided to the controller 930 for further processing (eg, for executing Equation 1). 934 When activated, the internal counter (Cnt 934 ) is reset (eg, reset to 0). The ripple counter 934 may be implemented in any manner known in the art (eg, such as using a flip-flop).

[0099] Decoder 928 may be implemented as a 1-out-of-n decoder in any manner known in the art.

[0100] The pulse control logic 922 is configured to activate the output Out in synchronization with the decoder 928 based on its input. 922 For example, in some embodiments, the pulse control logic 922 may include a delay circuit that activates the output Out at a delay time after its input is activated. 902 , so that the decoder 928 activates the output Out 504_i At the same time or shortly after, output Out 902 is activated.

[0101] Controller 930 is configured to control MUXes 924, 926, and 940, pulse generator 932, and ripple counter 934. Controller 930 is also configured to process the output of ripple counter 934, for example, to execute Equation 1. In some embodiments, controller 930 can be implemented as a general-purpose or custom controller or processor including, for example, combinational circuits. For example, in some embodiments, controller 930 includes a finite state machine (FSM). In some embodiments, controller 930 also includes a memory and is configured to execute instructions stored in the memory. Other implementations are also possible.

[0102] The pulse generator 932 is configured to generate pulses (eg, pulses having the same width). In some embodiments, the pulse generator 932 generates pulses when it is activated (eg, based on the input In 932 ) generates a pulse train (eg, a clock signal), and when deactivated (eg, based on an input In 932 ) stops generating the pulse train. In some embodiments, each time In is input 932 When activated, the pulse generator 932 outputs 932 932.

[0103] In some embodiments, the ADC 510 directly controls a specific input signal In of a specific analog counter 508. 508 To make the specific input signal In of the specific analog counter 508 508 Multiple activations during the signal conversion phase (step 606). For example, Figure 10A schematic diagram of a portion of a ToF system 1000 illustrating an ADC 910 according to an embodiment of the present invention is shown. The ToF system 500 may be implemented as the ToF system 1000. The addressing logic circuit 504 may be implemented as a decoder 928. The pulse control circuit 502 may be implemented as a pulse control logic 922.

[0104] Figure 10 The circuitry associated with a single analog counter 508 (e.g., counter 508_i) among the n analog counters 508 is illustrated, where the i-th analog counter 508 can be any one of the n analog counters 508. Some of the circuitry (e.g., decoder 928, pulse control logic 922, pulse generator 932, controller 930, MUX 940, and ripple counter 934) can be shared among all n analog counters 508. Other circuitry (e.g., MUX 1024, AND gates 506 and 936, analog counter 508, and comparator 938) can be replicated n times for each of the n histogram bins. Other implementations are also possible.

[0105] The ToF system 1000 operates in a similar manner to the ToF system 900. However, the ToF system 1000 includes a circuit for converting the output Out from the pulse generator 932 to 932 Propagates to the MUX 1024 of the i-th analog counter 508 .

[0106] Figure 11 Schematic diagram showing a portion of an ADC 1100 according to an embodiment of the present invention. ADC 910 may be implemented as ADC 1100.

[0107] like Figure 11 As shown, the controller 930 can implement Equation 1 using a latch 1132 and an adder 1134. For example, after the signal conversion phase (step 606) of the i-th analog counter 508 is completed, the count Cnt 934 (At this time it corresponds to Cnt 剩余 ) is stored in the latch 1132. After the full-scale conversion phase (step 706) of the i-th analog counter 508, the adder 1134 is fed from the count Cnt 934 (At this time it corresponds to Cnt 满量程 ) minus the contents of latch 1132. The resulting bin count Cnt 箱 is transmitted to the controller 1130 .

[0108] In some embodiments, latch 1132 can be implemented as a register, such as an m-bit register. Other implementations are also possible. In some embodiments, m is 8 bits or higher, such as 10 bits, 12 bits or higher. In some embodiments, it can be lower than 8 bits, such as 7 bits or lower.

[0109] Adder 1134 may be implemented in any manner known in the art.

[0110] In some embodiments, the controller 1130 can be implemented as a general-purpose or custom controller or processor including, for example, a combinational circuit. For example, in some embodiments, the controller 1130 includes a finite state machine (FSM). In some embodiments, the controller 1130 also includes a memory and is configured to execute instructions stored in the memory. Other implementations are also possible.

[0111] Figure 12 FIG. 1 is a schematic diagram of an analog counter 1200 according to an embodiment of the present invention. The analog counter 508 may be implemented as the analog counter 1200. The analog counter 1200 includes a charge transfer amplifier 1201 and a readout circuit 1211.

[0112] like Figure 9 、 Figure 10 and Figure 12 As shown, some embodiments can avoid the use of a sample and hold circuit coupled between the output of analog counter 508 (e.g., the source of transistor 1214) and comparator 938, which can advantageously result in a smaller, lower power implementation and can advantageously avoid kTC sampling noise associated with a sample and hold circuit. A current source (e.g., 950) can be coupled to output Out 508 , for example, to provide bias current for source follower transistor 1212 .

[0113] In some embodiments, storage capacitor 1210 may be implemented as, for example, a metal oxide semiconductor (MOS) capacitor, a metal oxide metal (MOM) capacitor, or a combination of MOM and MOS capacitors. Some embodiments may implement storage capacitor 1210 with a reverse biased diode. Other implementations are also possible.

[0114] Figure 13 A timing diagram illustrates waveforms associated with analog counter 1200 during execution of method 700 in accordance with an embodiment of the present invention. Figure 12 and Figure 13 We can understand together.

[0115] During the reset phase (602), the reset transistor 1202 reduces the voltage V rstand turns on while transistor 1204 turns off, thereby allowing storage capacitor 1210 to charge to the full-scale voltage V FS ,like Figure 13 During the reset phase (602), the voltage V cp It is also reset to voltage Vs by turning on transistor 1206 .

[0116] During the integration phase (604), each time the input In 508 When activated (eg, pulsed), charge flows from capacitor 1210 to capacitor 1208. 508 When high, capacitor 1208 charges until transistor 1204 is cut off from voltage Vs to voltage V in -V th , where V th is the threshold voltage of transistor 1204. Therefore, whenever the input In 508 When activated, a quantized amount of charge is transferred out of capacitor 1210. Once transistor 1204 is turned off (when input In 508 is disabled), transistor 1206 is turned on (eg, pulsed) to reduce the voltage V cp Reset to Vs, thus inputting In 508 When activated, it allows the next charge transfer.

[0117] In some embodiments, the voltage V cap In each input 508 The voltage step size ΔV when activated can be given by the following formula

[0118]

[0119] where ΔV in In 508 The voltage when activated is V in With inputIn 508 The voltage when it is disabled is V in The difference between the two, C 1208 is the capacitance of capacitor 1208, and C 1210 is the capacitance of capacitor 1210. From Equation 2, it can be seen that the voltage V cap The voltage step size ΔV may not be affected. In some embodiments, the voltage step size ΔV may be kept constant by maintaining a constant voltage Vs. In some embodiments, the voltage Vs may be adjusted to change the voltage step size ΔV and thereby change the dynamic range (input In) of the analog counter 1200. 508 Reach voltage V ref The maximum number of activations required).

[0120] During the conversion phase (steps 606 and 706), transistor 1214 is turned on, causing the voltage V cap Visible to, for example, comparator 938 via transistor 1212 , which is in a source follower configuration.

[0121] like Figure 13 As shown, during the integration phase (604) and the conversion phase (steps 606 and 706), the source voltage V RT The gate voltage V of the transistor 1202 is maintained at reset rst Below and at the bulk voltage V of the bulk terminal of the reset transistor 1202 RTB Hereinafter, the reset transistor 1202 is in the off state. For example, in some embodiments, during the integration phase (604) and during the conversion phase (steps 606 and 706), the voltage V RT is 3V and the voltage V rst and V RTB When turned off, the reset transistor 1202 can advantageously reduce the power supply voltage V RT Leakage into storage capacitor 1210, which can advantageously improve the accuracy of the analog counter.

[0122] In some embodiments, the voltage V RTB can be maintained at 4V and the voltage V RT It can be converted between 3.3V and 4V, for example. Figure 13 In some embodiments, the voltage V RT can be maintained at 3.3V, and the voltage V RTB It can be converted between 3.3V and 4V to achieve the same voltage difference, such as Figure 13 Different voltages may also be used, such as higher than 3.3V (eg, 5V or higher) or lower than 3.3V (eg, 3V or lower).

[0123] In some embodiments, when the input In 508 When activated, the voltage V in is 1.1V, and when the input In 508 When disabled, the voltage V in is 0 V. Other voltages can also be used.

[0124] In some embodiments, the voltage V SF This could be, for example, 3.3 V. Other voltages could also be used.

[0125] In some embodiments, voltage Vs may be, for example, 300 mV. Other voltages may also be used.

[0126] In some embodiments, voltage Vg is used to compensate for the bulk effect on the threshold voltage of transistor 1206 when transistor 1206 is activated. In some embodiments, voltage Vg remains below the threshold so that transistor 1206 acts as a resistor to discharge capacitor 1208.

[0127] In some embodiments, capacitor 1210 may have a capacitance 100 times greater than capacitor 1208. Other ratios may also be used, such as 90, 50, or lower, or such as 150, 200, or higher. For example, in some embodiments, capacitor 1210 may have a capacitance of 100 fF and capacitor 1208 may have a capacitance of 1 fF. Other capacitances may also be used.

[0128] Figure 14 1 shows a schematic diagram of an analog counter 1400 according to an embodiment of the present invention. The analog counter 508 can be implemented as the analog counter 1400. The analog counter 1400 operates in a similar manner to the analog counter 1200. However, the analog counter 1400 includes a circuit for generating a counter signal based on an input In. 508 Inverter 1402 controls voltage Vg. The analog counter further implements capacitor 1210 as a MOS capacitor 1410.

[0129] Figure 15 A diagram illustrating a portion of a ToF system 1500 according to an embodiment of the present invention is shown. The ToF system 1500 includes a SPAD array 1504, a TDC group 1502, a histogram generation circuit group 1518, and an ADC group 1510. The SPAD array 1504 includes a plurality of pixels 1501. The pixels 1501 include a SPAD (e.g., 202) or a SPAD (e.g., 302) and a SPAD front-end circuit (e.g., a quench transistor and one or more additional transistors, such as the SPAD front-end circuit 2004, for example). Figure 20A shown).

[0130] ToF systems 100 , 500 , 900 , and 1000 may be implemented as ToF system 1500 . SPAD array 104 may be implemented as SPAD array 1504 .

[0131] like Figure 15As shown, the SPAD array 1504 may include a plurality of SPAD pixels 1501 arranged in M ​​columns and N rows. In some embodiments, M may be 96 and N may be 64. In some embodiments, M may be higher than 96, such as 128, 256, or higher, or lower than 96, such as 64, 48, 36, or lower. In some embodiments, N may be higher than 64, such as 96, 128, 256, or higher, or lower than 64, such as 48, 36, or lower. In some embodiments, M may be equal to N. In some embodiments, the SPAD array may include thousands or millions of pixels. For example, in some embodiments, a 1MP array may be implemented by using M equal to N equal to 1000. In some embodiments, for example, each pixel may include a micro-pixel of a 4×4 SPAD through an OR tree (e.g., 304). Other implementations are also possible.

[0132] like Figure 15 As shown, in some embodiments, the TDC group 1502 may include a plurality of TDCs 102 arranged in M ​​columns of N TDCs 102 , where each TDC 102 is coupled to a corresponding SPAD pixel 1501 .

[0133] like Figure 15 As shown, in some embodiments, the histogram generation circuit group 1518 may include a plurality of histogram generation circuits 118 arranged into M columns of N histogram generation circuits 118 , where each histogram generation circuit 118 is coupled to a respective TDC 102 .

[0134] like Figure 15 As shown, in some embodiments, the ADC group 1510 can include M ADCs 510, where each ADC 510 is coupled to the N histogram generation circuits 118 in the same column (e.g., one ADC 510 per column of the SPAD array 1504). For example, in some embodiments, the same ADC 510 can be used to sequentially read histogram bin counts from each of the M histogram generation circuits 118 in the same column. In some embodiments, the ADC group 1510 can include more than one ADC 510 per column, such as two ADCs per column, or more, such as N ADCs 510 per column. In some embodiments using N ADCs 510 per column, each ADC 510 is coupled to a corresponding histogram generation circuit 118.

[0135] In some embodiments, the ToF system 1500 can be advantageously used in a global shutter mode, wherein all pixels (e.g., 1501) of an image sensor (e.g., SPAD array 1504) are integrated simultaneously (e.g., step 604), thereby advantageously capturing the entire ToF image at the same time. In some embodiments, the ToF system 1500 can also be advantageously used in a rolling shutter mode, wherein a ToF image is captured by scanning a scene row by row or column by column.

[0136] The ToF system 1500 may be implemented with different numbers of TDCs 102, histogram generation circuits 118, and / or ADCs 510. For example, in some embodiments, M×N ADCs 510 may be used, which may advantageously allow for simultaneous readout of all ToF histograms associated with the M×N histogram generation circuits 118 of the histogram generation circuit group 1518.

[0137] Figure 16 A diagram illustrating a portion of a ToF system 1600 according to an embodiment of the present invention is shown. The ToF systems 100, 500, 900, and 1000 may be implemented as the ToF system 1600.

[0138] ToF system 1600 operates in a similar manner to ToF system 1500. However, ToF system 1600 includes a TDC group 1602 including M TDCs 102 (e.g., where each TDC 102 is coupled to N SPAD pixels 1501 (e.g., one TDC 102 per column of SPAD array 1504). ToF 1600 also includes a histogram generation circuit group 1618 including M histogram generation circuits 118 (e.g., where each histogram generation circuit 118 is coupled to a respective TDC 102 (e.g., one TDC 102 per column of SPAD array 1504). ToF 1600 may also include a single ADC 510 shared across the multiple histogram generation circuits 118 of histogram generation circuit group 1618 (e.g., a single shared ADC 510 for SPAD array 1504).

[0139] In some embodiments, ToF system 1600 can be advantageously used in a rolling shutter mode, eg, with a lower area footprint than, for example, ToF system 1500 .

[0140] Figure 17 1 shows a top view of a layout 1700 illustrating a possible implementation of a portion of a ToF system 1600 (not to scale) according to an embodiment of the present invention. Figure 17As shown, the TDC 102 can be arranged between the SPAD array 1504 and the histogram generation circuit 1518, wherein all TDCs 102 are arranged together, all histogram generation circuits 118 are arranged together, and all ADCs 510 are arranged together. Other implementations are also possible. For example, in some embodiments, a ToF system (e.g., ToF systems 100, 500, 900, 1000, 1500, and / or 1600) can be implemented using a 3D stack in which the top die includes a SPAD (e.g., 202, 302) and the bottom die includes the TDC 102 and the histogram generation circuit 118. In some embodiments, the top die may also include at least a portion of the front-end circuitry of the SPAD.

[0141] In one embodiment of the present invention, low-power clocking is advantageously implemented by using LVDS latches as part of the front end of a timing circuit (e.g., TDC 102). By using LVDS latches to route clock signals, some embodiments advantageously reduce the power consumption of a ToF system (e.g., 100, 500, 900, 1000, 1500, and / or 1600) without sacrificing performance.

[0142] Figure 18 An LVDS latch 1800 is shown in accordance with an embodiment of the present invention. Figure 18 The left side of FIG. 1 shows a schematic diagram of an LVDS latch 1800 . Figure 18 The right side of FIG shows a schematic symbol of LVDS latch 1800. Figure 18 As shown, the signal V in_lvds 、V PHI and is the input signal of the LVDS latch 1800, and the signal V out_lvdsA and V out_lvdsB is the output signal of LVDS latch 1800. Figure 18 As shown in the right part, some embodiments may optionally output a signal and

[0143] In some embodiments, the signal V PHI and It is a differential signal with a relatively low average voltage (eg, 500 mV to 600 mV) and a relatively low peak-to-peak voltage (eg, 100 mV to 200 mV). Other values ​​may also be used.

[0144] During normal operation, when the input signal V in_lvdsWhen V is low (deasserted), the latch formed by transistors 1804, 1808, 1814, and 1818 is disabled (because transistor 1810 is off). in_lvds When LOW, LVDS latch 1800 consumes little or no current. Figure 18 As shown, when the input signal V in_lvds When the signal is low, transistors 1802 and 1812 pull up the signal and This results in an output signal V out_lvdsA and V out_lvdsB Is low.

[0145] When V in_lvds When the output signal V changes from low to high out_lvdsA and V out_lvdsB The state depends on the V in_lvds When the input signal V changes from low to high PHI and For example, if V in_lvds When the signal V changes from low state to high state PHI and are high and low respectively, the output signal V out_lvdsA latches to a high state and outputs the signal V out_lvdsB latched to a low state. If the V in_lvds When the signal V changes from low state to high state PHI and are low and high respectively, the output signal V out_lvdsA latched to a low state and output signal V out_lvdsB latched to a high state.

[0146] from Figure 18 It can be seen that the LVDS latch 1800 signal V PHI and Drives the high impedance input gate, which is driven by the input signal V in_lvds trigger, and when the input signal V in_lvds When V is low, the LVDS latch 1800 is turned off by the tail transistor 1810. Thus, in some embodiments, the LVDS latch 1800 can advantageously consume little or no power except during state transitions (e.g., during the period between signal V in_lvds rise time or fall time).

[0147] In some embodiments, the signal V PHI and It can be a clock signal, such as from CLK 采样For example, in some embodiments, a low power differential signal (eg, a 200 mV peak-to-peak signal with an average voltage of 600 mV) may be used to separate multiple out-of-phase clock signals CLK. 采样 is propagated to TDC 102. For example, in the digital code Out 102 In an embodiment where the word is 7 bits, 7 out-of-phase clock signals may be propagated from the timing generation circuit 108 to the TDC 102 along with 7 low power differential signals. The TDC 102 may then generate a signal based on the 7 out-of-phase clock signals and the output of the SPAD (e.g., signal In 102 )Generate 7-digit code Out 102 By propagating the ToF system's clock signal(s) using one or more LVDS latches, some embodiments may advantageously achieve power savings associated with not propagating the clock signal from a source (e.g., timing generation circuitry 108) to TDC 102 at full swing.

[0148] Figure 19 An LVDS latch 1900 is shown in accordance with an embodiment of the present invention. Figure 19 The top portion of FIG. 1 shows a schematic diagram of LVDS latch 1900 . Figure 19 The bottom portion of FIG shows a schematic diagram of LVDS latch 1900. Figure 19 As shown, the signal V in_lvds and and V PHI and is the input signal of the LVDS latch 1900, and the signal V out_lvdsA and V out_lvdsB is the output signal of LVDS latch 1900. Figure 19 As shown at the bottom, some embodiments may optionally output a signal and In some embodiments, the signal The signal LVDS latch 1900 may be generated for the LVDS latch 1900 by circuitry external to the LVDS latch 1900. In some embodiments, the signal Instead of receiving the signal, the LVDS latch 1900 may be generated, for example, using an inverter (not shown) of the LVDS latch 1900. As the input of LVDS latch 1900.

[0149] LVDS latch 1900 operates in a similar manner to LVDS latch 1800. However, LVDS latch 1900 replaces transistor 1810 with transistors 1902, 1904, 1922, and 1924 to implement a 3-transistor stack implementation (compared to the 4-transistor stack implementation of LVDS latch 1800). In some embodiments, implementing the LVDS latch in a 3-transistor stack implementation advantageously allows for the use of a lower power supply voltage (VDD) compared to a 4-transistor stack implementation.

[0150] In some embodiments, the ToF systems 100 , 500 , 900 , 1000 , 1500 , and / or 1600 may implement LVDS latches (eg, 1800 and / or 1900 ) as part of the front end of the TDC 102 .

[0151] In some embodiments, using a ToF histogram with a small number of bins may advantageously allow for a small implementation and may advantageously allow for the incorporation of histogram generation circuitry (e.g., 118) within the pixel. For example, Figure 20A Pixel 2000 is shown as part of a SPAD array 2003 in accordance with an embodiment of the present invention. Pixel 2000 includes a SPAD 2002, SPAD front-end circuitry 2004, and TDC and histogram generation circuitry 2018. Figure 20B A timing diagram for pixel 2000 according to an embodiment of the present invention is shown. Figure 20A and Figure 20B We can understand together.

[0152] like Figure 20A and Figure 20B As can be seen from the graph, pixel 2000 is capable of generating a 2-bin ToF histogram. For example, when SPAD 2002 generates a SPAD event (e.g., when SPAD 2002 receives a photon), the voltage V 2002 rises, thus the signal In 102 The LVDS latch 1900 then generates a pulse according to the signal In 102 When the pulse input signal V PHI and The state of the output signal V out_lvdsA Or output signal V out_lvdsB For example, if the signal In 102 When pulsed, the signal V PHI Above signal Then bin 0 is incremented. If the signal In 102 When pulsed, the signal V PHI Below signal Then box 1 is incremented.

[0153] In some embodiments, the signal CLK 采样 Can be used as a low voltage differential signal V PHI and The timing is transmitted from the timing generation circuit 108 to the LVDS latch 1900 of the pixel 2000. Figure 20B As shown, the signal V PHI and This can be achieved with a sine waveform. Other waveforms, such as a square wave, can also be used.

[0154] like Figure 20A As shown, SPAD front-end circuit 2004 can be implemented with a quench transistor 2006 and a chain of inverters (e.g., 2008, 2010, and 2012). Inverters 2008, 2010, and 2012 can be understood as forming routing circuit 112 that couples the output of SPAD 2002 to the input of LVDS latch 1900.

[0155] from Figure 20A and Figure 20B As can be seen in FIG, the LVDS latch 1900 operates as both a TDC (eg, 102) and a decoder (eg, 928), wherein the LVDS latch 1900 operates according to the timing of the SPAD event (eg, when In 102 is asserted) to increment bin 0 or bin 1. In some embodiments, pixel 2000 may use other types of LVDS latches, such as LVDS latch 1800. In some embodiments, for example, where the LVDS latch does not use signal In some embodiments (eg, such as LVDS latch 1800), inverter 2012 may be omitted (eg, as shown in front-end circuit 2404 of FIG. 24).

[0156] In some embodiments, pixel 2000 operates as an indirect ToF (ITOF) sensor, where the light source (e.g., 106) operates as a continuous wave modulated light source (e.g., with a 50% duty cycle), and where the distance to the object is calculated based on the phase of the returning light, e.g., as captured by bins 0 and 1 of pixel 2000. For example, in some embodiments, the distance to the object d t It can be determined by the following equation (e.g., based on pixel 2000)

[0157]

[0158] where c is the speed of light, Δt l is the time period during which the light source (eg, 106) is turned on, Cnt bin1 and Cnt bin0 are the counts of bin 1 and bin 0 respectively.

[0159] Figure 21 A diagram illustrating a portion of a ToF system 2100 is shown, according to an embodiment of the present invention. The ToF system 2100 includes a SPAD array 2003 and an ADC group 1610. The SPAD array 2003 includes a plurality of pixels 2000.

[0160] like Figure 21 As shown, the ToF system 2100 can operate in global shutter mode. A single ADC 510 can be used to sequentially read out a ToF histogram from the pixels 2000. In some embodiments, more ADCs 510 can be used. For example, in some embodiments, the ToF system 2100 can implement the ADC group 1510 instead of the ADC group 1610.

[0161] In some embodiments, the ToF system 2100 can be implemented in a monolithic semiconductor substrate, for example, in a manner similar to the layout 1700. In some embodiments, the ToF 2100 can be implemented using a 3D stack in which the top die includes the SPAD (e.g., 2002) and the bottom die includes the SPAD front-end circuit 2004 and the TDC and histogram generation circuit 2018. For example, Figure 22 2 shows a perspective view illustrating a layout 2200 of a possible implementation of a portion of a ToF system 2100 (not to scale) according to an embodiment of the present invention. Figure 22 As shown, the top die 2202 includes the SPAD array 2002; and the bottom die 2204 includes a corresponding plurality of pixels 2206, where each pixel 2206 includes the SPAD front-end circuit 2004, and the TDC and histogram generation circuit 2018. Other implementations are also possible. For example, in some embodiments, the top die 2202 may include a portion of the front-end circuit 2004, such as a quench element or a front-end inverter (e.g., 2008, 2010).

[0162] In some embodiments, top die 2202 and bottom die 2204 may be bonded using a hybrid bond.Other implementations are also possible.

[0163] like Figure 22 As shown, pixel array 2206 can be disposed directly below SPAD array 2002. In some embodiments, an ADC group (eg, 1510, 1610) can be disposed adjacent to pixel array 2206 in bottom die 2204.

[0164] In some embodiments, a ToF histogram with more than 2 bins can be implemented inside a pixel of a SPAD array. For example, Figure 23APixel 2300 according to an embodiment of the present invention is shown. Pixel 2300 includes SPAD 2002, SPAD front-end circuit 2004, TDC 2302 and histogram generation circuit 2318. TDC 2302 includes a circuit that receives a corresponding differential signal and The histogram generation circuit 2318 includes two LVDS latches 1900. The histogram generation circuit 2318 includes a decoder 2328 and four analog counters 508. The decoder 928 can be implemented as the decoder 2328. The TDC 102 can be implemented as the TDC 2302. The SPAD array 2003 can be implemented using the pixel array 2300.

[0165] Figure 23B shows a diagram illustrating a differential signal received by pixel 2300 according to an embodiment of the present invention. and Timing diagram of . Figure 23A and Figure 23B We can understand together.

[0166] like Figure 23B As shown, the differential signal and Can be different phases.

[0167] from Figure 23A and Figure 23B As can be seen from the figure, pixel 2300 is able to generate a 4-bin ToF histogram. For example, when the signal In 102 When pulsed, the LVDS latch 1900 then switches to the same value according to the signal In 102 The pulsed input signal and The state of the output signal V out_lvdsA_1 Or output signal V out_lvdsB_1 And the output signal V out_lvdsA_2 Or output signal V out_lvdsB_2 For example, if the signal In 102 When pulsed, the signal V PHI1 Below signal (exist Figure 23B 0) and the signal V PHI2 Below signal (exist Figure 23B If the signal In 102 When pulsed, the signal V PHI1 Above signal And the signal V PHI2 Below signal Then box 1 is incremented. If the signal In 102 When pulsed, the signal V PHI1 Above signal And the signal V PHI2 Above signal Then box 2 is incremented. If the signal In 102 When pulsed, the signal V PHI1 Below signal And the signal V PHI2 Above signal Then bin 3 is incremented. In some embodiments, relative to the input signal and The state, bin sequence can be different.

[0168] In some embodiments, the signal CLK 采样 Can be used as two low voltage differential signals and The signal is transmitted from the timing generation circuit 108 to the LVDS latch 1900 of the pixel 2000. and This can be achieved with a sine waveform. Other waveforms, such as a square wave, can also be used.

[0169] like Figure 23A As shown, TDC 2302 is implemented using two LVDS latches 1900. In some embodiments, TDC 2302 may use other types of LVDS latches, such as LVDS latch 1800.

[0170] In some embodiments, the sizes of bins 0, 1, 2, and 3 (e.g., the magnitude of the time period covered by each of bins 0, 1, 2, and 3) can be the same. In some embodiments, the sizes of bins 0, 1, 2, and 3 (e.g., the magnitude of the time period covered by each of bins 0, 1, 2, and 3) can be different. In some embodiments, one or more bins can be used for blanking. In some embodiments where one or more bins are used for blanking, the corresponding analog counter 508 can be omitted.

[0171] In some embodiments, the LVDS latches (e.g., 1800, 1900) used as part of the TDC (e.g., 102, 2302) can be reused as comparators (e.g., 938) for ADC conversions. For example, Figure 24APixel 2400 according to an embodiment of the present invention is shown. Pixel 2400 includes SPAD 2002, SPAD front-end circuitry 2404, and TDC and histogram generation circuitry 2418. TDC and histogram generation circuitry 2418 includes LVDS latch 1800, self-referencing control circuitry 2412, two analog counters 508 (one for bins 0 and 1, respectively), OR gates 2406, 2407, and 2410, switches 2420, 2422, 2424, 2426, 2428, 2430, 2432, 2434, 2436, 2438, and current source 2450. Pixel 2000 can be implemented as pixel 2400.

[0172] In some embodiments, OR gates 2406, 2408, and 2410 can be implemented outside pixel 2400, and the outputs of the OR gates (2406, 2408, and 2410) can be shared by multiple pixels (e.g., in a column). By implementing OR gates 2406, 2407, and 2410 outside pixel 2400, some embodiments advantageously achieve smaller pixel sizes. By implementing OR gates 2406, 2407, and 2410 within pixel 2400, some embodiments advantageously reduce the complexity of routing.

[0173] In some embodiments, additional switches may be used to selectively connect corresponding inputs of analog counter 508 to ground to avoid having floating inputs when the corresponding switches (2438, 2436) are open.

[0174] Figure 24B The states of switches 2420 , 2422 , 2424 , 2426 , 2428 , 2430 , 2432 , 2434 , 2436 , 2438 are shown for different operating modes of pixel 2400 in accordance with an embodiment of the present invention. Figure 24A and Figure 24B We can understand together.

[0175] like Figure 24A and Figure 24B As can be seen in FIG, pixel 2400 is capable of generating a 2-bin ToF histogram. For example, during integration mode (step 604), switches 2422, 2424, 2432, 2436, and 2438 are closed, switches 2420, 2426, 2428, 2430, and 2434 are open, and pixel 2400 operates in a similar manner to pixel 2000. Thus, in some embodiments, LVDS latch 1800 operates as a TDC and decoder during integration mode. In some embodiments, the output Out of self-referenced control circuit 2412 is 938 It may be tri-stated during integration mode (step 604).

[0176] from Figure 24A and Figure 24B As can be seen, during the conversion mode (steps 606, 706) of bin 0 or bin 1, the LVDS latch 1800 serves as a latch for connecting the output of the analog counter 508 (e.g., associated with bin 0 or bin 1) to the reference voltage V ref For example, during the conversion mode of bin 0 (steps 606, 706), switches 2420, 2422, 2424, 2428, 2432, and 2436 are open, while switches 2426, 2430, 2434, and 2438 are closed. When the LVDS latch 1800 receives a pulse from the pulse generator 932 of the ADC 910, it outputs V out_lvdsA Pulse and output Out 508_0 Once the output Out 508_0 Reaching the reference voltage V ref , output V out_lvdsB Pulsing causes the self-referenced control circuit 2412 to assert (eg, transition from high to low), thereby causing the AND gate 936 of the ADC 910 to freeze, thereby stopping the ripple counter 934 from counting.

[0177] Similarly, during the conversion mode of bin 1 (steps 606, 706), switches 2422, 2424, 2426, 2430, 2432, and 2438 are open, while switches 2420, 2428, 2434, and 2436 are closed. When the LVDS latch 1800 receives a pulse from the pulse generator 932 of the ADC 910, it outputs V out_lvdsB Pulse and output Out 508_1 Once the output Out 508_1 Reaching the reference voltage V ref , output V out_lvdsA Pulsing causes the self-referenced control circuit 2412 to assert (eg, transition from high to low), thereby causing the AND gate 936 of the ADC 910 to freeze, thereby stopping the ripple counter 934 from counting.

[0178] from Figure 24A and Figure 24B As can be seen in FIG, during integration mode, LVDS latch 1800 operates simultaneously as a TDC (e.g., 102) and a decoder (e.g., 928). In some embodiments, pixel 2000 can use other types of LVDS latches, such as LVDS latch 1900 (e.g., by using front-end circuit 2004 and adding additional switches to couple the output of inverter 2012 to the LVDS latch).

[0179] In some embodiments, one or more combinations of states of signals S1, S2, and S3 may be prohibited. For example, in some embodiments, only one of S1, S2, and S3 may be "1" at the same time.

[0180] In some embodiments, the signals S1, S2, and S3 may be generated by the pixel 2400 ( Figure 24A 930. In some embodiments, signals S1, S2, and S3 may be generated by a controller (e.g., controller 520) implemented within the controller 930 (not shown). Other implementations are also possible.

[0181] Figure 25 2500 according to an embodiment of the present invention. The self-reference control circuit 2412 can be implemented as the self-reference control circuit 2500. Figure 24A and Figure 24B To understand Figure 25 .

[0182] like Figure 25 As shown, some embodiments may implement OR gate 2516 within self-referencing control circuit 2500 (and therefore within pixel 2400). In some embodiments, OR gate 2516 may be omitted, and instead the output of OR gate 2406 may be coupled to the gate of transistor 2508. In some embodiments, OR gate 2516 may be implemented external to pixel 2400, and the output of OR gate 2516 may be shared by multiple pixels (e.g., in a column).

[0183] like Figure 25 As shown, when signals S2 and S3 are both low, the output V 2508 In high impedance mode. At the start of the conversion of bin 0 or bin 1 (steps 606, 706), the D flip-flop 2518 is initialized to "1". Therefore, after the D flip-flop 2518 is initialized, the output Out 938 For high.

[0184] In some embodiments, the D flip-flop 2518 outputs V 2508 latches its D input during the falling transition of

[0185] During the conversion of bin 0 (steps 606, 706), switch S2 is high and switch S3 is low. Therefore, transistors 2508 and 2510 are both on, transistor 2504 is on and transistor 2502 is off. When the LVDS latch 1800 receives a pulse from the pulse generator 932 of the ADC 910, it outputs V out_lvdsA Pulse and output Out 508_0 decreases, and the output V out_lvdsB Therefore, when the output Out 508_0Keep above the reference voltage V ref When the transistor 2506 is turned on, the transistor 2512 is turned off, and the output is V 2508 Keep high. Once the output Out 508_0 Reaching the reference voltage V ref , output V out_lvdsB Pulsing causes transistor 2506 to be turned off briefly and transistor 2512 to be turned on briefly, thus causing the output V 2508 falls, thereby latching "0" into the D flip-flop 2518 and causing the output Out 938 Transitions to a low state, thereby stopping the ripple counter 934 from counting.

[0186] Similarly, during the conversion of bin 1 (steps 606, 706), switch S3 is high and switch S2 is low. Therefore, transistors 2508 and 2510 are both on, transistor 2502 is on, and transistor 2504 is off. When the LVDS latch 1800 receives a pulse from the pulse generator 932 of the ADC 910, the output V out_lvdsB Pulse and output Out 508_1 Decreases, while outputting V out_lvdsA Therefore, when the output Out 508_1 Keep above the reference voltage V ref When the transistor 2506 is turned on, the transistor 2512 is turned off, and the output is V 2508 Keep high. Once the output Out 508_1 Reaching the reference voltage V ref , output V out_lvdsA Pulsing causes transistor 2506 to be turned off briefly and transistor 2512 to be turned on briefly, thus causing the output V 2508 falls, thereby latching "0" into the D flip-flop 2518 and causing the output Out 938 Transitions to a low state, thereby stopping the ripple counter 934 from counting.

[0187] In some embodiments, D flip-flop 2518 may be implemented as part of ADC 910 .

[0188] Example embodiments of the present invention are summarized here. Other embodiments can also be understood from the entire content of the specification and the claims submitted herewith.

[0189] Example 1. A method comprising: resetting corresponding count values ​​of a plurality of analog counters to initial count values, each of the plurality of analog counters corresponding to a histogram bin of a time-of-flight (ToF) histogram; after resetting the corresponding count values ​​of the plurality of analog counters, receiving a plurality of digital addresses from a time-to-digital converter (TDC), the TDC having an input coupled to a single-photon avalanche diode (SPAD); during an integration period, for each received digital address of the plurality of digital addresses, selecting one of the plurality of analog counters based on the received digital address, and changing the corresponding count value of the selected one analog counter by a discrete amount toward a second count value, the second count value being different from the initial count value, wherein each analog counter has a final count value at the end of the integration period; and after the integration period, determining a corresponding final bin count for each histogram bin of the ToF histogram based on the final count value of the corresponding analog counter.

[0190] Example 2. A method according to Example 1, wherein the initial count value corresponds to a first voltage, wherein the second count value corresponds to a second voltage different from the first voltage, wherein resetting the respective count values ​​of the plurality of analog counters comprises resetting the voltage of an associated storage capacitor of each analog counter to the first voltage, and wherein changing the count value of a selected one of the analog counters comprises changing the voltage of the associated storage capacitor toward the second voltage by a discrete voltage value.

[0191] Example 3. A method according to one of Examples 1 or 2, wherein the first voltage corresponds to a full-scale voltage that is higher than the second voltage, and wherein changing the voltage of the associated storage capacitor toward the second voltage by the discrete voltage value includes decreasing the voltage of the associated storage capacitor toward the second voltage by the discrete voltage value.

[0192] Example 4. The method of one of Examples 1 to 3, wherein the associated storage capacitor of each analog counter comprises a metal oxide semiconductor (MOS) capacitor or a metal oxide metal (MOM) capacitor or a reverse biased diode.

[0193] Example 5. The method according to one of Examples 1 to 4 further includes: determining the relevant remaining bin count of each histogram bin of the ToF histogram after the integration period and during the signal conversion period, wherein determining the relevant remaining bin count of each histogram bin includes: providing a plurality of pulses to the input of each analog counter; and for each analog counter, counting the relevant remaining number of pulses until the voltage of the relevant storage capacitor reaches the second voltage, wherein the relevant remaining bin count of each histogram bin is equal to the relevant remaining number of pulses of the corresponding analog counter, wherein determining the relevant final bin count of each histogram bin includes determining the relevant final bin count of each histogram bin based on the relevant remaining bin count.

[0194] Example 6. The method according to one of Examples 1 to 5 further includes: after the signal conversion cycle, resetting the voltage of the associated storage capacitor of each analog counter to the first voltage, and determining the associated full-scale bin count of each histogram bin, wherein determining the associated full-scale bin count of each histogram bin includes: providing multiple pulses to the input of each analog counter; and for each analog counter, counting the total number of associated pulses until the voltage of the associated storage capacitor reaches the second voltage from the first voltage, wherein the associated full-scale bin count of each histogram bin is equal to the associated total number of pulses of the corresponding analog counter, and wherein determining the associated final bin count of each histogram bin is also based on the associated full-scale bin count.

[0195] Example 7. A method according to one of Examples 1 to 6, wherein a ripple counter is used to count each of the associated remaining pulse numbers and each of the associated total pulse numbers, and wherein determining the associated final bin count for each histogram bin includes: latching the associated remaining bin count into a count latch; and subtracting the contents of the count latch from the output of the ripple counter using an adder to obtain the associated final bin count.

[0196] Example 8. A method according to one of Examples 1 to 7, wherein each digital address of the plurality of digital addresses comprises m bits, m being a positive integer greater than or equal to 1, wherein the plurality of analog counters comprises n analog counters, n being equal to 2m, and wherein selecting the one analog counter comprises using a decoder having n outputs respectively coupled to the n analog counters and a decoder input for receiving the plurality of digital addresses.

[0197] Example 9. The method of one of Examples 1 to 8, wherein the decoder comprises a low voltage digital signal (LVDS) latch.

[0198] Example 10. The method of one of Examples 1 to 9, wherein the decoder input is coupled to an output of a low voltage digital signal (LVDS) latch.

[0199] Example 11. The method of one of examples 1 to 10, wherein m is equal to 1 and n is equal to 2.

[0200] Example 12. The method of one of Examples 1 to 11, wherein the TDC comprises a low voltage digital signal (LVDS) latch.

[0201] Example 13. A method according to one of Examples 1 to 12, wherein each digital address of the plurality of digital addresses comprises 1 bit, wherein the plurality of analog counters comprises a first analog counter and a second analog counter, and wherein the LVDS latch comprises a first output coupled to the first analog counter and a second output coupled to the second analog counter.

[0202] Example 14. A time-of-flight (ToF) system comprising: a plurality of single-photon avalanche diodes (SPADs) configured to generate SPAD events; a plurality of time-to-digital converters (TDCs) coupled to the plurality of SPADs, wherein each of the plurality of TDCs is configured to generate a digital address based on the SPAD events generated by a corresponding SPAD in the plurality of SPADs; a plurality of histogram generation circuits, each of the plurality of histogram generation circuits coupled to a corresponding TDC in the plurality of TDCs, wherein each histogram generation circuit comprises: an addressing logic circuit having a plurality of outputs and an input configured to receive a digital address from the corresponding TDC, and a plurality of analog counters, wherein each of the plurality of analog counters comprises an input coupled to a corresponding output in the plurality of outputs of the addressing logic circuit, wherein each analog counter comprises an associated storage capacitor; and an analog-to-digital converter (ADC) coupled to the plurality of analog counters, wherein: each histogram generation circuit is configured To reset the voltage of the associated storage capacitor of each analog counter to a first voltage, the addressing logic circuit is configured to, after the resetting of the plurality of analog counters during an integration period, for each received digital address, select one of the plurality of analog counters based on the received digital address and assert the input of the selected one analog counter, wherein the selected one analog counter is configured to change the voltage of the associated storage capacitor of the selected one analog counter by a discrete voltage value toward a second voltage when the input of the selected one analog counter is asserted, wherein the associated storage capacitor of each analog counter is configured to have a final voltage at the end of the integration period, and the ADC is configured to convert the final voltage of the associated storage capacitor of each analog counter into a corresponding digital count, wherein each digital count is associated with a histogram bin of a ToF histogram, and wherein the associated final bin count of each histogram bin of the ToF histogram is based on the associated digital count.

[0203] Example 15. A ToF system according to example 14, wherein the first voltage is higher than the second voltage.

[0204] Example 16. A ToF system according to one of Examples 14 or 15, wherein each analog counter comprises: a charge transfer amplifier including the associated storage capacitor and having an input coupled to the input of the analog counter; and a readout circuit having an output coupled to the charge transfer amplifier and coupled to an input of the associated storage capacitor, and an output coupled to the ADC.

[0205] Example 17. A ToF system according to one of Examples 14 to 16, wherein each storage capacitor comprises a metal oxide semiconductor (MOS) capacitor or a metal oxide metal (MOM) capacitor or a reverse biased diode.

[0206] Example 18. A ToF system according to one of Examples 14 to 17, wherein the charge transfer amplifier comprises: an input transistor having a control terminal coupled to the input of the analog counter and a current path coupled to the output of the charge transfer amplifier; a reset transistor having a current path coupled between the output of the charge transfer amplifier and a first power supply terminal; and

[0207] A first transistor has a current path coupled between the current path of the input transistor and a second power supply terminal.

[0208] Example 19. The ToF system of one of Examples 14 to 18, wherein the reset transistor includes a body terminal coupled to a third power supply terminal different from the first power supply terminal.

[0209] Example 20. A ToF system according to one of Examples 14 to 19, wherein each of the digital addresses includes m bits, m is a positive integer greater than or equal to 1, wherein the plurality of analog counters includes n analog counters, n is equal to 2m, wherein the addressing logic circuit includes a decoder having n outputs, and wherein each histogram generation circuit further includes: n first logic gates, each of the n first logic gates having a first input respectively coupled to the n outputs of the decoder; and a pulse control circuit having an output coupled to a second input of each of the n first logic gates.

[0210] Example 21. A ToF system according to one of Examples 14 to 20, wherein the ADC includes: a comparator having a first input coupled to an analog counter of the n analog counters and a second input configured to receive the second voltage; a pulse generator configured to pulse the input of each of the multiple analog counters during a signal conversion cycle; and a ripple counter having an input coupled to an output of the comparator.

[0211] Example 22. A ToF system according to one of Examples 14 to 21, wherein the comparator is arranged inside a SPAD pixel of a SPAD array.

[0212] Example 23. The ToF system of one of Examples 14 to 22 further includes a timing generation circuit configured to provide m out-of-phase clock signals to the plurality of TDCs and to provide a trigger signal to an illumination source, wherein each TDC is configured to generate the digital address based on the m out-of-phase clock signals.

[0213] Example 24. A ToF system according to one of Examples 14 to 23, wherein the m out-of-phase clock signals are m differential out-of-phase clock signals, and wherein each TDC includes m low-voltage digital signal (LVDS) latches, each of the m LVDS latches having a differential clock input and a latch input, the differential clock input being configured to receive a corresponding differential out-of-phase clock signal among the m differential out-of-phase clock signals, and the latch input being configured to receive a SPAD event.

[0214] Example 25. A ToF system according to one of Examples 14 to 24, further comprising a SPAD array, the SPAD array comprising a pixel array, the pixel array comprising the plurality of SPADs, wherein each pixel of the SPAD array comprises a SPAD from the plurality of SPADs, and a SPAD front-end circuit.

[0215] Example 26. A ToF system according to one of Examples 14 to 25, wherein the ADC is configured to provide a plurality of pulses to the input of each analog counter during a signal conversion cycle, and for each analog counter, count the associated remaining number of pulses until the voltage of the associated storage capacitor reaches the second voltage, wherein the ADC is configured to convert the final voltage of the associated storage capacitor of each analog counter into a corresponding digital count based on the count of the associated remaining number of pulses of the corresponding analog counter.

[0216] Example 27. A ToF system according to one of Examples 14 to 26, wherein each histogram generation circuit is configured to reset the voltage of the associated storage capacitor of each analog counter to the first voltage after the signal conversion cycle, and wherein the ADC is configured to provide multiple pulses to the input of each analog counter during a full-scale conversion cycle, and for each analog counter, count the number of full-scale pulses until the voltage of the associated storage capacitor reaches the second voltage from the first voltage, wherein the ADC is configured to convert the final voltage of the associated storage capacitor of each analog counter into the corresponding digital count based on the count of the number of full-scale pulses of the corresponding analog counter.

[0217] Example 28. A time-of-flight (ToF) system, comprising: a single-photon avalanche diode (SPAD) array, comprising a pixel array, each pixel of the pixel array comprising a SPAD and a SPAD front-end circuit; a plurality of time-to-digital converters (TDCs) coupled to corresponding SPADs of the SPAD array, wherein each of the plurality of TDCs is configured to generate a digital address based on a SPAD event generated by the corresponding SPAD, wherein each of the digital addresses comprises m bits, where m is a positive integer greater than or equal to 1; and a plurality of histogram generation circuits, each of the plurality of histogram generation circuits comprising: an addressing logic circuit having having n outputs and inputs configured to receive digital addresses from the respective TDCs, n analog counters, n being equal to 2m, wherein each of the n analog counters comprises an input coupled to a respective one of the n outputs of the addressing logic circuit, wherein each analog counter comprises an associated storage capacitor, n first logic gates, each of the n first logic gates having a first input coupled to the n outputs of the addressing logic circuit, respectively, and a pulse control circuit having an output coupled to a second input of each of the n first logic gates; and an analog-to-digital converter (ADC) coupled to the n analog counters.

[0218] Example 29. A ToF system according to Example 28, wherein the ADC includes: a comparator having a first input coupled to a first analog counter of the n analog counters and a second input configured to receive a reference voltage; a pulse generator having an output coupled to the input of the first analog counter; and a ripple counter having an input coupled to the output of the comparator.

[0219] Although the present invention has been described with reference to illustrative embodiments, this description is not intended to be construed as limiting. Various modifications and combinations of the illustrative embodiments, as well as other embodiments of the present invention, will become apparent to those skilled in the art by reference to the specification. Accordingly, the appended claims are intended to cover any such modifications or embodiments.

Claims

1. A method for time-of-flight (ToF) operation, comprising: resetting respective count values ​​of a plurality of analog counters to initial count values, each analog counter of the plurality of analog counters corresponding to a histogram bin of a ToF histogram; receiving a plurality of digital addresses from a time-to-digital converter (TDC) after resetting the respective count values ​​of the plurality of analog counters, the TDC having an input coupled to a single photon avalanche diode (SPAD); during an integration period, for each received digital address in the plurality of digital addresses, selecting one of the plurality of analog counters based on the received digital address and changing the corresponding count value of the selected one of the analog counters by a discrete amount toward a second count value that is different from the initial count value, wherein each analog counter has a final count value at the end of the integration period; as well as After the integration period, an associated final bin count for each histogram bin of the ToF histogram is determined based on the final count value of the corresponding analog counter.

2. The method of claim 1 , wherein the initial count value corresponds to a first voltage, wherein the second count value corresponds to a second voltage different from the first voltage, wherein resetting the respective count values ​​of the plurality of analog counters comprises resetting a voltage of an associated storage capacitor of each analog counter to the first voltage, and wherein changing the count value of the selected one of the analog counters comprises changing the voltage of the associated storage capacitor toward the second voltage by discrete voltage values.

3. The method of claim 2 , wherein the first voltage corresponds to a full-scale voltage that is higher than the second voltage, and wherein changing the voltage of the associated storage capacitor toward the second voltage by the discrete voltage value comprises decreasing the voltage of the associated storage capacitor toward the second voltage by the discrete voltage value.

4. The method according to claim 2, further comprising: After the integration period and during a signal conversion period, determining a residual bin count associated with each histogram bin of the ToF histogram, wherein determining the residual bin count associated with each histogram bin comprises: providing a plurality of pulses to an input of each analog counter; and For each analog counter, an associated number of remaining pulses is counted until the voltage of the associated storage capacitor reaches the second voltage, wherein the associated remaining bin count of each histogram bin is equal to the associated number of remaining pulses of the corresponding analog counter, wherein determining the associated final bin count of each histogram bin comprises determining the associated final bin count of each histogram bin based on the associated remaining bin count.

5. The method according to claim 4, further comprising: After the signal conversion period, resetting the voltage of the associated storage capacitor of each analog counter to the first voltage and determining an associated full-scale bin count for each histogram bin, wherein determining the associated full-scale bin count for each histogram bin comprises: providing a plurality of pulses to an input of each of said analog counters; and For each analog counter, an associated total number of pulses is counted until the voltage of the associated storage capacitor reaches the second voltage from the first voltage, wherein the associated full-scale bin count of each histogram bin is equal to the associated total number of pulses of the corresponding analog counter, and wherein determining the associated final bin count of each histogram bin is further based on the associated full-scale bin count.

6. The method of claim 5 , wherein a ripple counter is configured to count each of the associated remaining pulse numbers and each of the associated total pulse numbers, and wherein determining the associated final bin count for each of the histogram bins comprises: latching the relevant remaining box count into a count latch; as well as The contents of the count latch are subtracted from the output of the ripple counter using an adder to obtain the associated final bin count.

7. The method according to claim 1, wherein each of the plurality of digital addresses comprises m bits, m being a positive integer greater than or equal to 1, wherein the plurality of analog counters comprises n analog counters, n being equal to 2 m , and wherein selecting the one analog counter comprises using a decoder having n outputs respectively coupled to the n analog counters and a decoder input for receiving the plurality of digital addresses. The method of claim 7 , wherein the decoder comprises a low voltage digital signal (LVDS) latch.

9. The method of claim 7, wherein the decoder input is coupled to an output of a low voltage digital signal (LVDS) latch.

10. The method of claim 7, wherein m is equal to 1 and n is equal to 2. The method of claim 1 , wherein the TDC comprises a low voltage digital signal (LVDS) latch.

12. The method of claim 11 , wherein each of the plurality of digital addresses comprises 1 bit, wherein the plurality of analog counters comprises a first analog counter and a second analog counter, and wherein the LVDS latch comprises a first output coupled to the first analog counter and a second output coupled to the second analog counter.

13. A time-of-flight (ToF) system, comprising: a plurality of single photon avalanche diodes (SPADs) configured to generate SPAD events; a plurality of time-to-digital converters (TDCs) coupled to the plurality of SPADs, wherein each TDC of the plurality of TDCs is configured to generate a digital address based on a SPAD event generated by an associated SPAD of the plurality of SPADs; a plurality of histogram generation circuits, each histogram generation circuit of the plurality of histogram generation circuits coupled to a corresponding TDC of the plurality of TDCs, wherein each histogram generation circuit comprises: an addressing logic circuit having a plurality of outputs and an input configured to receive a digital address from the corresponding TDC, and a plurality of analog counters, wherein each of the plurality of analog counters includes an input coupled to a respective one of the plurality of outputs of the addressing logic circuit, wherein each analog counter includes an associated storage capacitor; and an analog-to-digital converter (ADC) coupled to the plurality of analog counters, wherein: Each histogram generation circuit is configured to reset the voltage of the associated storage capacitor of each analog counter to a first voltage, The addressing logic circuit is configured to, after the resetting of the plurality of analog counters during an integration period, for each received digital address, select one of the plurality of analog counters based on the received digital address, and asserting the input of the selected one of the analog counters, wherein the selected one of the analog counters is configured to change the voltage of the associated storage capacitor of the selected one of the analog counters toward a second voltage by a discrete voltage value when the input of the selected one of the analog counters is asserted, wherein the associated storage capacitor of each of the analog counters is configured to have a final voltage at the end of the integration period, and The ADC is configured to convert the final voltage of the associated storage capacitor of each analog counter into a corresponding digital count, wherein each digital count is associated with a histogram bin of a ToF histogram, and wherein the associated final bin count of each histogram bin of the ToF histogram is based on the associated digital count. The ToF system according to claim 13 , wherein the first voltage is higher than the second voltage.

15. The ToF system of claim 13 , wherein each analog counter comprises: a charge transfer amplifier including the associated storage capacitor and having an input coupled to the input of the analog counter; as well as A readout circuit has an input coupled to the output of the charge transfer amplifier and to the associated storage capacitor, and an output coupled to the ADC. 16 . The ToF system according to claim 15 , wherein each storage capacitor comprises a metal oxide semiconductor (MOS) capacitor, a metal oxide metal (MOM) capacitor, or a reverse biased diode.

17. The ToF system of claim 15, wherein the charge transfer amplifier comprises: an input transistor having a control terminal coupled to the input of the analog counter and a current path coupled to the output of the charge transfer amplifier; a reset transistor having a current path coupled between the output of the charge transfer amplifier and a first power supply terminal; as well as A first transistor has a current path coupled between the current path of the input transistor and a second power supply terminal. 18 . The ToF system of claim 17 , wherein the reset transistor comprises a body terminal coupled to a third power supply terminal different from the first power supply terminal.

19. The ToF system according to claim 13, wherein each of the digital addresses comprises m bits, m being a positive integer greater than or equal to 1, wherein the plurality of analog counters comprises n analog counters, n being equal to 2 m , wherein the addressing logic circuit comprises a decoder having n outputs, and wherein each histogram generation circuit further comprises: n first logic gates, each of the n first logic gates having a first input coupled to the n outputs of the decoder, respectively; as well as A pulse control circuit has an output coupled to the second input of each of the n first logic gates.

20. The ToF system of claim 19, wherein the ADC comprises: a comparator having a first input coupled to an analog counter of the n analog counters and a second input configured to receive the second voltage; a pulse generator configured to pulse the input of each of the plurality of analog counters during a signal conversion cycle; as well as A ripple counter has an input coupled to the output of the comparator. The ToF system according to claim 20 , wherein the comparator is disposed inside a SPAD pixel of a SPAD array.

22. The ToF system of claim 19, further comprising a timing generation circuit configured to provide m out-of-phase clock signals to the plurality of TDCs and to provide a trigger signal to an illumination source, wherein each TDC is configured to generate the digital address based on the m out-of-phase clock signals.

23. The ToF system of claim 22 , wherein the m out-of-phase clock signals are m differential out-of-phase clock signals, and wherein each TDC comprises m low voltage digital signal (LVDS) latches, each of the m LVDS latches having a differential clock input and a latch input, the differential clock input being configured to receive a corresponding differential out-of-phase clock signal among the m differential out-of-phase clock signals, and the latch input being configured to receive a SPAD event.

24. The ToF system according to claim 13, further comprising a SPAD array, the SPAD array comprising a pixel array, the pixel array comprising the plurality of SPADs, wherein each pixel of the SPAD array comprises a SPAD from the plurality of SPADs and a SPAD front-end circuit.

25. The ToF system of claim 13 , wherein the ADC is configured to provide a plurality of pulses to the input of each analog counter during a signal conversion period, and for each analog counter, count an associated number of remaining pulses until the voltage of the associated storage capacitor reaches the second voltage, wherein the ADC is configured to convert the final voltage of the associated storage capacitor of each analog counter into a corresponding digital count based on the count of the associated number of remaining pulses of the corresponding analog counter.

26. The ToF system of claim 25 , wherein each histogram generation circuit is configured to reset the voltage of the associated storage capacitor of each analog counter to the first voltage after the signal conversion period, and wherein the ADC is configured to provide a plurality of pulses to the input of each analog counter during a full-scale conversion period, and to count the number of full-scale pulses for each analog counter until the voltage of the associated storage capacitor reaches the second voltage from the first voltage, wherein the ADC is configured to convert the final voltage of the associated storage capacitor of each analog counter into the corresponding digital count based on the count of the number of full-scale pulses of the corresponding analog counter.

27. A time-of-flight (ToF) system, comprising: A single-photon avalanche diode (SPAD) array includes a pixel array, each pixel of the pixel array includes a SPAD and a SPAD front-end circuit; a plurality of time-to-digital converters (TDCs) coupled to corresponding SPADs of the SPAD array, wherein each TDC of the plurality of TDCs is configured to generate a digital address based on a SPAD event generated by the corresponding SPAD, wherein each of the digital addresses comprises m bits, where m is a positive integer greater than or equal to 1; A plurality of histogram generation circuits, each of the plurality of histogram generation circuits comprising: an addressing logic circuit having n outputs and an input configured to receive a digital address from the corresponding TDC, n analog counters, n equals 2 m , wherein each of the n analog counters comprises an input coupled to a respective one of the n outputs of the addressing logic circuit, wherein each analog counter comprises an associated storage capacitor, n first logic gates, each of the n first logic gates having a first input coupled to a respective one of the n outputs of the addressing logic circuit, and a pulse control circuit having an output coupled to a second input of each of the n first logic gates; as well as An analog-to-digital converter (ADC) is coupled to the n analog counters.

28. The ToF system of claim 27, wherein the ADC comprises: a comparator having a first input coupled to a first analog counter of the n analog counters and a second input configured to receive a reference voltage; a pulse generator having an output coupled to an input of the first analog counter; as well as A ripple counter has an input coupled to the output of the comparator.

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