A server system

Abstract

The application discloses a server system applied to the technical field of hardware architecture, and comprises a bottom plate for connecting mainboards, N mainboards connected with the bottom plate, and one CPU arranged on each mainboard; N is a positive integer not less than 2; when the server system is a full-interconnected server system, UPI interface modules of the CPUs of the N mainboards are connected into a communication loop through UPI connectors and cables to form N CPU systems; when the server system is a non-interconnected server system, the N mainboards work independently to form N single-path CPU systems. The application can improve the flexibility of the server system, realize flexible partition processing, and enable the N mainboards to form N CPU systems or N single-path CPU systems.

Description

Technical Field

[0001] This invention relates to the field of hardware architecture technology, and in particular to a server system. Background Technology

[0002] With the rapid development of servers and their increasingly widespread applications, the processor manufacturers used in servers are no longer monopolistic; multiple manufacturers and platforms compete and complement each other. Furthermore, there are more stringent requirements for the integration and density of server systems, leading to increasingly complex requirements for cabling layouts and hardware configurations within a fixed chassis size.

[0003] Most server motherboards on the market today are only compatible with processors from a single manufacturer. This means that current server motherboards are typically customized for specific processor manufacturers, resulting in low server hardware density and the inability to select partitioning methods for multi-processor systems based on actual needs. For example... Figure 1 This is a schematic diagram of the architecture of a commonly used 2U2 server system. CPU0, CPU1, PCH (Platform Controller Hub, integrated southbridge), BMC (Board Management Controller), and CPLD (Complex Programmable Logic Device) are all arranged on the same motherboard. If any one of the CPUs (Central Processing Unit) in CPU0 and CPU1, or the PCH, BMC chip, or other components are damaged, the motherboard will no longer be usable. Figure 1 CPU0 and CPU1 in the system constitute a 2-way CPU system. Their UPI (Ultra Path Interconnect) interface is routed through the PCB (Printed Circuit Board) on the board to complete the communication connection.

[0004] Due to its low flexibility, traditional solutions require customized server systems for different scenarios, such as those with high computing power requirements. Figure 1 The above-mentioned solution is a 2-way CPU system. In cases where CPU core utilization is required to be high, two single-way CPU systems need to be specially configured.

[0005] In conclusion, how to effectively build server systems and improve their flexibility to achieve flexible partitioning is a technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0006] The purpose of this invention is to provide a server system that can be used to effectively build server systems, improve flexibility, and enable flexible partitioning.

[0007] To solve the above-mentioned technical problems, the present invention provides the following technical solution:

[0008] A server system, characterized in that it comprises:

[0009] The base plate used to connect to the motherboard;

[0010] N motherboards are connected to the base plate, and each motherboard is equipped with one CPU; N is a positive integer not less than 2;

[0011] When the server system is a fully interconnected server system, the UPI interface modules of the CPUs of N motherboards are connected to form a communication loop through UPI connectors and cables to form an N-way CPU system.

[0012] When the server system is an unconnected server system, N motherboards work independently to form N single-socket CPU systems.

[0013] Preferably, for any one motherboard, PCIe connectors are provided on both the front and back sides of the motherboard.

[0014] Preferably, for any one motherboard, the motherboard is provided with PCIe gold fingers, an EXAMAX high-density connector interface and a power connection interface, and the PCIe gold fingers of the motherboard are connected to the corresponding slots of the base plate, the EXAMAX high-density connector interface of the motherboard is connected to the corresponding EXAMAX high-density connector interface of the base plate, and the power connection interface of the motherboard is connected to the corresponding power connection interface of the base plate.

[0015] Preferably, each slot on the base plate is connected to a corresponding CDFP interface, and for any slot whose distance to its corresponding CDFP interface exceeds a first distance threshold, the slot is connected to its corresponding CDFP interface via a retimer.

[0016] Preferably, for any one motherboard, the motherboard is provided with a network card interface;

[0017] The network card interface of any one or more of the N motherboards is connected to the OCP network card interface of the base plate.

[0018] Preferably, the base plate is provided with x y-channel riser connectors, and any motherboard can connect up to 8*z PCIe channels to the riser connectors of the base plate.

[0019] For any one of the N motherboards, the motherboard is provided with z 8-channel PCIe interfaces and right-angle connectors that are respectively connected to the z 8-channel PCIe interfaces.

[0020] Where x, y, and z are all positive integers.

[0021] Preferably, when N=4 and the server system is a fully interconnected server system, the UPI interface modules of the CPUs of the N motherboards are connected to form a communication loop through UPI connectors and cables to form a 4-way CPU system.

[0022] Among them, the UPI interface module of the CPU of the first motherboard is connected to the UPI interface module of the CPU of the second motherboard through a UPI connector and a cable to form a communication loop, and the UPI interface module of the CPU of the third motherboard is connected to the UPI interface module of the fourth motherboard through a UPI connector and a cable to form a communication loop.

[0023] The UPI interface module of the CPU of any one of the first motherboards and the second motherboards is connected to the UPI interface module of the CPU of any one of the third motherboards and the fourth motherboards to form a communication loop through a UPI connector and cable, or through two EXAMAX high-density connector interfaces on the baseboard to form a communication loop.

[0024] Preferably, when the UPI interface module of the CPU of the first motherboard and the UPI interface module of the CPU of the third motherboard are connected to form a communication loop through the two EXAMAX high-density connector interfaces of the baseboard, the UPI interface module of the CPU of the second motherboard and the UPI interface module of the CPU of the fourth motherboard are connected to form a communication loop through the two EXAMAX high-density connector interfaces of the baseboard.

[0025] When the UPI interface module of the CPU of the first motherboard and the UPI interface module of the CPU of the fourth motherboard are connected to form a communication loop through the two EXAMAX high-density connector interfaces on the baseboard, the UPI interface module of the CPU of the second motherboard and the UPI interface module of the CPU of the third motherboard are connected to form a communication loop through the two EXAMAX high-density connector interfaces on the baseboard.

[0026] Preferably, when N≥3 and the server system is a partially interconnected server system, at least K motherboards have CPU UPI interface modules connected to form a communication loop through UPI connectors and cables to form a K-way CPU system.

[0027] Where K is a positive integer not less than 2 and K < N.

[0028] Preferably, among the N motherboards, at least one motherboard works independently to form a single-processor CPU system.

[0029] The technical solution provided in this invention provides a baseboard for connecting motherboards, and N motherboards connected to the baseboard. Since each motherboard has one CPU, damage to a single motherboard will not affect the use of other motherboards. In this application, the UPI interface modules of different CPUs are not directly connected via the PCB within the board; instead, UPI connectors are used, allowing connection via cables. Furthermore, when the server system is a fully interconnected server system, the UPI interface modules of the CPUs on the N motherboards are connected via UPI connectors and cables to form a communication loop, constituting an N-way CPU system. When the server system is a non-interconnected server system, the N motherboards operate independently, constituting N single-way CPU systems. In other words, this application supports both N motherboards forming an N-way CPU system and N motherboards forming N single-way CPU systems, offering high flexibility. In summary, this application effectively constructs a server system, improves flexibility, enables flexible partitioning, and allows N motherboards to form both an N-way CPU system and N single-way CPU systems. Attached Figure Description

[0030] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0031] Figure 1 This is a schematic diagram of the architecture of a commonly used 2U2 server system.

[0032] Figure 2 This is a schematic diagram of the first structure of the server system in this invention;

[0033] Figure 3 This is a schematic diagram of the second structure of the server system in this invention;

[0034] Figure 4 This is a schematic diagram of the third structure of the server system in this invention;

[0035] Figure 5 This is a schematic diagram of the fourth structure of the server system in this invention;

[0036] Figure 6 This is a schematic diagram of the fifth structure of the server system in this invention. Detailed Implementation

[0037] The core of this invention is to provide a server system that improves flexibility, enables flexible partitioning, and allows N motherboards to form an N-way CPU system, or N motherboards to form N single-way CPU systems.

[0038] To enable those skilled in the art to better understand the present invention, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. Obviously, the described embodiments are merely some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0039] Please refer to Figure 2 , Figure 2 This is a schematic diagram of the structure of a server system according to the present invention. The server system may include:

[0040] Base plate 20 for connecting motherboard 10;

[0041] N motherboards 10 are connected to the base plate 20, and each motherboard 10 is equipped with one CPU; N is a positive integer not less than 2;

[0042] When the server system is a fully interconnected server system, the UPI interface modules of the CPUs of N motherboards 10 are connected to form a communication loop through UPI connectors and cables to form an N-way CPU system.

[0043] When the server system is an unconnected server system, N motherboards 10 work independently to form N single-socket CPU systems.

[0044] Specifically, in Figure 2 In the implementation method, N=2, and Figure 2 In this implementation, the server system is a non-interconnected server system, meaning that the two motherboards 10 work independently to form two single-socket CPU systems.

[0045] The base plate 20 of this application is used to connect the main board 10. Figure 2 In this embodiment, the base plate 20 has four slots that can connect one to four motherboards 10.

[0046] To avoid the situation in traditional solutions where "if a single CPU on a motherboard fails, even if another CPU on the same motherboard is not faulty, the non-faulty CPU cannot be used, meaning the motherboard still needs to be replaced," the single motherboard 10 in this application will only have one CPU chip. For example... Figure 2The CPU chips on the two motherboards 10 are labeled CPU0 and CPU1, respectively.

[0047] It should be noted that due to the CPU configuration, when any CPU on the motherboard 10 operates independently, its UPI0 interface needs to be connected to its own UPI1 interface. However, in the solution of this application, since it is also necessary to support the connection of the CPU's UPI interface module to other CPUs' UPI interface modules via cables, corresponding connectors can be provided for each UPI interface of the UPI interface module. Of course, in some cases, if there are many UPI interfaces, i.e., when achieving full interconnection, these UPI interfaces may not be needed, or when using a UPI interface, a cable connection is not required. In such cases, from a cost-saving perspective, corresponding connectors may not be necessary for these UPI interfaces. However, any CPU must have at least corresponding UPI0 and UPI1 connectors, i.e. Figure 2 The UPI0 and UPI1 connectors are included.

[0048] In other words, Figure 2 In the implementation method, for CPU0, it is necessary to connect the UPI0 interface of CPU0 to the UPI0 connector, connect the UPI1 interface of CPU0 to the UPI1 connector, and connect the UPI0 connector to the UPI1 connector, thereby realizing the connection between the UPI0 interface of CPU0 and the UPI1 interface of CPU0 itself.

[0049] Similarly, for Figure 2 In the implementation method, CPU1 also needs to connect its UPI0 interface to its own UPI1 interface so that CPU1 can work independently.

[0050] Furthermore, for any one of the CPUs mentioned in the following implementation, if the CPU is set to work independently, it is also necessary to connect the CPU's UPI0 interface with the CPU's own UPI1 interface.

[0051] See also Figure 3 ,exist Figure 3 In the implementation method, N=2, and Figure 3 In this implementation, the server system is an interconnected server system, that is, the UPI interface modules of the CPUs of the two motherboards 10 are connected to form a communication loop through UPI connectors and cables to form a 2-way CPU system.

[0052] The CPU's UPI interface module can include multiple UPI interfaces, typically four, labeled UPI0, UPI1, UPI2, and UPI3. The UPI interface module of each CPU in this application includes four UPI interfaces. Of course, in other specific embodiments, CPUs may have more UPI interfaces, without affecting the implementation of this invention. Furthermore, this invention can support CPUs from different manufacturers for different motherboards, without affecting the implementation of this invention.

[0053] It should also be noted that when constructing an N-way CPU system, the number of UPI interfaces in the UPI interface module required by each CPU depends on the specific value of N. As long as the communication loop can be formed through the UPI interface modules of each CPU via UPI connectors and cables, it is sufficient.

[0054] For example in Figure 3 In this implementation, for CPU0 and CPU1, only UPI0 and UPI1 are needed in their UPI interface modules. The required UPI connectors are the UPI0 and UPI1 connectors corresponding to the UPI0 and UPI1 interfaces of CPU0, and the UPI0 and UPI1 connectors corresponding to the UPI0 and UPI1 interfaces of CPU1. Figure 3 The system requires the use of two motherboards, which together have a total of four UPI interfaces and four UPI connectors, to implement a dual-CPU system.

[0055] Compared to traditional motherboards 10 which only arrange components on one side, in one specific embodiment of the present invention, for any motherboard 10, PCIe connectors are provided on both the front and back sides to improve the resource density of the server system of this application. Of course, the specific positions of the PCIe connectors can be arranged as needed.

[0056] In one specific embodiment of the present invention, for any motherboard 10, the motherboard 10 is provided with PCIe gold fingers, EXAMAX high-density connector interface and power connection interface, and the PCIe gold fingers of the motherboard 10 are connected to the corresponding slots of the base plate 20, the EXAMAX high-density connector interface of the motherboard 10 is connected to the corresponding EXAMAX high-density connector interface of the base plate 20, and the power connection interface of the motherboard 10 is connected to the corresponding power connection interface of the base plate 20.

[0057] The motherboard 10 in this application needs to be connected to the base plate 20. In this embodiment, by connecting the PCIe gold fingers of the motherboard 10 to the corresponding slots of the base plate 20, in addition to enabling PCIe routing and functioning as a PCIe connector, it also serves to fix the motherboard 10. For example Figure 2 and Figure 3 In this implementation, the PCIe gold fingers of the left motherboard 10 are connected to slot 0 of the baseboard 20. The specific connection position of the PCIe gold fingers to the CPU 0 can be set as needed, as not shown in the figure. For example, for the five PCIe interfaces (PE0 to PE5) in the figure, it can be connected to the PE0 interface of the CPU 0. Accordingly, Figure 2 and Figure 3 In this implementation, the PCIe gold finger of the right motherboard 10 is connected to the slot 1 of the base plate 20. The specific connection position of the PCIe gold finger to the CPU1 can also be set as needed, which is not shown in the figure. For example, it can be connected to the PE0 interface of the CPU1.

[0058] The EXAMAX high-density connector interface of the motherboard 10 connects to the corresponding EXAMAX high-density connector interface of the baseboard 20. The specific wiring layout inside the EXAMAX high-density connector can be set and adjusted according to actual needs. The EXAMAX high-density connector can achieve a large number of wirings while occupying little space.

[0059] The power connection interface of the motherboard 10 needs to be connected to the corresponding power connection interface of the base plate 20 to ensure that the corresponding devices in the motherboard 10 can be powered. In the various figures of this application, the power connection interface of the motherboard 10 and the power connection interface of the base plate 20 are both represented by PWR.

[0060] In one specific embodiment of the present invention, each slot of the base plate 20 is connected to the corresponding CDFP interface, and for any slot whose distance to its corresponding CDFP interface exceeds a first distance threshold, the slot is connected to its corresponding CDFP interface through a re-timer.

[0061] The CDFP interface, also known as the CDFP connector, stands for 400Gb / s (16 x 25Gb / s) Pluggable Transceiver, which is a 16-channel pluggable connector.

[0062] In this embodiment, the base plate 20 is provided with multiple CDFP interfaces, which are connected to the corresponding slots respectively. Furthermore, for any one slot, if the distance between the slot and its corresponding CDFP interface exceeds a first distance threshold, it indicates that the distance between the slot and the corresponding CDFP interface is too far. Considering the need to ensure the high-speed transmission of PCIe signals, the slot will connect to its corresponding CDFP interface through a retimer.

[0063] For example Figure 4 and Figure 5In this implementation, slots Slot0 and Slot2 are far from their respective CDFP interfaces, therefore a retimer is set for both. Figure 4 The two Retims in it. Additionally, it should be noted that... Figure 4 and Figure 5 In this embodiment, for ease of viewing the accompanying drawings, only the connection between slot Slot0 and slot Slot2 and the gold fingers of the corresponding motherboard 10 is shown, and the connection between slot Slot1 and slot Slot3 and the gold fingers of the corresponding motherboard 10 is not shown.

[0064] In one specific embodiment of the present invention, for any one motherboard 10, the motherboard 10 is provided with a network card interface;

[0065] The network card interface of any one or more of the N motherboards 10 is connected to the OCP network card interface of the base plate 20.

[0066] In this implementation, the network card interface of the motherboard 10 can be connected to the OCP (Open Compute Project) network card interface of the baseboard 20 to achieve high-speed and long-distance data transmission through the OCP network card. Furthermore, in this implementation, the network card interfaces of any one or more of the N motherboards 10 can be connected to the OCP network card interface of the baseboard 20. Through the Multi-Host OCP function, the failure of a single motherboard 10 will not affect the network card functionality of the other motherboards 10.

[0067] In practical applications, with Figure 4 Taking the motherboard 10 where CPU0 is located as an example, the PCIe interface X4 in the upper left position can be used as the network card interface of the motherboard 10, and the network card interface can be connected to the OCP network card interface of the base plate 20.

[0068] In addition, it should be noted that Figure 2 and Figure 3 The motherboard 10 in the image can be considered as the front part of the motherboard 10. However, in practical applications, the UPI1 connector is usually located on the back of the motherboard 10. Figure 2 and Figure 3 For ease of viewing, the UPI1 connector is shown on the front side of the motherboard 10.

[0069] Figure 4 and Figure 5 The motherboard 10 in the image can be considered as the back of the motherboard 10. Similarly, the CPU is located on the front of the motherboard 10, but... Figure 4 and Figure 5 For easier viewing, the CPU is still shown on the back of the motherboard 10.

[0070] In one specific embodiment of the present invention, the base plate 20 is provided with x y-channel riser connectors, and any one motherboard 10 connects at most 8*z PCIe channels to the riser connectors of the base plate 20.

[0071] For any one of the N motherboards 10, the motherboard 10 is provided with z 8-channel PCIe interfaces and right-angle connectors that are connected to the z 8-channel PCIe interfaces respectively.

[0072] Where x, y, and z are all positive integers.

[0073] by Figure 4 Taking the implementation method as an example, in this case, x = 2, y = 64, and z = 5. That is... Figure 4 In the motherboard 20, there are two ×64 riser connectors. Since the motherboard 10 has five 8-channel PCIe interfaces and right-angle connectors that connect to these five 8-channel PCIe interfaces, any one motherboard 10 can connect up to 8*5=40 PCIe channels to the riser connectors of the motherboard 20.

[0074] Of course, in practical applications, motherboard 10 typically does not connect the 8*z PCIe lanes to the riser connectors on the backplane 20, for example, for Figure 4 In this implementation, each motherboard 10 can connect two × 8 PCIe interfaces to the riser connector of the baseboard 20, i.e. Figure 4 In this case, for each motherboard 10, two ×8 PCIe interfaces (P1×8 and P2×8) can be connected to the riser connector of the baseboard 20. Figure 4 In the P1×8RA section, it means a right-angle connector that connects to P1×8, and RA stands for (RightAngle).

[0075] In this embodiment, the riser connector of the base plate 20 facilitates the flexible use of the PCIe lanes of the motherboard 10, and the use of right-angle connectors is to facilitate wiring.

[0076] In one specific embodiment of the present invention, when N=4 and the server system is a fully interconnected server system, the UPI interface modules of the CPUs of the N motherboards 10 are connected to form a communication loop through UPI connectors and cables to form a 4-way CPU system.

[0077] Among them, the UPI interface module of the CPU of the first motherboard 10 is connected to the UPI interface module of the CPU of the second motherboard 10 through a UPI connector and a cable to form a communication loop, and the UPI interface module of the CPU of the third motherboard 10 is connected to the UPI interface module of the fourth motherboard 10 through a UPI connector and a cable to form a communication loop.

[0078] The UPI interface module of the CPU of any one of the motherboards 10 and 2 can be connected to the UPI interface module of the CPU of any one of the motherboards 10 and 3 or 4 via a UPI connector and cable to form a communication loop, or via two EXAMAX high-density connector interfaces on the base plate 20 to form a communication loop.

[0079] The specific value of N can be set and selected according to actual needs, and N=4 in this implementation method is a commonly used scheme in practical applications.

[0080] To construct a 4-way CPU system, Figure 4 Taking the implementation method as an example, the UPI interface module of CPU0 needs to be connected to the UPI interface module of CPU1 through a UPI connector and cable to form a communication loop. The connection method can be found in [reference]. Figure 3 ,therefore Figure 4 Not shown in the diagram. Similarly, the UPI interface module of CPU2 needs to be connected to the UPI interface module of CPU3 via a UPI connector and cable to form a communication loop. The connection method is the same as... Figure 3 The principle is the same, therefore Figure 4 It is not shown in the middle either.

[0081] Next, the CPU of one of the motherboards 10 (Motherboard 10) and 2 (Motherboard 10), and the CPU of one of the motherboards 10 (Motherboard 3) and 4 (Motherboard 10) need to be selected, and their UPI interface modules need to be connected for communication. Of course, the specific interface in the selected UPI interface module needs to be an unused UPI interface. For example, when connecting the UPI interface module of CPU0 to the UPI interface module of CPU1 through a UPI connector and cable to form a communication loop, UPI0 and UPI1 of CPU0 and UPI0 and UPI1 of CPU1 are used. Then, for example, when connecting the UPI interface module of CPU1 to the UPI interface module of CPU3, either UPI2 or UPI3 of CPU1 can be selected.

[0082] Furthermore, in this embodiment, after selecting the CPU of one of the motherboards 10 (first motherboard 10 and second motherboard 10) and the CPU of one of the motherboards 10 (third motherboard 10 and fourth motherboard 10), there are two ways to connect their UPI interface modules for communication. One way is to connect them into a communication loop using a UPI connector and cable, for example... Figure 5 One method involves connecting the UPI2 pins of both devices to their respective UPI2 connectors, and then connecting them via cables to form a communication loop. The other method is... Figure 4 In this implementation, the UPI2 of both devices is connected to their respective EXAMAX. Of course, in this implementation, the corresponding EXAMAX on the base plate 20 needs to be connected to form a communication loop between the two UPI2 devices.

[0083] Figure 4 and Figure 5 The diagram shows the fully interconnected scheme when N=4. When N=8, it can be divided into 2 groups, with each group having 4 CPUs. Figure 4 or Figure 5 For the fully interconnected solution, regarding communication between the two groups, one CPU can be randomly selected from each group, and their UPI3 interfaces can be connected to form a communication loop via UPI3 connectors and cables. Alternatively, their UPI3 interfaces can be connected to form a communication loop via corresponding EXAMAX interfaces on the baseboard 20. The principle is the same as described above and will not be repeated. N=2, 4, and 8 are commonly used solutions in practical applications. N is usually set to a maximum of 10, meaning the baseboard 20 has 10 slots. For larger numbers of N, the size requirements for the baseboard 20 become very high, and the space occupied is large, so it is not commonly used. Of course, for specific applications where there is a need for more than 10 slots, a design can be made to connect the corresponding number of baseboards 20 without affecting the implementation of this invention.

[0084] In one specific embodiment of the present invention, when the UPI interface module of the CPU of the first motherboard 10 and the UPI interface module of the CPU of the third motherboard 10 are connected to form a communication loop through the two EXAMAX high-density connector interfaces of the base plate 20, the UPI interface module of the CPU of the second motherboard 10 and the UPI interface module of the CPU of the fourth motherboard 10 are connected to form a communication loop through the two EXAMAX high-density connector interfaces of the base plate 20.

[0085] When the UPI interface module of the CPU of the first motherboard 10 and the UPI interface module of the CPU of the fourth motherboard 10 are connected to form a communication loop through the two EXAMAX high-density connector interfaces of the baseboard 20, the UPI interface module of the CPU of the second motherboard 10 and the UPI interface module of the CPU of the third motherboard 10 are connected to form a communication loop through the two EXAMAX high-density connector interfaces of the baseboard 20.

[0086] For example Figure 6 In this implementation, the UPI interface module of the CPU (CPU1) of the second motherboard 10 and the UPI interface module of the CPU (CPU3) of the fourth motherboard 10 are connected to form a communication loop through two EXAMAX high-density connector interfaces on the baseboard 20. Similarly, the UPI interface module of the CPU (CPU0) of the first motherboard 10 and the UPI interface module of the CPU (CPU2) of the third motherboard 10 are connected to form a communication loop through two EXAMAX high-density connector interfaces on the baseboard 20. Figure 6 Compared to Figure 5 The difference lies in the fact that a redundant communication loop is set up, which further improves the reliability of the solution. For example, if the communication loop between CPU1 and CPU3 fails, the effective communication between the four CPUs can still be guaranteed through the communication loop between CPU0 and CPU2.

[0087] In one specific embodiment of the present invention, when N≥3 and the server system is a partially interconnected server system, at least K CPU UPI interface modules of motherboard 10 are connected to form a communication loop through UPI connectors and cables to form a K-way CPU system.

[0088] Where K is a positive integer not less than 2 and K < N.

[0089] In the aforementioned embodiments, the server system is used as a fully interconnected server system or as a non-interconnected server system. This embodiment takes into account that the server system can also be used as a partially interconnected server system. In this case, at least K CPU UPI interface modules of motherboard 10 are connected to form a communication loop through UPI connectors and cables to form a K-way CPU system, and K < N.

[0090] For example, for Figure 4 and Figure 5In this N=4 implementation, the UPI interface module of CPU0 can be connected to the UPI interface module of CPU1 through a UPI connector and cable to form a communication loop. At the same time, the UPI interface module of CPU2 can be connected to the UPI interface module of CPU3 through a UPI connector and cable to form a communication loop. However, these two communication loops work independently. That is, the server system at this time includes two 2-way CPU systems.

[0091] Furthermore, in one specific embodiment of the present invention, when the server system is a partially interconnected server system, at least one of the N motherboards 10 operates independently to form a single-processor CPU system.

[0092] In this implementation, when the server system is a partially interconnected server system, it not only includes at least a K-way CPU system, but also at least one motherboard 10 working independently, for example, for Figure 4 and Figure 5 In this N=4 implementation, the UPI interface module of CPU0 can be connected to the UPI interface module of CPU1 through a UPI connector and cable to form a communication loop. At the same time, CPU2 and CPU3 are set to work independently. That is, the server system at this time includes one 2-way CPU system and two single-way CPU systems.

[0093] When a server system is used as a fully interconnected server system, it has high computing power and is suitable for scenarios requiring a large amount of computing. When a server system is used as a non-interconnected server system, its CPU core utilization is high. For example, this setting is often required when using it in the cloud. When a server system is used as a partially interconnected server system, performance can be balanced. The specific partitions of the partially interconnected server system can be designed according to the specific business scenario. For example, in the example above, the server system includes one 2-way CPU system and two single-way CPU systems.

[0094] The technical solution provided in this invention provides a base plate 20 for connecting motherboards 10, and N motherboards 10 connected to the base plate 20. Since each motherboard 10 has one CPU, damage to a single motherboard 10 will not affect the use of other motherboards 10. In this application, the UPI interface modules of different CPUs are not directly connected via the PCB on the board; instead, UPI connectors are used, allowing connection via cables. Furthermore, when the server system is a fully interconnected server system, the UPI interface modules of the CPUs on the N motherboards 10 are connected via UPI connectors and cables to form a communication loop, constituting an N-way CPU system. When the server system is a non-interconnected server system, the N motherboards 10 operate independently, constituting N single-way CPU systems. In other words, this application supports the use of N motherboards 10 to form an N-way CPU system, and also supports the use of N motherboards 10 to form N single-way CPU systems, offering high flexibility. In summary, this application effectively constructs a server system, improves flexibility, and enables flexible partitioning. N motherboards 10 can be used to form an N-way CPU system, or N motherboards 10 can be used to form N single-way CPU systems.

[0095] It should also be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0096] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.

[0097] This article uses specific examples to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only for the purpose of helping to understand the technical solutions and core ideas of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made to the present invention without departing from the principles of the present invention, and these improvements and modifications also fall within the protection scope of the present invention.

Claims

1. A server system, characterized in that, include: The base plate used to connect to the motherboard; N motherboards are connected to the base plate, and each motherboard is equipped with one CPU; N is a positive integer not less than 2; When the server system is a fully interconnected server system, the UPI interface modules of the CPUs of N motherboards are connected to form a communication loop through UPI connectors and cables to form an N-way CPU system. When the server system is an unconnected server system, N motherboards work independently to form N single-processor CPU systems; wherein, for any one CPU, when the CPU is set to work independently, the CPU's UPI0 interface is connected to the CPU's own UPI1 interface. For any one motherboard, the motherboard is provided with PCIe gold fingers, EXAMAX high-density connector interface and power connection interface, and the PCIe gold fingers of the motherboard are connected to the corresponding slot of the base plate, the EXAMAX high-density connector interface of the motherboard is connected to the corresponding EXAMAX high-density connector interface of the base plate, and the power connection interface of the motherboard is connected to the corresponding power connection interface of the base plate. When N=4, and the server system is a fully interconnected server system, the UPI interface modules of the CPUs of N motherboards are connected to form a communication loop through UPI connectors and cables to form a 4-way CPU system. Among them, the UPI interface module of the CPU of the first motherboard is connected to the UPI interface module of the CPU of the second motherboard through a UPI connector and a cable to form a communication loop, and the UPI interface module of the CPU of the third motherboard is connected to the UPI interface module of the fourth motherboard through a UPI connector and a cable to form a communication loop. The UPI interface module of the CPU of any one of the first motherboard and the second motherboard is connected to the UPI interface module of the CPU of any one of the third motherboard and the fourth motherboard to form a communication loop through a UPI connector and cable, or through two EXAMAX high-density connector interfaces on the base plate to form a communication loop. When N≥3, and the server system is a partially interconnected server system, there are at least K motherboards whose CPU UPI interface modules are connected to form a communication loop through UPI connectors and cables to form a K-way CPU system. Where K is a positive integer not less than 2 and K < N.

2. The server system according to claim 1, characterized in that, For any given motherboard, PCIe connectors are provided on both the front and back sides.

3. The server system according to claim 1, characterized in that, Each slot on the base plate is connected to a corresponding CDFP interface, and for any slot whose distance to its corresponding CDFP interface exceeds a first distance threshold, the slot is connected to its corresponding CDFP interface via a retimer.

4. The server system according to claim 1, characterized in that, For any given motherboard, the motherboard is equipped with a network card interface; The network card interface of any one or more of the N motherboards is connected to the OCP network card interface of the base plate.

5. The server system according to claim 1, characterized in that, The base plate is provided with x y-channel riser connectors, and any motherboard can connect up to 8*z PCIe channels to the riser connectors of the base plate. For any one of the N motherboards, the motherboard is provided with z 8-channel PCIe interfaces and right-angle connectors that are respectively connected to the z 8-channel PCIe interfaces. Where x, y, and z are all positive integers.

6. The server system according to claim 1, characterized in that, When the UPI interface module of the CPU of the first motherboard and the UPI interface module of the CPU of the third motherboard are connected to form a communication loop through the two EXAMAX high-density connector interfaces on the baseboard, the UPI interface module of the CPU of the second motherboard and the UPI interface module of the CPU of the fourth motherboard are connected to form a communication loop through the two EXAMAX high-density connector interfaces on the baseboard. When the UPI interface module of the CPU of the first motherboard and the UPI interface module of the CPU of the fourth motherboard are connected to form a communication loop through the two EXAMAX high-density connector interfaces on the baseboard, the UPI interface module of the CPU of the second motherboard and the UPI interface module of the CPU of the third motherboard are connected to form a communication loop through the two EXAMAX high-density connector interfaces on the baseboard.

7. The server system according to claim 1, characterized in that, Among N motherboards, at least one motherboard works independently to form a single-processor CPU system.

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