Pulse signal width measurement device, method, system and medium

Abstract

Provided are a pulse signal width measurement device, method, system, and medium. The device includes: a buffer chain comprising N first buffers, N first AND gates having one input connected to a pulse signal and another input connected to the output of a corresponding first buffer, and corresponding N flip-flops coupled to the output of each first AND gate, wherein the N first buffers are connected end to end; a path delay adjustment circuit, wherein the input of the path delay adjustment circuit receives the pulse signal and the output of the path delay adjustment circuit is connected to the input of the first buffer; a control device, which controls the delay generated by the path delay adjustment circuit to reduce the delay from the preset delay by at least one preset adjustment step according to a preset adjustment step during each adjustment until the output of the Pth flip-flop changes; and a measuring device, which measures the width of the pulse signal based on at least the output results of the outputs of the respective flip-flops, the delay of each first buffer, and the delay of the path delay adjustment circuit.

Description

Technical Field

[0001] The present application relates to the field of integrated circuits, and more particularly, to a pulse signal width measurement device, method, system, and medium for measuring the delay of a critical path. Background Art

[0002] Modern integrated circuits are subject to process variations during manufacturing, resulting in performance differences between finished products. For example, some integrated circuits can operate at 3 GHz, while others can only operate at 2.8 GHz. The operating speed of an integrated circuit is often determined by the latency of critical paths within the chip. Critical paths are typically those with the longest latency within the IC. To calibrate the performance of integrated circuits, the latency of critical paths can be directly measured during factory testing. This measurement can be performed using time-to-digital conversion circuits.

[0003] In addition, during the operation of an integrated circuit, the delay of the internal path of the integrated circuit will fluctuate due to the influence of aging, temperature, and power supply voltage. This may cause the delay of certain key paths in the integrated circuit to exceed the clock cycle, resulting in errors in the operation of the integrated circuit.

[0004] Therefore, it is necessary to accurately measure the delay of certain critical paths in integrated circuits. Summary of the Invention

[0005] According to one aspect of the present application, a pulse signal width measurement device is provided, comprising: a buffer chain including N first buffers, N first AND gates having one input connected to a pulse signal and another input connected to the output of the corresponding first buffer, and corresponding N flip-flops coupled to the output of each first AND gate, wherein the output of each of the N first buffers is connected to the input of the next first buffer, wherein N is a positive integer greater than 1; a path delay adjustment circuit, wherein the input of the path delay adjustment circuit receives the pulse signal, and the output of the path delay adjustment circuit is connected to the input of the first buffer in the buffer chain; a control device, which controls the delay generated by the path delay adjustment circuit to reduce the delay from the preset delay by at least one preset adjustment step according to a preset adjustment step during each adjustment until the output of the Pth flip-flop changes, wherein P is a positive integer less than or equal to N; and a measuring device, which is connected to the output of each flip-flop and the control device, and measures the width of the pulse signal based on at least the results output by the output of each flip-flop, the delay of each first buffer, and the delay of the path delay adjustment circuit just before the output of the Pth flip-flop changes.

[0006] According to another aspect of the present application, a pulse signal width measurement method for a pulse signal width measurement device is provided, wherein the pulse signal width measurement device includes: a buffer chain including N first buffers, N first AND gates having one input connected to a pulse signal and another input connected to the output of a corresponding first buffer, and corresponding N flip-flops coupled to the output of each first AND gate, wherein the output of each of the N first buffers is connected to the input of a subsequent first buffer, wherein N is a positive integer greater than 1; a path delay adjustment circuit, wherein the input of the path delay adjustment circuit receives the pulse signal, and the output of the path delay adjustment circuit is connected to the input of a first buffer in the buffer chain; wherein the pulse signal width measurement method includes: controlling the delay generated by the path delay adjustment circuit to decrease from the preset delay by at least a preset adjustment step size according to a preset adjustment step size during each adjustment until the output of the Pth flip-flop changes, wherein P is a positive integer less than or equal to N; and measuring the width of the pulse signal based on at least the results output by the output of each flip-flop, the delay of each first buffer, and the delay of the path delay adjustment circuit immediately before the output of the Pth flip-flop changes.

[0007] According to another aspect of the present application, a computer system is provided, comprising: a processor; and a memory coupled to the processor and storing computer-executable instructions therein, for performing a pulse signal width measurement method when executed by the processor.

[0008] According to another aspect of the present application, a computer-readable medium is provided, on which a computer program is stored, wherein the program implements a pulse signal width measurement method when executed by a processor.

[0009] Various aspects of the present application adopt a path delay adjustment circuit to greatly improve the measurement accuracy; the measurement structure is converted into a ring oscillator measurement, which is more accurate and reduces the error impact of process deviation, aging, routing and other factors on the accuracy of the measurement structure; a signal latch circuit is used to generate the clock signal of the trigger to avoid the metastable phenomenon of the trigger; the measurement accuracy is high; compared with the use of digital-to-analog conversion circuits, resistors and capacitors, etc., this structure can use a pure digital structure (such as a multiplexer, logic circuit and latch structure, etc.), which can be implemented using devices in the standard device library and can be directly synthesized, which is very friendly to the integrated circuit design process; this structure is resistant to aging interference, even if the circuit delay increases due to aging, the measurement accuracy is less affected; this structure only requires a very small area overhead and has little impact on the original integrated circuit design. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0011] Figure 1 FIG. 4 shows an overall block diagram of a time-to-digital conversion circuit according to an embodiment of the present application.

[0012] Figure 2A Shown is a circuit and waveform diagram for converting critical path delay into a pulse signal. Figure 2B A waveform diagram showing the conversion of critical path delay into a pulse signal is shown.

[0013] Figure 3A Shown is a circuit and waveform diagram for converting the time delay difference between two rising signals into a pulse signal. Figure 3B The waveform diagram of the conversion of the delay difference of two rising signals into a pulse signal is shown.

[0014] Figure 4 FIG. 1 is a block diagram showing an embodiment of a pulse signal width measurement device according to an embodiment of the present application.

[0015] Figure 5 FIG. 4 is a block diagram showing another embodiment of a pulse signal width measurement device according to an embodiment of the present application.

[0016] Figure 6 The output waveform diagram of each first buffer and the first AND gate in the buffer chain is shown when an exemplary pulse signal waveform is input and the path delay adjustment circuit is not considered according to an embodiment of the present application.

[0017] Figure 7 A schematic circuit diagram of a signal latch circuit according to an embodiment of the present application is shown.

[0018] Figure 8A A circuit diagram of an embodiment of a path delay adjustment circuit according to an embodiment of the present application is shown.

[0019] Figure 8B A circuit diagram of another embodiment of a path delay adjustment circuit according to an embodiment of the present application is shown.

[0020] Figure 9 A schematic diagram showing a time-to-digital conversion circuit designed in the present application is placed in each region where a critical path exists according to an embodiment of the present application.

[0021] Figure 10A flow chart of a pulse signal width measuring method of a pulse signal width measuring device according to an embodiment of the present application is shown.

[0022] Figure 11 A block diagram of an exemplary computer system suitable for implementing embodiments of the present application is shown.

[0023] Figure 12 A schematic diagram of a non-transitory computer-readable storage medium according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0024] Reference will now be made in detail to specific embodiments of the present application, examples of which are illustrated in the accompanying drawings. Although the present application will be described in conjunction with specific embodiments, it will be understood that the present application is not intended to be limited to the described embodiments. On the contrary, it is intended to cover variations, modifications, and equivalents within the spirit and scope of the present application as defined by the appended claims. It should be noted that the method steps described herein can be implemented by any functional block or functional arrangement, and any functional block or functional arrangement can be implemented as a physical entity or a logical entity, or a combination of the two.

[0025] In traditional technology, time-to-digital conversion circuits can be used to measure the delay of critical paths and determine the status of integrated circuits, such as whether they are over-aged or have insufficient power supply voltage.

[0026] Time-to-digital conversion circuits are also widely used in measuring the time interval between two signals, such as in ultrasonic flow meters, high-energy physics and nuclear physics, various handheld / airborne or fixed high-precision laser rangefinders, laser radars, laser scanners and other fields.

[0027] Typically, the critical path delay or time interval between two signals that a time-to-digital converter needs to measure is in the range of several nanoseconds or even hundreds of picoseconds. During measurement, the critical path delay or time interval between two signals is first converted into a pulse signal. The width of the pulse signal is the critical path delay or time interval between the two signals. Time-to-digital converters typically measure the number of logic gates the signal under test passes through, and their accuracy depends on the delay per logic gate.

[0028] However, the existing technology has a complex design structure, and its accuracy depends on the buffer delay, which has the problem of insufficient precision. At the same time, due to the influence of aging, the buffer delay will change, resulting in inaccurate measurement; measuring the path delay requires a long time, which in turn affects the normal operation of the critical path; some designs use analog circuits, which are complex and difficult to implement in advanced processes.

[0029] The solution of the present application further improves the measurement accuracy of the pulse width through a path delay adjustment scheme, which can reach 25% of the delay of a single buffer; further, by converting the measurement structure into a ring oscillator, the impact of errors caused by factors such as aging and routing on the measurement accuracy of the present application is reduced; the present application can complete the measurement of the critical path delay in as little as 4 clock cycles, and has little impact on the critical path; and the present application can be implemented using a purely digital circuit, which is convenient to implement and easy to integrate.

[0030] Figure 1 FIG. 4 shows an overall block diagram of a time-to-digital conversion circuit 100 according to an embodiment of the present application.

[0031] like Figure 1 As shown, the time-to-digital conversion circuit 100 designed in this application mainly includes three parts: a pulse signal conversion device 101, a pulse signal width measurement device 102 and a control device 103. The pulse signal conversion device 101 mainly converts the object to be measured (for example, the delay of the critical path, or the time interval to be measured between two signals, etc.) into a pulse signal, and the width of the pulse signal is the value of the object to be measured (that is, the time interval). The pulse signal width measurement device is used to measure the width of the pulse signal output by the pulse signal conversion device 101. The control device is used to control the operation of the pulse signal conversion device 101 and the pulse signal width measurement device.

[0032] Figure 2A Shown is a circuit and waveform diagram for converting critical path delay into a pulse signal.

[0033] The same signal is passed through two paths (one path has the delay of the critical path, and the other path does not have the delay) and then input into the XOR gate to obtain a pulse signal with the delay of the critical path as the width.

[0034] Specifically, the starting point of the path is typically the output signal of a flip-flop, for example. The output of the flip-flop's output signal, which is passed through the critical path, and the output of the flip-flop are directly passed through a wire (i.e., they are still input signals to the critical path) and simultaneously input into a two-port XOR gate. Due to the delay in the critical path, there is a delay difference between the two signals input into the XOR gate. According to the characteristics of the XOR gate, when there is a difference between the two input signals (for example, when the high-level output of the flip-flop is still low after passing through the critical path (because the high-level output has not yet completed the critical path), while the direct output of the flip-flop is high), the XOR gate output will be high. Otherwise, when both input signals are high (i.e., when the high-level output of the flip-flop completes the critical path and outputs a high level, the direct output of the flip-flop is still high) or low (for example, when no signal is input), the XOR gate output is low.

[0035] Specifically, Figure 2B The waveform diagram shows how the critical path delay is converted into a pulse signal. By configuring the trigger at the starting point of the critical path so that the input to the critical path is a rising-edge signal, the output of the critical path is a rising-edge signal delayed by the critical path delay. After these two signals pass through an XOR gate, a pulse signal with a width equal to the critical path delay is output. In other words, the pulse signal is the output of the XOR gate, obtained by taking the signal at the starting point of the integrated circuit's critical path through the critical path and the signal at the starting point as the two inputs.

[0036] Here, using an XOR gate to obtain the above-mentioned specific output is only an example. Other circuits that can obtain the above-mentioned specific output after receiving the above-mentioned two inputs are also included in the present disclosure and are not described in detail here.

[0037] In addition to measuring the critical path delay using the above method to obtain a pulse signal with a width equal to the critical path delay, the width of the converted pulse signal can also be used to measure the delay difference between the rising edges of two signals to be measured.

[0038] Figure 3A The circuit and waveform diagram for converting the time delay difference of two rising signals into a pulse signal are shown. The time delay difference between the rising edges of the two signals to be measured is the width of the converted pulse signal. Figure 3B The waveform diagram of the time delay difference between two rising signals is shown. After the two signals pass through the XOR gate, a pulse signal with a width equal to the time delay difference between the rising edges of the signal to be measured can be output.

[0039] Of course, the above examples all use the rising edge as the starting point of the delay difference. However, in actual circuits, the falling edge can also be used as the starting point of the delay difference, and a pulse signal with a width equal to the delay difference of the falling edge of the signal to be measured is output. At the same time, the XOR gate must also be transformed into other gates to achieve the above conversion.

[0040] Figure 4 FIG. 4 is a block diagram showing an embodiment of a pulse signal width measurement device 400 according to an embodiment of the present application.

[0041] The pulse signal width measurement device 400 includes: a buffer chain 401, comprising N first buffers 4011, N first AND gates 4012, one input of which is connected to a pulse signal and the other input of which is connected to the output of the corresponding first buffer 4011, and corresponding N flip-flops 4013 (flip-flop 1 to flip-flop N) coupled to the output of each first AND gate 4012, wherein the output of each of the N first buffers 4011 is connected to the input of the next first buffer 4011, wherein N is a positive integer greater than 1; and a path delay adjustment circuit 402, wherein the input of the path delay adjustment circuit 402 receives the pulse signal, and the output of the path delay adjustment circuit 402 is connected to an input end of the first buffer 4011 in the buffer chain 401; a control device 403, controlling the delay generated by the path delay adjustment circuit 402 to be reduced from the preset delay by at least one preset adjustment step according to a preset adjustment step at each adjustment until the output of the P-th trigger 4013 changes, where P is a positive integer and is less than or equal to N; a measuring device 404, connected to the output ends of each trigger 4013 and the control device 403, and measuring the high-precision width of the pulse signal based on the results output by the output ends of each trigger 4013 and the delay of each first buffer 4011 and the delay of the path delay adjustment circuit 402 just before the output of the P-th trigger 4013 changes.

[0042] In this way, the solution of adding the path delay adjustment circuit 402 improves the measurement accuracy to the preset adjustment step size of the path delay adjustment circuit 402 .

[0043] Figure 5 FIG. 5 is a block diagram showing another embodiment of a pulse signal width measurement device 500 according to an embodiment of the present application. Figure 5 Zhongyu Figure 4 The same parts are identified by the same reference numerals. Figure 5 .

[0044] Next, we will explain it with other figures Figure 4 The structure and operation of each device in.

[0045] Figure 6 1 shows the output waveforms of the first buffers 4011 and the first AND gates 4012 in the buffer chain 401 when an exemplary pulse signal waveform is input and the path delay adjustment circuit 402 is not considered according to an embodiment of the present application.

[0046] like Figure 6 As shown, when a pulse signal to be measured with a width to be measured is input, after the delay of the first buffer 4011, the output of the first buffer 4011 is as shown in FIG. Figure 6As shown in FIG. 4 , the waveform has the same width as shown in FIG. 4 , and then after the delay of the second first buffer 4011, the output of the second first buffer 4011 is as shown in FIG. Figure 6 As shown, by analogy, it can be seen that the waveform output by each first buffer 4011 is the same as the pulse signal to be measured, except that the output of each first buffer 4011 will further delay the pulse signal to be measured by the delay of the first buffer 4011.

[0047] After the first AND gate 4012 is added to perform an AND operation on the pulse signal to be measured and the output of the first buffer 4011, when the pulse signal to be measured is at a high level, the output of the first AND gate 4012 is the same as the output signal of the first buffer 4011 connected to the first AND gate 4012, that is, when the pulse signal to be measured is at a high level and the output signal of the first buffer 4011 input to the first AND gate 4012 is also at a high level, the output of the first AND gate 4012 is at a high level; otherwise, the output of the first AND gate 4012 is always at a low level. Figure 6 The waveform of the pulse signal, the output signal of the first AND gate 4012 is as follows Figure 6 As shown, the output signal of the second first AND gate 4012 is as follows Figure 6 As shown, and so on, until the output of the mth first AND gate 4012 is at a high level, and the output of the (m+1)th first AND gate 4012 is not at a high level, where m is a positive integer.

[0048] Under the control of the first AND gate 4012 for signal propagation control, the rising edge of the pulse signal to be measured can only propagate through m first buffers 4011 within the time corresponding to the pulse signal width, where m<=N, so that the first AND gate 4012 for signal propagation control connected to these m first buffers 4011 can output a pulse signal, such as Figure 6 By recording the number of first AND gates 4012 outputting excessively high-level pulse signals, the width of the pulse signals measured by the same number of first buffers 4011 can be recorded, that is, the number multiplied by the delay of the first buffer 4011.

[0049] Of course, this measurement result is rough. As long as the pulse signal width exceeds the total delay of the (m-1)th first buffer 4011 by less than the delay of one first buffer 4011, the rising edge of the measured pulse signal will propagate through m first buffers 4011 within the time corresponding to the pulse signal width. The exact amount by which the pulse signal width exceeds the total delay of the (m-1)th first buffer 4011 is imprecise. According to embodiments of the present application, the pulse signal width can be further accurately measured using the path delay adjustment circuit 402.

[0050] The specific high-precision measurement operation and function of the path delay adjustment circuit 402 according to the embodiment of the present application are introduced below.

[0051] In conventional technology, there is no path delay adjustment circuit 402, only the first buffer 4011 and the first AND gate 4012. If the measurement is performed using only the buffer chain 401, the resolution of the pulse signal measurement is equal to the delay of a single buffer on the buffer chain 401. That is, if the delay of the first buffer 4011 is known to be approximately 5 ps, Figure 6 As shown, the output of the mth first AND gate 4012 is high, while the output of the m+1th first AND gate 4012 is not high. Therefore, the roughly measured pulse signal width is m × 5 ps. However, in reality, the pulse signal width may be between (m-1) × 5 ps and m × 5 ps. This is because as long as the pulse signal width is greater than the delay of the m-1 first buffers 4011 and less than the delay of the m+1 first buffers 4011, the output of the first AND gate 4012 of the mth first buffer 4011 will be a high-level pulse. Therefore, the measurement accuracy of using only the buffer chain 401 is insufficient. In actual experiments, if the pulse signal width to be measured is 300 ps, ​​the measurement error corresponding to the buffer with a 5 ps delay is 1.67%, which will lead to insufficient accuracy.

[0052] Therefore, the present application further introduces a path delay adjustment circuit 402, and the output waveforms of the first buffers 4011 and the first AND gates 4012 are Figure 6 Different but can be used as a reference Figure 6 That is, the waveform output by the first buffer 4011 must be Figure 6 The delay of the path delay adjustment circuit 402 is further delayed based on the delay itself (note that Figure 6 (The delay of the path delay adjustment circuit 402 is not shown in the figure), and the subsequent first buffer 4011 also needs to be further delayed. Then, the path delay adjustment circuit 402 is controlled by the control device 403, which can gradually reduce the overall delay of the path delay adjustment circuit 402 in very small steps.

[0053] Assume that the delay of first buffer 4011 in buffer chain 401 is 5 ps, the preset delay of path delay adjustment circuit 402 is initially 10 ps, ​​the preset adjustment step size is 1 ps, and the actual width of the pulse signal to be measured is 58 ps. Here, the preset adjustment step size is typically smaller than the delay of one first buffer 4011, thereby further refining the delay of first buffer 4011. During the initial measurement, if the results show that the output of the first ten first flip-flops 4013 transitions from a low level to a high level, the rough width of the pulse signal to be measured can be inferred to be (10 ps + 10 × 5 ps) = 60 ps, ​​which is significantly different from the actual pulse signal width and lacks accuracy.

[0054] At this time, the delay of the path delay adjustment circuit 402 can be gradually reduced by a preset adjustment step size of, for example, 1 ps. When the delay of the path delay adjustment circuit 402 is reduced to 8 ps, the measurement result shows that the outputs of the first 10 triggers 4013 are still high, and it is estimated that the width of the pulse signal to be measured is 68 ps. The delay of the path delay adjustment circuit 402 is further reduced. When the delay of the path delay adjustment circuit 402 is reduced to 7 ps, the measurement result shows that the output of the 11th trigger 4013 changes from a low level to a high level, that is, the measurement result has changed, indicating over-adjustment. The last measurement result should be used as the basis, that is, the delay of the path delay adjustment circuit 402 just before the output of the 11th trigger 4013 changes from a low level to a high level, that is, 8 ps. Therefore, the measurement results show that the high-precision width of the pulse signal to be measured is (8ps+10×5ps)=58ps. Compared with the traditional technology that only uses the first buffer 4011 and the first AND gate 4012 for measurement, the accuracy is improved to 1ps fineness, instead of the 5ps fineness of the first buffer 4011.

[0055] Therefore, the solution of adding the path delay adjustment circuit 402 according to the embodiment of the present application improves the measurement accuracy to the fineness of the preset adjustment step size of the path delay adjustment circuit 402.

[0056] Thus, through the buffer link 401 of this structure, according to the Figure 6 As shown in FIG. 4 , it can be seen intuitively that the width of the pulse signal has passed through the delay of the path delay adjustment circuit 402 and the delays of several first buffers 4011 , thereby measuring the width of the pulse signal to be measured with high precision.

[0057] Of course, the structure in which only the first buffer 4011 and the first AND gate 4012 are directly connected to the clock input port of the trigger 4013 may result in the trigger 4013 performing data sampling when the first AND gate 4012 outputs a high level. In this case, the width of the high level pulse output by the first AND gate 4012 may be too narrow, resulting in failure to meet the timing requirements of the trigger 4013, causing sampling failure or the occurrence of a metastable state.

[0058] Therefore, another embodiment of the present application introduces a signal latch circuit (refer to Figure 5 as well as Figure 7 ), when the high-level pulse width generated by the first AND gate 4012 used for signal propagation control is narrow, the signal latch circuit can also stably change the output from a low level to a high level, providing a stable rising edge sampling signal for the trigger 4013 clock port.

[0059] Figure 7 FIG. 4 shows a schematic circuit diagram of a signal latch circuit 700 according to an embodiment of the present application.

[0060] For the mth first AND gate 4012 (m is a positive integer and can be any integer from 1 to N), a signal latch circuit 700 consisting of an OR gate 701 and a second AND gate 702 is added (e.g. Figure 7 (as shown), both the OR gate 701 and the second AND gate 702 have two inputs and one output. One input of the OR gate 701 is the output of the mth first AND gate 4012 used for signal propagation control. The other input of the OR gate 701 is the output of the second AND gate 702 in the signal latch circuit 700. The output port of the OR gate 701 is connected to an input port of the second AND gate 702 in the signal latch circuit 700 and, as the output of the signal latch circuit 700, is connected to the clock signal input port of the mth first flip-flop 4013. The other input signal of the second AND gate 702 in the signal latch circuit 700 is a reset signal for the signal latch circuit 700, which is controlled by the control device 403 and is at a low level during reset.

[0061] Combine Figure 5The signal latch circuit 700 operates in the following manner: 1) Before measurement begins, the control device 403 sets the reset signal of the signal latch circuit 700 to a low level. Simultaneously, since the measurement state is not in progress, the input of the pulse signal width measurement device 500 remains low, causing the output of the first AND gate 4012 used for signal propagation control to be low. Consequently, the output of the signal latch circuit 700 also remains low. 2) After the signal latch circuit 700 is reset, the control device 403 sets the reset signal of the signal latch circuit 700 to a high level. At this point, the signal latch circuit 700 can be used to capture the high level output of the first AND gate 4012 used for signal propagation control. 3) Once the output of the first AND gate 4012 used for signal propagation control changes from a low level to a high level, the output of the OR gate 701 is high, thereby causing the output of the second AND gate 702 to be high. Even after the output of the first AND gate 4012 changes to a low level, the output of the OR gate 701 remains high because one input of the OR gate 701 (i.e., the output of the second AND gate 702) is high. That is, the output of OR gate 701 transitions from a low level to a high level, and signal latch circuit 700 latches this high level value, generating a rising edge signal at the clock port of flip-flop 4013, which then samples the data of flip-flop 4013. Of course, flip-flop 4013 is reset before measurement, causing its output to be low. During the measurement process, data port D of flip-flop 4013 remains high. Once the clock port connected to OR gate 701 receives a rising edge signal (output by OR gate 701) for sampling, the output terminal Q of flip-flop 4013 transitions from a low level to a high level.

[0062] Through the signal latch circuit 700, even when the high-level pulse width generated by the first AND gate 4012 used for signal propagation control is narrow, the signal latch circuit 700 can latch this high level and provide a stable rising edge sampling signal for the trigger 4013 clock port, so as to meet the timing requirements of the trigger 4013 and eliminate sampling failure or metastable phenomena.

[0063] Next, a specific circuit embodiment of the path delay adjustment circuit 402 is introduced.

[0064] Figure 8A FIG. 4 shows a circuit diagram of an embodiment of a path delay adjustment circuit 402 according to an embodiment of the present application.

[0065] In this embodiment, the path delay adjustment circuit 402 includes M first multiplexers (MUXs) 801, where M is a positive integer. The input of each first multiplexer 801 is connected to at least two second buffers 802 having different buffering times. During each adjustment, the control device 403 inputs a respective path delay adjustment signal to the selection signal terminal of each first multiplexer 801 to select one of the at least two second buffers 802, thereby controlling the delay generated by the path delay adjustment circuit 402 to be reduced from a preset delay by at least a preset adjustment step size. The control device 403 can input a respective path delay adjustment signal to each first multiplexer 801 to individually adjust the delay caused by the second buffers 802 passed by each first multiplexer 801.

[0066] For example, there are five first multiplexers 801, each of which has an input connected to two second buffers 802 with different buffering times (e.g., 1 ps, 2 ps, etc.). That is, depending on which second buffer 802 is selected, each first multiplexer 801 can cause a delay of 1 ps or 2 ps. If the initial delay is 10 ps, ​​all five first multiplexers 801 select the second buffer 802 with a delay of 2 ps. Assuming a preset adjustment step size of 1 ps, if the delay generated by the control path delay adjustment circuit 402 is to be reduced by a preset adjustment step size, i.e., 1 ps, from the preset delay, a first multiplexer 801 can be controlled to select the second buffer 802 with a delay of 1 ps instead of the second buffer 802 with a delay of 2 ps. This reduces the total delay of all five first multiplexers 801 to 9 ps. Similarly, for other numbers of first multiplexers 801, other buffering times, and other preset adjustment step sizes, the same adjustment can be performed.

[0067] Figure 8B FIG. 4 shows a circuit diagram of another embodiment of a path delay adjustment circuit 402 according to an embodiment of the present application.

[0068] In this embodiment, the path delay adjustment circuit 402 includes a first multiplexer 801' having multiple input terminals, each of which is connected to at least two second buffer groups 802' having different total buffering times. The different buffering times can be achieved by varying the number of second buffers in the second buffer groups 802'. During each adjustment, the control device 403 inputs a path delay adjustment signal to the selection signal terminal of the first multiplexer 801' to select one of the at least two second buffer groups 802', thereby controlling the delay generated by the path delay adjustment circuit 402 to reduce the delay from a preset delay by at least a preset adjustment step size. The control device 403 can input respective path delay adjustment signals to the first multiplexer 801' to individually adjust the delay caused by the second buffers passed by the first multiplexer 801'.

[0069] For example, if the delay of each buffer is 1 ps, and there are five second buffer groups 802' in total, the first second buffer group 802' includes five buffers, the second second buffer group 802' includes four buffers, and so on. Assuming the preset adjustment step size is 1 ps, if the delay generated by the control path delay adjustment circuit 402 is to be reduced from the preset delay of 5 ps by one preset adjustment step size, i.e., 1 ps, the first multiplexer 801' can be controlled to select the second second buffer group 802' to achieve a delay of 4 ps. The same applies to other delays.

[0070] certainly Figure 8A and Figure 8B Only two exemplary embodiments of the path delay adjustment circuit 402 are shown, but the present application is not limited thereto. Any circuit structure that can meet the delay adjustment effect is included in the present disclosure.

[0071] In the above, the path delay adjustment circuit 402 is used to more finely adjust the delay, thereby stopping before reaching a critical point. That is, if the critical point is exceeded (for example, the delay of the path delay adjustment circuit 402 is 7 ps), the output of the latch connected to the first AND gate 4012 of the Pth first buffer 4011 is flipped (from a low level to a high level). Then, the output is adjusted back (for example, the delay of the path delay adjustment circuit 402 is 8 ps), so that the latch connected to the first AND gate 4012 of the Pth first buffer 4011 returns to a low level. In other words, the fixed delay of the path delay adjustment circuit 402 of 8 ps is the optimal delay. In this way, the measurement device 404 measures the high-precision width of the pulse signal by adding the total delay of the first (P-1) first buffers 4011 to the delay of the path delay adjustment circuit 402 before the output of the Pth flip-flop 4013 changes, to obtain the high-precision width of the pulse signal. In this example, assuming P=11, the high-precision width of the pulse signal is calculated to be (10×5ps+8ps)=58ps.

[0072] Of course, the above measurement example assumes that the delays of first buffer 4011 and second buffer 802 are known. However, it should be noted that due to chip manufacturing process variations, even if identical buffers are selected during design to form buffer chain 401, differences in buffer delays within the same buffer chain 401 may exist after chip manufacturing. Furthermore, factors such as aging and temperature may also affect buffer delays, and buffer delays may also change over time. Therefore, there may be an error between the actual buffer delay and the measured value, and therefore, it cannot be directly calculated by cumulative calculation based on the known designed value. Furthermore, for the first AND gate 4012, used for signal propagation control, to output a high-level signal, it requires that the high-level overlap time of the two input signals must exceed a minimum threshold. This results in potential measurement errors using the above method, including this minimum threshold time.

[0073] To eliminate errors introduced by the first AND gate 4012 and the routing used for signal propagation control, a clock signal of known width can be measured before actual measurement. The difference between the measured result and the known width of the clock signal is the aforementioned error. The pulse width of the measured signal is the difference between the actual measurement result and the error, while random error can be calculated by the adjustment step size of the path delay adjustment circuit 402. This is because the pulse width of the measured signal is the coarse delay of the N buffers plus the adjusted delay of the path delay adjustment circuit 402. Assuming the adjustment step size of the path delay adjustment circuit 402 is 7 ps, the pulse width of the measured signal is typically between the coarse delay of the N buffers plus 7 ps*j and the coarse delay of the N buffers plus 7 ps*(j+1). (7 ps*j and 7 ps*(j+1) are the delays of the path delay adjustment circuit 402 obtained from two consecutive adjustments.) The pulse width of the signal to be measured may be very close to (the coarse delay of N buffers plus 7ps*j)) or (the coarse delay of N buffers plus 7ps*(j+1)), so the error in the worst case is 7ps (i.e., the adjustment step size of the path delay adjustment circuit 402).

[0074] The following solutions of the present application can further solve the above problems, achieve the above effects, and further improve the measurement accuracy.

[0075] In one embodiment, in order to eliminate the difference in delay between the designed and actual buffers and to eliminate the delay impact caused by routing, a second multiplexer is introduced into the design.

[0076] refer to Figure 5 The pulse signal width measuring device 404 further includes a second multiplexer 501, a plurality of groups of odd-numbered NOT gates 502, a counter 503 and a timer 504. Figure 5 The example in the figure shows that each group of odd-numbered NOT gates 502 includes only one NOT gate (a circle represents a NOT operation). However, to achieve ring oscillation, each group of odd-numbered NOT gates 502 can actually include another number of NOT gates. For example, each group of odd-numbered NOT gates 502 can include three NOT gates, but this is not a limitation. Of course, the number of NOT gates in each group is preferably the same, so that the circuit delays or errors caused by these groups of NOT gates are substantially the same.

[0077] The multiple input ends of the second multiplexer 501 receive the output signals of the output ends of N first buffers 4011 and receive pulse signals and clock signals with predetermined pulse widths through multiple groups of odd-numbered NOT gates 502. The output end of the second multiplexer 501 is connected to the path delay adjustment circuit 402. The output end of the path delay adjustment circuit 402 is also connected to the counter 503. The counter 503 is also connected to the timer 504.

[0078] The measurement process of the pulse signal width measurement device 500, which includes a second multiplexer 501, multiple groups of odd-numbered NOT gates 502, a counter 503, and a timer 504, is as follows:

[0079] In order to measure the errors caused by the actual buffer delay, threshold time, and routing, the control device 403 outputs a ring oscillator switching signal to the selection signal terminal of the second multiplexer 501, so as to measure the error using a clock signal with a known pulse width:

[0080] First, in the high-precision measurement step:

[0081] The second multiplexer 501 is controlled to select a clock signal having a predetermined pulse width. The measuring device 404 adjusts the delay through the path delay adjustment circuit 402 and the control device 403. During each adjustment, the delay generated by the path delay adjustment circuit 402 is controlled to be reduced from the preset delay by at least one preset adjustment step according to the preset adjustment step until the output of the Qth trigger 4013 changes, and the delay of the path delay adjustment circuit 402 is fixed at a state just before the output of the Qth trigger 4013 changes, where Q is a positive integer and is less than or equal to N.

[0082] At this time, the state just before the output of the Qth trigger 4013 changes, that is, the output of the (Q-1)th first AND gate 4012 corresponding to the 1st first buffer 4011 to the (Q-1)th first buffer 4011 is a high level, and the outputs of other first AND gates 4012 are low levels.

[0083] This step is to fix the most appropriate delay of the path delay adjustment circuit 402 to obtain a high-precision measurement result of the pulse width. However, the measurement result still contains the above-mentioned errors caused by the actual delay of the buffer, threshold time and routing.

[0084] Next, during the calibration step:

[0085] The control device 403 controls the second multiplexer 501 to select the output of the Q-1th first buffer 4011, uses the timer 504 to use the counter 503 to count the ring oscillation within a predetermined timing to measure the error-bearing width of the clock signal, and uses the difference between the predetermined pulse width and the error-bearing width as the error.

[0086] Here, since the second multiplexer 501 selects the output of the Q-1th first buffer 4011, the output passes through an odd number of NOT gates 502, a path delay adjustment circuit 402, and the 1st first buffer 4011 to the Q-1th first buffer 4011, which forms a ring oscillator including an odd number of NOT gates 502, a path delay adjustment circuit 402, and the 1st first buffer 4011 to the Q-1th first buffer 4011.

[0087] In one example, the pulse signal width measurement device 404 adjusts the path delay adjustment circuit 402. For example, if the result shows that the delay of the path delay adjustment circuit 402 is 8 ps, the outputs of the AND gates of the first ten flip-flops 4013 change from a low level to a high level. If the delay of the path delay adjustment circuit 402 is 7 ps, and the output of the AND gate of the 11th flip-flop 4013 changes from a low level to a high level, the control device 403 adjusts the second multiplexer 501 to select the output signal of the 10th flip-flop 4013. In this way, the pulse signal width measurement device 404 is configured as a ring oscillator including an odd number of NOT gates 502, the path delay adjustment circuit 402, and the first through tenth first buffers 4011.

[0088] Then, the timer 504 counts the ring oscillations using the counter 503 within the predetermined timing to measure the error width of the clock signal, which includes dividing the predetermined timing by the number of ring oscillations counted by the counter 503 within the predetermined timing to measure the error width of the clock signal.

[0089] In one example, if timer 504 sets a predetermined timer, such as 1 μs, and counter 503 counts 10,000 oscillations within that predetermined timer, the pulse width measurement device 500 measures the clock signal with an error of 0.1 ns. In this way, by using counter 503 and timer 504 to count and measure the ring oscillator, a precise delay with error can be obtained for the pulse signal width to be measured. However, assuming the predetermined pulse width of the input clock signal is 1 / 12 ns, the difference between the predetermined pulse width of 1 / 12 ns and the error-bearing width of 1 / 10 ns is taken as the error: 1 / 10 ns - 1 / 12 ns ≈ 0.0167 ns.

[0090] In this way, the pulse signal width measurement device 500 is configured as a ring oscillator for precise measurement. Through the embodiment of the present application, the errors of the entire pulse signal width measurement device 500 due to the actual delay of the buffer, the threshold time and the routing are obtained, which can effectively resist the delay changes of the buffer link 401 caused by aging and reduce the impact of aging on measurement accuracy.

[0091] Next, we introduce how to measure the width of practically any pulse signal with high accuracy and error-free.

[0092] In high-precision and error-free measurement mode:

[0093] The control device 403 controls the second multiplexer 501 to select the pulse signal to be measured, and the measuring device 404 measures through the high-precision mode and calibration steps to obtain the error-bearing width of the pulse signal to be measured, and subtracts the error from the error-bearing width of the pulse signal to be measured to obtain the high-precision and error-free width of the pulse signal.

[0094] Specifically, for the pulse signal to be measured, the measurement in the high-precision mode and the calibration step includes: first, in the high-precision measurement step:

[0095] The second multiplexer 501 is controlled to select the pulse signal to be measured, and the measuring device 404 adjusts the delay through the path delay adjustment circuit 402 and the control device 403. During each adjustment, the delay generated by the path delay adjustment circuit 402 is controlled to be reduced from the preset delay by at least one preset adjustment step according to the preset adjustment step until the output of the Qth trigger 4013 changes, and the delay of the path delay adjustment circuit 402 is fixed at the state just before the output of the Qth trigger 4013 changes, where Q is a positive integer and is less than or equal to N.

[0096] Next, during the calibration step:

[0097] The control device 403 controls the second multiplexer 501 to select the output of the Q-1th first buffer 4011, and uses the timer 504 to use the counter 503 to count the ring oscillations within a predetermined timing to measure the error width of the pulse signal to be measured.

[0098] Next, subtract the error from the error-bearing width of the pulse signal to be measured to obtain the high-precision and error-free width of the pulse signal:

[0099] In the error removal step:

[0100] The control device 403 subtracts the error previously calculated using the clock signal of the predetermined width from the error-bearing width of the pulse signal to be measured, thereby obtaining a high-precision and error-free width of the pulse signal.

[0101] It should be noted that, in order to reduce the interference of routing on delay measurement, it may be required that the routing distance from each first buffer 4011 to the second multiplexer 501 is equal during routing.

[0102] In summary, the measurement process of the time-to-digital conversion circuit proposed in each embodiment of the present application is as follows:

[0103] 1) First, calibration is performed. A clock signal with a known pulse width is input into a pulse signal width measurement device. By adjusting the path delay adjustment circuit until the output of the trigger changes, a high-precision value of the clock pulse signal is obtained. Then, the control device controls the multiplexer to convert the pulse signal width measurement device into a ring oscillator. The counter and timer are used to accurately measure the width of the clock pulse signal to be measured. This is compared with the known pulse width value of the clock signal to obtain the measurement error of this structure.

[0104] 2) The signal of the critical path to be measured or the time interval between two to be measured is converted into a pulse signal to be measured using a pulse conversion device, and input into a pulse signal width measurement device for measurement. Removing the error from the measurement result is the actual high-precision and error-free measurement result.

[0105] When the various embodiments of the present application are used for critical path delay measurement, since there is more than one critical path in the integrated circuit, a time-to-digital conversion circuit designed by the present application can be placed in each area where a critical path exists, such as Figure 9 shown. Figure 9 A schematic diagram shows a time-to-digital conversion circuit designed in this application placed in each area where a critical path exists. If multiple critical paths exist in a given area, these critical paths can share a single time-to-digital conversion circuit. The outputs of the different critical paths simply need to be fed into the time-to-digital conversion circuit through a multiplexer.

[0106] The various embodiments of the present application adopt a path delay adjustment circuit to greatly improve the measurement accuracy; the measurement structure is converted into a ring oscillator measurement, which provides more accurate measurement and reduces the error impact of process deviation, aging, routing and other factors on the accuracy of the measurement structure; a signal latch circuit is used to generate the clock signal of the trigger to avoid the metastable phenomenon of the trigger; the measurement accuracy is high, and the random measurement error is less than 1ps under the 12nm process; compared with the use of digital-to-analog conversion circuits, resistors and capacitors, etc., this structure uses a pure digital structure (such as multiplexers, logic circuits and latch structures, etc.), which can be implemented using devices in the standard device library and can be directly synthesized, which is very friendly to the integrated circuit design process; this structure is resistant to aging interference, even if the circuit delay increases due to aging, the measurement accuracy is less affected; this structure only requires a very small area overhead and has little impact on the original integrated circuit design.

[0107] Figure 10 FIG. 1 is a flowchart of a pulse signal width measuring method 1000 of a pulse signal width measuring device according to an embodiment of the present application.

[0108] In a pulse signal width measurement method 1000 for a pulse signal width measurement device, the pulse signal width measurement device includes: a buffer chain, including N first buffers, N first AND gates having one input connected to a pulse signal and another input connected to the output of a corresponding first buffer, and corresponding N triggers coupled to the output of each first AND gate, and each output of the N first buffers is connected to the input of a next first buffer, wherein N is a positive integer greater than 1; and a path delay adjustment circuit, wherein the input of the path delay adjustment circuit receives the pulse signal, and the output of the path delay adjustment circuit is connected to the input of a first buffer in the buffer chain.

[0109] The pulse signal width measurement method includes: step 1001, controlling the delay generated by the path delay adjustment circuit to reduce by at least one preset adjustment step from the preset delay according to the preset adjustment step at each adjustment until the output of the P-th trigger changes, where P is a positive integer and is less than or equal to N; step 1002, measuring the width of the pulse signal based on at least the results output by the output terminals of each trigger and the delay of each first buffer and the delay of the path delay adjustment circuit just before the output of the P-th trigger changes.

[0110] In this way, the solution of adding a path delay adjustment circuit and performing specific adjustments improves the measurement accuracy to the preset adjustment step size of the path delay adjustment circuit.

[0111] In one embodiment, a path delay adjustment circuit includes M first multiplexers, where M is a positive integer, an input terminal of each first multiplexer is connected to at least two second buffers having different buffering times, and step 1001 of controlling the delay generated by the path delay adjustment circuit to reduce the delay from the preset delay by at least one preset adjustment step according to a preset adjustment step during each adjustment includes: during each adjustment, inputting a respective path delay adjustment signal to a selection signal terminal of each first multiplexer to select one of the at least two second buffers, thereby controlling the delay generated by the path delay adjustment circuit to reduce the delay from the preset delay by at least one preset adjustment step.

[0112] In one embodiment, a path delay adjustment circuit includes a first multiplexer, wherein an input terminal of the first multiplexer is connected to at least two second buffer groups having different total buffering times. Step 1001 of controlling the delay generated by the path delay adjustment circuit to decrease from the preset delay by at least one preset adjustment step according to a preset adjustment step during each adjustment includes: inputting a path delay adjustment signal to a selection signal terminal of the first multiplexer to select one of the at least two second buffer groups during each adjustment, thereby controlling the delay generated by the path delay adjustment circuit to decrease from the preset delay by at least one preset adjustment step.

[0113] In this way, through different embodiments of the path delay adjustment circuit and different delay adjustment methods, the delay generated by the path delay adjustment circuit is controlled to be reduced from the preset delay by at least a preset adjustment step.

[0114] In one embodiment, the pulse signal width measuring device further includes a second multiplexer, multiple groups of odd-numbered NOT gates, a counter, and a timer, wherein the multiple input ends of the second multiplexer respectively receive the output signals of the output ends of the N buffers through the multiple groups of odd-numbered NOT gates and receive the pulse signal and the clock signal with a predetermined pulse width, the output end of the second multiplexer is connected to the path delay adjustment circuit, the output end of the path delay adjustment circuit is also connected to the counter, and the counter is also connected to the timer.

[0115] In one embodiment, the method further includes: outputting a ring oscillator switching signal to a selection signal terminal of the second multiplexer to:

[0116] In the high-precision measurement step: controlling the second multiplexer to select a clock signal having a predetermined pulse width, controlling the delay generated by the path delay adjustment circuit to decrease from the preset delay by at least one preset adjustment step according to a preset adjustment step at each adjustment, until the output of the Qth flip-flop changes, and fixing the delay of the path delay adjustment circuit to a state immediately before the output of the Qth flip-flop changes, where Q is a positive integer and is less than or equal to N,

[0117] During the calibration step:

[0118] controlling the second multiplexer to select the output of the Q-1th first buffer, using a timer to count the ring oscillations using a counter within a predetermined timing to measure the error width of the clock signal, and using the difference between the predetermined pulse width and the error width as an error;

[0119] The step 1002 of measuring the width of the pulse signal based on at least the output results of the output terminals of the respective flip-flops, the delay of each first buffer, and the delay of the path delay adjustment circuit immediately before the output of the P-th flip-flop changes includes:

[0120] In high-precision and error-free measurement mode:

[0121] The second multiplexer is controlled to select the pulse signal, and the error-bearing width of the pulse signal to be measured is obtained through measurement in high-precision mode and calibration steps. The error is subtracted from the error-bearing width of the pulse signal to be measured to obtain the high-precision and error-free width of the pulse signal.

[0122] In one embodiment, the steps of controlling the second multiplexer to select the pulse signal, the measuring device performing measurements in a high-precision mode and a calibration step to obtain the error-bearing width of the pulse signal to be measured, and subtracting the error from the error-bearing width of the pulse signal to obtain the high-precision and error-free width of the pulse signal include:

[0123] In the high-precision measurement step: controlling the second multiplexer to select the pulse signal to be measured, the measuring device adjusting the delay of the path delay adjustment circuit and the control device, controlling the delay generated by the path delay adjustment circuit to decrease from the preset delay by at least one preset adjustment step according to a preset adjustment step during each adjustment, until the output of the Qth flip-flop changes, and fixing the delay of the path delay adjustment circuit to a state immediately before the output of the Qth flip-flop changes, where Q is a positive integer and is less than or equal to N;

[0124] In the calibration step: the control device controls the second multiplexer to select the output of the Q-1th first buffer, and uses the timer to use the counter to count the ring oscillation within a predetermined time to measure the error width of the pulse signal to be measured;

[0125] In the error removal step:

[0126] The control device subtracts the error previously calculated by the clock signal of the predetermined width from the error-bearing width of the pulse signal to be measured, thereby obtaining the high-precision and error-free width of the pulse signal.

[0127] In this way, the pulse signal width measurement device is configured as a ring oscillator for precise measurement. Through the embodiments of the present application, the errors of the entire pulse signal width measurement device due to the actual delay of the buffer, the threshold time and the routing are obtained, which can effectively resist the buffer link delay changes caused by aging and reduce the impact of aging on measurement accuracy.

[0128] In one embodiment, the step of using a timer to count ring oscillations using a counter within a predetermined timing to measure the error width of the clock signal includes: dividing the predetermined timing by the count of ring oscillations by the counter within the predetermined timing to measure the error width of the clock signal.

[0129] In one embodiment, step 1002 of measuring the width of the pulse signal based on at least the results of the output of each trigger and the delay of each first buffer, and the delay of the path delay adjustment circuit just before the output of the P-th trigger changes, includes: adding the total delay of the first (P-1) first buffers to the delay of the path delay adjustment circuit just before the output of the P-th trigger changes to obtain a high-precision width of the pulse signal.

[0130] In one embodiment, the pulse signal width measuring device further includes: N signal latch circuits, wherein each buffer is connected to the clock input of the corresponding trigger through its own signal latch circuit, wherein the input of each trigger receives a high level, wherein each signal latch circuit includes: a first AND gate, whose first input is connected to the output of the corresponding buffer, and whose second input receives the pulse signal; an OR gate, whose first input is connected to the output of the first AND gate, and whose output is connected to the clock input of the corresponding trigger; a second AND gate, whose output is connected to the second input of the OR gate, whose first input is connected to the output of the OR gate, and whose second input receives a signal latch circuit reset signal, which is a low level when reset.

[0131] In one embodiment, the pulse signal is the output of an XOR gate obtained by using the signal of the starting point of the critical path of the integrated circuit through the critical path, the signal obtained through the critical path, and the signal of the starting point as two inputs of the XOR gate.

[0132] In summary, the measurement process of the time-to-digital conversion circuit proposed in each embodiment of the present application is as follows:

[0133] 1) First, calibration is performed. A clock signal with a known pulse width is input into a pulse signal width measurement device. By adjusting the path delay adjustment circuit until the output of the trigger changes, a high-precision value of the clock pulse signal is obtained. Then, the control device controls the multiplexer to convert the pulse signal width measurement device into a ring oscillator. The counter and timer are used to accurately measure the width of the clock pulse signal to be measured. This is compared with the known pulse width value of the clock signal to obtain the measurement error of this structure.

[0134] 2) The signal of the critical path to be measured or the time interval between two to be measured is converted into a pulse signal to be measured using a pulse conversion device, and input into a pulse signal width measurement device for measurement. Removing the error from the measurement result is the actual high-precision and error-free measurement result.

[0135] The various embodiments of the present application adopt a path delay adjustment circuit to greatly improve the measurement accuracy; the measurement structure is converted into a ring oscillator measurement, which provides more accurate measurement and reduces the error impact of process deviation, aging, routing and other factors on the accuracy of the measurement structure; a signal latch circuit is used to generate the clock signal of the trigger to avoid the metastable phenomenon of the trigger; the measurement accuracy is high, and the random measurement error is less than 1ps under the 12nm process; compared with the use of digital-to-analog conversion circuits, resistors and capacitors, etc., this structure uses a pure digital structure (such as multiplexers, logic circuits and latch structures, etc.), which can be implemented using devices in the standard device library and can be directly synthesized, which is very friendly to the integrated circuit design process; this structure is resistant to aging interference, even if the circuit delay increases due to aging, the measurement accuracy is less affected; this structure only requires a very small area overhead and has little impact on the original integrated circuit design.

[0136] Figure 11 A block diagram of an exemplary computer system suitable for implementing embodiments of the present application is shown.

[0137] The computer system may include a processor (H1); a memory (H2) coupled to the processor (H1) and storing computer executable instructions therein for performing the steps of various methods of the embodiments of the present application when executed by the processor.

[0138] The processor (H1) may include, but is not limited to, one or more processors or microprocessors, etc.

[0139] The memory (H2) may include, but is not limited to, for example, random access memory (RAM), read-only memory (ROM), flash memory, EPROM memory, EEPROM memory, registers, computer storage media (such as hard disk, floppy disk, solid-state drive, removable disk, CD-ROM, DVD-ROM, Blu-ray disc, etc.).

[0140] In addition, the computer system may also include a data bus (H3), an input / output (I / O) bus (H4), a display (H5), and input / output devices (H6) (eg, keyboard, mouse, speakers, etc.).

[0141] The processor (H1) can communicate with external devices (H5, H6, etc.) through an I / O bus (H4) via a wired or wireless network (not shown).

[0142] The memory (H2) may also store at least one computer-executable instruction for executing various functions and / or steps of methods in the embodiments described in the present technology when the processor (H1) executes the instruction.

[0143] In one embodiment, the at least one computer executable instruction may also be compiled into or constitute a software product, wherein one or more computer executable instructions are executed by a processor to perform the various functions and / or method steps in the embodiments described in the present technology.

[0144] Figure 12 A schematic diagram of a non-transitory computer-readable storage medium according to an embodiment of the present disclosure is shown.

[0145] like Figure 12 As shown, the computer-readable storage medium 1220 stores instructions, such as computer-readable instructions 1210. When the computer-readable instructions 1210 are executed by the processor, the power supply voltage detection method described with reference to the above figures can be executed. The computer-readable storage medium includes, but is not limited to, volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory (cache), etc. Non-volatile memory may include, for example, read-only memory (ROM), hard disk, flash memory, etc. For example, the computer-readable storage medium 1220 can be connected to a computing device such as a computer, and then, when the computing device executes the computer-readable instructions 1210 stored on the computer-readable storage medium 1220, the above methods can be performed.

[0146] Of course, the above-mentioned specific embodiments are merely examples and not limitations, and those skilled in the art can, according to the concept of the present application, merge and combine some steps and devices from the various embodiments described separately above to achieve the effects of the present application. Such merged and combined embodiments are also included in the present application, and such merges and combinations are not described one by one here.

[0147] Note that the advantages, strengths, and effects mentioned in this disclosure are merely examples and not limitations, and should not be construed as necessarily possessed by each embodiment of this application. Furthermore, the specific details disclosed above are provided for illustrative purposes and to facilitate understanding, not limitations, and the details do not necessarily limit this application to the use of the specific details.

[0148] The block diagrams of the devices, devices, equipment, and systems involved in this disclosure are merely illustrative examples and are not intended to require or imply that they must be connected, arranged, or configured in the manner shown in the block diagrams. As will be appreciated by those skilled in the art, these devices, devices, equipment, and systems can be connected, arranged, or configured in any manner. Words such as "include," "comprise," "have," and the like are open-ended words, meaning "including but not limited to," and can be used interchangeably therewith. The words "or" and "and" used herein refer to the words "and / or" and can be used interchangeably therewith, unless the context clearly indicates otherwise. The word "such as" used herein refers to the phrase "such as but not limited to," and can be used interchangeably therewith.

[0149] The step flow charts and the above method descriptions in this disclosure are merely illustrative examples and are not intended to require or imply that the steps of the various embodiments must be performed in the order given. As will be appreciated by those skilled in the art, the order of the steps in the above embodiments can be performed in any order. Words such as "thereafter," "then," "next," and the like are not intended to limit the order of the steps; these words are only used to guide the reader through the description of these methods. In addition, any reference to an element in the singular, such as using the articles "a," "an," or "the," is not to be construed as limiting the element to the singular.

[0150] In addition, the steps and devices in the various embodiments of this document are not limited to being implemented in a certain embodiment. In fact, according to the concept of this application, relevant partial steps and partial devices in the various embodiments of this document can be combined to conceive new embodiments, and these new embodiments are also included in the scope of this application.

[0151] Each operation of the method described above may be performed by any suitable means capable of performing the corresponding functions. The means may include various hardware and / or software components and / or modules, including but not limited to hardware circuits, application specific integrated circuits (ASICs) or processors.

[0152] The various illustrated logic blocks, modules, and circuits may be implemented or described using a general-purpose processor, a digital signal processor (DSP), an ASIC, a field programmable gate array signal (FPGA) or other programmable logic device (PLD), discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor may be a microprocessor, but as an alternative, the processor may be any commercially available processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, multiple microprocessors, a microprocessor cooperating with a DSP core, or any other such configuration.

[0153] The steps of the method or algorithm described in conjunction with the present disclosure can be directly embedded in hardware, in a software module executed by a processor, or in a combination of the two. The software module can exist in any form of tangible storage medium. Some examples of storage media that can be used include random access memory (RAM), read-only memory (ROM), flash memory, EPROM memory, EEPROM memory, registers, hard disks, removable disks, CD-ROMs, etc. A storage medium can be coupled to a processor so that the processor can read information from the storage medium and write information to the storage medium. In an alternative embodiment, the storage medium can be integral to the processor. A software module can be a single instruction or many instructions and can be distributed over several different code segments, between different programs, and across multiple storage media.

[0154] The methods disclosed herein include actions for implementing the described methods. Methods and / or actions may be interchangeable with one another without departing from the scope of the claims. In other words, unless a specific order of actions is specified, the order and / or use of specific actions may be modified without departing from the scope of the claims.

[0155] The above functions can be implemented by hardware, software, firmware or any combination thereof. If implemented in software, the functions can be stored as instructions on a tangible computer-readable medium. The storage medium can be any available tangible medium that can be accessed by a computer. By way of example and not limitation, such computer-readable media can include RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices or any other tangible medium that can be used to carry or store desired program codes in the form of instructions or data structures and can be accessed by a computer. As used herein, disk and disc include compact discs (CDs), laser discs, optical discs, digital versatile discs (DVDs), floppy discs and Blu-ray discs, wherein disks usually reproduce data magnetically, while discs reproduce data optically using lasers.

[0156] Thus, a computer program product can perform the operations presented herein. For example, such a computer program product can be a computer-readable tangible medium having instructions tangibly stored (and / or encoded) thereon, the instructions being executable by a processor to perform the operations described herein. The computer program product can include packaging materials.

[0157] Software or instructions may also be transmitted via a transmission medium. For example, software may be transmitted from a website, server, or other remote source using a transmission medium such as coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, or microwave.

[0158] In addition, the modules and / or other appropriate means for carrying out the methods and techniques described herein can be downloaded and / or otherwise obtained by the user terminal and / or base station when appropriate. For example, such a device can be coupled to a server to facilitate the transmission of the means for carrying out the methods described herein. Alternatively, the various methods described herein can be provided via a storage component (e.g., RAM, ROM, a physical storage medium such as a CD or a floppy disk) so that the user terminal and / or base station can obtain the various methods when being coupled to the device or providing a storage component to the device. In addition, any other appropriate technology for providing the methods and techniques described herein to a device can be utilized.

[0159] Other examples and implementations are within the scope and spirit of this disclosure and the appended claims. For example, due to the nature of software, the functions described above can be implemented using software performed by a processor, hardware, firmware, hardwiring, or any combination of these. Features that implement the functions can also be physically located in various locations, including being distributed so that parts of the functions are implemented at different physical locations. Moreover, as used herein, including as used in the claims, "or" used in a list of items that begin with "at least one" indicates a separate list, so that, for example, a list of "at least one of A, B, or C" means A or B or C, or AB or AC or BC, or ABC (i.e., A and B and C). In addition, the wording "exemplary" does not mean that the example described is preferred or better than other examples.

[0160] Various changes, substitutions, and modifications of the technology described herein may be made without departing from the teachings of the appended claims. Moreover, the scope of the claims of this disclosure is not limited to the specific aspects of the processes, machines, manufactures, compositions of things, means, methods, and actions described above. Currently existing or later developed processes, machines, manufactures, compositions of things, means, methods, or actions that perform substantially the same function or achieve substantially the same results as the corresponding aspects described herein may be utilized. Accordingly, the appended claims include within their scope such processes, machines, manufactures, compositions of things, means, methods, or actions.

[0161] The above description of the disclosed aspects is provided to enable any person skilled in the art to make or use the present application. Various modifications to these aspects will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other aspects without departing from the scope of the present application. Therefore, the present application is not intended to be limited to the aspects shown herein, but rather to be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0162] The above description has been provided for the purpose of illustration and description. Furthermore, this description is not intended to limit the embodiments of the present application to the forms disclosed herein. Although a number of example aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, alterations, additions, and sub-combinations thereof.

Claims

1. A pulse signal width measuring device, comprising: A buffer chain comprising N first buffers, N first AND gates having one input terminal connected to a pulse signal and another input terminal connected to an output of a corresponding first buffer, and corresponding N flip-flops coupled to an output terminal of each first AND gate, wherein the output terminal of each of the N first buffers is connected to an input terminal of a next first buffer, wherein N is a positive integer greater than 1; a path delay adjustment circuit, wherein an input end of the path delay adjustment circuit receives a pulse signal, and an output end of the path delay adjustment circuit is connected to an input end of a first buffer in the buffer chain; a control device for controlling the delay generated by the path delay adjustment circuit to decrease from the preset delay by at least one preset adjustment step size according to a preset adjustment step size during each adjustment until the output of the P-th trigger changes, where P is a positive integer and is less than or equal to N; A measuring device is connected to the output terminals of the respective triggers and the control device, and measures the width of the pulse signal based on at least the results outputted by the output terminals of the respective triggers, the delay of each first buffer, and the delay of the path delay adjustment circuit just before the output of the P-th trigger changes.

2. The device according to claim 1, wherein The path delay adjustment circuit includes M first multiplexers, where M is a positive integer. An input terminal of each first multiplexer is connected to at least two second buffers having different buffering times. During each adjustment, the control device inputs a respective path delay adjustment signal to a selection signal terminal of each first multiplexer to select one of the at least two second buffers, thereby controlling the delay generated by the path delay adjustment circuit to be reduced from a preset delay by at least a preset adjustment step.

3. The device according to claim 1, wherein The path delay adjustment circuit includes a first multiplexer, an input end of the first multiplexer is connected to at least two second buffer groups with different total buffer times, and during each adjustment, the control device inputs a path delay adjustment signal to the selection signal end of the first multiplexer to select one of the at least two second buffer groups, so as to control the delay generated by the path delay adjustment circuit to be reduced from a preset delay by at least a preset adjustment step.

4. The apparatus according to claim 1 , further comprising a second multiplexer, a plurality of groups of odd-numbered NOT gates, a counter, and a timer. in, The plurality of input terminals of the second multiplexer respectively receive the output signals of the output terminals of the N first buffers through the plurality of groups of odd-numbered NOT gates and receive the pulse signal and a clock signal with a predetermined pulse width. The output end of the second multiplexer is connected to the path delay adjustment circuit, the output end of the path delay adjustment circuit is further connected to the counter, and the counter is further connected to the timer.

5. The device according to claim 4, wherein The control device outputs a ring oscillator switching signal to the selection signal terminal of the second multiplexer to: In high-precision measurement step mode: The second multiplexer is controlled to select the clock signal having a predetermined pulse width, and the measuring device controls the delay generated by the path delay adjustment circuit to decrease from the preset delay by at least one preset adjustment step according to a preset adjustment step during each adjustment through the delay adjustment circuit and the control device, until the output of the Qth flip-flop changes, thereby fixing the delay of the path delay adjustment circuit at a state immediately before the output of the Qth flip-flop changes, where Q is a positive integer and is less than or equal to N. During the calibration step: controlling the second multiplexer to select the output of the Q-1th first buffer, using the timer to count the ring oscillations using the counter within a predetermined timing to measure the error width of the clock signal, and using the difference between the predetermined pulse width and the error width as an error; In high-precision and error-free measurement mode: controlling the second multiplexer to select the pulse signal, the measuring device performing the high-precision measurement step mode and the calibration step to obtain the error-bearing width of the pulse signal to be measured, and subtracting the error from the error-bearing width of the pulse signal to be measured to obtain the high-precision and error-free width of the pulse signal, in, The measuring the error width of the clock signal by using the timer to count the ring oscillations using a counter within a predetermined timing includes dividing the predetermined timing by the number of ring oscillations counted by the counter within the predetermined timing to measure the error width of the clock signal.

6. The device according to claim 5, wherein Controlling the second multiplexer to select the pulse signal, the measuring device performing the high-precision measurement step mode and the calibration step to obtain an error-bearing width of the pulse signal to be measured, and subtracting the error from the error-bearing width of the pulse signal to be measured to obtain a high-precision and error-free width of the pulse signal includes: In the high-precision measurement step: controlling the second multiplexer to select the pulse signal to be measured, the measuring device adjusting the delay of the path delay adjustment circuit and the control device, controlling the delay generated by the path delay adjustment circuit to decrease from the preset delay by at least one preset adjustment step according to a preset adjustment step during each adjustment, until the output of the Qth flip-flop changes, and fixing the delay of the path delay adjustment circuit to a state immediately before the output of the Qth flip-flop changes, where Q is a positive integer and is less than or equal to N; In the calibration step: the control device controls the second multiplexer to select the output of the Q-1th first buffer, and uses the timer to use the counter to count the ring oscillation within a predetermined timing to measure the error width of the pulse signal to be measured; In the error removal step: The control device subtracts the error previously calculated by the clock signal of the predetermined width from the error-bearing width of the pulse signal to be measured, thereby obtaining the high-precision and error-free width of the pulse signal.

7. The device according to claim 1, wherein The measuring device measures the high-precision width of the pulse signal through the following steps: The total delay of the first (P-1) first buffers is added to the delay of the path delay adjustment circuit before the output of the P-th trigger changes to obtain the high-precision width of the pulse signal.

8. The apparatus according to claim 1, further comprising: N signal latch circuits, wherein each buffer is connected to the clock input terminal of the corresponding trigger through its own signal latch circuit, wherein the input terminal of each trigger receives a high level, Wherein, each signal latch circuit includes: A first AND gate, wherein a first input terminal is connected to an output terminal of a corresponding buffer and a second input terminal receives a pulse signal; an OR gate, a first input of which is connected to the output of the first AND gate, and an output of which is connected to the clock input of the corresponding flip-flop; The second AND gate has its output connected to the second input of the OR gate, its first input connected to the output of the OR gate, and its second input receiving a reset signal of the signal latch circuit, which is at a low level during reset.

9. The device according to claim 1, wherein The pulse signal is an output of an XOR gate obtained by using a signal of a starting point of a critical path of an integrated circuit through the critical path and a signal of the starting point as two inputs of the XOR gate.

10. A pulse signal width measuring method using a pulse signal width measuring device, wherein the pulse signal width measuring device comprises: A buffer chain comprising N first buffers, N first AND gates having one input terminal connected to a pulse signal and another input terminal connected to an output of a corresponding first buffer, and corresponding N flip-flops coupled to an output terminal of each first AND gate, wherein the output terminal of each of the N first buffers is connected to an input terminal of a next first buffer, wherein N is a positive integer greater than 1; a path delay adjustment circuit, wherein an input end of the path delay adjustment circuit receives a pulse signal, and an output end of the path delay adjustment circuit is connected to an input end of a first buffer in the buffer chain; The pulse signal width measurement method includes: During each adjustment, the delay generated by the path delay adjustment circuit is controlled to decrease from the preset delay by at least one preset adjustment step size according to a preset adjustment step size until the output of the P-th trigger changes, where P is a positive integer and is less than or equal to N; The width of the pulse signal is measured based on at least the results outputted by the output terminals of the respective flip-flops, the delay of each first buffer, and the delay of the path delay adjustment circuit just before the output of the Pth flip-flop changes.

11. The method according to claim 10, wherein: The path delay adjustment circuit includes M first multiplexers, where M is a positive integer, and the input end of each first multiplexer is connected to at least two second buffers with different buffering times, and The step of controlling the delay generated by the path delay adjustment circuit to reduce the delay from the preset delay by at least one preset adjustment step according to the preset adjustment step during each adjustment comprises: During each adjustment, a respective path delay adjustment signal is input to the selection signal terminal of each first multiplexer to select one of the at least two second buffers, so as to control the delay generated by the path delay adjustment circuit to be reduced from the preset delay by at least one preset adjustment step.

12. The method according to claim 10, wherein: The path delay adjustment circuit includes a first multiplexer, the input end of the first multiplexer is connected to at least two second buffer groups with different total buffer times, and The step of controlling the delay generated by the path delay adjustment circuit to reduce the delay from the preset delay by at least one preset adjustment step according to the preset adjustment step during each adjustment comprises: During each adjustment, a path delay adjustment signal is input to the selection signal terminal of the first multiplexer to select one of the at least two second buffer groups, so as to control the delay generated by the path delay adjustment circuit to be reduced from the preset delay by at least one preset adjustment step.

13. The method according to claim 10, wherein: The pulse signal width measuring device further includes a second multiplexer, multiple groups of odd-numbered NOT gates, a counter, and a timer. The plurality of input terminals of the second multiplexer respectively receive the output signals of the output terminals of the N first buffers and receive the pulse signal and a clock signal with a predetermined pulse width through the plurality of groups of odd-numbered NOT gates. The output end of the second multiplexer is connected to the path delay adjustment circuit, the output end of the path delay adjustment circuit is further connected to the counter, and the counter is further connected to the timer.

14. The method according to claim 13, further comprising: Outputting a ring oscillator switching signal to the selection signal terminal of the second multiplexer to: In high-precision measurement step mode: controlling the second multiplexer to select the clock signal having the predetermined pulse width, controlling the delay generated by the path delay adjustment circuit to decrease from the predetermined delay by at least one predetermined adjustment step according to a predetermined adjustment step during each adjustment until the output of the Qth flip-flop changes, and fixing the delay of the path delay adjustment circuit at a state immediately before the output of the Qth flip-flop changes, where Q is a positive integer and is less than or equal to N, During the calibration step: controlling the second multiplexer to select the output of the Q-1th first buffer, using the timer to count the ring oscillations using the counter within a predetermined timing to measure the error width of the clock signal, and using the difference between the predetermined pulse width and the error width as an error; The step of measuring the width of the pulse signal based on at least the output results of the output terminals of the respective triggers, the delay of each first buffer, and the delay of the path delay adjustment circuit immediately before the output of the P-th trigger changes includes: In high-precision and error-free measurement mode: controlling the second multiplexer to select the pulse signal, obtaining the error-bearing width of the pulse signal to be measured through the high-precision measurement step mode and the calibration step, and subtracting the error from the error-bearing width of the pulse signal to be measured to obtain the high-precision and error-free width of the pulse signal, The step of using the timer to count the ring oscillations using a counter within a predetermined timing to measure the error width of the clock signal includes: dividing the predetermined timing by the count of the ring oscillations by the counter within the predetermined timing to measure the error width of the clock signal.

15. The method according to claim 14, wherein The steps of controlling the second multiplexer to select the pulse signal, the measuring device performing the high-precision measurement step mode and the calibration step to obtain the error-bearing width of the pulse signal to be measured, and subtracting the error from the error-bearing width of the pulse signal to be measured to obtain the high-precision and error-free width of the pulse signal include: In the high-precision measurement step: controlling the second multiplexer to select the pulse signal to be measured, the measuring device adjusting the delay of the path delay adjustment circuit and the control device, controlling the delay generated by the path delay adjustment circuit to decrease from the preset delay by at least one preset adjustment step according to a preset adjustment step during each adjustment, until the output of the Qth flip-flop changes, and fixing the delay of the path delay adjustment circuit to a state immediately before the output of the Qth flip-flop changes, where Q is a positive integer and is less than or equal to N; In the calibration step: the control device controls the second multiplexer to select the output of the Q-1th first buffer, and uses the timer to use the counter to count the ring oscillation within a predetermined timing to measure the error width of the pulse signal to be measured; In the error removal step: The control device subtracts the error previously calculated by the clock signal of the predetermined width from the error-bearing width of the pulse signal to be measured, thereby obtaining the high-precision and error-free width of the pulse signal.

16. The method according to claim 10, wherein The step of measuring the width of the pulse signal based on at least the results outputted by the output terminals of the respective flip-flops, the delay of each first buffer, and the delay of the path delay adjustment circuit immediately before the output of the P-th flip-flop changes comprises: The total delay of the first (P-1) first buffers is added to the delay of the path delay adjustment circuit before the output of the P-th trigger changes to obtain the high-precision width of the pulse signal.

17. The method according to claim 10, wherein The pulse signal width measuring device further includes: N signal latch circuits, wherein each buffer is connected to the clock input terminal of the corresponding trigger through its own signal latch circuit, wherein the input terminal of each trigger receives a high level, Wherein, each signal latch circuit includes: A first AND gate, wherein a first input terminal is connected to an output terminal of a corresponding buffer and a second input terminal receives a pulse signal; an OR gate, a first input of which is connected to the output of the first AND gate, and an output of which is connected to the clock input of the corresponding flip-flop; The second AND gate has its output connected to the second input of the OR gate, its first input connected to the output of the OR gate, and its second input receiving a reset signal of the signal latch circuit, which is at a low level during reset.

18. The method according to claim 10, wherein The pulse signal is an output of an XOR gate obtained by using a signal of a starting point of a critical path of an integrated circuit through the critical path and a signal of the starting point as two inputs of the XOR gate.

19. A computer system comprising: processor; A memory is coupled to the processor and stores therein computer executable instructions for performing the method according to any one of claims 10 to 18 when executed by the processor.

20. A computer readable medium having a computer program stored thereon, wherein: When the program is executed by a processor, the method according to any one of claims 10 to 18 is implemented.

Images