A method and system for testing PA bus physical layer signals and master-slave station equipment

Abstract

The present invention discloses a method and system for testing the physical layer signal of a PA bus and master-slave station equipment. The steps of the method are as follows: 1. By collecting the physical signal waveform characteristics on the PA dual bus, analyze whether the amplitude, overshoot, waveform pulse rise time and fall time, signal period, duty cycle, and BIT unit jitter of the physical communication signal waveform meet the PA standard requirements; 2. Monitor the working status of the master station in the PA bus system, and determine the type of the master station and the master station data information by analyzing the signal structure sent by the master station; 3. Monitor the working status of each slave station in the PA bus system, and determine the slave station device type and slave station data information through the master station communication signal and the slave station response signal. The present invention obtains various information of the master and slave stations by analyzing the bus data information; at the same time, by collecting the actual physical waveform signal of the bus, the difference between the waveform and the standard waveform is analyzed, and it does not affect the operating status of the overall system.

Description

Technical Field

[0001] The invention relates to the technical field of field bus, and in particular to a master station device, a slave station device and a communication physical signal quality test of a PA bus communication system. Background Art

[0002] At present, PA fieldbus applications are increasing. There are relevant standards for PA master station equipment, slave station equipment, and bus twisted pair cables. There are also testing standards for independent equipment, that is, various indicators of a single device can be tested, but there is no testing method for the working status of each device in a PA full system with complete actual wiring. The present invention fills the relevant gaps and tests the physical waveforms on the master station, slave station and bus system in the working state in the complete PA bus system without affecting the operating status of the overall system. Summary of the invention

[0003] The purpose of the present invention is to provide a method and system for testing the physical layer signal of a PA bus and the master and slave station equipment, so as to solve the technical problem of obtaining various information of the master and slave stations by analyzing the bus data information; at the same time, by collecting the actual physical waveform signal of the bus, the difference between the waveform and the standard waveform is analyzed without affecting the operating status of the overall system.

[0004] A method for testing PA bus physical layer signals and master-slave station devices of the present invention comprises the following steps:

[0005] By analyzing the bus data information, the information of the master and slave stations is obtained; at the same time, the difference between the waveform and the standard waveform is analyzed by collecting the actual physical waveform signal of the bus; the bus data information and the actual physical waveform signal of the bus are collected by connecting the interface module to the PA bus in the working state. After the interface module is connected to the bus, it is in a silent state; after the interface module is connected to the bus, the bus voltage signal is AC coupled and then a DC bias is applied. 10 , raise the alternating signal to near VDD / 2, control the range to VDD / 2-1~VDD / 2+1, and then send the signal to the analog signal acquisition module 2 and analog-to-logic modules 3 ;Through the analog signal acquisition module 2 , the physical signal after AC coupling is collected at high speed, and the collected data enters the central processing unit 7 Perform subsequent processing; convert analog to logic module 3 , so that the signal alternating near the VDD / 2 level becomes a TTL signal consisting of "0" and "1" and is sent to the central processing unit 7 ; Through the central processing unit 7 Process physical signal data and logical signals separately; central processing unit 7Processing analog signal acquisition module 2 Provided physical signal data, analyze the physical level information of the bus signal based on the data, and provide various reports; the report content includes signal amplitude, symmetry of signal peak value and trough value relative to the median value, signal rise time, signal fall time, signal period / frequency, signal bit jitter, signal overshoot, signal undershoot; central processing unit 7 Processing analog to logic module 3 Provided logical signal data, analyze the bus signal communication layer and application layer information based on the data, and provide various reports; the report content includes master station information, slave station information; central processing unit 7 Control Logic Output Module 6 , output logic signal with communication data, through analog signal output module 4 The logic signal is converted into an analog signal. The analog signal output module can output analog signals of different amplitudes as needed, and then pass through the bus interface module 1 Sent to the bus and participate in the entire PA system communication; central processing unit 7 According to the master station information and slave station information, the master station is simulated and a communication signal is sent to any slave station. This communication signal can be changed according to the test rules to test the signal recognition ability of the slave station; Interaction module 9 The interactive module communicates with the PC through the universal serial port, sends the bus information to the PC, receives the configuration command issued by the PC, and determines the central processing unit according to the command. 7 The operation function.

[0006] The method for testing the PA bus physical layer signal and the master-slave station equipment, wherein the output amplitude is set to extremely low values ​​of 155mV and 70mV, so as to measure the slave station's signal resolution of 150mV and anti-interference capability of 70mV.

[0007] The method for testing the PA bus physical layer signal and the master-slave station equipment, wherein the communication data is added with a communication data preamble, and the slave station is tested for distinguishing the signal preamble and the normal signal logic.

[0008] The method for testing the PA bus physical layer signal and the master-slave station equipment changes the period of two certain logic signals to test the slave station's tolerance to bit jitter.

[0009] A system for testing PA bus physical layer signals and master and slave station devices, comprising:

[0010] Power Processing Module 8 , step down the universal 12V or 24V power supply to transform it into a VDD power supply system for powering all modules of this system;

[0011] PA bus interface module 1 , this system is connected to the working PA bus through the PA bus interface module, and is not affected by the bus polarity; at the time of connection, the PA bus interface module and other modules of this system will not absorb any current from the bus or release any current to the bus; when this system is in a silent state, all modules will not absorb any current from the bus or release any current to the bus; after the interface module is connected to the bus, the bus voltage signal is AC coupled and then a DC bias is applied 10 , raise the alternating signal to near VDD / 2, control the range to VDD / 2-1~VDD / 2+1, and then send the signal to the analog signal acquisition module 2 and analog-to-logic modules 3 ,During this process, there is no impact on the signals on the bus;

[0012] Analog signal acquisition module 2 , which is composed of a high-resistance follower circuit and a high-speed AD sampling circuit, collects the physical signal after AC coupling at high speed, and the collected data enters the central processing unit 7 Carry out subsequent processing;

[0013] Analog to Logic Module 3 , which is composed of a bandpass filter circuit and a signal comparison circuit, so that the signal alternating near the VDD / 2 level is converted into a TTL signal consisting of "0" and "1" and sent to the central processing unit 7 ;

[0014] Central Processing Unit 7 , process the physical signal data and logical signal separately, and perform subsequent functions according to the processed results; central processing unit 7 Processing analog signal acquisition module 2 Provided physical signal data, analyze the physical layer information of the bus signal based on the data, and provide various reports; the report content includes but is not limited to signal amplitude, symmetry of signal peak value and trough value relative to the median, signal rise time, signal fall time, signal period / frequency, signal bit jitter (period deviation of different signals), signal overshoot (part exceeding the mean of peak value), signal undershoot (part below the mean of trough value); Central Processing Unit 7 Processing analog to logic module 3 Provided logical signal data, analyze bus signal communication layer and application layer information based on the data, and provide various reports; the report content includes but is not limited to master station information and slave station information;

[0015] Control Logic Output Module 6 , controlled by the central processing unit 7 control, the logic output module 6Output logic signals with communication data;

[0016] Analog signal output module 4 , logic output module 6 Output logic signal with communication data through the analog signal output module 4 Convert logic signals into analog signals, analog signal output module 4 Output analog signals of different amplitudes as needed, and then pass through the bus interface module 1 Sent to the bus, participating in the communication of the entire PA system; the communication data adds a communication data preamble to test the slave station's logical discrimination of the signal preamble and normal signal; the output amplitude is set to an extremely low value of 155mV and 70mV, to measure the slave station's signal resolution of 150mV and anti-interference ability of 70mV;

[0017] The central processing unit 7 According to the master station information and slave station information, the master station is simulated to send a communication signal to any slave station. This communication signal can be changed according to the test rules to test the signal recognition ability of the slave station.

[0018] Advantages and positive effects of the present invention:

[0019] The present invention proposes a new and complete testing method for the entire industrial PA bus system, which is beneficial to all PA bus application sites, and can clearly understand the bus information at the bottom signal level. Compared with the bus information obtained from the main station or PLC, it is more direct and accurate, which is conducive to a more reasonable configuration of the bus and a more standardized, accurate and smoother signal.

[0020] The present invention can be used as a bus interface to exchange data with a PC at a low cost, and the PC can perform more advanced data analysis and processing, and can even receive PC instructions to interfere with and influence the PA bus. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 It is a system principle block diagram of the present invention.

[0022] Figure 2 It is a principle block diagram of the bus interface module of the present invention.

[0023] Figure 3 It is a principle block diagram of the analog signal acquisition module of the present invention.

[0024] Figure 4 It is a principle block diagram of the analog-to-logic module of the present invention.

[0025] Figure 5 It is a principle block diagram of the analog signal output module of the present invention. DETAILED DESCRIPTION

[0026] The specific working steps and principles of the present invention are as follows: Power processing module 8 , the universal 12V or 24V power supply is stepped down to transform into a VDD power supply system for powering all modules of the present invention.

[0027] The present invention provides a PA bus interface module 1 The present invention is connected to the PA bus in working state through the interface module, and can be unaffected by the bus polarity. At the time of connection, the interface module and other modules of the present invention will not absorb any current from the bus or release any current to the bus, that is, they will not affect the current state of the bus at all, that is, they will not affect the voltage signal on the bus, so as to achieve completely undisturbed access. After the interface module is connected to the bus, when the present invention is in a silent state, all modules of the present invention will not absorb any current from the bus or release any current to the bus, that is, they will not affect the current state of the bus at all. At this time, the present invention also has no effect on the PA bus.

[0028] After the interface module is connected to the bus, the bus voltage signal is AC coupled and then a DC bias is applied. 10 , raise the alternating signal to near VDD / 2, control the range to VDD / 2-1~VDD / 2+1, and then send the signal to the analog signal acquisition module 2 and analog-to-logic modules 3 ,According to the previous text, there is no impact on the signals on the bus during this process.

[0029] Analog signal acquisition module 2 , which is composed of a high-resistance follower circuit and a high-speed AD sampling circuit, collects the physical signal after AC coupling at high speed, and the collected data enters the central processing unit 7 Perform subsequent processing.

[0030] Analog to Logic Module 3 , which is composed of a bandpass filter circuit and a signal comparison circuit, so that the signal alternating near the VDD / 2 level is converted into a TTL signal consisting of "0" and "1" and sent to the central processing unit 7 .

[0031] Central Processing Unit 7 The physical signal data and logical signal are processed separately, and subsequent functions are performed based on the processed results.

[0032] Central processing unit of the present invention 7 Processing analog signal acquisition module 2Based on the provided physical signal data, the physical layer information of the bus signal is analyzed and various reports are provided. The report content includes but is not limited to the signal amplitude, the symmetry of the signal peak value and the trough value relative to the median value, the signal rise time, the signal fall time, the signal period / frequency, the signal bit jitter (the period deviation of different signals), the signal overshoot (the part exceeding the peak value mean), the signal undershoot (the part below the trough value mean), etc.

[0033] Central processing unit of the present invention 7 Processing analog to logic module 3 Provided logic signal data, analyze bus signal communication layer and application layer information based on the data, and provide various reports. The report content includes but is not limited to master station information, slave station information, etc.

[0034] Central Processing Unit 7 Control Logic Output Module 6 , output logic signal with communication data, through analog signal output module 4 The logic signal is converted into an analog signal. The analog signal output module can output analog signals of different amplitudes as needed, and then pass through the bus interface module 1 Sent to the bus and participate in the entire PA system communication. Central Processing Unit 7 The master station simulation can be performed based on the master station information and slave station information, and a communication signal can be sent to any slave station. This communication signal can be modified to test the signal recognition capability of the slave station.

[0035] Through three aspects of transformation, all slave equipment is tested and evaluated;

[0036] 1. Amplitude setting: The amplitude can be set to very low values ​​(155mV and 70mV) to measure the slave's signal resolution (150mV) and anti-interference ability (70mV);

[0037] 2. Add communication data preamble to test the slave station's logical distinction between signal preamble and normal signal;

[0038] 3. Change the period of two logic signals (test bit jitter) to test the slave's tolerance to bit jitter.

[0039] The interactive module in the present invention 9 By communicating with the PC through the universal serial port, the interactive module of the present invention sends the bus information (master station information, slave station information, physical signal data, logical signal information) to the PC, which can perform more detailed analysis; the interactive module of the present invention can receive the configuration command issued by the PC and determine the operating function of the present invention according to the command.

[0040] The system of the present invention is shown in Figure 1-Figure 5As shown, it includes: bus access module, analog signal acquisition module, analog to logic module, logic signal analysis module, logic signal output module, analog signal output module, central processing unit, power processing module, switching module (see Figure 1 ); its working principle is as described in the above working method and steps. It adopts independent power supply mode, can be connected to the PA bus without disturbance, can silently monitor the signal on the bus, and can controllably send signals to the bus at data intervals; it only connects to the PA bus through the bus access module, and does not need to distinguish the polarity of the PA bus, and does not absorb or release current from the bus, and has no effect on the signal on the bus; it can simulate a slave device on the PA bus system, monitor the signal on the PA bus, analyze the physical signal waveform information, analyze the logical information of the data signal, and analyze the master device information and working status on the PA bus system; it can simulate a master device on the PA bus system, actively send specific signals to all slave devices on the PA bus, induce the slave devices to reply to the response message, and thus obtain various information of all slave devices on the PA bus system; the amplitude of the signal sent to the PA bus is controllable, which is used to test the signal sensitivity and anti-interference of all slaves; the preamble code of the signal sent to the PA bus is variable, which is used to test the preamble resolution effect of all slaves; it receives the general computer control signal through the switching module and outputs various signals that need to be sent.

[0041] Figure 2 In the process, the bus signal first passes through the rectifier bridge, the high-resistance circuit, and then AC coupling before being sent to the subsequent functional modules; Figure 3 In the process, the PA bus signal is DC biased after AC coupling, so that the signal is between VDD / 2-1 and VDD / 2+1; Figure 4 In the process, the PA bus signal is AC coupled, filtered, and then passes through the comparator to become a TTL signal and enter the MCU; Figure 5 In the circuit, the entire output module is a current control circuit. Through the application of the operational amplifier, the voltage U of the output transistor emitter is determined by the output voltage of the analog switch. Through the control of the analog switch, the transistor emitter voltage can be changed. The emitter voltage acts on the negative resistor R of PA to form a current I (emitter voltage / resistance to ground) through the resistor. This current is basically equal to the transistor's I b +I c current, the emitter voltage changes, resulting in I c Changes, that is, changes in the PA bus current, thus forming different signal values. R is composed of a group of parallel resistors. The connection of resistors is controlled by switches. By connecting different resistor combinations, I c The value of this part of the resistance mainly changes the amplitude of the signal.

Claims

1. A method for testing PA bus physical layer signals and master and slave station devices, characterized in that: The bus message data information and bus physical waveform signal are collected by connecting the PA bus interface module to the working PA bus. When the PA bus interface module is connected to the bus, all modules are in a silent state where they do not absorb or release any current from the bus. After the PA bus interface module is connected to the bus, the bus voltage signal is AC-coupled and then a DC bias is applied to increase the AC-coupled signal to near VDD / 2, with the range controlled within VDD / 2-1 to VDD / 2+1. The DC-biased signal is then sent to the analog signal acquisition module and the analog-to-logic module respectively. The analog signal acquisition module collects the DC-biased signal at high speed, and the collected data of the bus physical waveform signal enters the central processing unit for subsequent processing. The analog-to-logic module converts the signal alternating near the VDD / 2 level into a TTL logic signal of the bus message data information consisting of "0" and "1" and sends it to the central processing unit. The central processing unit processes the data of the bus physical waveform signal and the TTL logic signal of the bus message data information respectively. The central processing unit processes the data of the bus physical waveform signal provided by the analog signal acquisition module, analyzes the physical level information of the bus signal, and provides a waveform data report. The report contains The content includes signal amplitude, symmetry of signal peak value and trough value relative to the median value, signal rise time, signal fall time, signal period / frequency, signal bit jitter, signal overshoot and signal undershoot; the central processing unit processes the TTL logic signal of the bus message data information provided by the analog-to-logic module, analyzes the bus signal communication layer and application layer information, and provides a communication data report; the report content includes master station information and slave station information; the central processing unit controls the logic signal output module, outputs the TTL logic signal with communication data, and converts the TTL logic signal with communication data into an analog signal through the analog signal output module. The analog signal output module outputs analog signals of different amplitudes as needed, and then sends them to the bus through the PA bus interface module to participate in the communication of the entire PA system; the central processing unit performs master station simulation based on the master station information and slave station information, and sends a communication signal to any slave station. This communication signal is changed according to the test rules to test the signal recognition ability of the slave station; The interactive module communicates with the PC through a universal serial port, sends bus information to the PC, receives configuration commands sent by the PC, and determines the operating function of the central processing unit according to the commands.

2. A method for testing PA bus physical layer signals and master-slave station devices according to claim 1, characterized in that: The communication data is added with a communication data preamble to test the logic discrimination capability of the slave station to the communication data preamble and normal signals.

3. A method for testing PA bus physical layer signals and master-slave station devices according to claim 1, characterized in that: Change the period of two TTL logic signals with communication data to test the slave's tolerance to bit jitter.

4. A system for testing PA bus physical layer signals and master and slave station devices, characterized in that: include: The power processing module performs voltage reduction processing on the general 12V or 24V power supply and transforms it into a VDD power supply system for powering all modules of this system; PA bus interface module, this system is connected to the PA bus in working state through the PA bus interface module, and is not affected by the bus polarity; At the time of connection, the system is in a silent state where all modules do not absorb or release any current from the bus; After the PA bus interface module is connected to the bus, the bus voltage signal is AC-coupled and then a DC bias is applied to increase the AC-coupled signal to near VDD / 2, with the range controlled between VDD / 2-1 and VDD / 2+1. The DC-biased signal is then sent to the analog signal acquisition module and the analog-to-logic module respectively. In this process, there is no effect on the signal on the bus. The analog signal acquisition module, which consists of a high-resistance follower circuit and a high-speed AD sampling, performs high-speed acquisition of the DC biased signal. The acquired bus physical waveform signal data enters the central processing unit for subsequent processing; The analog-to-logic module is composed of a bandpass filter circuit and a signal comparison circuit, which converts the signal alternating near the VDD / 2 level into a TTL logic signal of the bus message data information composed of "0" and "1" and sends it to the central processing unit; The central processing unit processes the data of the bus physical waveform signal and the TTL logic signal of the bus message data information respectively, and performs subsequent functions according to the processed results; the central processing unit processes the data of the bus physical waveform signal provided by the analog signal acquisition module, analyzes the physical layer information of the bus signal, and provides a waveform data report; the report content includes signal amplitude, symmetry of the signal peak value and trough value relative to the median, signal rise time, signal fall time, signal period / frequency, signal bit jitter, signal overshoot and signal undershoot; the central processing unit processes the TTL logic signal of the bus message data information provided by the analog to logic module, analyzes the bus signal communication layer and application layer information, and provides a communication data report; the report content includes master station information and slave station information; The logic signal output module is controlled by the central processing unit and outputs TTL logic signals with communication data; Analog signal output module, the TTL logic signal with communication data output by the logic signal output module is converted into an analog signal through the analog signal output module, the analog signal output module outputs analog signals with different amplitudes as needed, and then sends them to the bus through the PA bus interface module to participate in the communication of the entire PA system; the communication data is added with a communication data preamble to test the logic discrimination ability of the slave station to the communication data preamble and normal signals; The interactive module communicates with the PC through the universal serial port. The interactive module sends bus information to the PC. The interactive module receives the configuration command issued by the PC and determines the operation function of the central processing unit according to the command. Among them, the central processing unit performs master station simulation according to the master station information and slave station information, and sends communication signals to any slave station. At the same time, this communication signal is changed according to the test rules to test the signal recognition ability of the slave station.

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