A C-like 60 on-chip network architecture with a molecular plane structure

Abstract

The present invention belongs to the field of on-chip network architectures, and specifically relates to an on-chip network architecture imitating the C 60 molecular plane structure. The on-chip network architecture of the present invention consists of 12 routers and 20 cores, and the routers and cores are connected into a whole in the way of imitating the C 60 molecular plane structure. Specifically, each core is connected to 3 routers, and each router is connected to 5 cores. At the same time, cores cannot directly interact with each other in terms of data, and data needs to be transmitted through routers. Compared with traditional 2D on-chip networks, the connectivity of the on-chip network architecture proposed by the present invention is increased by 25%, and the longest path requires 3 router forwards, and the data transmission efficiency is increased by 25%. Thanks to the efficient design of the router module, the architecture of the present invention can support various network forms such as ordinary networks, merged networks, and forwarding networks, and has strong data transmission flexibility.

Description

Technical Field

[0001] The present invention belongs to the field of on-chip network architectures, and particularly relates to an on-chip network architecture imitating the C 60 molecular plane structure, and more particularly to an on-chip network architecture imitating the C 60 molecular plane structure applied to electroencephalogram (EEG) signal recognition. Background Art

[0002] EEG signal recognition has always been a direction actively explored and developed by humans. With the help of computer science, neuroscience, and brain science, efforts are made to study the mechanisms of brain information representation, transformation, and recognition rules, ultimately enabling machines to be directly controlled by the human brain by familiarizing themselves with human cognitive laws. Currently, related research on EEG signal recognition has achieved good results in fields such as clinical medicine, cognitive and emotional monitoring.

[0003] In principle, an EEG signal recognition system generally consists of modules such as EEG signal input, signal data processing and conversion, classification and recognition of characteristic signals, and output of recognition results. The EEG signal input module collects EEG signals with certain characteristics through wearable or implantable devices, and describes these characteristic signals with parameters. The signal data processing and conversion module processes the collected continuous EEG signals through methods such as analog-to-digital conversion for further calculation. The classification and recognition module of characteristic signals performs inference calculations based on the characteristic signals obtained after processing the source signals to determine the relationship between human brain consciousness and the characteristic signals. The output module of recognition results is the final module of the EEG signal recognition system, which controls external devices according to the recognition results. For example, it controls a robotic arm to move up, down, left, or right through the human brain to achieve the purpose of human-machine interaction.

[0004] Currently, there are still many limitations in EEG recognition technology. The classification and recognition of characteristic signals, as the most important intermediate link, are usually implemented by neural networks. A neural network is a mathematical model that mimics the structure and function of a biological neural network, consisting of multiple node layers connected together, including an input layer, a hidden layer, and an output layer. Information needs to be transmitted between different node layers, involving a large amount of data routing. A node layer consists of multiple nodes, and each node represents a specific function mapping, also known as a neuron. They are connected to the previous node layer through synapses and have corresponding weights and thresholds. If the output of a certain node is higher than the specified threshold, then the node will be activated and output data to the next node layer of the network; otherwise, the data will not be transmitted to the next node layer of the network.

[0005] The traditional implementation method of neural network inference calculation is the "CPU + GPU" hybrid computing mode; the CPU is responsible for controlling the data scheduling, copying the data from the memory to the GPU for calculation, and returning the data result after calculation to the memory. However, this traditional method needs to access the memory frequently, and has disadvantages such as low efficiency, high power consumption, and large cost overhead. People have realized that a dedicated integrated circuit needs to be designed for neural network algorithms to improve the calculation speed and data transmission efficiency, and the neural network accelerator has emerged as the times require.

[0006] In the neural network accelerator, each layer of the neural network is encapsulated as a core, and the core is responsible for performing the calculation of the neural network. The data between the cores is transmitted through a router. In the development process of the neural network accelerator, the access of a large number of weight parameters and the forwarding of data such as calculation results pose extremely high requirements on the on-chip network architecture. A reasonably designed architecture can greatly improve the data transmission efficiency and significantly enhance the inference efficiency of the neural network. The IBM team proposed the True north architecture. There is a router in each of the four directions of the southeast, northwest, south, and east of each core, which is responsible for receiving the core data from other different directions and transmitting the output data of its own core to the specified direction at the same time. This method is essentially a point-to-point transmission from one core to another core, with low flexibility; the data transmission delay is large between cores that are far away; each core has four routers, and the resource overhead is also relatively large. Summary of the Invention

[0007] In view of the above problems, the present invention provides an on-chip network architecture imitating the C 60 molecular plane structure.

[0008] The technical solution of the present invention is as follows:

[0009] An on-chip network architecture imitating the C 60 molecular plane structure, the on-chip network architecture is composed of 12 routers and 20 cores, and the routers and cores are connected into a whole in the way of imitating the C 60 molecular plane structure. Specifically, each core is connected to 3 routers, each router is connected to 5 cores, and the data between the cores is interacted through the routers. The input data source of each core can be off-chip or other cores (transmitted through the router), and the result after its own calculation can also be output to off-chip or other cores through the router.

[0010] The data transmission method of the on-chip network architecture is as follows: Each network has an input layer, a hidden layer, and an output layer; each layer of the network has one or more cores, and the cores are responsible for computing and routing the computed results. The data transmission direction is: off-chip - input layer core - router - hidden layer core - router - output layer core - router - off-chip. Configure the parameters of the data processing network in the registers of each selected core and router, including at least the router ID, core location, input core ID, and target core ID;

[0011] The method for the router to transmit data is as follows: Each router stores the configuration parameters of 5 cores connected to it. Build a data processing network according to the configuration parameters and simultaneously determine whether the router is enabled. If so, the core requests data transmission from the router. At the same time, the router matches its own ID with the router ID contained in the received data. If the match is successful, the current router is activated; otherwise, the router stops working. When the router is activated, it establishes a connection with the core that requests data transmission, caches the received data, and completes a handshake with the core. After the cache is full, it sends the data to the target core at once, and then clears the cache to prepare for the next round of transmission. If the input of the target core is full, it does not respond to the handshake and retains the data in the cache until the target core is idle.

[0012] The advantages of the present invention mainly include:

[0013] 1. A novel on-chip network architecture design method imitating the C 60 molecular plane structure is proposed.

[0014] 2. Compared with the traditional 2D on-chip network, the connectivity of the on-chip network architecture proposed by the present invention is increased by 25%, the longest path requires 3 router forwards, and the data transmission efficiency is increased by 25%.

[0015] 3. The multi-functional router module supports multiple routing modes, and the data transmission flexibility is strong; the router supports merging and forwarding the output computed results of 1 to 3 cores to another core, and also supports forwarding the output computed result of one core to other 1 to 3 cores; therefore, due to the efficient design of the router module, the present invention can support various network forms such as ordinary networks, merging networks, and forwarding networks. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 It is a system framework diagram of an on-chip network architecture design method imitating the C 60 molecular plane structure proposed by the present invention;

[0017] Figure 2 It is a diagram of the traditional 2D on-chip network architecture;

[0018] Figure 3 It is an on-chip network architecture imitating the C 60Routing internal parameter configuration diagram of the on-chip network architecture design method with a molecular plane structure;

[0019] Figure 4 A kind of C-like proposed by the present invention 60 Schematic diagram of the routing internal module of the on-chip network architecture design method with a molecular plane structure;

[0020] Figure 5 A kind of C-like proposed by the present invention 60 Routing and core data transfer timing diagram of the on-chip network architecture design method with a molecular plane structure;

[0021] Figure 6 A kind of C-like proposed by the present invention 60 Network function display diagram of the on-chip network architecture design method with a molecular plane structure;

[0022] Figure 7 A kind of C-like proposed by the present invention 60 Schematic diagram of the working process of the on-chip network architecture design method with a molecular plane structure;

[0023] Figure 8 A kind of C-like proposed by the present invention 60 Specific embodiment of the on-chip network architecture design method with a molecular plane structure; Detailed implementation mode

[0024] The present invention will be described in detail below with reference to the accompanying drawings and embodiments.

[0025] Figure 1 A kind of C-like proposed by the present invention 60 System framework diagram of the on-chip network architecture design method with a molecular plane structure. This on-chip network architecture consists of 12 routers and 20 cores in total. Each core and router has a unique ID to distinguish different cores and routers. Each core is connected to 3 routers, and each router is connected to 5 cores. They are connected into a whole in a C-like 60 Molecular plane structure. The cores are equivalent to the node layers of the neural network, and the routers represent the connections between different node layers. Cores cannot directly interact with each other in terms of data and need to transfer data through routers. When this 3D architecture is unfolded, the longest path is the path between the core at the center point and the core in the upper left corner, which requires the forwarding of 3 routers.

[0026] Figure 2It is a diagram of a traditional 2D on-chip network architecture. There is a router in each of the four directions (east, south, west, and north) of each core, which is responsible for receiving core data from other cores in different directions and transmitting the output data of its own core to the specified direction. The longest path is the path between the core at the center point and the core in the upper left corner, which requires the forwarding of 4 routers. Compared with the traditional 2D on-chip network architecture, the data transmission efficiency of the present invention is increased by 25%.

[0027] When calculating the connectivity of the traditional 2D on-chip network architecture, taking the TrueNorth architecture as an example, the four routers around it are combined and regarded as one. Each router is connected to one core and to other routers in 4 surrounding directions. Its connectivity = (number of cores * 1 + number of routers * 5) / (number of cores + number of routers). Since each core corresponds to one router, the number of cores is equal to the number of routers, and the connectivity is 3.0. The connectivity of the on-chip network architecture proposed by the present invention = (number of cores * 3 + number of routers * 5) / (number of cores + number of routers). The number of cores is 20 and the number of routers is 12. Substituting these values, the connectivity is 3.75. Compared with the traditional 2D on-chip network architecture, the connectivity is also increased by 25%, and the architecture is more stable.

[0028] Figure 3 It is a C-like one proposed by the present invention 60Routing internal parameter configuration diagram of the on-chip network architecture design method with a molecular plane structure. The configuration information of the five cores connected to the router will be stored in registers. The current core selects a router for data transmission. Define the current core as the source core. The source core obtains data from the outside or other cores. Define the core that provides the data as the input core of the source core. The calculation result of the source core is transmitted through the router to the outside of the chip or other cores for further processing. Define the core that performs further processing as the target core of the source core. Each core has 4 16-bit register parameters. Among them, the [4:0] bits of register 1_1 represent the ID of the current (source) core, the [6:5] bits represent the number of input cores of the current core. The input of the current core comes from the outside of the chip or other cores. The possible values are 2’b00\2’b01\2’b10\2’b11. 2’b00 means the input of the current core comes from the outside of the chip. The [8:7] bits represent the network position of the current core. 2’b01 represents the input layer, 2’b10 represents the output layer, 2’b11 represents the hidden layer, and 2’b00 is invalid. The upper 7 bits are reserved and not processed. The highest bit of register 1_2 is reserved. The [14:10] bits represent the ID of input core 1, the [9:5] bits represent the ID of input core 2, and the [4:0] bits represent the ID of input core 3. If the input of the current core comes from the outside of the chip, all the input core IDs are 0. The highest bit of register 1_3 is reserved. The [14:10] bits represent the ID of target core 1, the [9:5] bits represent the ID of target core 2, and the [4:0] bits represent the ID of target core 3. The [15:13] bits of register 1_4 are reserved. The [12:0] bits represent the number of neurons of the current core. Note that the number of neurons = register 1_4[12:0] + 1, that is, 13’h0000~13’h1fff represents the number of neurons 1~8192.

[0029] Figure 4 An imitation C proposed by the present invention 60Schematic diagram of the routing internal module of the on-chip network architecture design method with a molecular plane structure, including a controller module 1, a cache module 2, and a register module 3. Five cores connected to the router input the selected route ID to the current router. The controller module 1 determines whether to enable the current router by matching the current route ID information 4 with these input signals. If there is a match between the route ID selected by a core and the current route ID, the current router is enabled. If there is no match, the clock gating is turned off and the current router does not work. When the source core initiates a data transfer request, the controller module 1 temporarily stores the source core data 5 in the cache module 2 and completes the handshake. After the cache is full, the data 6 is sent to the next layer of the network, that is, the destination core, at one time, and then the cache is cleared to prepare for the next transfer; if the input of the destination core is full, the handshake is not responded to, and the data in the cache module 2 is retained until the destination core is idle. When it comes to the network merging function, since 2 to 3 different cores are simultaneously used as the input of another core, it is necessary to sort these 2 to 3 input cores with a fixed priority. Among them, the input core 1 has the highest priority, the priority decreases in turn, and the input core 3 has the lowest priority.

[0030] Figure 5 The timing diagram of data transfer between the router and the core shows the complete data transfer process from the source core to the destination core, including the timing 7 of the source core requesting data transfer to the router and the timing 8 of the router transferring data to the destination core. When the source core requests data transfer to the router in timing 7, it is necessary to complete the handshake protocol. The source core first raises the write request signal, and the router determines whether to raise the write response signal according to the status of the destination core. If the input of the destination core is not full, the write response signal is raised to complete the handshake and receive the single-bit data transmitted by the current core. Otherwise, the write response signal remains low, and the current core cannot complete the handshake and the calculation will stop. After 16 single-bit data are transmitted cumulatively, the cache is full, and the router raises the data valid signal as shown in timing 8, and at the same time transfers the multi-bit data to the destination core at one time. Since it is known before the data transfer that the input of the destination core is not full, there is no handshake in this data transfer process.

[0031] Figure 6 An imitation of C proposed by the present invention 60Network function display diagram of the on-chip network architecture design method for the molecular plane structure. The present invention supports deploying up to 4 neural networks simultaneously on this architecture, with a total of 20 cores, so there are 20 layers in total. The 4 networks need to reasonably allocate these 20 cores, and the sum of the network layers should be less than or equal to 20. The routing and cores are connected in the way of imitating the C60 molecular plane structure. Cores do not communicate directly with each other, and data needs to be forwarded by the routing. Each core supports up to 3 input cores and 3 target cores. Based on this, setting a reasonable network transmission path can achieve flexible and efficient inter-layer communication of neural networks. The ordinary network means that there is no association between the 4 networks and they can operate independently without being affected by the other networks; the merged network is realized by configuring multiple input cores, and the outputs of 2 to 3 networks are merged and forwarded to another network; the forwarding network is realized by configuring multiple target cores, and one network is forwarded to 1 to 3 other networks. There is no priority sorting in the forwarding network, and the network output results are forwarded to the other networks simultaneously.

[0032] As Figure 7 shown, it is a schematic diagram of the working process of the architecture of the present invention, and its working steps include:

[0033] Step 1, configure the registers. Each of the 5 cores connected to the routing has Figure 3 a set of parameters shown in, and write them into the corresponding registers. The routing will perform the next step according to these configuration information.

[0034] Step 2, determine whether the routing is enabled, turn off the clock of the unused routing, and enable the routing selected by the core.

[0035] Step 3, the core sends a data transmission request to the routing.

[0036] Step 4, the routing responds to the request, completes the handshake, and caches the data of the core. There is a cache for each core in the routing, which is used to temporarily store the transmission data of the core.

[0037] Step 5, determine whether to suspend the current core according to the status of the target core. When the input of the target core is full and cannot receive data anymore, suspend the current core, and the routing will no longer serve the current core. Due to the uncompleted handshake protocol, the current core will suspend calculation until the target core is idle. When the input of the target core is not full, the routing sends the calculation result of the current core to the target core for the next layer of calculation.

[0038] Embodiment

[0039] This example is based on the on-chip network architecture proposed by the present invention, and aims at the problems of low data transmission efficiency and inflexible transmission path in the electroencephalogram signal recognition system based on the spiking neural network algorithm, and proposes a specific solution. Specifically, an imitation C is built on the FPGA 60The on-chip network architecture of the molecular surface structure is deployed on it with a spiking neural network algorithm (SNN) to identify EEG signals. Specifically, the input EEG signal data is calculated through the core, and then efficiently forwarded to other cores or outside the chip through routing, and finally the external device is controlled to respond, including:

[0040] S1. Collect EEG signals. After preprocessing, the data is input into FPGA in the form of binary single-bit numbers. The input raw data is defined as 688+16 (2 channels) single-bit pulse inputs per group. There are 10 groups (i.e. 10 timesteps) in total, which are input into the core in sequence.

[0041] S2. Configuration register parameters, including core ID (20 cores in total), routing ID (12 routes in total), routing ID used by the core, the position of the core in the neural network (input layer, hidden layer or output layer), and the data transmission path of the core. The current core processes the input data and sends the calculation results to the target core. If the current core is in the input layer, the input comes from outside the architecture or another core (called the input core). If the current core is in the hidden layer or output layer, the input only comes from the input core. In addition, when the current core is in the output layer, if there is no target core, it means that the pulse neural network calculation is completed and the recognition result will be routed and output to the outside of the chip.

[0042] S3. Determine whether the current route is enabled based on register parameters. Each route is connected to five cores, and each core is connected to three routes. The core will select a route to serve it. The current route will be activated only when the route ID used by the core matches the ID of the current route. Routes that are not used by the core will be clock-gated to turn off the clock and stop working. This method can reduce system power consumption.

[0043] S4. After the current core completes the calculation, it initiates a data transmission request to the selected route. The route caches the data and completes the handshake. When the cache is full, the data is transmitted to the next layer of the network. If the data in the cache has not been taken away by the next layer, the handshake will not be responded to when the cache is full. Only after the handshake is completed can the current core start the next round of calculation. This method ensures that data will not be lost. In addition, when multiple cores need the service of the same route at the same time, the service order is determined according to the fixed priority.

[0044] S5. After the router accepts the data transmission request of the current core and caches the data, if the cache is full, it will send all the data in the cache to the next level, that is, the target core, at one time. If the input of the target core is full and cannot receive the data in the cache, the router will not initiate the transmission, but instead pause serving the current core until the target core is idle, and then send the calculation results in the cache to the target core. The process of data transmission to the target core does not require the use of a handshake protocol because the transmission is only initiated when the target core is idle.

[0045] S6. The network output is divided into 4 categories, representing 4 recognition results of "up, down, left, and right". After the output layer of the spiking neural network finishes the calculation, the output data is statistically analyzed, and the category with the largest value is taken as the final recognition result. The router transmits the recognition result to the outside of the chip, and the external device performs corresponding operations according to the classification result.

[0046] The specific implementation manner of this example is as Figure 8 shown, which shows the merged network mode of this architecture and reflects the characteristics of multi-function and flexible reconfiguration of this architecture.

[0047] This on-chip network architecture is finally implemented on the Xilinx xc7z035ffg676-2 FPGA. The electroencephalogram signals collected by the external device are divided into two channels, and the data output by the two channels are respectively used for inference calculation of the input networks 1 and 2, and finally merged and forwarded to network 3. In the figure, network 1 is a three-layer spiking neural network with a scale of "688*640*618*64". The first-layer core ID is 7, containing 640 neurons, and each neuron has 688 synapses; the second-layer core ID is 6, containing 618 neurons, and each neuron has 640 synapses; the third-layer core ID is 1, containing 64 neurons, and each neuron has 618 synapses; network 2 is a single-layer spiking neural network with a scale of "16*16", the core ID is 2, containing 16 neurons, and each neuron has 16 synapses; network 3 is a two-layer spiking neural network with a scale of "80*128*4". The first-layer core ID is 4, containing 128 neurons, and each neuron has 80 synapses; the second-layer core ID is 5, containing 4 neurons, and each neuron has 128 synapses; the input of network 3 comes from networks 1 and 2, that is, the input of core 4 (C4) comes from cores 1 and 2 (C1, C2).

[0048] When configuring the parameters, taking the input layer C7 of Network 1 and the input layer C4 of Network 3 as examples: The input of C7 comes from the outside, so there is no source core. The calculation result is only sent to one target core, C6, and the number of neurons is 640. Therefore, the register parameters corresponding to C7 are "16’h0087, 16’h0000, 16’h1800, 16’h027f". The input of C4 comes from 2 source cores, C1 and C2. The calculation result is sent to the target core C5, and the number of neurons is 128. Therefore, the register parameters corresponding to C4 are "16’h00c4, 16’h0440, 16’h1400, 16’h007f".

[0049] Taking the hidden layer C6 of Network 1 as an example: The input of C6 comes from C7, and the output is transmitted to C1. There are 618 neurons. Therefore, the register parameters corresponding to C6 are "16’h01a6, 16’h1c00, 16’h0400, 16’h025f". Similarly, for the output layer C5 of Network 3, since there is no target core, the network recognition result of C5 will be sent outside the chip. Its corresponding register parameters are "16’h0125, 16’h1000, 16’h0000, 16’h0003".

[0050] After configuring the parameters, enable routers 1 and 2 (R1, R2). The electroencephalogram signal channel 1 inputs to Network 1 in the form of data with 688 bits and 10 timesteps; channel 2 inputs to Network 2 in the form of data with 16 bits and 10 timesteps. The first-layer calculation is performed in C7 and C2. The calculation result of C7 (640 bits) is sent to C6 through R2, and the calculation result of C6 (618 bits) is sent to C1 through R2. When C7 and C6 both need the service of R2, they are arranged in the order of fixed priority. In this embodiment, the priority of C7 is higher than that of C6. Next, in Network 3, R1 sequentially sends the calculation result of C1 (64 bits) and the calculation result of C2 (16 bits) to C4. The priority of C1 is higher than that of C2. When R1 serves C1, C2 is suspended. Similarly, when R1 serves C2, C1 is suspended. Then C4 sends the calculation result (128 bits) to C5 through R1. As the output layer without a target core, C5 sends the final network calculation result (4 bits, 4 classifications) to the outside of the chip through R1. The external device counts the number of times each bit output of the output layer C5 is 1 in 10 timesteps, and then obtains the recognition result and makes corresponding operations to achieve human-computer interaction in this way.

[0051] The above description includes the necessary technical designs in the present invention. Those of ordinary skill in the art can build a network architecture based on the description and complete the deployment of the neural network, so other technical details will not be elaborated.

Claims

1. A Network-on-Chip architecture imitating the C 60 molecular plane structure It is characterized in that The on-chip network architecture is composed of 12 routers and 20 cores, and the routers and cores are connected as a whole in a way that imitates the C 60 molecular plane structure. Specifically, each core is connected to 3 routers, and each router is connected to 5 cores. Data interaction between cores is carried out through routers. The input data source of each core is off-chip or other cores, and the result after the core's own calculation is output to off-chip or other cores through the router; the data transmission mode of the on-chip network architecture is as follows: a network is formed by an input layer, a hidden layer, and an output layer; each layer of the network has one or more cores, and the cores are responsible for computing and routing the computed results. The data transmission direction is: off-chip - input layer core - router - hidden layer core - router - output layer core - router - off-chip; the parameters of the data processing network are configured in the registers of each selected core and router, including at least the router ID, core location, input core ID, and target core ID. The method for the router to transmit data is as follows: each router stores the configuration parameters of 5 cores connected to it, constructs a data processing network according to the configuration parameters, and simultaneously determines whether the router is enabled. If so, the core requests data transmission from the router. At the same time, the router matches its own ID with the router ID contained in the received data. If the match is successful, the current router is activated; otherwise, the router stops working. After the router is activated, it establishes a connection with the core that requests data transmission, caches the received data, and completes a handshake with the core. After the cache is full, the data is sent to the target core at one time, and then the cache is cleared to prepare for the next round of transmission. If the input of the target core is full, it does not respond to the handshake and retains the data in the cache until the target core is idle.

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