Three-dimensional phase change memory write circuit with temperature compensation and write operation method

Abstract

The application discloses a three-dimensional phase change memory write circuit with temperature compensation and a write operation method. In view of the influence of temperature on threshold voltage of a storage unit and on off-state current, temperature compensation is performed through word line power supply and bit line power supply respectively. When the influence of temperature on leakage current is compensated, the influence of off-state current on different positions of the storage unit is considered. Therefore, when the influence of temperature on off-state current is compensated, the storage unit is divided into a plurality of storage blocks according to positions, and output voltages are divided into a plurality of groups. Different output voltages correspond to different storage blocks, so that different degrees of temperature compensation are performed on the storage unit at different positions. According to the application, the temperature compensation of off-state current reduces the failure rate of write operation which increases with the increase of temperature; and the temperature compensation of threshold voltage reduces unnecessary power waste and the probability of error half-voltage opening during write operation caused by the increase of temperature.

Description

Technical Field

[0001] This invention belongs to the field of memory technology, and more specifically, relates to a three-dimensional phase-change memory write circuit and write operation method with temperature compensation function. Background Technology

[0002] To address the issues of small capacity of dynamic random access memory (DRAM) and high latency of NAND flash memory in computing systems, the industry has proposed phase-change random access memory (3D phase-change memory) with dual threshold switches as a solution to these problems.

[0003] However, due to the temperature-dependent off-state current (Ioff) and threshold voltage (Vth) of OTS, voltage write operations in phase-change random access memory (3D phase-change memory) with dual threshold switches are affected by temperature. Writing logic state "1" to a cell in the cross-point array involves applying a pulse with a fixed duration and an amplitude greater than Vts to the selected cell, thus crystallizing the PCM. Writing logic state "0" involves applying a pulse with a fixed duration and an amplitude greater than Vtr to the selected cell in the cross-point array, thus amorphizing the PCM. As temperature increases, the off-state current of the OTS increases exponentially, causing the leakage current flowing through the word and bit lines in the array to change with temperature. The voltage drop (Vdrop) on the word and bit lines also changes with temperature, resulting in a decrease in the effective voltage applied to the selected memory cell as the Vdrop increases due to the Ioff of other unselected cells. Failure to address this temperature-dependent voltage drop could increase the failure rate of voltage write operations. Increased temperature will also cause the threshold voltage to decrease almost linearly. Similarly, failing to address the effect of temperature variations on the threshold voltage could lead to unnecessary power consumption waste and incorrect half-voltage turn-on during voltage write operations. Therefore, in summary, temperature compensation is required for voltage write operations in three-dimensional phase-change memory. Summary of the Invention

[0004] In view of the above-mentioned defects or improvement needs of the prior art, the present invention provides a three-dimensional phase change memory write circuit and write operation method with temperature compensation function. Its purpose is to perform temperature compensation on the voltage write operation of the three-dimensional phase change memory and reduce the impact of temperature change on the write operation.

[0005] To achieve the above objectives, according to one aspect of the present invention, a three-dimensional phase-change memory (PCM) write circuit with temperature compensation is provided. The PCM has arrayed memory cells, each located at (WLx, Bly), where x is the word line position and y is the bit line position. All memory cells are divided into N memory blocks. The (x+y) value of each memory cell in different blocks lies in different intervals, while the (x+y) value of each memory cell in the same block lies in the same interval. The write circuit includes a word line power supply circuit and a bit line power supply circuit.

[0006] The output voltage V of the word line power supply circuit WL_in The voltage variation coefficient with temperature is γ, which is the same as the voltage variation coefficient of the threshold voltage of the memory cell with temperature, and is used to provide word line voltage to the selected memory cell.

[0007] The output branch of the bit-line power supply circuit has N voltage divider resistors connected in series. An output terminal is drawn from each voltage divider resistor to obtain N output terminals. The i-th output terminal is the output terminal drawn from the i-th voltage divider resistor Ri, and the corresponding i-th output voltage is... Among them, the output voltage V BL_ini The voltage variation coefficient with temperature is δi, and it is the opposite of the voltage variation coefficient with temperature of the bit line receiving voltage of the i-th memory block. The resistance values ​​of the voltage divider resistors satisfy... The i-th output voltage is V BL_ini Used to provide bit line voltage to the candidate memory cell in the i-th memory block.

[0008] In one embodiment, the word line power supply circuit includes a threshold voltage temperature compensation circuit and a word line voltage output terminal, wherein the word line voltage output terminal includes an operational amplifier OP1, a voltage source Vdc1, an operational amplifier OP2, a PMOS transistor M1, an NMOS transistor M2, and a resistor R;

[0009] The output voltage V of the temperature compensation circuit for the threshold voltage WL_BG1 It has a voltage variation coefficient γ;

[0010] The voltage source Vdc1 and the output voltage V WL_BH The superimposed input is fed into the inverting input terminal of operational amplifier OP1. The non-inverting input terminal of operational amplifier OP1 is connected to the drain of PMOS transistor M1 to form the first terminal. The output terminal of operational amplifier OP1 is connected to the gate of PMOS transistor M1. The source of PMOS transistor M1 is used to connect to an external positive voltage source.

[0011] The inverting input of the operational amplifier OP2 is connected to the original word line voltage V. WLThe non-inverting input terminal is connected to the drain of NMOS transistor M2 to form the second terminal, the output terminal of operational amplifier OP2 is connected to the gate of NMOS transistor M2, and the source of NMOS transistor M2 is grounded;

[0012] The two ends of resistor R are connected to the first end and the second end respectively, and the output voltage of the word line power supply circuit is led out from the first end.

[0013] In one embodiment, the word line power supply circuit further includes an array word line input, which includes an operational amplifier OP3, a PMOS transistor M3, and a capacitor C1.

[0014] The inverting input terminal of the operational amplifier OP3 is connected to the first terminal of the word line voltage output to obtain the voltage V. WL_BG1 The non-inverting input terminal is connected to the drain of PMOS transistor M3 to form the third terminal, which is grounded through capacitor C1. The output terminal of operational amplifier OP3 is connected to the gate of PMOS transistor M3, and the source of PMOS transistor M3 is connected to an external voltage source. The voltage output from the third terminal is used as the output voltage V of the word line power supply circuit. WL_in Connect the selected character line.

[0015] In one embodiment, the bit line power supply circuit includes a temperature compensation circuit for off-state current and a bit line voltage output terminal, wherein the bit line voltage output terminal includes a voltage source Vdc2, an operational amplifier OP4, an operational amplifier OP5, a PMOS transistor M4, an NMOS transistor M5, and N voltage divider resistors R1 to RN.

[0016] The output voltage V of the temperature compensation circuit for the off-state current BL_BG It has a voltage variation coefficient δ1;

[0017] The inverting input terminal of the operational amplifier OP4 is connected to the original bit line voltage V. BL The positive input terminal is connected to the drain of PMOS transistor M4 to form the fourth terminal, and the source of PMOS transistor M4 is used to connect to an external negative voltage source.

[0018] The voltage source Vdc2 and the output voltage V BL_BG The superimposed input is fed into the inverting input terminal of the operational amplifier OP5. The non-inverting input terminal of OP5 is connected to the drain of NMOS transistor M5 to form the fifth terminal. The output terminal of operational amplifier OP5 is connected to the gate of NMOS transistor M5, and the source of NMOS transistor M5 is grounded.

[0019] N voltage divider resistors are connected in series between the fourth and fifth terminals, and resistors R1 to RN are connected sequentially from the fifth terminal to the fourth terminal. The first output terminal is drawn from the fifth terminal, and the i-th output terminal is drawn from between resistors R(i-1) and Ri.

[0020] In one embodiment, the bit line power supply circuit further includes an array bit line input, which includes an operational amplifier OP6, an NMOS transistor M6, and a capacitor C2.

[0021] The non-inverting input terminal of the operational amplifier OP6 is connected to the i-th output terminal of the bit line voltage output circuit. The inverting input terminal is connected to the drain of the NMOS transistor M6 to form the sixth terminal. The sixth terminal is grounded to the operational amplifier through capacitor C2. The output terminal of OP6 is connected to the gate of the NMOS transistor M6, and the source of the NMOS transistor M6 is connected to an external negative voltage source. The voltage output from the sixth terminal is used as the i-th output voltage V of the bit line power supply circuit. BL_ini .

[0022] In one embodiment, a selection circuit is further included, which, when receiving a signal to select any bit line in the i-th memory block, connects the i-th output terminal of the bit line voltage output pole and the array bit line input pole to provide the i-th output voltage V to the corresponding bit line. BL_ini .

[0023] In one embodiment, the temperature compensation circuit for the threshold voltage or the temperature compensation circuit for the off-state current includes: NMOS transistors M11 to M12, PMOS transistors M13 to M15, transistors Q1 to Q(M-2), and resistors R11 to R12.

[0024] The sources of PMOS transistors M13 to M15 are all connected to an external voltage source, and their gates are all interconnected.

[0025] The drain of PMOS transistor M13 is connected to the drain of NMOS transistor M11. The source and gate of NMOS transistor M11 are connected. The source of NMOS transistor M11 is connected to the emitter of transistor Q1. The base and collector of transistor Q1 are connected and grounded.

[0026] The gate and drain of PMOS transistor M14 are connected, the drain of PMOS transistor M14 is connected to the drain of NMOS transistor M12, the gate of NMOS transistor M12 is connected to the gate of NMOS transistor M11, the source of NMOS transistor M12 is connected to the emitter of transistor Q2 through resistor R11, and the base and collector of transistor Q2 are connected and grounded.

[0027] The drain of PMOS transistor M15 is connected to the emitter of transistor Q3 through resistor R12. Transistors Q3 to Q(M-2) are connected in sequence, and the base and collector of each transistor are connected. The collector of transistor Q(M-2) is grounded.

[0028] The voltage at the drain terminal of PMOS transistor M15 is used as the output voltage of the temperature compensation circuit.

[0029] In the temperature compensation circuit for the threshold voltage, the ratio of the emitter areas of transistors Q2 and Q1, and the value of M, satisfy the condition that the output voltage V of the temperature compensation circuit for the threshold voltage is... WL_BH It has a voltage variation coefficient γ;

[0030] In the temperature compensation circuit for off-state current, the ratio of the emitter areas of transistors Q2 and Q1, and the value of M, satisfy the condition that the output voltage V of the temperature compensation circuit for off-state current is... WL_BG It has a voltage variation coefficient δ1.

[0031] According to the second aspect of this invention, a write operation method for a three-dimensional phase-change memory with temperature compensation is provided. All memory cells are divided into N memory blocks according to their location. The (x+y) value of each memory cell in different memory blocks is in different intervals, and the (x+y) value of each memory cell in the same memory block is in the same interval. The write operation method is based on the aforementioned three-dimensional phase-change memory write circuit with temperature compensation, and includes:

[0032] Determine the memory block where the selected memory cell is located. When the selected memory cell is in the i-th memory block, connect the word line power supply circuit to the word line corresponding to the selected memory cell, and connect the i-th output voltage in the bit line power supply circuit to the bit line corresponding to the selected memory cell, so as to select the memory cell and write data.

[0033] According to a third aspect of the present invention, a three-dimensional phase-change memory (PCM) write circuit with temperature compensation is provided. The PCM has arrayed memory cells, each located at (WLx, BLy), where x is the word line position and y is the bit line position. All memory cells are divided into N memory blocks. The (x+y) value of each memory cell in different blocks is in different intervals, and the (x+y) value of each memory cell in the same block is in the same interval. The write circuit includes a word line power supply circuit and a bit line power supply circuit.

[0034] The output voltage V of the bit line power supply circuit BL_in The voltage change coefficient with temperature is γ, which is the opposite of the voltage change coefficient of the threshold voltage of the memory cell with temperature.

[0035] The output branch of the word line power supply circuit has N voltage divider resistors connected in series. An output terminal is drawn from each voltage divider resistor to obtain N output terminals. The i-th output terminal is the output terminal drawn from the i-th voltage divider resistor Ri, and the corresponding i-th output voltage is... Among them, the output voltage V WL_inThe voltage variation coefficient with temperature is δi, and it is the opposite of the voltage variation coefficient of the word line received voltage of the i-th memory block with temperature. The resistance values ​​of the voltage divider resistors satisfy... The i-th output voltage is V WL_ini Used to provide word line voltage to the candidate memory cell in the i-th memory block.

[0036] According to a fourth aspect of the present invention, a write operation method for a three-dimensional phase-change memory with temperature compensation is provided. All memory cells are divided into N memory blocks according to their location. The (x+y) value of each memory cell in different memory blocks is in different intervals, and the (x+y) value of each memory cell in the same memory block is in the same interval. The write operation method is based on the aforementioned three-dimensional phase-change memory write circuit with temperature compensation, and includes:

[0037] Determine the memory block where the selected memory cell is located. When the selected memory cell is in the i-th memory block, connect the bit line power supply circuit to the bit line corresponding to the selected memory cell, and connect the i-th output voltage in the word line power supply circuit to the word line corresponding to the selected memory cell, so as to select the memory cell and write the data.

[0038] In summary, compared with the prior art, the above-described technical solutions conceived by this invention can achieve the following beneficial effects:

[0039] (1) This invention addresses the effects of temperature on the threshold voltage of memory cells and the off-state current Ioff by simultaneously compensating for temperature through both word line power supply and bit line power supply. The word line power supply compensates for one type of temperature effect, while the bit line power supply compensates for the other. One approach of this invention is to select word line power supply to compensate for the effect of temperature on the threshold voltage and select bit line power supply to compensate for the effect of temperature on the off-state current Ioff. Another approach is to select bit line power supply to compensate for the effect of temperature on the threshold voltage and select word line power supply to compensate for the effect of temperature on the off-state current Ioff. Temperature compensation for the off-state current Ioff reduces the write operation failure rate, which increases with temperature. Temperature compensation for the threshold voltage Vth reduces unnecessary power consumption waste and the probability of erroneous half-voltage enable during write operations caused by temperature increases.

[0040] (2) When compensating for the effect of temperature on leakage current, considering that the position of the storage cell in the array is different and the off-state current Ioff is different at the same temperature, the storage cell is divided into multiple storage blocks according to its position when compensating for the effect of temperature on the off-state current Ioff. The storage cells in each storage block are located in the same range, and the output voltage is divided into multiple groups. Different output voltages correspond to different storage blocks, thereby performing different degrees of temperature compensation for storage cells in different positions.

[0041] (3) To compensate for the effect of temperature on leakage current, the output voltage is divided into multiple voltages using voltage divider resistors. Each output voltage corresponds to a voltage variation coefficient that changes with temperature. By setting the voltage divider resistors, the resistance values ​​of the voltage divider resistors are made to meet the following requirements. The same circuit can be used to simultaneously output N voltages with different coefficients of change in the output branch to compensate for the influence of the off-state current Ioff at different locations. Attached Figure Description

[0042] Figure 1 A circuit block diagram of a first type of three-dimensional phase-change memory write circuit with temperature compensation function according to an embodiment;

[0043] Figure 2 The circuit diagram for the first type of word line voltage output pole;

[0044] Figure 3 This is a circuit diagram of the array word line input poles according to one embodiment;

[0045] Figure 4 A circuit diagram of a word line power supply circuit according to one embodiment;

[0046] Figure 5 The circuit diagram for the first type of bit line voltage output pole;

[0047] Figure 6 This is a circuit diagram of the array bit line input poles according to one embodiment;

[0048] Figure 7 A circuit diagram of a bit line power supply circuit according to one embodiment;

[0049] Figure 8 A circuit diagram of a temperature compensation circuit according to one embodiment;

[0050] Figure 9 A circuit block diagram of a second type of three-dimensional phase-change memory write circuit with temperature compensation function according to an embodiment;

[0051] Figure 10 The circuit diagram for the second type of word line voltage output pole;

[0052] Figure 11 The circuit diagram for the second type of bit line voltage output pole;

[0053] Figure 12 The following are simulation results of the threshold voltage at 25-85℃ for one embodiment, wherein (a) to (c) are It curves of different effective voltages at 25℃, (d) to (f) are It curves of different effective voltages at 45℃, (g) to (i) are It curves of different effective voltages at 65℃, and (g) to (l) are It curves of different effective voltages at 85℃.

[0054] Figure 13 The simulation results are for the selected cell current of a 4*4 three-dimensional phase change memory array with temperature compensation for the threshold voltage Vth added at 25-85℃. Among them, (a) to (d) correspond to the simulation results at 25℃, 45℃, 65℃ and 85℃, respectively.

[0055] Figure 14 The current simulation results of the selected cell of a 4*4 three-dimensional phase change memory array without temperature compensation for the threshold voltage Vth at 25℃ and a vdd amplitude of 0.6V are shown.

[0056] Figures 15(a) to 15(d) The simulation results are as follows: high voltage of selected cell in a 129*128 three-dimensional phase change memory array without temperature compensation for off-state current Ioff at 25℃, 45℃, 65℃ and 85℃ respectively.

[0057] Figure 16 The simulation results of the high voltage terminal voltage of the selected cell of a 129*128 three-dimensional phase change memory array with temperature compensation for the off-state current Ioff are shown in (a) to (c), which correspond to the simulation results at 45℃, 65℃ and 85℃ respectively. Detailed Implementation

[0058] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention. Furthermore, the technical features involved in the various embodiments of this invention described below can be combined with each other as long as they do not conflict with each other.

[0059] To facilitate understanding of this invention, the three-dimensional phase-change memory and its write operation are first described. The memory cells in the three-dimensional memory are arranged in an array, with word lines and bit lines interleaved so that each memory cell can be selected via both word lines and bit lines. The location of a memory cell is defined as WLxBLy, where x represents the word line position of the selected memory cell, and y represents the bit line position of the selected memory cell. When a write operation is required on a memory cell located at WLxBLy, a word line voltage V needs to be applied to the x-th word line. WL Apply bit line voltage V to the y-th bit line BL Select the memory cell located at WLxBLy and apply an effective voltage V to it. eff Through effective voltage V eff Controlling the state of the storage unit to achieve data writing, when the effective voltage V effThe memory cell is turned on when its threshold voltage is exceeded; otherwise, it cannot be turned on. The word line voltage and bit line voltage provide effective voltage to the selected memory cell. However, as the word line and bit line voltages are transferred from the input to the memory cell, leakage current causes a voltage drop of V. drop(Ioff) and the voltage drop V caused by the turn-on current drop(Ion) Therefore, the effective voltage V eff =V WL -V BL -V drop(Ioff) -V drop(Ion) Typically, the word line voltage is a positive voltage, while the bit line voltage is a negative voltage with the opposite amplitude. The voltage drop V due to leakage current can be approximately calculated using a formula. drop(Ioff) =(x*(x-1)+y*(y-1))*I off *R / 2. Where x is the word line position of the selected memory cell, and y is the bit line position of the selected memory cell. For example, for a memory cell located at WL10BL12, x = 10, y = 12. The larger the sum of x and y, the farther away the selected memory cell is, and the corresponding voltage drop V... drop(Ioff) The larger the leakage current I, the greater it will be. At the same time, the leakage current I varies with different temperatures. off These differences ultimately lead to variations in effective voltage depending on temperature and the location of the storage cell.

[0060] Based on this, the present invention proposes a three-dimensional phase change memory write circuit and write operation method with temperature compensation function.

[0061] like Figure 1 The diagram shown is a block diagram of a temperature-compensated three-dimensional phase-change memory write circuit in one embodiment, which includes a temperature-compensated word line power supply circuit and a temperature-compensated bit line power supply circuit.

[0062] Among them, the output voltage V of the word line power supply circuit WL_in It changes with temperature, and the coefficient of voltage change with temperature is γ. The voltage variation coefficient γ′ of the threshold voltage of the memory cell with temperature is the same. Therefore, when designing the word line power supply circuit, it is necessary to obtain the voltage variation coefficient γ′ of the threshold voltage with temperature in advance, which can be obtained through simulation. Different testing tools and methods may yield different voltage variation coefficients γ′, resulting in some error compared to the actual coefficient, but overall, it will approach the actual coefficient. Therefore, when designing the word line power supply circuit, its voltage variation coefficient γ can be made the same as the measured threshold voltage variation coefficient to make it approach the actual threshold voltage variation coefficient, although some error is acceptable to achieve temperature compensation. For example, when the threshold voltage variation coefficient γ′ = 1, the voltage variation coefficient γ of the word line power supply circuit can be set to 1.1, 1.0, 0.9, 0.8, etc., as long as the compensation within a certain range can offset all or part of the fluctuations and reduce the influence of temperature. For example, when the threshold voltage decreases by 10mV with temperature, since the voltage variation coefficient of the word line power supply circuit's output voltage with temperature is the same as that of the threshold voltage, the word line voltage also decreases by approximately 10mV. Based on the effective voltage V... eff =V WL -V BL -V drop(Ioff) -V drop(Ion) Without considering other changes, the effective voltage also decreases by about 10mV, which is basically synchronized with the change in the threshold voltage. This can reduce unnecessary power consumption waste during write operations caused by temperature changes and the probability of incorrect half-voltage turn-on.

[0063] In the design of the bitline power supply circuit, considering that the off-state current Ioff varies depending on the location of the memory cell in the array, and the voltage drop caused by leakage current also varies, the effective voltage received by the memory cell at different locations will differ even with the same bitline input. Therefore, as needed, the array can be divided into N location regions, and the memory array can be divided into N memory blocks according to the location intervals, with each memory block corresponding to a location interval. For example, if x+y belongs to [0, A1], then the memory cell belongs to block 1; if x+y belongs to [A1, A2], then the memory cell belongs to block 2; and if x+y belongs to [An-1, An], then the memory cell belongs to block n. If the array size is B1*B2, then An = B1 + B2. For each memory block, the voltage variation coefficient δi′ of the bitline received voltage with temperature is obtained through simulation. This bitline received voltage is the actual voltage transmitted to the current memory cell, and it is the actual received voltage after considering the influence of bitline leakage current.

[0064] Based on this, the output branch of the bit-line power supply circuit designed in this invention has N voltage divider resistors connected in series. An output terminal is drawn from each voltage divider resistor to obtain N output terminals. The i-th output terminal is the output terminal drawn from the i-th voltage divider resistor Ri, and the corresponding i-th output voltage is... Among them, the output voltage V BL_ini The voltage variation coefficient with temperature is δi, and it is the opposite of the voltage variation coefficient with temperature of the bit line receiving voltage of the i-th memory block. The resistance values ​​of the voltage divider resistors satisfy... The i-th output voltage is V BL_ini This is used to provide bit line voltage to the candidate memory cell in the i-th memory block. According to the formula for calculating the effective voltage, when the bit line receiving voltage decreases due to temperature, the output voltage of the bit line power supply circuit can be increased; conversely, when the bit line receiving voltage increases due to temperature, the output voltage of the bit line power supply circuit can be decreased to offset the temperature effect and maintain a stable effective voltage. Therefore, the output voltage V... BL_ini The voltage variation coefficient δi with temperature is the same as the negative of the voltage variation coefficient of the bit line receiving voltage of the i-th memory block with temperature. Moreover, in this circuit, only the output voltage variation coefficient δ1 of the first output terminal needs to be adjusted by the front-end circuit. The variation coefficients of other output terminals can be achieved by adjusting the resistance value of the voltage divider. The circuit structure is simple and controllable.

[0065] In one embodiment, such as Figure 2 As shown, the word line power supply circuit includes a threshold voltage temperature compensation circuit and a word line voltage output terminal. The word line voltage output terminal includes operational amplifier OP1, voltage source Vdc1, operational amplifier OP2, PMOS transistor M1, NMOS transistor M2, and resistor R. The output voltage V of the threshold voltage temperature compensation circuit is... WL_BG It has a voltage variation coefficient γ. The voltage source Vdc1 and the output voltage V... WL_BH The superimposed input is connected to the inverting input of op-amp OP1. The non-inverting input of op-amp OP1 is connected to the drain of PMOS transistor M1 to form the first terminal. The output of op-amp OP1 is connected to the gate of PMOS transistor M1. The source of PMOS transistor M1 is used to connect to an external positive voltage source. The inverting input of op-amp OP2 is connected to the original word line voltage V. WL The non-inverting input terminal is connected to the drain of NMOS transistor M2 to form the second terminal. The output terminal of operational amplifier OP2 is connected to the gate of NMOS transistor M2, and the source of NMOS transistor M2 is grounded. The two ends of resistor R are connected to the first and second terminals respectively, and the output voltage of the word line power supply circuit is drawn from the first terminal. The original word line voltage V is connected to the inverting input terminal of operational amplifier OP2. WLThis represents the word line voltage under normal conditions without considering temperature compensation. While the voltage variation coefficient of the temperature compensation circuit for the threshold voltage meets design requirements, its output amplitude may deviate from the original word line voltage V. WL By setting the voltage source Vdc1, the amplitude of the output voltage can be adjusted so that the output voltage amplitude at room temperature is similar to the original word line voltage V. WL Equal. In this circuit, at room temperature, by adjusting the voltage source Vdc1 and detecting the current in resistor R, when the current in resistor R is 0, it indicates that the output voltage amplitude has been adjusted to match the original word line voltage V. WL Equal. Moreover, since the output voltage may change if the resistance of the memory cell changes when power is supplied to the memory cell, this embodiment can also ensure that the output voltage is not affected by the subsequent circuitry by setting the word line voltage output pole.

[0066] Furthermore, such as Figure 3 and Figure 4 As shown, the word line power supply circuit further includes an array word line input terminal, which includes an operational amplifier OP3, a PMOS transistor M3, and a capacitor C1; the inverting input terminal of the operational amplifier OP3 is connected to the first terminal of the word line voltage output terminal to obtain the voltage V. WL_BG1 The non-inverting input terminal is connected to the drain of PMOS transistor M3 to form the third terminal, which is grounded through capacitor C1. The output terminal of operational amplifier OP3 is connected to the gate of PMOS transistor M3, and the source of PMOS transistor M3 is connected to an external positive voltage source. The voltage output from the third terminal is used as the output voltage V of the word line power supply circuit. WL_in Connect the selected word line. Since changes in the memory cell current can affect the operational amplifier's state, this embodiment ensures that the output voltage is unaffected by changes in the memory cell current by setting the input terminals of the array word lines.

[0067] In one embodiment, such as Figure 5 As shown, the bit line power supply circuit includes a temperature compensation circuit for off-state current and a bit line voltage output terminal. The bit line voltage output terminal includes a voltage source Vdc2, operational amplifier OP4, operational amplifier OP5, PMOS transistor M4, NMOS transistor M5, and N voltage divider resistors R1 to RN. The output voltage V of the temperature compensation circuit for off-state current is... BL_BG It has a voltage variation coefficient δ1. The inverting input terminal of the operational amplifier OP4 is connected to the original bit line voltage V. BL The positive input terminal is connected to the drain of PMOS transistor M4 to form the fourth terminal, and the source of PMOS transistor M4 is used to connect an external negative voltage source. The voltage source Vdc2 is connected to the output voltage V. BL_BGThe superimposed input is connected to the inverting input of the operational amplifier OP5. The non-inverting input of OP5 is connected to the drain of NMOS transistor M5 to form the fifth terminal. The output of operational amplifier OP5 is connected to the gate of NMOS transistor M5, and the source of NMOS transistor M5 is grounded. N voltage divider resistors are connected in series between the fourth and fifth terminals, and resistors R1 to RN are connected sequentially from the fifth terminal to the fourth terminal. The first output terminal is led out from the fifth terminal, and the i-th output terminal is led out from between resistor R(i-1) and Ri. Similar to the function of the word line voltage output, the bit line voltage output can both adjust the amplitude of the output voltage and ensure that the output voltage is not affected by the subsequent array.

[0068] Furthermore, such as Figure 6 and Figure 7 As shown, the bit line power supply circuit further includes an array bit line input terminal, which includes an operational amplifier OP6, an NMOS transistor M6, and a capacitor C2. The non-inverting input terminal of the operational amplifier OP6 is connected to the i-th output terminal of the bit line voltage output terminal, and the inverting input terminal is connected to the drain of the NMOS transistor M6 to form the sixth terminal. The sixth terminal is grounded through the capacitor C2. The output terminal of the operational amplifier OP6 is connected to the gate of the NMOS transistor M6, and the source of the NMOS transistor M6 is connected to an external negative voltage source. The voltage output from the sixth terminal is used as the i-th output voltage V of the bit line power supply circuit. BL_ini Similar to the array word line input, this array bit line input ensures that the output voltage is unaffected by changes in the memory cell current.

[0069] In one specific embodiment, a selection circuit is further included. This selection circuit, when receiving a signal to select any bit line in the i-th memory block, connects the i-th output terminal of the bit line voltage output pole and the array bit line input pole to provide the i-th output voltage V to the corresponding bit line. BL_ini .like Figure 7 As shown, when the candidate memory cell is located in the first memory block, the first output terminal of the bit line voltage output is connected to the column bit line input, and the bit line voltage is provided to the bit line of the candidate memory cell through the column bit line input. The operation of other memory blocks is the same as that of the first memory block.

[0070] In one embodiment, the temperature compensation circuit for the threshold voltage and the temperature compensation circuit for the off-state current can use temperature compensation circuits with the same structural framework. The parameters of the relevant components in the temperature compensation circuit are adjusted to respectively satisfy the temperature compensation requirements for the threshold voltage and the off-state current. For example... Figure 8As shown, the temperature compensation circuit includes NMOS transistors M11-M12, PMOS transistors M13-M15, transistors Q1-Q(M-2), and resistors R11-R12. The sources of PMOS transistors M13-M15 are all connected to an external voltage source, and their gates are all interconnected. The drain of PMOS transistor M13 is connected to the drain of NMOS transistor M11. The source and gate of NMOS transistor M11 are connected, and the source of NMOS transistor M11 is connected to the emitter of transistor Q1. The base and collector of transistor Q1 are connected and grounded. The gate and drain of PMOS transistor M14 are connected, and the drain of PMOS transistor M14 is connected to the drain of NMOS transistor M12. The gate of NMOS transistor M12... The gate of NMOS transistor M11 is connected to the gate of transistor M12. The source of NMOS transistor M12 is connected to the emitter of transistor Q2 through resistor R11. The base and collector of transistor Q2 are connected and grounded. The drain of PMOS transistor M15 is connected to the emitter of transistor Q3 through resistor R12. Transistors Q3 to Q(M-2) are connected in sequence, with the base and collector of each transistor connected. The collector of transistor Q(M-2) is grounded. The voltage at the drain of PMOS transistor M15 is used as the output voltage of the temperature compensation circuit. The output voltage of this temperature compensation circuit can be expressed as V = a1*VT + a2*VD, where VT is the thermal voltage and VD is the turn-on voltage of the diode. The voltage variation coefficient of the output voltage with temperature can be approximately expressed as a1*(85uV / K) - a2*(1.6mV / K), where a1 = (R2 / R1)*ln(N), N is the ratio of the emitter areas of Q2 and Q1, and a2 = M, where M is the number of diodes formed by the transistors in the branch containing R2. This formula can guide the adjustment of circuit parameters to obtain a specific voltage variation coefficient and output voltage. In the temperature compensation circuit for the threshold voltage, the ratio of the emitter areas of transistors Q2 and Q1 and the value of M satisfy the condition that the output voltage V of the temperature compensation circuit for the threshold voltage is... WL_BH It has a voltage variation coefficient γ. In the temperature compensation circuit for off-state current, the ratio of the emitter areas of transistors Q2 and Q1 and the value of M satisfy the condition that the output voltage V of the temperature compensation circuit for off-state current is... WL_BG It has a voltage variation coefficient δ1.

[0071] Accordingly, the present invention also relates to a write operation method based on the above-mentioned three-dimensional phase-change memory write circuit with temperature compensation function. Before performing the specific write operation, all memory cells are divided into N memory blocks according to their positions based on the actual situation. The (x+y) value of each memory cell in different memory blocks is in different intervals, and the (x+y) value of each memory cell in the same memory block is in the same interval. Then, the write operation is performed, specifically: the memory block where the selected memory cell is located is determined. When the selected memory cell is in the i-th memory block, the word line power supply circuit is connected to the word line corresponding to the selected memory cell, and the i-th output voltage in the bit line power supply circuit is connected to the bit line corresponding to the selected memory cell to select the memory cell and write the data.

[0072] Accordingly, this invention also proposes another three-dimensional phase-change memory write circuit with temperature compensation. The main difference between this circuit and the first one described above is that it utilizes the bit line power supply circuit to compensate for the temperature effect of the threshold voltage, and the word line power supply circuit to compensate for the temperature effect of the off-state current Ioff. In this case, the effective voltage is calculated using the formula V... eff =V WL -V BL -V drop(Ioff) -V drop(Ion) When the threshold voltage decreases with increasing temperature, the output voltage of the bit line power supply circuit needs to increase with increasing temperature to reduce the final effective voltage and follow the change in threshold voltage. Therefore, the voltage change coefficient of the bit line power supply circuit's output voltage with temperature needs to be the opposite of the voltage change coefficient of the memory cell's threshold voltage with temperature. When the word line receiving voltage decreases with temperature, leading to a decrease in effective voltage, the output voltage of the word line power supply circuit needs to increase with temperature. Conversely, when the word line receiving voltage decreases with increasing temperature, leading to an increase in effective voltage, the output voltage of the word line power supply circuit needs to decrease with temperature. Therefore, the voltage change coefficient of the word line power supply circuit's output voltage with temperature needs to be the opposite of the voltage change coefficient of the i-th memory block's word line receiving voltage with temperature. Based on this, another three-dimensional phase-change memory write circuit with temperature compensation includes a word line power supply circuit and a bit line power supply circuit, wherein...

[0073] The output voltage V of the bit line power supply circuit BL_in The voltage change coefficient with temperature is γ, which is the opposite of the voltage change coefficient of the threshold voltage of the memory cell with temperature.

[0074] The output branch of the word line power supply circuit has N voltage divider resistors connected in series. An output terminal is drawn from each voltage divider resistor to obtain N output terminals. The i-th output terminal is the output terminal drawn from the i-th voltage divider resistor Ri, and the corresponding i-th output voltage is... Among them, the output voltage V WL_in The voltage variation coefficient with temperature is δi, and it is the opposite of the voltage variation coefficient of the word line received voltage of the i-th memory block with temperature. The resistance values ​​of the voltage divider resistors satisfy... The i-th output voltage is V WL_ini This circuit is used to provide word line voltage to the selected memory cells in the i-th memory block. For specific circuit design details, please refer to the design of the first type of circuit, for example... Figure 9 As shown, the word line power supply circuit here also includes a temperature compensation circuit for the state current, a word line voltage output, and an array word line input. The bit line power supply circuit also includes a temperature compensation circuit for the threshold voltage, a bit line voltage output, and an array bit line input. Figure 10 As shown, the difference between the word line voltage output terminal in this scheme and the first scheme is that N voltage divider resistors are connected in series between the first and second terminals, and an output terminal is drawn from each voltage divider resistor. Figure 11 As shown, the difference between the bit line voltage output pole in this scheme and the bit line voltage output pole in the first scheme is that a resistor R is connected in series between the fourth and fifth terminals, and an output terminal is brought out.

[0075] Correspondingly, based on the second type of three-dimensional phase-change memory write circuit with temperature compensation, a write operation method is also proposed. Similar to the above, before performing the write operation, all memory cells are first divided into N memory blocks according to their positions. The (x+y) value of each memory cell in different memory blocks is in different intervals, while the (x+y) value of each memory cell in the same memory block is in the same interval. Then, the write operation is performed, specifically: determining the memory block where the selected memory cell is located. When the selected memory cell is in the i-th memory block, the bit line power supply circuit is connected to the bit line corresponding to the selected memory cell, and the i-th output voltage in the word line power supply circuit is connected to the word line corresponding to the selected memory cell, thus selecting the memory cell and writing the data.

[0076] By using the above-described three-dimensional phase-change memory write circuit and write operation method with temperature compensation, the failure rate of write operations, which increases with temperature, can be reduced by temperature compensation of the off-state current Ioff; and the temperature compensation of the threshold voltage Vth can reduce unnecessary power consumption waste and the probability of incorrect half-voltage turn-on during write operations caused by temperature rise.

[0077] The following detailed description is provided in conjunction with specific embodiments.

[0078] Example 1:

[0079] Temperature compensation for the threshold voltage Vth of a 4x4 three-dimensional phase-change memory array is performed. This simulation uses the simulation library file of the SMIC 0.18 process. The voltage write operation uses a "1 / 2V" scheme. The memory cells in the three-dimensional phase-change memory array are OTS cells connected in series with PCM cells. In this example, a model was built using Veriloga for simulation. The OTS cell has a high impedance of approximately 8MΩ and a low impedance of approximately 60KΩ; the PCM cell has a high impedance of 80KΩ and a low impedance of 6KΩ. A simulation test circuit is used. By connecting Vdd to the WL0 terminal and Vcc to the BL0 terminal, the cell located at WL0BL0 is selected. Vdd is a pulse with a rise and fall time of 2ns and a pulse width of 14ns. Vcc is a pulse with the opposite amplitude to Vdd but otherwise identical. All other word lines and bit lines are grounded. The pulse amplitude of Vdd is set as a parameter for parameter scanning, and the simulation results of the threshold voltage at 25-85℃ are as follows. Figure 12 As shown, it can be seen that as the temperature increases, the threshold voltage decreases at a rate of approximately 3.34 mV / K, i.e., γ′=-3.34 mV / K. Following the first approach, a word line power supply circuit is added, where the output voltage follows the temperature change of the threshold voltage (i.e., the temperature coefficient of the output voltage is approximately -3.34 mV / K). Simulation results of the WL word line input voltage for the selected unit are obtained at temperatures ranging from 25-85℃. The word line input voltages at 25℃, 45℃, 65℃, and 85℃ are 457.322 mV, 391.894 mV, 324.447 mV, and 255.087 mV, respectively. It can be seen that the output voltage of the temperature compensation circuit is input to WL0 through the word line input stage, and the output voltage decreases as the temperature rises, following the decrease in the threshold voltage. The sham positioning line voltage is unaffected by temperature and remains consistently -450mV. Since the nearest cell is selected, and neglecting the voltage drop across the connection resistance, the effective voltage across the selected cell at 25℃ is 907.322mV. Figure 12 It can be seen that the threshold voltage of the cell is 0.9V at 25℃, so the cell is in the on state. Figure 13 The figure shows the simulation results of the selected unit current at 25-85℃. Figure 13 It can be seen that the current of the cell at 25℃ is approximately 15uA, which is about 1V / 66KΩ, consistent with the current order of magnitude of OTS and PCM cells in a low-resistance state in memory. Similarly, at 45, 65, and 85℃, the temperature-compensated word line voltages are 391.894mV, 324.447mV, and 255.087mV respectively, so the voltages on the selected cell are 841.894mV, 774mV, and 705.087mV respectively. Figure 12 It can be seen that the threshold voltages of the cell at 45, 65, and 85℃ are 0.85V, 0.75V, and 0.7V respectively, so the cell is in the ON state in all of them. Figure 13As shown, the current of the cell is approximately 15uA, which is about 1V / 66KΩ, consistent with the current order of magnitude of OTS and PCM cells in a low-resistance state in memory. Furthermore, due to... Figure 13 It can be seen that after the cell is turned on, the current remains at 15uA without any sudden drop, indicating that the cell set was successful. In the OTS-PCM series memory cell, the OTS switching resistance changes from high to low. Almost simultaneously, the PCM, heated by the current, crystallizes from high to low resistance and remains in a crystalline state (the current should be around 9uA for pure OTS switching). This shows that the temperature compensation effect for the threshold voltage Vth is quite good; the array's word line voltage follows the threshold voltage's temperature change, reducing the power consumption of the selected cell without affecting the cell set function. Figure 14 The current simulation results for the selected cell are shown at 25℃ and a Vdd amplitude of 0.6V. Observation Figure 11 The current amplitude spiked to 15µA at 12ns and then plummeted to 9µA at 22ns, indicating that the OTS cell in the selected memory cell was enabled and the PCM cell had transitioned from a crystalline to an amorphous state. Therefore, 1.2V is the cell's Vtr (amorphization threshold voltage), with a half-voltage of 0.6V. The amorphization threshold voltage Vtr is less affected by ambient temperature; its effect is negligible at a temperature change of 60℃. Figure 12 It can be seen that at 85℃ and with a Vdd amplitude of 0.6V, the cell does not reach the crystallization threshold voltage Vts and will not turn on. Therefore, when a reset operation is performed with a voltage of 1.2V, the half-selected cell (referring to other unselected cells on the same word line or position line as the selected cell) will not be partially turned on. In summary, the temperature compensation effect is good.

[0080] Example 2:

[0081] Temperature compensation for the off-state current Ioff of a 129*128 three-dimensional phase-change memory array is performed. This simulation uses the simulation library file of the SMIC 0.18 process. The voltage write operation uses a "1 / 2V" scheme. In this example, a model was built using Veriloga for simulation. The high-resistance state of the OTS cell is approximately 8MΩ, and the low-resistance state is approximately 60KΩ; the high-resistance state of the PCM cell is 80KΩ, and the low-resistance state is 6KΩ. The threshold voltage of the OTS-PCM connected in series is approximately 0.86V, unaffected by temperature. The simulation purely considers the impact of the off-state current Ioff on the three-dimensional phase-change memory array to clearly demonstrate the effect of temperature compensation for Ioff. The simulation test circuit selects the cell located at WL128 and BL127 by connecting Vdd to the WL128 and Vcc to the BL127. Vdd is a pulse with a rise and fall time of 2ns and a pulse width of 14ns. Vcc is a pulse with the opposite amplitude to Vdd but identical in all other aspects. All other word lines and bit lines are grounded. The 129*128 three-dimensional phase-change memory array consists of 16*16 8*8 three-dimensional phase-change memory mini-array modules connected together with 16 1*8 three-dimensional phase-change memory mini-array modules. With the interconnect resistance set to 100 ohms per unit distance, the word line interconnect resistance of the cell located at WL0BL0 is 100Ω, and the bit line interconnect resistance is 100Ω. For cells located at WL1BL0 / WL0BL1, the word / bit line interconnect resistance is 200Ω, and the bit / word line interconnect resistance is 100Ω. Therefore, the word line interconnect resistance of the cell located at WL128BL127 is 12900Ω, and the bit line interconnect resistance is 12800Ω. A parameter scan was performed with the ambient temperature (Temp) set as the parameter to obtain the simulated current results of the selected cell with a Vdd pulse amplitude of 860mV at 25-85℃. Simultaneously, the high-side voltage (word line receiving voltage) of the selected cell was scanned at 25-85℃, and the results are as follows. Figures 15(a) to 15(d) As shown, the low-side voltage (bit line receive voltage) is approximately the negative of the high-side voltage, and the effective voltage of the selected cell is approximately twice the high-side voltage. Figure 15 shows that as temperature increases, the off-state current increases, leading to a higher Vdrop loss on the selected path. This causes the high-side voltage amplitude of the selected cell to drop from 486mV at 25℃ to 474mV at 45℃, 455mV at 65℃, and 433mV at 85℃. Furthermore, the simulated current of the selected cell oscillates around 5uA in the latter half of the 45℃ and 65℃ periods, and in the majority of the 85℃ period. This indicates that the OTS jumps between the on and off states, and the PCM changes from on to off. The higher the temperature, the earlier the unstable state of the cell appears, indicating that the increased temperature causes the effective voltage on the cell to drop insufficiently to stabilize the cell in the on state. Figures 15(a) to 15(d)It can be seen that the high-side voltage of the cell drops from 486mV at 25℃ to 433mV at 85℃, with a drop rate of approximately 1mV / ℃, i.e., δ′=-1mV / ℃. Since the word line length and bit line length of the memory cell WL128BL127 are basically equal, it can be assumed that its low-side voltage (bit line receiving voltage) is approximately the negative of the high-side voltage. That is, the low-side voltage of the cell rises from -486mV at 25℃ to -433mV at 85℃. A word line temperature compensation circuit for temperature compensation of the off-state current is added. The temperature compensation coefficient of this temperature compensation circuit is 1mV / ℃. The simulation results of adding temperature compensation for the off-state current Ioff are simulated by using Vdd pulse amplitudes of 870mV, 880mV, and 890mV, with Vdd connected to the WL128 terminal and -Vdd connected to the BL127 terminal. Simulation results are provided for the selected cell current and high-side voltage of a 129*128 three-dimensional phase-change memory array with temperature compensation for the off-state current Ioff. Figure 16 It can be seen that the selected unit is in the conducting state at 45, 65 and 85℃, with an A current of about 13uA and a high-side voltage of 479mV, 474mV and 461mV respectively, indicating that the temperature compensation effect is good.

[0082] Those skilled in the art will readily understand that the above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A write circuit for a three-dimensional phase-change memory with temperature compensation, wherein the three-dimensional phase-change memory has arrayed memory cells, each memory cell being located at (WLx, BLy), where, x represents the word line position of the corresponding memory cell, y represents the bit line position of the corresponding memory cell, all memory cells are divided into N memory blocks, the (x+y) value of each memory cell in different memory blocks is in different intervals, and the (x+y) value of each memory cell in the same memory block is in the same interval. The write circuit is characterized by including a word line power supply circuit and a bit line power supply circuit, wherein... The output voltage of the word line power supply circuit The voltage variation coefficient with temperature is It has the same voltage variation coefficient as the threshold voltage of the memory cell with temperature, and is used to provide word line voltage to the selected memory cell; The output branch of the bit-line power supply circuit has N voltage divider resistors connected in series. An output terminal is drawn from each voltage divider resistor to obtain N output terminals. The i-th output terminal is the output terminal drawn from the i-th voltage divider resistor Ri, and the corresponding i-th output voltage is... , Let be the output terminal drawn from the first voltage divider resistor R1 and the corresponding first output voltage, where the output voltage is... The voltage variation coefficient with temperature is Furthermore, the voltage coefficient of the voltage divider resistor is the same as the negative of the voltage change coefficient of the bit line receiving voltage of the i-th memory block with temperature, and the resistance value satisfies... , The first output voltage Voltage variation coefficient with temperature, first output voltage Voltage variation coefficient with temperature Controlled by the adjustment of the front-end circuit, the i-th output voltage is Used to provide bit line voltage to the candidate memory cell in the i-th memory block.

2. The three-dimensional phase-change memory write circuit with temperature compensation function as described in claim 1, characterized in that, The word line power supply circuit includes a temperature compensation circuit for the threshold voltage and a word line voltage output terminal. The word line voltage output terminal includes an operational amplifier OP1, a voltage source Vdc1, an operational amplifier OP2, a PMOS transistor M1, an NMOS transistor M2, and a resistor R. The output voltage of the temperature compensation circuit for the threshold voltage It has voltage variation coefficient ; The voltage source Vdc1 and the output voltage The superimposed input is fed into the inverting input terminal of operational amplifier OP1. The non-inverting input terminal of operational amplifier OP1 is connected to the drain of PMOS transistor M1 to form the first terminal. The output terminal of operational amplifier OP1 is connected to the gate of PMOS transistor M1. The source of PMOS transistor M1 is used to connect to an external positive voltage source. The inverting input of the operational amplifier OP2 is connected to the original word line voltage. The non-inverting input terminal is connected to the drain of NMOS transistor M2 to form the second terminal, the output terminal of operational amplifier OP2 is connected to the gate of NMOS transistor M2, and the source of NMOS transistor M2 is grounded; The two ends of resistor R are connected to the first end and the second end respectively, and the output voltage of the word line power supply circuit is led out from the first end.

3. The three-dimensional phase-change memory write circuit with temperature compensation function as described in claim 2, characterized in that, The word line power supply circuit also includes an array word line input, which includes an operational amplifier OP3, a PMOS transistor M3, and a capacitor C1. The inverting input terminal of the operational amplifier OP3 is connected to the first terminal of the word line voltage output to obtain the voltage. The non-inverting input terminal is connected to the drain of PMOS transistor M3 to form the third terminal, which is grounded through capacitor C1. The output terminal of operational amplifier OP3 is connected to the gate of PMOS transistor M3, and the source of PMOS transistor M3 is connected to an external voltage source. The voltage output from the third terminal is used as the output voltage of the word line power supply circuit. Connect the selected character line.

4. The three-dimensional phase-change memory write circuit with temperature compensation function as described in claim 1, characterized in that, The bit line power supply circuit includes a temperature compensation circuit for off-state current and a bit line voltage output terminal. The bit line voltage output terminal includes a voltage source Vdc2, an operational amplifier OP4, an operational amplifier OP5, a PMOS transistor M4, an NMOS transistor M5, and N voltage divider resistors R1~RN. The output voltage of the temperature compensation circuit for the off-state current It has voltage variation coefficient ; The inverting input terminal of the operational amplifier OP4 is connected to the original bit line voltage. The positive input terminal is connected to the drain of PMOS transistor M4 to form the fourth terminal, and the source of PMOS transistor M4 is used to connect to an external negative voltage source. The voltage source Vdc2 and the output voltage The superimposed input is fed into the inverting input terminal of the operational amplifier OP5. The non-inverting input terminal of OP5 is connected to the drain of NMOS transistor M5 to form the fifth terminal. The output terminal of operational amplifier OP5 is connected to the gate of NMOS transistor M5, and the source of NMOS transistor M5 is grounded. N voltage divider resistors are connected in series between the fourth and fifth terminals, and resistors R1 to RN are connected sequentially from the fifth terminal to the fourth terminal. The first output terminal is drawn from the fifth terminal, and the i-th output terminal is drawn from between resistors R(i-1) and Ri.

5. The three-dimensional phase-change memory write circuit with temperature compensation function as described in claim 4, characterized in that, The bit line power supply circuit also includes an array bit line input, which includes an operational amplifier OP6, an NMOS transistor M6, and a capacitor C2. The non-inverting input terminal of the operational amplifier OP6 is connected to the i-th output terminal of the bit line voltage output circuit. The inverting input terminal is connected to the drain of the NMOS transistor M6 to form the sixth terminal. The sixth terminal is grounded to the operational amplifier through capacitor C2. The output terminal of OP6 is connected to the gate of the NMOS transistor M6, and the source of the NMOS transistor M6 is connected to an external negative voltage source. The voltage output from the sixth terminal is used as the i-th output voltage of the bit line power supply circuit. .

6. The three-dimensional phase-change memory write circuit with temperature compensation function as described in claim 5, characterized in that, It also includes a selection circuit, which, when receiving a signal to select any bit line in the i-th memory block, connects the i-th output terminal of the bit line voltage output pole and the array bit line input pole to provide the i-th output voltage to the corresponding bit line. .

7. The three-dimensional phase-change memory write circuit with temperature compensation function as described in claim 2 or 4, characterized in that, The temperature compensation circuit includes: NMOS transistors M11~M12, PMOS transistors M13~M15, transistors Q1~Q(M-2), and resistors R11~R12; The sources of PMOS transistors M13 to M15 are all connected to an external voltage source, and their gates are all interconnected. The drain of PMOS transistor M13 is connected to the drain of NMOS transistor M11. The source and gate of NMOS transistor M11 are connected. The source of NMOS transistor M11 is connected to the emitter of transistor Q1. The base and collector of transistor Q1 are connected and grounded. The gate and drain of PMOS transistor M14 are connected, the drain of PMOS transistor M14 is connected to the drain of NMOS transistor M12, the gate of NMOS transistor M12 is connected to the gate of NMOS transistor M11, the source of NMOS transistor M12 is connected to the emitter of transistor Q2 through resistor R11, and the base and collector of transistor Q2 are connected and grounded. The drain of PMOS transistor M15 is connected to the emitter of transistor Q3 through resistor R12. Transistors Q3 to Q(M-2) are connected in sequence, and the base and collector of each transistor are connected. The collector of transistor Q(M-2) is grounded. The voltage at the drain terminal of PMOS transistor M15 is used as the output voltage of the temperature compensation circuit. When the temperature compensation circuit is a threshold voltage temperature compensation circuit, the ratio of the emitter areas of transistors Q2 and Q1 and the value of M satisfy the condition that the output voltage of the threshold voltage temperature compensation circuit is... It has voltage variation coefficient ; When the temperature compensation circuit is a temperature compensation circuit for off-state current, the ratio of the emitter areas of transistors Q2 and Q1 and the value of M satisfy the condition that the output voltage of the temperature compensation circuit for off-state current is... It has voltage variation coefficient .

8. A write operation method for a three-dimensional phase-change memory with temperature compensation, characterized in that, All storage cells are divided into N storage blocks according to their location. The (x+y) value of each storage cell in different storage blocks is in a different range, and the (x+y) value of each storage cell in the same storage block is in the same range. The write operation method is based on the three-dimensional phase change memory write circuit with temperature compensation as described in any one of claims 1 to 7, and includes: Determine the memory block where the selected memory cell is located. When the selected memory cell is in the i-th memory block, connect the word line power supply circuit to the word line corresponding to the selected memory cell, and connect the i-th output voltage in the bit line power supply circuit to the bit line corresponding to the selected memory cell, so as to select the memory cell and write data.

9. A write circuit for a three-dimensional phase-change memory with temperature compensation, wherein the three-dimensional phase-change memory has arrayed memory cells, each memory cell being located at (WLx, BLy), where, x represents the word line position of the corresponding memory cell, y represents the bit line position of the corresponding memory cell, all memory cells are divided into N memory blocks, the (x+y) value of each memory cell in different memory blocks is in different intervals, and the (x+y) value of each memory cell in the same memory block is in the same interval. The write circuit is characterized by including a word line power supply circuit and a bit line power supply circuit, wherein... The output voltage of the bit line power supply circuit The voltage variation coefficient with temperature is It is the opposite of the voltage change coefficient of the threshold voltage of the storage cell as a function of temperature; The output branch of the word line power supply circuit has N voltage divider resistors connected in series. An output terminal is drawn from each voltage divider resistor to obtain N output terminals. The i-th output terminal is the output terminal drawn from the i-th voltage divider resistor Ri, and the corresponding i-th output voltage is... , Let be the output terminal drawn from the first voltage divider resistor R1 and the corresponding first output voltage, where the output voltage is... The voltage variation coefficient with temperature is Furthermore, the voltage coefficient of the voltage difference between the word line received voltage of the i-th memory block and the temperature is the opposite of the voltage coefficient of the voltage divider resistor, and the resistance value satisfies the following condition. , The first output voltage Voltage variation coefficient with temperature, first output voltage Voltage variation coefficient with temperature Controlled by the adjustment of the front-end circuit, the i-th output voltage is Used to provide word line voltage to the candidate memory cell in the i-th memory block.

10. A write operation method for a three-dimensional phase-change memory with temperature compensation, characterized in that, All storage cells are divided into N storage blocks according to their location. The (x+y) value of each storage cell in different storage blocks is in a different range, and the (x+y) value of each storage cell in the same storage block is in the same range. The write operation method is based on the three-dimensional phase change memory write circuit with temperature compensation as described in claim 9, and includes: Determine the memory block where the selected memory cell is located. When the selected memory cell is in the i-th memory block, connect the bit line power supply circuit to the bit line corresponding to the selected memory cell, and connect the i-th output voltage in the word line power supply circuit to the word line corresponding to the selected memory cell, so as to select the memory cell and write the data.

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