Method for electrical compensation of super-junction device structure

Abstract

A method for compensating electrical properties of a super-junction device structure, comprising: providing a first batch of wafers, the first batch of wafers comprising a test wafer and a plurality of to-be-compensated wafers; forming a first epitaxial layer in the test wafer, the first epitaxial layer having first ions; obtaining a first resistance value of the first epitaxial layer; obtaining an optimal resistance value corresponding to the first epitaxial layer in a super-junction device structure of the first batch of wafers; obtaining an epitaxial doping process parameter deviation value corresponding to adjustment of the first resistance value to the optimal resistance value; compensating an epitaxial doping process according to the epitaxial doping process parameter deviation value; and forming a second epitaxial layer in the to-be-compensated wafers using the compensated process parameter. By converting the total amount of first ion doping into an accurate resistance value for characterization, the process parameter adjustment has an accurate basis, so as to improve the doping mismatch of the super-junction device structure in the to-be-compensated wafers and improve the electrical properties of the super-junction device structure.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to an electrical compensation method for a superjunction device structure. Background Technology

[0002] A superjunction is composed of alternating P-type thin layers (also called P-type pillars) and N-type thin layers (also called N-type pillars) formed in a semiconductor substrate. A P-type pillar and its adjacent N-type pillar form a superjunction unit. Devices employing superjunctions are called superjunction devices, such as superjunction MOSFETs. The resurf technique, which utilizes the charge balance of the P-type and N-type thin layers to reduce the surface electric field in bulk, can improve the reverse breakdown voltage of the device while maintaining a low on-resistance.

[0003] The PN-spaced pillar structure is the most distinctive feature of superjunctions. There are two main methods for fabricating PN-spaced pillar structures: one involves multiple epitaxial layers and ion implantation, and the other uses deep trench etching and epitaxial growth indexing (EPI) filling. The latter method involves fabricating superjunction devices using trench technology. This requires first etching trenches of a certain depth and width on an N-type doped epitaxial layer on a semiconductor substrate, such as silicon, and then filling the etched trenches with P-type doped silicon epitaxial material using EPI filling.

[0004] The key technical challenge in fabricating superjunction devices using trench technology lies in the trench filling process. Trench filling is performed simultaneously with etching. Etching is introduced to eliminate defects such as voids inside the trench caused by premature closure at the top of the trench. However, due to the etching effect, the filling speed is extremely slow, resulting in very low epitaxial filling efficiency and extremely high costs. Especially as the pitch and trench opening continue to shrink, an even slower filling rate is needed to achieve good filling results, significantly increasing capacity requirements and raising costs considerably. The pitch of a superjunction is the sum of the trench width and the trench spacing, which is also the sum of the widths of an N-type pillar and a P-type pillar, i.e., the width of a single superjunction cell.

[0005] Existing experiments show that when the in-plane mismatch between the volumes of the P-type and N-type pillars is controlled at 10%, and the process level is 10%, the in-plane doping mismatch of the device is less than 10%, and the worst-case breakdown voltage (BV) is still above 650V. When the doping mismatch is 0%, it corresponds to perfect doping, and the breakdown voltage is around 750V. When the doping mismatch is -20%, the breakdown voltage drops to around 420V. Therefore, by adjusting the compensation to make the total doping amount of the P-type pillars and the N-type pillars closer, the improvement in the reverse breakdown voltage (BV) is more significant.

[0006] However, existing technologies still have many problems in adjusting and compensating for the total doping amount of P-type pillars and N-type pillars in superjunction device structures. Summary of the Invention

[0007] The technical problem solved by this invention is to provide an electrical compensation method for superjunction device structures to improve doping mismatch and enhance the electrical performance of superjunction device structures.

[0008] To address the aforementioned problems, the present invention provides an electrical compensation method for a superjunction device structure, comprising: providing a first batch of wafers, the first batch of wafers including a test wafer and several wafers to be compensated, the test wafer having a first superjunction trench, and the wafers to be compensated having a second superjunction trench, the volume of the first superjunction trench and the volume of the second superjunction trench being the same; forming a first epitaxial layer in the first superjunction trench using a first epitaxial doping process, the first epitaxial layer being doped with first ions, the first epitaxial doping process having first epitaxial doping process parameters; performing an electrical test on the first epitaxial layer to obtain a first resistance value of the first epitaxial layer, the total doping amount of the first ions in the first epitaxial layer being mapped to the first resistance value; and obtaining the electrical compensation method for the superjunction device structure of the first batch of wafers. The optimal total amount of first ions doped in the first epitaxial layer is mapped to an optimal resistance value. A resistance database is obtained, which includes several sets of resistance values ​​of epitaxial layers with different ion doping amounts, and epitaxial doping process parameters corresponding to each resistance value. Based on the resistance database, the deviation value of the epitaxial doping process parameters corresponding to adjusting the first resistance value to the optimal resistance value is obtained. Based on the deviation value of the epitaxial doping process parameters, the first epitaxial doping process parameters in the first epitaxial doping process are corrected and compensated to obtain a second epitaxial doping process, which has second epitaxial doping process parameters. A second epitaxial layer is formed in the second superjunction trench using the second epitaxial doping process, and the second epitaxial layer is doped with the first ions.

[0009] Optionally, after the first epitaxial layer is formed in the test wafer, an electrical test is performed on the first epitaxial layer to obtain a first resistance value of the first epitaxial layer.

[0010] Optionally, after forming a superjunction device structure in the test wafer, an electrical test is performed on the first epitaxial layer to obtain a first resistance value of the first epitaxial layer.

[0011] Optionally, the first epitaxial layer includes a first end and a second end opposite to each other. The method for performing an electrical test on the first epitaxial layer to obtain a first resistance value of the first epitaxial layer includes: applying a first constant current between the first end and the second end of the first epitaxial layer; obtaining a first test voltage between the first end and the second end of the first epitaxial layer; and obtaining a first resistance value of the first epitaxial layer based on the first test voltage and the first constant current.

[0012] Optionally, the method for obtaining the optimal total doping amount of the first ion doped in the first epitaxial layer of the superjunction device structure of the first batch of wafers includes: providing historical processed wafer data, wherein the historical processed wafer data includes the optimal total doping amount of the first ion doped in the epitaxial layer of the superjunction device structure of different batches of wafers; and obtaining the optimal total doping amount of the first ion doped in the first epitaxial layer of the superjunction device structure of the first batch of wafers based on the historical processed wafer data.

[0013] Optionally, the method for obtaining the resistance database includes: forming several sets of test structures, each test structure including a third superjunction trench and a test epitaxial layer located within the third superjunction trench, wherein the total amount of the first ion doping in the test epitaxial layer is different in different test structures, and the volume of the third superjunction trench is the same as the volume of the second superjunction trench; obtaining the epitaxial doping process parameters corresponding to each set of test structures; performing electrical tests on each set of test structures to obtain the resistance value corresponding to each set of test structures; and establishing a mapping relationship between the resistance value of each set of test structures and the epitaxial doping process parameters to obtain the resistance database.

[0014] Optionally, the test epitaxial layer of each group of test structures includes opposing third and fourth terminals. The method for performing electrical tests on each group of test structures and obtaining the resistance value corresponding to each group of test structures includes: applying a second constant current between the third and fourth terminals of the test epitaxial layer; obtaining a second test voltage between the third and fourth terminals of the test epitaxial layer; and obtaining the resistance value corresponding to each group of test structures based on the second test voltage and the second constant current.

[0015] Optionally, the first ion includes: an N-type ion or a P-type ion.

[0016] Optionally, before or after forming the second epitaxial layer, the method further includes forming a plurality of gate structures within the wafer to be compensated.

[0017] Optionally, the gate structure includes a trench gate structure.

[0018] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0019] In the electrical compensation method for the superjunction device structure of the present invention, an electrical test is performed on the first epitaxial layer to obtain a first resistance value of the first epitaxial layer. The total doping amount of the first ion in the first epitaxial layer is mapped to the first resistance value. Additionally, the optimal total doping amount of the first ion in the first epitaxial layer of the superjunction device structure of the first batch of wafers is obtained, and this optimal total doping amount is mapped to an optimal resistance value. By converting the characterization of the total doping amount of the first ion into a precise resistance value, and then using the first resistance value and the optimal resistance value as a basis, the corresponding epitaxial doping process parameter deviation value is obtained. The epitaxial doping process is then adjusted and compensated using this deviation value to improve the doping mismatch in the superjunction device structure of the wafer to be compensated, thereby enhancing the electrical performance of the superjunction device structure. Attached Figure Description

[0020] Figure 1 This is a schematic diagram of the electrical compensation method for the superjunction device structure in an embodiment of the present invention;

[0021] Figures 2 to 6 This is a schematic diagram of the steps in the electrical compensation method for the superjunction device structure in an embodiment of the present invention. Detailed Implementation

[0022] As described in the background section, existing technologies still present many challenges in adjusting and compensating for the total doping amount of P-type pillars and N-type pillars in superjunction device structures. These will be explained in detail below.

[0023] Currently, it is very difficult to accurately measure and characterize the volume of deep trenches in superjunction devices. Therefore, it is impossible to obtain the total amount of ions in the P-type pillars, and consequently, it is impossible to adjust and compensate for the total amount of doping in the P-type and N-type pillars. This results in a high doping mismatch between the P-type and N-type pillars, which affects the electrical performance of the superjunction device structure.

[0024] Based on this, the present invention provides an electrical compensation method for a superjunction device structure. The method involves performing electrical tests on the first epitaxial layer to obtain a first resistance value. The total doping amount of the first ion in the first epitaxial layer is mapped to the first resistance value. Furthermore, the optimal total doping amount of the first ion in the first epitaxial layer of the superjunction device structure of the first batch of wafers is obtained, and this optimal total doping amount is mapped to an optimal resistance value. By converting the characterization of the total doping amount of the first ion into a precise resistance value, and then using the first resistance value and the optimal resistance value as a basis, the corresponding epitaxial doping process parameter deviation value is obtained. This deviation value is then used to adjust and compensate the epitaxial doping process, thereby improving the doping mismatch in the superjunction device structure of the wafer to be compensated, and ultimately enhancing the electrical performance of the superjunction device structure.

[0025] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0026] Figure 1 This is a flowchart of an electrical compensation method for a superjunction device structure according to an embodiment of the present invention, including:

[0027] Step S101: Provide a first batch of wafers, which includes test wafers and several wafers to be compensated. The test wafers have a first superjunction trench, and the wafers to be compensated have a second superjunction trench. The volume of the first superjunction trench and the volume of the second superjunction trench are the same.

[0028] Step S102: A first epitaxial layer is formed in the first superjunction trench using a first epitaxial doping process. The first epitaxial layer is doped with first ions. The first epitaxial doping process has first epitaxial doping process parameters.

[0029] Step S103: Perform an electrical test on the first epitaxial layer to obtain the first resistance value of the first epitaxial layer, and map the total doping amount of the first ions in the first epitaxial layer to the first resistance value.

[0030] Step S104: Obtain the optimal total amount of first ions doped in the first epitaxial layer of the superjunction device structure of the first batch of wafers. The optimal total amount of first ions in the first epitaxial layer is mapped to the optimal resistance value.

[0031] Step S105: Obtain the resistance database, which includes several sets of resistance values ​​of epitaxial layers with different ion doping amounts, and the epitaxial doping process parameters corresponding to each resistance value.

[0032] Step S106: According to the resistance database, obtain the epitaxial doping process parameter deviation value corresponding to adjusting the first resistance value to the optimal resistance value;

[0033] Step S107: Based on the deviation value of the epitaxial doping process parameters, the first epitaxial doping process parameters in the first epitaxial doping process are corrected and compensated to obtain the second epitaxial doping process, wherein the second epitaxial doping process has the second epitaxial doping process parameters.

[0034] Step S108: A second epitaxial layer is formed in the second superjunction trench using the second epitaxial doping process, and the second epitaxial layer is doped with the first ions.

[0035] The steps of the optical proximity correction method are described in detail below with reference to the accompanying drawings.

[0036] Figures 2 to 6 This is a schematic diagram of the steps in the electrical compensation method for the superjunction device structure in an embodiment of the present invention.

[0037] Please refer to Figure 2 The first batch of wafers is provided, which includes a test wafer 100 and a number of wafers to be compensated 200. The test wafer 100 has a first superjunction trench 101, and the wafers to be compensated 200 have a second superjunction trench 201. The volume of the first superjunction trench 101 and the volume of the second superjunction trench 201 are the same.

[0038] It should be noted that the first batch of wafers refers to wafers from the same batch. The size of the first batch of wafers, as well as the subsequent process flow and process environment, are the same. Therefore, the volume of the first superjunction trench 101 formed in the test wafer 100 is the same as the volume of the second superjunction trench 201 formed in the wafer to be compensated 200.

[0039] The number of test wafers 100 is one, and their function is to: first run the set process on the test wafer 100, and then test the device structure formed on the test wafer 100. If the test result meets the expectations, then several of the compensation wafers 200 will run according to the set process; if the test result does not meet the expectations, then the parameters in the set process will be corrected and compensated, and the compensation wafers 200 will run according to the corrected and compensated process.

[0040] In this embodiment, the test wafer 100 is used to detect the total amount of first ions doped in the first epitaxial layer subsequently formed in the first superjunction trench 101.

[0041] In this embodiment, before forming the first superjunction trench 101, the method further includes: forming a plurality of first gate structures 102 in the test wafer; correspondingly, forming a plurality of second gate structures 202 in the wafer to be compensated 200.

[0042] In this embodiment, the first gate structure 102 and the second gate structure 202 are trench gate structures; in other embodiments, the first gate structure and the second gate structure may also be planar gate structures.

[0043] In other embodiments, the first gate structure may be formed within the test wafer after the first superjunction trench is formed. Similarly, the second gate structure may be formed within the wafer to be compensated after the second superjunction trench is formed.

[0044] Please refer to Figure 3 A first epitaxial layer 103 is formed in the first superjunction trench 101 using a first epitaxial doping process. The first epitaxial layer 103 is doped with first ions. The first epitaxial doping process has first epitaxial doping process parameters.

[0045] In this embodiment, the first ion is a P-type ion, and the first epitaxial layer 103 is a P-type pillar; in other embodiments, the first ion may also be an N-type ion, and the corresponding first epitaxial layer is an N-type pillar.

[0046] It should be noted that the first epitaxial doping process parameters in the first epitaxial doping process are the initial process parameters. By first forming the first epitaxial layer 103 on the test wafer 100, in subsequent testing, if the total amount of first ion doping in the first epitaxial layer 103 of the test wafer 100 meets the expectation, that is, the doping mismatch between P-type pillars and N-type pillars is within a preset range, then the wafer to be compensated 200 will also be run according to the first epitaxial doping process; if the total amount of first ion doping in the first epitaxial layer 103 of the test wafer 100 does not meet the expectation, that is, the doping mismatch between P-type pillars and N-type pillars exceeds the preset range, then the first epitaxial doping process parameters in the first epitaxial doping process need to be corrected and compensated, and the wafer to be compensated 200 will be run according to the corrected and compensated process.

[0047] This embodiment addresses how to perform electrical compensation when the doping mismatch between P-type and N-type pillars exceeds a preset range.

[0048] Please refer to Figure 4 Electrical tests are performed on the first epitaxial layer 103 to obtain the first resistance value of the first epitaxial layer 103. The total doping amount of the first ion in the first epitaxial layer 103 is mapped to the first resistance value.

[0049] In this embodiment, after the first epitaxial layer 103 is formed in the test wafer 100, an electrical test is performed on the first epitaxial layer 103 to obtain a first resistance value. Since only the total doping amount of the first ions in the first epitaxial layer 103 is detected, it can be detected immediately after the formation of the first epitaxial layer 103, thereby significantly reducing the detection cycle.

[0050] In other embodiments, after the superjunction device structure (i.e., all components contained in the superjunction device structure) is formed in the test wafer, the first epitaxial layer can be electrically tested to obtain a first resistance value of the first epitaxial layer.

[0051] In this embodiment, the first epitaxial layer 103 includes a first end 103a and a second end 103b opposite to each other. The method for performing an electrical test on the first epitaxial layer 103 to obtain a first resistance value of the first epitaxial layer 103 includes: applying a first constant current between the first end 103a and the second end 103b of the first epitaxial layer 103; obtaining a first test voltage between the first end 103a and the second end 103b of the first epitaxial layer 103; and obtaining a first resistance value of the first epitaxial layer based on the first test voltage and the first constant current.

[0052] In this embodiment, since measuring the volume of the first superjunction trench 101 is difficult, the total amount of first ion doping in the first epitaxial layer 103 formed within the first superjunction trench 101 cannot be accurately obtained. Since the dose of the first ion doped in the first epitaxial layer 103 is negatively correlated with the resistance of the first epitaxial layer 103, the characterization of the total amount of first ion doping in the first epitaxial layer 103 can be converted into a precise resistance value for characterization.

[0053] Please continue to refer to this. Figure 4 The optimal total amount of first ions doped in the first epitaxial layer 103 of the first batch of wafers is obtained, and the optimal total amount of first ions in the first epitaxial layer 103 is mapped to the optimal resistance value.

[0054] In this embodiment, the method for obtaining the optimal total doping amount of the first ion doped in the first epitaxial layer 103 in the superjunction device structure of the first batch of wafers includes: providing historical wafer processing data, wherein the historical wafer processing data includes the optimal total doping amount of the first ion doped in the epitaxial layer in the superjunction device structure of different batches of wafers; and obtaining the optimal total doping amount of the first ion doped in the first epitaxial layer 103 in the superjunction device structure of the first batch of wafers based on the historical wafer processing data.

[0055] It should be noted that the historical processed wafer data refers to the wafer data that has already been processed. By searching the historical data, the optimal total amount of the first doping of the first ion in the first epitaxial layer 103 of the superjunction device structure of the first batch of wafers can be obtained.

[0056] Please refer to Figure 5 Obtain a resistance database, which includes several sets of resistance values ​​of epitaxial layers with different ion doping amounts, and epitaxial doping process parameters corresponding to each resistance value.

[0057] In this embodiment, the method for obtaining the resistance database includes: forming several sets of test structures 300, each test structure 300 including a third superjunction trench (not shown), a test epitaxial layer 301 located within the third superjunction trench, wherein the total amount of the first ion doping in the test epitaxial layer 301 within different test structures 300 is different, and the volume of the third superjunction trench is the same as the volume of the second superjunction trench 201; obtaining the epitaxial doping process parameters corresponding to each set of test structures 300; performing electrical tests on each set of test structures 300 to obtain the resistance value corresponding to each set of test structures 300; and establishing a mapping relationship between the resistance value of each set of test structures 300 and the epitaxial doping process parameters to obtain the resistance database.

[0058] In this embodiment, the test epitaxial layer 301 of each group of test structures 300 includes a third terminal 301a and a fourth terminal 301b. The method for performing electrical tests on each group of test structures 300 and obtaining the resistance value corresponding to each group of test structures 300 includes: applying a second constant current between the third terminal 301a and the fourth terminal 301b of the test epitaxial layer 301; obtaining a second test voltage between the third terminal 301a and the fourth terminal 301b of the test epitaxial layer 301; and obtaining the resistance value corresponding to each group of test structures 300 based on the second test voltage and the second constant current.

[0059] Please continue to refer to this. Figure 5 Based on the resistance database, the epitaxial doping process parameter deviation value corresponding to adjusting the first resistance value to the optimal resistance value is obtained.

[0060] In this embodiment, the deviation value of the epitaxial doping process parameters can be obtained by comparing the epitaxial doping process parameters mapped to the first resistance value with the epitaxial doping process parameters mapped to the optimal resistance value.

[0061] Please continue to refer to this. Figure 5Based on the deviation value of the epitaxial doping process parameters, the first epitaxial doping process parameters in the first epitaxial doping process are corrected and compensated to obtain the second epitaxial doping process, wherein the second epitaxial doping process has the second epitaxial doping process parameters.

[0062] In this embodiment, the second epitaxial doping process parameters of the second epitaxial doping process are the same as the epitaxial doping process parameters mapped to the optimal resistance value.

[0063] Please refer to Figure 6 The second epitaxial layer 203 is formed in the second superjunction trench 201 using the second epitaxial doping process, and the second epitaxial layer 203 is doped with the first ions.

[0064] In this embodiment, the characterization of the total amount of first ion doping is converted into a precise resistance value for characterization. Then, based on the first resistance value and the optimal resistance value, the corresponding epitaxial doping process parameter deviation value is obtained. The epitaxial doping process is adjusted and compensated using the epitaxial doping process parameter deviation value to improve the doping mismatch of the superjunction device structure in the wafer 200 to be compensated, thereby improving the electrical performance of the superjunction device structure.

[0065] In this embodiment, after forming the second epitaxial layer 203, the method further includes: forming the remaining components (not shown) required for forming the superjunction device structure within the wafer to be compensated 200.

[0066] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. An electrical compensation method for a superjunction device structure, characterized in that, The method comprises the following steps: providing a first batch of wafers, the first batch of wafers comprising a test wafer and a plurality of to-be-compensated wafers, the test wafer having a first super-junction trench therein, the to-be-compensated wafers having a second super-junction trench therein, the first super-junction trench having a same volume as the second super-junction trench; forming a first epitaxial layer in the first super-junction trench by using a first epitaxial doping process, the first epitaxial layer being doped with first ions, the first epitaxial doping process having first epitaxial doping process parameters; performing electrical property testing on the first epitaxial layer to obtain a first resistance value of the first epitaxial layer, the total amount of doping of the first ions in the first epitaxial layer mapping the first resistance value; obtaining an optimal total amount of doping of the first ions doped in the first epitaxial layer in a super-junction device structure of the first batch of wafers, the optimal total amount of doping of the first ions in the first epitaxial layer mapping an optimal resistance value; obtaining a resistance database, the resistance database comprising resistance values of a plurality of groups of epitaxial layers doped with different total amounts of ions and epitaxial doping process parameters corresponding to each resistance value; obtaining an epitaxial doping process parameter deviation value corresponding to an adjustment of the first resistance value to the optimal resistance value according to the resistance database; modifying and compensating the first epitaxial doping process parameters in the first epitaxial doping process according to the epitaxial doping process parameter deviation value to obtain a second epitaxial doping process, the second epitaxial doping process having second epitaxial doping process parameters; forming a second epitaxial layer in the second super-junction trench by using the second epitaxial doping process, the second epitaxial layer being doped with the first ions.

2. The method of electrical compensation of super junction device structure according to claim 1, wherein, After forming the first epitaxial layer in the test wafer, performing electrical property testing on the first epitaxial layer to obtain a first resistance value of the first epitaxial layer.

3. The method of electrical compensation of super junction device structure of claim 1, wherein, After forming a super-junction device structure in the test wafer, performing electrical property testing on the first epitaxial layer to obtain a first resistance value of the first epitaxial layer.

4. The method of electrical compensation of super junction device structure of claim 1, wherein, The first epitaxial layer comprises opposite first and second ends, and the method of performing electrical property testing on the first epitaxial layer to obtain a first resistance value of the first epitaxial layer comprises: applying a first constant current between the first and second ends of the first epitaxial layer; obtaining a first test voltage between the first and second ends of the first epitaxial layer; and obtaining the first resistance value of the first epitaxial layer according to the first test voltage and the first constant current.

5. The method of electrical compensation of super junction device structure of claim 1, wherein, The method of obtaining an optimal total amount of doping of the first ions doped in the first epitaxial layer in a super-junction device structure of the first batch of wafers comprises: providing historical wafer processing data, the historical wafer processing data comprising optimal total amounts of doping of the first ions doped in epitaxial layers in super-junction device structures of different batches of wafers; and obtaining the optimal total amount of doping of the first ions doped in the first epitaxial layer in the super-junction device structure of the first batch of wafers according to the historical wafer processing data.

6. The method of electrical compensation of super junction device structure of claim 1, wherein, The method for obtaining the resistance database comprises: forming a plurality of groups of test structures, the test structures comprising a third super-junction trench, a test epitaxial layer located in the third super-junction trench, the test epitaxial layer having different total amounts of the first ion doping in different test structures, the volume of the third super-junction trench being the same as the volume of the second super-junction trench; obtaining an epitaxial doping process parameter corresponding to each group of test structures; performing electrical property testing on each group of test structures to obtain a resistance value corresponding to each group of test structures; and forming a mapping relationship between the resistance value and the epitaxial doping process parameter of each group of test structures to obtain the resistance database.

7. The method of electrical compensation of super junction device structure as claimed in claim 6, wherein, The test epitaxial layer of each group of test structures comprises opposite third and fourth ends, and the method for obtaining the resistance value corresponding to each group of test structures by performing electrical property testing on each group of test structures comprises: applying a second constant current between the third and fourth ends of the test epitaxial layer; obtaining a second test voltage between the third and fourth ends of the test epitaxial layer; and obtaining the resistance value corresponding to each group of test structures according to the second test voltage and the second constant current.

8. The method of electrical compensation of super junction device structure of claim 1, wherein, The first ion comprises an N-type ion or a P-type ion.

9. The method of electrical compensation of super junction device structure of claim 1, wherein, The method further comprises, before or after forming the second epitaxial layer, forming a plurality of gate structures in the wafer to be compensated.

10. The method of electrical compensation of super junction device structure of claim 9, wherein, The gate structure comprises a trench gate structure.

Images