Silicon-on-insulator substrate with enhanced charge trapping efficiency and high resistivity

By epitaxially depositing an epitaxial layer and a polycrystalline silicon charge trapping layer on a high resistivity single-crystal semiconductor substrate to form a multilayer structure, the problem of low charge trapping efficiency in the prior art is solved, and the performance and stability of radio frequency devices are improved.

CN115763496BActive Publication Date: 2026-07-17GLOBALWAFERS CO LTD
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
GLOBALWAFERS CO LTD
Filing Date
2017-10-09
Publication Date
2026-07-17

AI Technical Summary

Technical Problem

Existing technologies struggle to effectively trap charge reversal or accumulation layers when fabricating high resistivity silicon-on-insulator substrates, leading to parasitic power loss and device nonlinearity, which in turn affects the performance of radio frequency devices.

Method used

By epitaxially depositing an epitaxial layer on a high resistivity single-crystal semiconductor substrate and then depositing a polycrystalline silicon charge trapping layer thereon, followed by bonding it with a dielectric layer, a multilayer structure is formed to trap charges, thereby enhancing charge trapping efficiency.

Benefits of technology

It significantly improves the performance of radio frequency devices, reduces second and third harmonic distortion, solves the process and metrology challenges in the fabrication of high resistivity substrates, and avoids performance degradation caused by contaminant diffusion.

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Abstract

The present application relates to silicon-on-insulator substrates with enhanced charge trapping efficiency and high resistivity. A multilayer semiconductor-on-insulator structure is provided, wherein the handle substrate and the epitaxial layer in interface contact with the handle substrate comprise electrically active dopants of opposite type. The epitaxial layer is depleted of free carriers from the handle substrate, thereby resulting in high apparent resistivity, which improves the functioning of the structure in RF devices.
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Citation Information

Patent Citations

  • Multi-layer type semiconductor device with semiconductor element layers stacked in opposite directions and manufacturing method thereof

    US5189500A

  • Method of manufacturing high resistivity SOI wafers with charge trapping layers based on terminated si deposition

    US20150115480A1

  • High resistivity semiconductor-on-insulator wafer and a method of manufacturing

    WO2016081356A1