Semiconductor device and method of forming the same

Abstract

A semiconductor device and a method of forming the same. The forming method includes: providing a substrate, forming a dielectric layer on the top of the substrate, forming an opening in the dielectric layer, the opening penetrating the dielectric layer and extending into the substrate to a partial thickness; forming an optoelectronic layer in the opening; removing a partial thickness of the dielectric layer on the side of the optoelectronic layer, forming a trench surrounding the optoelectronic layer in the dielectric layer, and the trench exposing the optoelectronic layer; forming a covering layer covering the dielectric layer and the optoelectronic layer, and the covering layer also filling the trench. The formation of the trench increases the filling angle around the optoelectronic layer, correspondingly improves the filling effect of the covering layer between the dielectric layer and the optoelectronic layer, thereby reducing the probability of void defects generated in the covering layer, and further facilitating the improvement of the performance of the semiconductor device (for example, reliability performance).

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of semiconductor manufacturing, and particularly to a semiconductor device and a method for forming the same. Background Art

[0002] Silicon photonics technology is a new generation of technology based on silicon or silicon-based substrate materials, which uses existing CMOS (Complementary Metal Oxide Semiconductor) processes for the development and integration of optical devices. Silicon photonics technology is compatible with CMOS processes, combining the characteristics of ultra-large scale and ultra-high precision manufacturing of integrated circuit technology and the advantages of ultra-high speed and ultra-low power consumption of photonics technology. It is a disruptive technology to cope with the failure of Moore's Law.

[0003] As one of the core devices of a silicon photonics architecture, an optoelectronic layer has the function of realizing the conversion of optical signals to electrical signals. Summary of the Invention

[0004] The problem solved by the embodiments of the present invention is to provide a semiconductor device and a method for forming the same, so as to improve the performance of the semiconductor device.

[0005] To solve the above problems, embodiments of the present invention provide a semiconductor device, including: a substrate; a dielectric layer located on the substrate; an opening located in the dielectric layer and the substrate, the bottom of the opening being lower than the surface of the substrate, and the top of the opening being flush with the top surface of the dielectric layer; an optoelectronic layer located in the opening; a trench located in a part of the thickness of the dielectric layer on the side of the optoelectronic layer, the trench surrounding the optoelectronic layer; and a covering layer located in the trench and on the top of the dielectric layer.

[0006] Correspondingly, embodiments of the present invention further provide a method for forming a semiconductor device, including: providing a substrate, forming a dielectric layer on the top of the substrate, forming an opening in the dielectric layer, the opening penetrating through the dielectric layer and extending into a part of the thickness of the substrate; forming an optoelectronic layer in the opening; removing a part of the thickness of the dielectric layer on the side of the optoelectronic layer, forming a trench surrounding the optoelectronic layer in the dielectric layer, and the trench exposing the optoelectronic layer; and forming a covering layer covering the dielectric layer and the optoelectronic layer, and the covering layer also filling the trench.

[0007] Compared with the prior art, the technical solutions of the embodiments of the present invention have the following advantages:

[0008] In the semiconductor device provided by the embodiment of the present invention, a trench is formed in the dielectric layer with a partial thickness on the side of the optoelectronic layer. The trench surrounds the optoelectronic layer. The setting of the trench makes the filling angle around the optoelectronic layer larger, correspondingly improving the filling effect of the covering layer between the dielectric layer and the optoelectronic layer, thereby reducing the probability of generating void defects in the covering layer, and further being beneficial to improving the performance of the semiconductor device (for example, reliability performance).

[0009] In the method for forming a semiconductor device provided by the embodiment of the present invention, before forming the covering layer, the dielectric layer with a partial thickness on the side of the optoelectronic layer is first removed, and a trench surrounding the optoelectronic layer is formed in the dielectric layer. Therefore, when the covering layer is formed, the covering layer also fills in the trench. The formation of the trench makes the filling angle around the optoelectronic layer larger, correspondingly improving the filling effect of the covering layer between the dielectric layer and the optoelectronic layer, thereby reducing the probability of generating void defects in the covering layer, and further being beneficial to improving the performance of the semiconductor device (for example, reliability performance). Description of the Drawings

[0010] Figures 1 to 3 are schematic structural diagrams corresponding to each step in a method for forming a semiconductor device;

[0011] Figure 4 is a schematic structural diagram of an embodiment of the semiconductor device of the present invention;

[0012] Figures 5 to 8 are schematic structural diagrams corresponding to each step in an embodiment of the method for forming a semiconductor device of the present invention. Detailed Embodiments

[0013] Currently, the performance of semiconductor devices still needs to be improved. The reason for the performance to be improved is analyzed in combination with a method for forming a semiconductor device.

[0014] Figures 1 to 3 are schematic structural diagrams corresponding to each step in a method for forming a semiconductor device.

[0015] Refer to Figure 1 , a substrate 10 is provided. A dielectric layer 20 is formed on the top of the substrate 10. An opening 15 is formed in the dielectric layer 20. The opening 15 penetrates through the dielectric layer 20 and extends into the substrate 10 with a partial thickness.

[0016] Refer to Figure 2 , an optoelectronic layer 30 is epitaxially grown in the opening 15.

[0017] Refer to Figure 3 , a covering layer 40 covering the dielectric layer 20 and the optoelectronic layer 30 is formed.

[0018] However, as Figure 2 shown, after the optoelectronic layer 30 is formed, affected by the epitaxial growth process, the top surface flatness of the optoelectronic layer 30 is relatively low, and the top surface flatness of the optoelectronic layer 30 and the dielectric layer 20 is also relatively low. It is easy to form a gap between the side walls of the optoelectronic layer 30 and the dielectric layer 20 (as shown by the dashed circle in Figure 2 ).

[0019] Correspondingly, the existence of the gap results in a poor filling effect of the cover layer 40 at the gap position when the cover layer 40 is formed, thereby causing void defects 45 to be generated in the cover layer 40, and further causing the performance (e.g., reliability performance) of the semiconductor device to decline.

[0020] Moreover, considering the high-temperature resistance characteristics of the optoelectronic layer 30 (the optoelectronic layer 30 is usually difficult to withstand high temperatures) and the damage problem of the optoelectronic layer 30, it is difficult to flexibly select the formation process of the cover layer 40 in order to improve the filling effect of the cover layer 40.

[0021] To solve the above technical problems, an embodiment of the present invention provides a method for forming a semiconductor device, including: providing a substrate, forming a dielectric layer on the top of the substrate, forming an opening in the dielectric layer, the opening penetrating the dielectric layer and extending into a part of the thickness of the substrate; forming an optoelectronic layer in the opening; removing a part of the thickness of the dielectric layer on the side of the optoelectronic layer, forming a trench surrounding the optoelectronic layer in the dielectric layer, and the trench exposing the optoelectronic layer; forming a cover layer covering the dielectric layer and the optoelectronic layer, and the cover layer also filling in the trench.

[0022] The formation of the trench increases the filling angle around the optoelectronic layer, correspondingly improving the filling effect of the cover layer between the dielectric layer and the optoelectronic layer, thereby reducing the probability of generating void defects in the cover layer, and further being beneficial to improving the performance (e.g., reliability performance) of the semiconductor device.

[0023] To make the above objects, features, and advantages of the embodiments of the present invention more obvious and understandable, the following will describe in detail the specific embodiments of the present invention with reference to the accompanying drawings.

[0024] Figure 4 is a schematic structural diagram of an embodiment of the semiconductor device of the present invention.

[0025] The semiconductor device includes: a substrate 500; a dielectric layer 600 located on the substrate 500; an opening (not labeled) located in the dielectric layer 600 and the substrate 500, the bottom of the opening being lower than the surface of the substrate 500, and the top of the opening being flush with the top surface of the dielectric layer 600; an optoelectronic layer 700 located in the opening; a trench 650 located in a partial thickness of the dielectric layer 600 on the side of the optoelectronic layer 700, the trench 650 surrounding the optoelectronic layer 700; and a cover layer 800 located in the trench 650 and on the top of the dielectric layer 600.

[0026] The substrate 500 is used to provide a process platform for the formation of the semiconductor device.

[0027] Specifically, the semiconductor device is an optical device.

[0028] As an example, the optical device is a silicon optical device. A silicon optical device is an optical device based on silicon or a silicon-based substrate material.

[0029] Therefore, in this embodiment, the material of the substrate 500 is silicon.

[0030] In some other embodiments, the material of the substrate may also be other types of substrates such as silicon germanide, silicon carbide, or a silicon-on-insulator substrate.

[0031] The opening is used to accommodate the optoelectronic layer 700. Specifically, the opening is used to provide a spatial position for the formation of the optoelectronic layer. The opening penetrates the dielectric layer 600 and extends into a partial thickness of the substrate 500.

[0032] The optoelectronic layer 700 is located in the opening. Correspondingly, the optoelectronic layer 700 is located in the substrate 500, and the top of the optoelectronic layer 700 is higher than the top of the substrate 500.

[0033] In the optical device, the optoelectronic layer 700 serves as a light absorption layer, which is used to detect optical signals and convert the optical signals into electrical signals.

[0034] In this embodiment, the optoelectronic layer 700 is located in a partial thickness of the substrate 500, so as to meet the normal working requirements of the optical device.

[0035] In this embodiment, the material of the optoelectronic layer 700 is a Ge-containing material. The Ge-containing material has high compatibility with the CMOS process.

[0036] As an example, the material of the optoelectronic layer 700 is Ge.

[0037] In this embodiment, the optoelectronic layer 700 is a film layer formed by epitaxial growth, so that the height of the optoelectronic layer 700 can be precisely controlled and the quality of the optoelectronic layer 700 is improved.

[0038] In this embodiment, affected by the epitaxial growth process and the material of the optoelectronic layer 700 (i.e., the Ge-containing material), the top surface of the optoelectronic layer 700 is a convex surface.

[0039] According to the thickness of the dielectric layer 600, the top of the dielectric layer 600 can be flush with the top of the optoelectronic layer 700, or higher than the top of the optoelectronic layer 700, or lower than the top of the optoelectronic layer 700.

[0040] The dielectric layer 600 surrounds the optoelectronic layer 700. The dielectric layer 600 is used to protect the top of the substrate 500 when the optoelectronic layer 700 is formed and confine the optoelectronic layer 700 in the target area (i.e., confined in the opening), thereby preventing the optoelectronic layer 700 from being formed on the top of the substrate 500 outside the target area.

[0041] The material of the dielectric layer 600 is correspondingly a dielectric material. Therefore, when the optoelectronic layer 700 is formed by the epitaxial growth process, the dielectric layer 600 will not serve as the basis for epitaxial growth, thereby ensuring that the surface of the substrate 500 exposed by the dielectric layer 600 serves as the basis for epitaxial growth, and further confining the optoelectronic layer 700 in the target area.

[0042] In this embodiment, the material of the dielectric layer 600 includes one or more of silicon oxide and silicon nitride to improve the process compatibility of the dielectric layer 600.

[0043] As an example, the material of the dielectric layer 600 is silicon oxide. Silicon oxide has good insulation and less stress generated by silicon oxide, which is beneficial to improving process reliability.

[0044] It should be noted that in other embodiments, other suitable dielectric materials can also be selected for the dielectric layer.

[0045] The trench 650 is located in a part of the thickness of the dielectric layer 600 on the side of the optoelectronic layer 700 and surrounds the optoelectronic layer 700. The setting of the trench 650 makes the filling angle around the optoelectronic layer 700 larger, correspondingly improving the filling effect of the cover layer 800 between the dielectric layer 600 and the optoelectronic layer 700, thereby reducing the probability of void defects generated in the cover layer 800, and further being beneficial to improving the performance of the semiconductor device (for example, reliability performance).

[0046] Therefore, in this embodiment, the dielectric layer 600 is located on the substrate 500 at the side of the optoelectronic layer 700. The dielectric layer 600 includes a first sub-dielectric layer 610 that circumferentially covers the sidewall of the optoelectronic layer 700, and a second sub-dielectric layer 620 that circumferentially covers the first sub-dielectric layer 610. The top surface of the first sub-dielectric layer 610 is lower than the top surface of the optoelectronic layer 700 and the top surface of the second sub-dielectric layer 620.

[0047] The provision of the trench 650 makes the top surface of the dielectric layer 600 stepped, and by using the first sub-dielectric layer 610 with a lower top surface, it is beneficial to eliminate the gap between the optoelectronic layer 700 and the dielectric layer 600, increase the filling angle around the optoelectronic layer 700, correspondingly improve the filling effect of the covering layer 800 between the dielectric layer 600 and the optoelectronic layer 700, thereby reducing the probability of void defects generated in the covering layer 800, and further being beneficial to improving the performance of the semiconductor device (for example, reliability performance).

[0048] It should be noted that the first sub-dielectric layer 610 and the second sub-dielectric layer 620 are of an integral structure. Therefore, the process for making the top surface of the dielectric layer 600 stepped is simple. For example, by etching a part of the dielectric layer 600 around the optoelectronic layer 700, the first sub-dielectric layer 610 with a lower top surface is formed.

[0049] Specifically, the top surface of the dielectric layer 600 is stepped, such that the second sub-dielectric layer 620, the first sub-dielectric layer 610, and the optoelectronic layer 700 enclose the trench 650, thereby increasing the filling angle around the optoelectronic layer 700. The covering layer 800 is filled in the trench 650, correspondingly improving the filling effect of the covering layer 800 in the trench 650.

[0050] The distance d1 from the bottom of the trench 650 to the top of the optoelectronic layer 700 should not be too small or too large. That is to say, the distance d1 from the top of the first sub-dielectric layer 610 to the top of the optoelectronic layer 700 should not be too small or too large. If the distance d1 from the bottom of the trench 650 to the top of the optoelectronic layer 700 is too large, that is, the distance d1 from the top of the first sub-dielectric layer 610 to the top of the optoelectronic layer 700 is too large, when the lateral dimension of the trench 650 is fixed (that is, when the width w1 of the first sub-dielectric layer 610 is fixed), it is likely to result in an excessive aspect ratio of the trench 650, thereby reducing the filling effect of the covering layer 800 in the trench 650, increasing the probability of void defects in the covering layer 800. Moreover, it is also likely to result in too small a thickness of the remaining dielectric layer 600 at the bottom of the trench 650 (that is, the thickness of the first sub-dielectric layer 610). Affected by process stability, it is likely to result in poor thickness uniformity of the first sub-dielectric layer 610, thereby increasing the probability of exposing the substrate 500 at the bottom of the trench 650 and correspondingly increasing the probability of damaging the substrate 500. If the distance d1 from the bottom of the trench 650 to the top of the optoelectronic layer 700 is too small, that is, the distance d1 from the top of the first sub-dielectric layer 610 to the top of the optoelectronic layer 700 is too small, it is likely to result in a poor effect of eliminating the gap between the optoelectronic layer 700 and the sidewall of the dielectric layer 600, thus making it difficult to increase the filling angle around the optoelectronic layer 700. Therefore, in this embodiment, the distance d1 from the bottom of the trench 650 to the top of the optoelectronic layer 700 is 100 nanometers to 300 nanometers, that is, the distance d1 from the top of the first sub-dielectric layer 610 to the top of the optoelectronic layer 700 is 100 nanometers to 300 nanometers. For example, the distance d1 from the top of the first sub-dielectric layer 610 to the top of the optoelectronic layer 700 is 150 nanometers, 200 nanometers or 250 nanometers.

[0051] Wherein, the lateral dimension of the trench 650 refers to the dimension of the trench along the direction perpendicular to the sidewall of the trench 650; the width w1 of the first sub-dielectric layer 610 refers to the dimension along the direction perpendicular to the sidewall of the second sub-dielectric layer 620.

[0052] Similarly, along the direction perpendicular to the sidewall of the trench 650, the lateral dimension w1 of the trench 650 should neither be too small nor too large. That is to say, the width w1 of the first sub-dielectric layer 610 should neither be too small nor too large. If the lateral dimension w1 of the trench 650 is too small, that is, the width w1 of the first sub-dielectric layer 610 is too small, it is likely to cause the capping layer 800 to be difficult to fill in the trench 650, and the filling effect of the capping layer 800 in the trench 650 is poor. If the lateral dimension w1 of the trench 650 is too large, that is, the width w1 of the first sub-dielectric layer 610 is too large, it will correspondingly increase the process cost and process time required to form the trench 650. Therefore, in this embodiment, along the direction perpendicular to the sidewall of the trench 650, the lateral dimension w1 of the trench 650 is 400 nanometers to 6000 nanometers, that is, the width w1 of the first sub-dielectric layer 610 is 400 nanometers to 6000 nanometers. For example, the width of the first sub-dielectric layer 610 is 800 nanometers, 1500 nanometers, 2000 nanometers, 3500 nanometers or 5000 nanometers.

[0053] The capping layer 800 correspondingly covers the dielectric layer 600 and the optoelectronic layer 700 and fills in the trench 650.

[0054] The capping layer 800 is used to protect the optoelectronic layer 700, thereby reducing the influence of subsequent processes on the optoelectronic layer 700, and correspondingly ensuring the compatibility between the formation process of the optical device and the CMOS process.

[0055] Specifically, the material of the capping layer 800 includes one or more of silicon oxide, polysilicon and silicon nitride to improve the process compatibility of the capping layer 800.

[0056] As an example, the material of the capping layer 800 is silicon oxide. Silicon oxide has good insulation properties, and the stress generated by silicon oxide is also small, which is beneficial to improving process reliability.

[0057] Among them, by increasing the filling angle around the optoelectronic layer 700, during the formation of the optical device, when the capping layer 800 is formed by a deposition process, the requirement for the filling performance of the deposition process is reduced. Therefore, a suitable deposition process can be selected based on the material characteristics of the optoelectronic layer 700 (for example, not resistant to high temperature). Therefore, it is easy to improve the filling effect of the capping layer 800 between the dielectric layer 600 and the optoelectronic layer 700 while reducing the probability of damage to the optoelectronic layer 300 caused by the deposition process used to form the capping layer 800.

[0058] Figures 5 to 8 It is a schematic structural diagram corresponding to each step in an embodiment of the method for forming a semiconductor device of the present invention.

[0059] Reference Figure 5 Figure 5 , a substrate 100 is provided, a dielectric layer 200 is formed on the top of the substrate 100, an opening 150 is formed in the dielectric layer 200, the opening 150 penetrates through the dielectric layer 200 and extends into the substrate 100 with a partial thickness.

[0060] The substrate 100 is used to provide a process platform for the formation of semiconductor devices.

[0061] Specifically, the semiconductor device is an optical device.

[0062] As an example, the optical device is a silicon optical device. A silicon optical device is an optical device based on silicon or a silicon-based substrate material.

[0063] Therefore, in this embodiment, the material of the substrate 100 is silicon.

[0064] In some other embodiments, the material of the substrate may also be other types of substrates such as silicon germanide, silicon carbide, or silicon-on-insulator substrate.

[0065] The opening 150 is used to form an optoelectronic layer. Specifically, the opening 150 is used to provide a spatial position for the formation of the optoelectronic layer.

[0066] The dielectric layer 200 is used to protect the top of the substrate 100 outside the opening 150, so as to prevent the optoelectronic layer from being formed on the top of the substrate 100 outside the opening 150 when the optoelectronic layer is formed subsequently.

[0067] The material of the dielectric layer 200 is correspondingly a dielectric material. Therefore, when the optoelectronic layer is formed by an epitaxial growth process subsequently, the dielectric layer 200 will not serve as the basis for epitaxial growth, thus ensuring that the surface of the substrate 100 exposed at the bottom and side walls of the opening 150 serves as the basis for epitaxial growth, and further restricting the optoelectronic layer in the opening 150.

[0068] In this embodiment, the material of the dielectric layer 200 includes one or more of silicon oxide and silicon nitride to improve the process compatibility of the dielectric layer 200.

[0069] As an example, the material of the dielectric layer 200 is silicon oxide. Silicon oxide has good insulation properties, and the stress generated by silicon oxide is also small, which is beneficial to improving process reliability.

[0070] In this embodiment, the thickness of the dielectric layer 200 is greater than the preset height of the optoelectronic layer above the substrate 100, so that after the optoelectronic layer is formed subsequently, the top of the dielectric layer 200 is higher than the top of the optoelectronic layer, and further restricts the optoelectronic layer in the opening 150 to ensure the morphology of the optoelectronic layer.

[0071] In other embodiments, the thickness of the dielectric layer may also be less than or equal to a preset height of the optoelectronic layer above the substrate.

[0072] As an example, after forming the dielectric layer 200 covering the top of the substrate 100, the dielectric layer 200 and a part of the thickness of the substrate 100 are etched in sequence to form the opening 150.

[0073] Reference Figure 6 , an optoelectronic layer 300 is formed in the opening 150 (as Figure 5 shown).

[0074] In the optical device, the optoelectronic layer 300 serves as a light absorption layer for detecting an optical signal and converting the optical signal into an electrical signal.

[0075] In this embodiment, in the step of forming the optoelectronic layer 300 in the opening 150, the material of the optoelectronic layer 300 is a Ge-containing material. The Ge-containing material has high compatibility with the CMOS process.

[0076] As an example, the material of the optoelectronic layer 300 is Ge.

[0077] In this embodiment, an epitaxial growth process is adopted to form the optoelectronic layer 300 in the opening 150.

[0078] The process controllability of the epitaxial growth process is relatively high, which is beneficial to precisely controlling the height of the optoelectronic layer 300; moreover, during the epitaxial growth process, taking the substrate 100 exposed by the opening 150 as the growth basis, it is easy to form an optoelectronic layer 300 with fewer impurities, thereby improving the quality of the optoelectronic layer 300.

[0079] It should be noted that according to the process requirements, the height of the optoelectronic layer 300 above the substrate 100 has a preset height H.

[0080] In this embodiment, since the thickness of the dielectric layer 200 is greater than the preset height of the optoelectronic layer above the substrate 100, after forming the optoelectronic layer 300, the top of the optoelectronic layer 300 is lower than the top of the dielectric layer 200.

[0081] In some other embodiments, when the thickness of the dielectric layer is less than the preset height of the optoelectronic layer above the substrate, after forming the optoelectronic layer, the top of the optoelectronic layer is higher than the top of the dielectric layer.

[0082] In other embodiments, when the thickness of the dielectric layer is equal to the preset height of the optoelectronic layer above the substrate, after forming the optoelectronic layer, the top of the optoelectronic layer is flush with the top of the dielectric layer.

[0083] It should also be noted that due to the influence of the epitaxial growth process and the material of the optoelectronic layer 300 (i.e., the Ge-containing material), the top surface of the optoelectronic layer 300 is a convex surface.

[0084] Correspondingly, since the top surface of the optoelectronic layer 300 is a convex surface, a gap 301 is likely to be formed between the optoelectronic layer 300 and the side wall of the opening 150.

[0085] Reference Figure 7 , remove a part of the thickness of the dielectric layer 200 on the side of the optoelectronic layer 300, and form a trench 250 surrounding the optoelectronic layer 300 in the dielectric layer 200, and the trench 250 exposes the optoelectronic layer 300.

[0086] The formation of the trench 250 increases the filling angle around the optoelectronic layer 300. Correspondingly, when forming a covering layer covering the dielectric layer 200 and the optoelectronic layer 300 subsequently, the filling effect of the covering layer between the dielectric layer 200 and the optoelectronic layer 300 is improved, thereby reducing the probability of void defects generated in the covering layer, and further facilitating the improvement of the performance of the semiconductor device (for example, reliability performance).

[0087] Moreover, by removing a part of the thickness of the dielectric layer 200, the remaining dielectric layer 200 still plays a protective role for the substrate 100, thereby reducing the probability of damage to the substrate 100 caused by the formation of the trench 250, and further facilitating the improvement of the performance of the semiconductor device.

[0088] Specifically, the step of forming the trench 250 includes: performing maskless etching on the dielectric layer 200 by using a wet etching process.

[0089] By selecting maskless etching, the photomask is omitted, thereby reducing the process cost.

[0090] Moreover, the wet etching process has the characteristic of isotropic etching, which not only produces vertical etching but also produces lateral etching. Since the optoelectronic layer 300 covers a part of the side wall of the dielectric layer 200 after the optoelectronic layer 300 is formed in the opening 150 (as Figure 5 shown), when performing vertical etching on the top of the dielectric layer 200, lateral etching is also performed on the side wall of the dielectric layer 200 exposed by the optoelectronic layer 300, thereby forming a trench 250 surrounding the optoelectronic layer 300 in the dielectric layer 200, which is equivalent to increasing the lateral dimension of the remaining opening 150 exposed by the optoelectronic layer 300.

[0091] In addition, compared with the dry etching process, the wet etching process causes less damage to the optoelectronic layer 300.

[0092] Correspondingly, in this embodiment, the thickness of the dielectric layer 200 after forming the trench 250 is less than the thickness of the dielectric layer 200 before forming the trench 250. That is to say, in the step of forming the dielectric layer 200, the dielectric layer 200 has a first thickness, and in the step of forming the trench 250, the dielectric layer 200 has a second thickness, and the second thickness is less than the first thickness.

[0093] It should be noted that since the top of the optoelectronic layer 300 is lower than the top of the dielectric layer 200 before forming the trench 250, this provides sufficient etching margin for etching the dielectric layer 200. After using an isotropic etching process to etch the dielectric layer 200 to form the trench 250, the probability of exposing the substrate 100 is relatively low.

[0094] In this embodiment, the etching solution used in the wet etching process includes a diluted hydrofluoric acid solution (DHF). The diluted hydrofluoric acid solution has a small etching rate for the optoelectronic layer 300, thereby reducing the damage to the optoelectronic layer 300.

[0095] In other embodiments, according to process requirements, a mask layer with a mask opening may also be formed on the top of the dielectric layer. The mask opening surrounds the optoelectronic layer and exposes the optoelectronic layer and a partial width of the dielectric layer outside the opening; after forming the mask layer, the dielectric layer with a partial thickness is etched along the mask opening to form a trench.

[0096] It should also be noted that when the second dielectric layer is formed subsequently, the covering layer also fills the trench 250. Therefore, the aspect ratio of the trench 250 affects the filling effect of the covering layer in the trench 250.

[0097] The distance d2 from the bottom of the trench 250 to the top of the optoelectronic layer 300 should neither be too small nor too large. If the distance d2 from the bottom of the trench 250 to the top of the optoelectronic layer 300 is too large, given a certain lateral dimension of the trench 250, it is likely to result in an excessive aspect ratio of the trench 250, thereby reducing the filling effect of the covering layer within the trench 250. In the area corresponding to the trench 250, the probability of void defects occurring in the covering layer becomes higher. Moreover, it is also likely to cause the thickness of the remaining dielectric layer 200 at the bottom of the trench 250 to be too small. Affected by process stability, the probability of the bottom of the trench 250 exposing the substrate 100 increases, correspondingly leading to a higher probability of damage to the substrate 100. If the distance d2 from the bottom of the trench 250 to the top of the optoelectronic layer 300 is too small, it is likely to result in a poor effect of eliminating the gap 301 between the optoelectronic layer 300 and the sidewall of the opening 150, thus making it difficult to increase the filling angle around the optoelectronic layer 300. Moreover, when the trench 250 is formed using an isotropic etching process (e.g., wet etching process), the distance from the bottom of the trench 250 to the top of the optoelectronic layer and the lateral dimension of the trench 250 affect each other, correspondingly resulting in too small a lateral dimension of the trench 250, thereby reducing the filling effect of the covering layer within the trench 250. Therefore, in this embodiment, the distance d2 from the bottom of the trench 250 to the top of the optoelectronic layer 300 is 100 nanometers to 300 nanometers. For example, the distance d2 from the bottom of the trench 250 to the top of the optoelectronic layer 300 is 150 nanometers, 200 nanometers, or 250 nanometers.

[0098] Wherein, the lateral dimension of the trench 250 refers to the dimension along the direction perpendicular to the sidewall of the trench 250.

[0099] Similarly, the lateral dimension w2 of the trench 250 should neither be too small nor too large. If the lateral dimension w2 of the trench 250 is too small, it is likely to cause difficulty in filling the covering layer within the trench 250, and the filling effect of the covering layer within the trench 250 is poor. If the lateral dimension w2 of the trench 250 is too large, it correspondingly leads to an increase in the process cost and process time required to form the trench 250. Moreover, when the trench 250 is formed using an isotropic etching process (e.g., wet etching process), it correspondingly causes the distance d2 from the bottom of the trench 250 to the top of the optoelectronic layer 300 to be too large. Therefore, in this embodiment, the lateral dimension of the trench 250 is 400 nanometers to 6000 nanometers. For example, the lateral dimension of the trench 250 is 800 nanometers, 1500 nanometers, 2000 nanometers, 3500 nanometers, or 5000 nanometers.

[0100] In addition, according to the initial thickness of the dielectric layer 200 and the etching amount of the dielectric layer 200, after the trench 250 is formed, the top of the remaining dielectric layer 200 can be flush with the top of the optoelectronic layer 300, or higher than the top of the optoelectronic layer 300, or lower than the top of the optoelectronic layer 300.

[0101] Reference Figure 8 , a covering layer 400 covering the dielectric layer 200 and the optoelectronic layer 300 is formed, and the covering layer 400 also fills the trench 250.

[0102] The covering layer 400 is used to protect the optoelectronic layer 300, thereby reducing the influence of subsequent processes on the optoelectronic layer 300, and correspondingly ensuring the compatibility between the forming process of the optical device and the CMOS process.

[0103] Specifically, the material of the covering layer 400 includes one or more of silicon oxide, polysilicon, and silicon nitride to improve the process compatibility of the covering layer 400.

[0104] As an example, the material of the covering layer 400 is silicon oxide. Silicon oxide has good insulation and relatively small stress generated, which is beneficial to improving process reliability.

[0105] Specifically, a covering layer 400 covering the dielectric layer 200 and the optoelectronic layer 300 is formed by chemical vapor deposition.

[0106] As an example, the chemical vapor deposition process is a plasma-enhanced chemical vapor deposition (PECVD) process. PECVD uses a radio frequency power supply to generate glow discharge to transfer energy to the reaction gas, allowing deposition on the substrate at a lower temperature. PECVD has ideal properties on the substrate, such as good adhesion, low pinhole density, and good step coverage.

[0107] Among them, the formation of the trench 250 reduces the requirements for the filling performance of the deposition process during the formation of the covering layer 400, so that a suitable deposition process can be selected based on the material characteristics of the optoelectronic layer 300 (for example, not resistant to high temperature), and the damage to the optoelectronic layer 300 can be reduced.

[0108] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be subject to the scope defined by the claims.

Claims

1. A semiconductor device, characterized in that, Comprising: A substrate; A dielectric layer located on the substrate; An opening located in the dielectric layer and the substrate, the bottom of the opening being lower than the substrate surface, and the top of the opening being flush with the top surface of the dielectric layer; An optoelectronic layer located in the opening; A groove located in a part of the thickness of the dielectric layer on the side of the optoelectronic layer, the groove surrounding the optoelectronic layer, and the groove being obtained by removing a part of the thickness of the dielectric layer on the side of the optoelectronic layer; A cover layer located in the groove and on the top of the dielectric layer.

2. The semiconductor device according to claim 1, wherein The material of the optoelectronic layer includes Ge.

3. The semiconductor device according to claim 1, wherein Along the direction perpendicular to the sidewall of the groove, the lateral dimension of the groove is 400 nanometers to 6000 nanometers.

4. The semiconductor device according to claim 1, wherein, The distance from the bottom of the groove to the top of the optoelectronic layer is 100 nanometers to 300 nanometers.

5. The semiconductor device according to claim 1, wherein, The top surface of the optoelectronic layer is a convex surface.

6. The semiconductor device according to claim 1, wherein, The material of the substrate includes silicon, silicon germanide, silicon carbide, or silicon on insulator.

7. The semiconductor device according to claim 1, wherein The material of the dielectric layer includes one or more of silicon oxide and silicon nitride.

8. The semiconductor device according to claim 1, wherein, The material of the cover layer includes one or more of silicon oxide, polysilicon, and silicon nitride.

9. A method for forming a semiconductor device, characterized in that, Comprising: Providing a substrate, on the top of which a dielectric layer is formed, an opening is formed in the dielectric layer, the opening penetrates the dielectric layer and extends into a part of the thickness of the substrate; Forming an optoelectronic layer in the opening; Removing a part of the thickness of the dielectric layer on the side of the optoelectronic layer to form a groove surrounding the optoelectronic layer in the dielectric layer, and the groove exposes the optoelectronic layer; Forming a cover layer covering the dielectric layer and the optoelectronic layer, and the cover layer also fills the groove.

10. The method for forming a semiconductor device according to claim 9, wherein, Using an epitaxial growth process to form the optoelectronic layer.

11. The method for forming a semiconductor device according to claim 9, wherein, In the step of forming the optoelectronic layer in the opening, the material of the optoelectronic layer includes Ge.

12. The method for forming a semiconductor device according to claim 9, wherein, In the step of forming the optoelectronic layer in the opening, the top of the optoelectronic layer is lower than the top of the dielectric layer.

13. The method for forming a semiconductor device according to claim 9, wherein, In the step of forming the groove, the distance from the bottom of the groove to the top of the optoelectronic layer is 100 nanometers to 300 nanometers.

14. The method for forming a semiconductor device according to claim 9, wherein, In the step of forming the groove, along the direction perpendicular to the sidewall of the groove, the lateral dimension of the groove is 400 nanometers to 6000 nanometers.

15. The method for forming a semiconductor device according to claim 9, wherein The step of forming the groove includes: performing maskless etching on the dielectric layer using a wet etching process.

16. The method for forming a semiconductor device according to claim 15, wherein, The etching solution used in the wet etching process includes a diluted hydrofluoric acid solution.

17. The method for forming a semiconductor device according to claim 9, wherein, Forming a cover layer covering the dielectric layer and the optoelectronic layer by chemical vapor deposition process.

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