A structured chip design architecture and method

Abstract

The present invention relates to a structured chip design architecture and method, which includes a segmentation component, an idle state signal adding component, a clock generation component and a clock tree synthesis component; the segmentation component is used to perform appropriate module segmentation and hierarchical segmentation on each submodule of each IP module of the chip; the idle state signal adding component is used to add a module idle state signal to each submodule; the clock generation component is used to call a clock gating unit before each submodule, generate a gated clock according to the corresponding module idle state signal and send it to the corresponding submodule; the clock tree synthesis component is used to, during clock tree synthesis, output a segmented long clock tree from the clock of the clock gating unit according to the idea of ​​segmenting a long clock tree.

Description

Technical Field

[0001] The present invention relates to the technical field of low-power design of chips, and in particular to a low-power design architecture and method for a SoC chip system and / or IP module structure. Background Art

[0002] With the increasing popularity of mobile devices, the limitation of battery capacity development speed and people's increasing requirements for green environmental protection, the research on ultra-low power design architecture and methods of chips has received more and more attention.

[0003] Excellent ultra-low power design can not only improve the reliability problem of the chip caused by heat, but also reduce the heat dissipation requirements of the chip package and the cooling system, which means the reduction of system cost. As we all know, there are many methods for ultra-low power design. According to empirical statistics, clock power consumption accounts for about 60% of the power consumption of the entire system. Traditional methods for optimizing clock power consumption include: 1. The clock management part in the power management module is for each IP module (such as Figure 1 CPU processor module, display controller module, etc.) respectively generate one or more clocks (such as Figure 1 GCLK0, GCLK1, etc.) are sent to the corresponding module. When the corresponding module is not working, the software will turn off the clock corresponding to the corresponding module to reduce the power consumption of this module when it is not in use. Second, use the logic synthesis tool to automatically insert the clock gating unit (ICG) to the front of the corresponding register group according to the logical condition status of the register group (FF group) (such as Figure 3 As shown), to reduce the power consumption of these register groups (FF groups).

[0004] During the clock tree synthesis of the physical implementation of the chip, due to the load value limit of the physical circuit fanout (a clock circuit unit can only push a certain number of clock circuit units at the next level) and the timing balance requirement (the delay from the clock starting point to each register clock port (pin) should be as equal as possible), after the clock tree synthesis, the entire clock network will become an inverted tree structure (such as Figure 2 As shown, Figure 2 Only the clock tree diagram of the CPU processor module is shown, and the clock tree diagram of other modules is similar. Figure 2 It can be seen that the large number of clock buffers (BUFs) inserted due to clock tree synthesis are constantly switching and consuming power. The more FF groups (register groups) a SoC chip or IP module has, the more clock BUFs are required, and the more power these uncontrolled clock BUFs consume.

[0005] The prior art has not proposed a technical solution that can solve the problem of large amounts of power consumption due to a large number of clock BUFs inserted during clock tree synthesis. Summary of the Invention

[0006] The present invention aims to provide a structured chip design architecture and method to solve the problem in the prior art that a large number of clock BUFs inserted during clock tree synthesis consume a large amount of power.

[0007] The purpose of the present invention is to address the deficiencies of the prior art and provide a structured chip design architecture, including a segmentation component, an idle state signal addition component, a clock generation component and a clock tree synthesis component; the segmentation component is used to perform appropriate module segmentation and hierarchical segmentation on each sub-module of each IP module of the chip; the idle state signal addition component is used to add a module idle state signal to each sub-module; the clock generation component is used to call a clock gating unit before each sub-module, generate a gated clock according to the corresponding module idle state signal and send it to the corresponding sub-module; the clock tree synthesis component is used to, during clock tree synthesis, output a segmented long clock tree from the clock of the clock gating unit according to the idea of ​​segmenting a long clock tree.

[0008] Preferably, the appropriate module segmentation specifically refers to merging submodules with similar functions into the same module, and limiting the number of register groups and FF groups of each submodule to 200.

[0009] Preferably, the hierarchical segmentation specifically refers to nesting each submodule into multiple levels of submodules according to the rules of logical function nesting.

[0010] Preferably, for a module having multiple sub-modules nested therein, the idle state signal of the module is the “AND” of the idle state signals of the multiple sub-modules therein.

[0011] Preferably, the idea of ​​segmented long clock tree is to insert the clock BUF in segments from the clock output of the clock gating unit, and each clock BUF is inserted after the clock gating unit as much as possible.

[0012] Preferably, the IP module includes a CPU processor module, a display controller module, an IO controller module, a memory module and / or a DSP processor module.

[0013] Preferably, the chip is a SoC chip system.

[0014] The present invention also provides a method for reducing power consumption of a structured chip design architecture, comprising the following steps:

[0015] The first step is to design and optimize each IP module of the chip, and perform appropriate module segmentation and hierarchical segmentation on each submodule of the IP module. The appropriate module segmentation specifically refers to merging submodules with similar functions into the same module and limiting the number of register groups and FF groups of each submodule to 200. The hierarchical segmentation specifically refers to nesting each submodule into multiple levels of submodules according to the rules of logical function nesting.

[0016] The second step is to add a module idle state signal to each submodule. For a module with multiple submodules nested inside it, the module idle state signal is the "AND" of the idle state signals of the multiple submodules inside it.

[0017] The third step is to call the clock gating unit before each submodule, generate a gated clock according to the corresponding module idle state signal and send it to the corresponding submodule;

[0018] Step 4: During clock tree synthesis, according to the idea of ​​segmented long clock tree, segment the long clock tree from the clock output of the clock gating unit, insert the clock BUF in segments, and try to insert each clock BUF after the clock gating unit;

[0019] Each IP module, submodule and corresponding clock tree of the chip can automatically shut down unnecessary circuits according to the idle state of the circuit, thereby reducing power consumption.

[0020] Preferably, the present invention also provides applications of the structured chip design architecture in clock gating, power domain and / or voltage domain.

[0021] Preferably, the present invention also provides application of the power consumption reduction method of the structured chip design architecture in clock gating, power domain and / or voltage domain.

[0022] Beneficial effects

[0023] Compared with the prior art, the present invention has the following beneficial effects:

[0024] The structured chip design architecture and method described in the present invention enable each IP module, sub-module, and corresponding clock tree of the entire SoC system to automatically shut down circuits that do not need to work at a certain moment in a multi-granular manner (multi-granularity here refers to the multi-granularity of coarse and fine granularity levels of different module levels) according to the idle state of the circuit, thereby minimizing power consumption.

[0025] Although the specific embodiments of the present invention use clock gating as an example to illustrate the structured low-power architecture and method, those skilled in the art can extend the structured design architecture and method to power domains, voltage domains, or a combination of the three. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The accompanying drawings are used to provide a further understanding of the technical solution of the present invention and constitute a part of the specification. Together with the specific embodiments of the present application, they are used to explain the technical solution of the present invention and do not constitute a limitation on the technical solution of the present invention.

[0027] Figure 1 This is a diagram of the SoC chip system clock architecture in the prior art.

[0028] Figure 2 This is a diagram of the system clock tree structure of a SoC chip in the prior art.

[0029] Figure 3 This is a schematic diagram of a module (hierarchical leaf) clock tree in the prior art.

[0030] Figure 4 This is a diagram of the SoC chip system clock architecture in the present invention.

[0031] Figure 5 This is a diagram of the SoC chip system clock tree structure in the present invention. DETAILED DESCRIPTION

[0032] The present invention is described in more detail below to facilitate understanding of the present invention.

[0033] The structured chip design architecture described in the present invention includes a splitting component, an idle state signal adding component, a clock generation component and a clock tree synthesis component; the splitting component is used to perform appropriate module splitting and hierarchical splitting on each sub-module of each IP module of the chip; the idle state signal adding component is used to add a module idle state signal (xxx_idle) to each sub-module; the clock generation component is used to call a clock gating unit (ICG) before each sub-module, generate a gated clock according to the corresponding module idle state signal and send it to the corresponding sub-module; the clock tree synthesis component is used to, when synthesizing the clock tree, output a segmented long clock tree from the clock of the clock gating unit (ICG) according to the idea of ​​segmenting the long clock tree.

[0034] Preferably, the appropriate module segmentation specifically refers to merging submodules with similar functions into the same module, and limiting the number of register groups and FF groups of each submodule to about 200.

[0035] Preferably, the hierarchical segmentation specifically refers to the rule of logical function nesting (referring to the rule of segmenting functional modules of different functional granularities such as large, medium and small, with the result that each large functional module is nested to contain one or several medium functional modules, and each medium functional module is nested to contain one or several small-scale functional modules. Figure 1 and Figure 2As shown, the entire chip is divided into multiple IP functional modules, and each IP functional module is further divided into levels 1, 2, 3... to leaf modules, etc.) and each sub-module is nested in multiple levels of sub-modules.

[0036] Preferably, for a module having multiple sub-modules nested therein, the idle state signal of the module is the “AND” of the idle state signals of the multiple sub-modules therein.

[0037] Preferably, the idea of ​​segmented long clock tree (as follows Figure 2 and Figure 3 The default long clock tree rule for clock tree synthesis is to automatically grow from the clock tree's starting point (root clock) to the clock input of the register group (FF group) of the hierarchical leaf module. Clock BUFs (clock buffers) are inserted arbitrarily throughout the entire clock path. A segmented long clock tree tells the clock tree synthesis tool to insert a specific clock BUF (clock buffer) between two clock gating cells (ICGs) or between a clock gating cell (ICG) and the clock input of the register group (FF group). A segmented long clock tree from the clock output of the clock gating cell (ICG) specifically refers to the segmented insertion of clock buffers, with each clock buffer inserted as far as possible after the clock gating cell (ICG).

[0038] like Figure 4 This is a diagram of the SoC system clock architecture in which a clock gating unit (ICG) is inserted before each IP module and the modules within the IP module. Figure 5 This diagram shows the clock tree structure of the clock gating unit (ICG) controlling the clock tree BUF after physical clock tree synthesis. This allows each IP module, submodule, and corresponding clock tree (BUF) in the entire SoC chip system to automatically shut down unused circuits at multiple levels and granularity based on the circuit's idle state, minimizing power consumption.

[0039] Preferably, the IP module includes a CPU processor module, a display controller module, an IO controller module, a memory module and / or a DSP processor module.

[0040] Preferably, the chip is a SoC chip system.

[0041] The present invention also provides a method for reducing power consumption of a structured chip design architecture, comprising the following steps:

[0042] The first step is to design and optimize each IP module, perform appropriate module segmentation (combining modules with similar functions into the same module, and limiting the number of register groups and FF groups in each submodule to approximately 200) and hierarchical segmentation (nesting each submodule into multiple levels according to the rules of logical function nesting);

[0043] The second step is to add a module idle state signal (xxx_idle) to each submodule. The idle state signal of a module with multiple nested submodules is the "AND" of the idle state signals of the multiple submodules inside it.

[0044] The third step is to call the clock gating unit (ICG) before each sub-module, generate a gated clock according to the idle state signal of the corresponding module and send it to the corresponding sub-module. The IP module is also processed similarly.

[0045] Step 4: During clock tree synthesis, according to the idea of ​​segmented long clock tree, the clock output of the clock gating unit (ICG) is segmented long clock tree (segmented insertion of clock BUF, each clock BUF is inserted after the ICG as much as possible);

[0046] In this way, each IP module, sub-module, and corresponding clock tree (BUF) of the entire SoC chip system can automatically shut down the circuits that do not need to work at a certain moment in a multi-granular and multi-level manner according to the idle state of the circuit, thereby reducing power consumption to a minimum.

[0047] The above embodiments of the present invention use clock gating as an example to illustrate the structured low-power architecture and method. However, those skilled in the art can extend the structured design architecture and method to power domains, voltage domains, or a combination of the three.

[0048] The preferred embodiments of the present invention are described above, but they are not intended to limit the present invention. Those skilled in the art may make improvements and changes to the embodiments disclosed herein without departing from the scope and spirit of the present invention.

Claims

1. Application of a structured chip design architecture in clock gating, power domain and / or voltage domain, characterized in that: The structured chip design architecture includes a splitting component, an idle state signal adding component, a clock generation component, and a clock tree synthesis component; the splitting component is used to perform appropriate module splitting and hierarchical splitting on each submodule of each IP module of the chip; the idle state signal adding component is used to add a module idle state signal to each submodule; the clock generation component is used to call a clock gating unit before each submodule, generate a gated clock according to the corresponding module idle state signal, and send it to the corresponding submodule; the clock tree synthesis component is used to, during clock tree synthesis, output a segmented long clock tree from the clock of the clock gating unit according to the idea of ​​segmented long clock tree; The IP module includes a CPU processor module, a display controller module, an IO controller module, a memory module and / or a DSP processor module; The chip is a SoC chip system; For a module that has multiple submodules nested inside it, the module's idle state signal is the "AND" of the idle state signals of the multiple submodules inside it; The idea of ​​segmented long clock tree is to insert clock buffers in segments from the clock output of the clock gating unit, and each clock buffer is inserted after the clock gating unit as much as possible. The appropriate module segmentation specifically refers to merging submodules with similar functions into the same module and limiting the number of register groups and FF groups of each submodule to 200.

2. Application of the structured chip design architecture according to claim 1 in clock gating, power domain and / or voltage domain, characterized in that: The hierarchical segmentation specifically refers to the nesting of each submodule into multiple levels of submodules according to the rules of logical function nesting.

3. A method for reducing power consumption of a structured chip design architecture in clock gating, power domain and / or voltage domain, characterized in that: The structured chip design architecture includes a splitting component, an idle state signal adding component, a clock generation component, and a clock tree synthesis component; the splitting component is used to perform appropriate module splitting and hierarchical splitting on each submodule of each IP module of the chip; the idle state signal adding component is used to add a module idle state signal to each submodule; the clock generation component is used to call a clock gating unit before each submodule, generate a gated clock according to the corresponding module idle state signal, and send it to the corresponding submodule; the clock tree synthesis component is used to, during clock tree synthesis, output a segmented long clock tree from the clock of the clock gating unit according to the idea of ​​segmented long clock tree; The method for reducing power consumption of the structured chip design architecture includes the following steps: The first step is to design and optimize each IP module of the chip, and perform appropriate module segmentation and hierarchical segmentation on each submodule of the IP module. The appropriate module segmentation specifically refers to merging submodules with similar functions into the same module and limiting the number of register groups and FF groups of each submodule to 200. The hierarchical segmentation specifically refers to nesting each submodule into multiple levels of submodules according to the rules of logical function nesting. The second step is to add a module idle state signal to each submodule. For a module with multiple nested submodules, the module idle state signal is the "AND" of the idle state signals of the multiple submodules inside it. The third step is to call the clock gating unit before each submodule, generate a gated clock according to the corresponding module idle state signal and send it to the corresponding submodule; Step 4: During clock tree synthesis, according to the idea of ​​segmented long clock tree, the clock tree is segmented from the clock output of the clock gating unit, and the clock buffer is inserted segmented. Each clock buffer is inserted after the clock gating unit as much as possible. Each IP module, submodule and corresponding clock tree of the chip can automatically shut down unnecessary circuits according to the idle state of the circuit, thereby reducing power consumption.

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