A vivado project RTL code extraction method and device

Abstract

This application relates to a method and apparatus for extracting RTL code from a Vivado project, belonging to the field of FPGA software verification technology. The method includes the following steps: S1, obtaining a preset Vivado project specified simulation path and an RTL code pre-storage path; reading the data lines containing RTL code from the *_compile.do file in the specified Vivado project simulation path and storing them in a preset storage file; modifying the DOS system recognition path of the preset storage file containing the RTL code data lines to a Windows system recognition path; and copying the RTL code to the RTL code pre-storage path based on the Windows system recognition path of the preset storage file. This application extracts RTL code from a Vivado project and performs corresponding configuration work, exhibiting high versatility and providing convenience for subsequent simulation work.

Description

Technical Field

[0001] This application relates to the field of FPGA software verification technology, specifically to a method and apparatus for extracting RTL code from a Vivado project. Background Technology

[0002] Verification and testing are crucial stages in the FPGA software project lifecycle. FPGA software testing and verification are divided into pre-simulation and post-simulation. The main purpose of testing and verification is to confirm whether the software fully implements the functions described in the design document. Pre-simulation of FPGA software is a behavioral-level simulation performed on the RTL code.

[0003] With the advancement of technology, FPGA software engineering projects are becoming increasingly large-scale. A single large FPGA project can have hundreds of RTL code modules, totaling tens of thousands or even hundreds of thousands of lines of code. Extracting the simulation RTL code is an essential step in FPGA software testing, crucial for calculating code size and building a simulation test platform.

[0004] Currently, when simulating Vivado projects, the required simulation RTL code is often extracted manually. This method is time-consuming, prone to errors, and prone to omissions.

[0005] Therefore, this paper proposes an efficient and fast method for extracting RTL code from Vivado projects to meet current RTL code extraction needs and overcome the problems of manual extraction methods. This method extracts RTL code from Vivado-based development projects for FPGA functional simulation, which results in high manpower and time costs for FPGA project verification and testing. Therefore, there is an urgent need to design an automated method to solve the above problems. Summary of the Invention

[0006] This application provides a method and apparatus for extracting RTL code from a Vivado project. Based on a pre-defined path, the RTL code of the Vivado project is extracted and corresponding configuration is performed. It has high versatility and can provide convenience for subsequent simulation work.

[0007] To achieve the above objectives, this application provides the following solution.

[0008] Firstly, this application provides a method for extracting RTL code from a Vivado project, the method comprising the following steps:

[0009] Obtain the preset simulation path of the Vivado project and the pre-stored path of the RTL code;

[0010] Read the data lines containing RTL code from the *_compile.do file in the specified simulation path of the Vivado project and store them in a preset storage file;

[0011] Change the default storage path for the data file containing RTL code from the DOS system recognition path to the Windows system recognition path;

[0012] Based on the Windows system recognition path for the preset storage file, the RTL code is copied to the preset RTL code storage path.

[0013] Furthermore, the data lines containing RTL code in the *_compile.do file of the specified simulation path in the Vivado project are read and stored in a preset storage file, including the following steps:

[0014] Iterate through the files in the specified simulation path of the Vivado project and search for the *_compile.do file;

[0015] Iterate through each line of the *_compile.do file, retrieve the data lines containing RTL code from the *_compile.do file, and store them in a preset storage file.

[0016] Furthermore, after reading the data lines containing RTL code from the *_compile.do file in the specified simulation path of the Vivado project and storing them in a preset storage file, and before modifying the DOS system recognition path of the preset storage file containing the data lines containing RTL code to the Windows system recognition path, the method includes the following steps:

[0017] Delete invalid characters from the preset storage file.

[0018] Furthermore, after copying the RTL code to the pre-stored RTL code path based on the Windows system identification path of the preset storage file, the method further includes the following steps:

[0019] Obtain the preset IP simulation file storage path;

[0020] Copy the IP simulation files required for the simulation to the IP simulation file storage path.

[0021] Specifically, the preset storage file is a txt file.

[0022] Secondly, this application provides an RTL code extraction device for a Vivado project, the device comprising:

[0023] The path acquisition module is used to obtain the preset simulation path of the Vivado project and the pre-stored path of the RTL code;

[0024] The code reading module is used to read the data lines containing RTL code from the *_compile.do file in the specified simulation path of the Vivado project and store them in a preset storage file;

[0025] The path modification module is used to change the DOS system-recognized path of the preset storage file containing data lines of RTL code to the Windows system-recognized path.

[0026] The code import module is used to copy RTL code to the pre-stored RTL code path based on the Windows system identification path of the preset storage file.

[0027] Furthermore, the code reading module is also used to traverse the files under the specified simulation path of the Vivado project to find the *_compile.do file;

[0028] The code reading module is also used to traverse each line of the *_compile.do file, obtain the data lines containing RTL code in the *_compile.do file, and store them in a preset storage file.

[0029] Furthermore, the code reading module is also used to delete invalid characters in the preset storage file.

[0030] Furthermore, the device also includes a simulated file reading module;

[0031] The simulation file reading module is used to obtain the preset IP simulation file storage path;

[0032] The simulation file reading module is used to copy the IP simulation files required for simulation to the IP simulation file storage path.

[0033] Furthermore, the preset storage file is a txt file.

[0034] The beneficial effects of the technical solution provided in this application include:

[0035] This application extracts the RTL code of the Vivado project based on a pre-defined path and performs corresponding configuration work, which has high versatility and can provide convenience for subsequent simulation work. Attached Figure Description

[0036] Terminology Explanation:

[0037] FPGA: Field Programmable Gate Array;

[0038] IP: Internet Protocol.

[0039] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0040] Figure 1 This is a flowchart illustrating the steps of the Vivado project RTL code extraction method provided in this application embodiment;

[0041] Figure 2 This is a structural block diagram of the RTL code extraction device for the Vivado project provided in the embodiments of this application. Detailed Implementation

[0042] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0043] The embodiments of this application will be further described in detail below with reference to the accompanying drawings.

[0044] This application provides a method and apparatus for extracting RTL code from a Vivado project. Based on a pre-defined path, the RTL code of the Vivado project is extracted and corresponding configuration is performed. This method has high versatility and can facilitate subsequent simulation work.

[0045] To achieve the aforementioned technical effects, the overall concept of this application is as follows:

[0046] A method for extracting RTL code from a Vivado project, comprising the following steps:

[0047] S1. Obtain the preset simulation path of the Vivado project and the pre-stored path of the RTL code;

[0048] S2. Read the data lines containing RTL code from the *_compile.do file in the specified simulation path of the Vivado project and store them in a preset storage file;

[0049] S3. Change the DOS system recognition path of the preset storage file containing data lines of RTL code to the Windows system recognition path;

[0050] S4. Based on the Windows system recognition path of the preset storage file, copy the RTL code to the RTL code pre-storage path.

[0051] The embodiments of this application will be further described in detail below with reference to the accompanying drawings.

[0052] See Figure 1 As shown in the figure, this application provides a method for extracting RTL code from a Vivado project, which includes the following steps:

[0053] S1. Obtain the preset simulation path of the Vivado project and the pre-stored path of the RTL code;

[0054] S2. Read the data lines containing RTL code from the *_compile.do file in the specified simulation path of the Vivado project and store them in a preset storage file;

[0055] S3. Change the DOS system recognition path of the preset storage file containing data lines of RTL code to the Windows system recognition path;

[0056] S4. Based on the Windows system recognition path of the preset storage file, copy the RTL code to the RTL code pre-storage path.

[0057] It should be noted that the technical solution of this application embodiment provides a method for quickly extracting RTL code and library files for simulation from a Vivado project in an automated manner;

[0058] In the field of FPGA software verification technology, there is often a need to independently simulate Vivado development software using Questsim simulation software. In this case, the RTL code of the Vivado project is a necessary file.

[0059] FPGA verification engineers often manually extract and copy the RTL code of a Vivado project one by one.

[0060] When the software is large in scale, the RTL file connection relationship is complex, and there are many IP cores, it often takes several hours or even one or two days to completely extract all the simulation RTL code of the Vivado project.

[0061] Through the technical solutions of the embodiments of this application, FPGA verification engineers can quickly complete the RTL code extraction of Vivado projects, and the RTL code extraction is accurate and complete.

[0062] The technical solution presented in this application improves the efficiency of RTL code extraction for Vivado-based engineering simulation and has promising application prospects.

[0063] In this embodiment, the RTL code of the Vivado project is extracted based on a pre-defined path, and corresponding configuration work is performed. This method has high versatility and can provide convenience for subsequent simulation work.

[0064] The technical solution of this application embodiment reads the simulation project script file under the Vivado project, automatically identifies the relative position statements of the simulation RTL code, automatically determines whether the read statement contains the position information of the simulation RTL code, and if the position statement information is identified, collects the position statement information, packages and organizes the RTL code position statement information and saves it to a new txt document, which is the RTL code path txt document.

[0065] After the RTL code path txt document is organized, invalid symbols in the txt document are automatically deleted and replaced, and the RTL code save path in the txt document is automatically modified to a format that the Windows system can recognize, and finally the RTL code path txt document that can be recognized by Windows is formed.

[0066] The system uses an automated process to identify and manipulate TXT files containing RTL code paths that can be recognized by Windows. It then copies the corresponding simulation RTL code to a folder where the RTL code is stored. Simultaneously, it copies the necessary IP simulation-related files to the same folder. This completes the extraction of RTL code for Vivado-based engineering simulation.

[0067] In summary, the present invention enables rapid extraction of RTL code for Vivado engineering simulation, overcoming the shortcomings of manual extraction of RTL code for Vivado engineering simulation.

[0068] The technical solution of this application supports FPGA software developed by Vivado, which can quickly extract RTL code written in VHDL and Verilog languages.

[0069] Furthermore, the data lines containing RTL code in the *_compile.do file of the specified simulation path in the Vivado project are read and stored in a preset storage file, including the following steps:

[0070] Iterate through the files in the specified simulation path of the Vivado project and search for the *_compile.do file;

[0071] Iterate through each line of the *_compile.do file, retrieve the data lines containing RTL code from the *_compile.do file, and store them in a preset storage file.

[0072] Furthermore, after reading the data lines containing RTL code from the *_compile.do file in the specified simulation path of the Vivado project and storing them in a preset storage file, and before modifying the DOS system recognition path of the preset storage file containing the data lines containing RTL code to the Windows system recognition path, the method includes the following steps:

[0073] Delete invalid characters from the preset storage file.

[0074] Furthermore, after copying the RTL code to the pre-stored RTL code path based on the Windows system identification path of the preset storage file, the method further includes the following steps:

[0075] Obtain the preset IP simulation file storage path;

[0076] Copy the IP simulation files required for the simulation to the IP simulation file storage path.

[0077] Specifically, the preset storage file is a txt file.

[0078] Based on the above technical solution, a specific implementation scenario is presented, including the following process:

[0079] The first step is to read the specified Vivado project simulation path, the folder path for pre-stored RTL code, and the folder path for pre-stored IP simulation-related files, all input from external sources.

[0080] The second step involves using automated software to traverse every file in the Vivado project simulation path and search for a file named *_compile.do.

[0081] The third step is to read the file named *_compile.do, traverse each line of the file, and use automated software to extract the lines containing RTL code identifiers from the *compile.do file and store them separately in a new txt file.

[0082] The fourth step is to use software to automatically delete invalid symbols from the txt file and update the txt file synchronously.

[0083] The fifth step involves using automated software to change the path recognized by the DOS system in the txt file to the path recognized by the Windows system, and then updating the txt file synchronously.

[0084] The sixth step involves using automated software to copy the RTL code to the storage path of the RTL code entered in S1, according to the file path described in the txt file that the Windows system recognizes and saves the RTL code.

[0085] Step 7: Using automated software processing, copy the IP simulation files required for the simulation to the IP simulation file storage path entered in S1.

[0086] See Figure 2 As shown, based on the same inventive concept as the method embodiment, this application embodiment provides an RTL code extraction device for a Vivado project, the device comprising:

[0087] The path acquisition module is used to obtain the preset simulation path of the Vivado project and the pre-stored path of the RTL code;

[0088] The code reading module is used to read the data lines containing RTL code from the *_compile.do file in the specified simulation path of the Vivado project and store them in a preset storage file;

[0089] The path modification module is used to change the DOS system-recognized path of the preset storage file containing data lines of RTL code to the Windows system-recognized path.

[0090] The code import module is used to copy RTL code to the pre-stored RTL code path based on the Windows system identification path of the preset storage file.

[0091] It should be noted that the technical solution of this application embodiment provides a method for quickly extracting RTL code and library files for simulation from a Vivado project in an automated manner;

[0092] In the field of FPGA software verification technology, there is often a need to independently simulate Vivado development software using Questsim simulation software. In this case, the RTL code of the Vivado project is a necessary file.

[0093] FPGA verification engineers often manually extract and copy the RTL code of a Vivado project one by one.

[0094] When the software is large in scale, the RTL file connection relationship is complex, and there are many IP cores, it often takes several hours or even one or two days to completely extract all the simulation RTL code of the Vivado project.

[0095] Through the technical solutions of the embodiments of this application, FPGA verification engineers can quickly complete the RTL code extraction of Vivado projects, and the RTL code extraction is accurate and complete.

[0096] The technical solution presented in this application improves the efficiency of RTL code extraction for Vivado-based engineering simulation and has promising application prospects.

[0097] In this embodiment, the RTL code of the Vivado project is extracted based on a pre-defined path, and corresponding configuration work is performed. This method has high versatility and can provide convenience for subsequent simulation work.

[0098] The technical solution of this application embodiment reads the simulation project script file under the Vivado project, automatically identifies the relative position statements of the simulation RTL code, automatically determines whether the read statement contains the position information of the simulation RTL code, and if the position statement information is identified, collects the position statement information, packages and organizes the RTL code position statement information and saves it to a new txt document, which is the RTL code path txt document.

[0099] After the RTL code path txt document is organized, invalid symbols in the txt document are automatically deleted and replaced, and the RTL code save path in the txt document is automatically modified to a format that the Windows system can recognize, and finally the RTL code path txt document that can be recognized by Windows is formed.

[0100] The system uses an automated process to identify and manipulate TXT files containing RTL code paths that can be recognized by Windows. It then copies the corresponding simulation RTL code to a folder where the RTL code is stored. Simultaneously, it copies the necessary IP simulation-related files to the same folder. This completes the extraction of RTL code for Vivado-based engineering simulation.

[0101] In summary, the present invention enables rapid extraction of RTL code for Vivado engineering simulation, overcoming the shortcomings of manual extraction of RTL code for Vivado engineering simulation.

[0102] The technical solution of this application supports FPGA software developed by Vivado, which can quickly extract RTL code written in VHDL and Verilog languages.

[0103] Furthermore, the code reading module is also used to traverse the files under the specified simulation path of the Vivado project to find the *_compile.do file;

[0104] The code reading module is also used to traverse each line of the *_compile.do file, obtain the data lines containing RTL code in the *_compile.do file, and store them in a preset storage file.

[0105] Furthermore, the code reading module is also used to delete invalid characters in the preset storage file.

[0106] Furthermore, the device also includes a simulated file reading module;

[0107] The simulation file reading module is used to obtain the preset IP simulation file storage path;

[0108] The simulation file reading module is used to copy the IP simulation files required for simulation to the IP simulation file storage path.

[0109] Furthermore, the preset storage file is a txt file.

[0110] It should be noted that in this application, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes the element.

[0111] The above are merely specific embodiments of this application, enabling those skilled in the art to understand or implement this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features claimed herein.

Claims

1. A method for extracting RTL code of vivado project, characterized in that, The method comprises the following steps: acquire the preset vivado project designated simulation path and the RTL code prestorage path; reading the vivado project designated simulation path the data line containing the RTL code in the _compile.do file is stored into the preset storage file modify the dos system recognition path of the preset storage file storing the data line containing the RTL code to the windows system recognition path; copy the RTL code to the RTL code prestorage path based on the windows system recognition path of the preset storage file; reading a vivado project designated simulation path storing the data line of the RTL code in the _compile.do file into a preset storage file, including the following steps: traversing files under a vivado project designated simulation path to find _compile.do file; traversing the compile the _compile.do file line by line storing the data lines containing RTL codes in the _compile.do file into a preset storage file the reading of the vivado project designated simulation path Before the modification of the DOS system recognizable path of the preset storage file storing the data line containing the RTL code into the windows system recognizable path, the method comprises the following steps: delete the invalid characters in the preset storage file; after copying the RTL code to the RTL code prestorage path based on the windows system recognition path of the preset storage file, the method further comprises the following steps: acquire the preset IP simulation file storage path; copy the IP simulation file required for simulation to the IP simulation file storage path.

2. The RTL code extraction method of the vivado project according to claim 1, characterized in that: the preset storage file is a txt file.

3. A vivado project RTL code extraction apparatus, characterized by, The device comprises; a path acquisition module for acquiring the preset vivado project designated simulation path and the RTL code prestorage path; a code reading module for reading the vivado project designated simulation path the data line containing the RTL code in the _compile.do file is stored into the preset storage file; a path modification module for modifying the dos system recognition path of the preset storage file storing the data line containing the RTL code to the windows system recognition path; a code import module for copying the RTL code to the RTL code prestorage path based on the windows system recognition path of the preset storage file; The code reading module is further configured to traverse files under a simulation path designated by the vivado project to find _compile.do file; The code reading module is further configured to traverse each line of the _compile.do file, obtain data lines containing RTL code in the _compile.do file, and store the data lines into a preset storage file. the code reading module is also used for deleting the invalid characters in the preset storage file; the device further comprises a simulation file reading module; the simulation file reading module is used for acquiring the preset IP simulation file storage path; the simulation file reading module is used for copying the IP simulation file required for simulation to the IP simulation file storage path.

4. The RTL code extraction device of the vivado project according to claim 3, characterized in that: the preset storage file is a txt file.

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