Full-size convolution calculator based on memristor crossbar array and convolution method thereof

Abstract

A full-scale convolution calculator based on a memristor crossbar array is characterized by comprising a convolution kernel matrix, an input array, and an output circuit that outputs the convolution result. A convolution method for a full-scale convolution calculator is described. The convolution kernel matrix acquires input data, which then transmits a pulse voltage signal below the memristor threshold voltage to the positive input of the convolution kernel. After passing through an arithmetic circuit, m data are obtained. Each data is connected to the input array and accumulated and summed within F convolution calculation units with the input data stored in the memristor crossbar array. The result is then output. This method significantly accelerates convolution calculations by increasing storage area, leveraging the high integration and size advantages of the memristor array. The convolver can perform convolution calculations on all convolution areas tiled on the convolution matrix in parallel, significantly increasing computational efficiency. The larger the input data, the more significant the effect.

Description

Technical Field

[0001] The present invention relates to a memristor cross array convolution algorithm, in particular to a full-size convolution calculator based on a memristor cross array and a convolution method thereof. Background Art

[0002] A memristor is a circuit device that represents the relationship between magnetic flux and charge. It has the same dimension as resistance, but unlike a resistor, its resistance is determined by the charge flowing through it. Therefore, by measuring the resistance of a memristor, we can determine the amount of charge flowing through it, thereby acting as a memory. The advent of nanoscale memristors holds promise for the realization of non-volatile random access memory. Furthermore, memristor-based random access memory offers advantages over traditional random access memory in terms of integration density, power consumption, and read / write speed. Furthermore, memristors are the best way to implement synapses in artificial neural networks in hardware.

[0003] Memristor-based neuromorphic computing systems offer a high-speed, low-power method for training neural networks. However, convolutional neural networks (CNNs), one of the most important models for image recognition, have seen various approaches using memristor crossbar arrays for full hardware implementation. Furthermore, these approaches demonstrate high accuracy. In addition to using different cores with shared inputs for parallel convolutional computations, multiple copies of the same core in a memristor array have been shown to enable parallel processing of different inputs. In terms of energy efficiency, memristor-based CNN neuromorphic systems offer significant improvements over the most mature GPU-based image processing technology.

[0004] Memristor convolution technology is currently immature, leading to the emergence of various memristor algorithm arrays. Existing memristor convolution machines store data by stretching convolution kernels of varying sizes into a single column. The image data to be processed is converted into a vector of the same size as the convolution kernel and input as a voltage into the memristor array storing the convolution kernel to perform the convolution calculation. Each input is limited to a vector of the convolution kernel size, limiting their efficiency when processing larger images. Summary of the Invention

[0005] In view of this, the present invention provides a full-size convolution calculator based on a memristor crossbar array, which can realize fully parallel convolution calculation of large image data.

[0006] A full-scale convolution calculator based on a memristor crossbar array, which mainly includes:

[0007] A convolution kernel matrix comprising 2 rows and m columns of memristor unit circuits, wherein the 2 rows of memristor unit circuits are used to collect target data, and the column output of each column of memristor unit circuits corresponds to and is connected to a column input of the input array;

[0008] Convolution matrix: includes n rows and m × d columns of memristor unit circuits, forming an n-row m × d convolution array. The n-row m × d convolution array is connected to the F group of output circuits according to the convolution kernel output logic;

[0009] The output circuit outputs the convolution result.

[0010] The corresponding arrangement of m columns of memristor unit circuits is the physical layer guarantee for achieving full-size convolution.

[0011] Furthermore, the memristor unit circuit is provided with a MOS tube, the source of the MOS tube is grounded, the drain is connected to the operational memristor, the operational memristor is connected to the data source, the operational memristor is used to calculate and store data, the gate of the MOS tube is connected to the row memristor, and the gate is also connected to the column selection signal source through the column memristor.

[0012] One MOS tube and three memristors form a memristor unit circuit, forming a single storage and computing unit. The operational memristor is used for calculation or storage, and the row memristor, column memristor and MOS tube together form a functional device for a bidirectional pulse-triggered control switch.

[0013] Furthermore, the operational memristors of the first row of memristor unit circuits of the convolution kernel matrix are connected in parallel to the same initial data source, and the operational memristors of the second row of memristor unit circuits are connected in parallel to the same delayed data source;

[0014] The row memristors of all memristor unit circuits are grounded;

[0015] The column memristors of the same column memristor unit circuit are connected in parallel to the same column selection signal source;

[0016] The drains of the memristor unit circuits in the same column are connected in parallel to the inverting input terminal of the first operational amplifier, the non-inverting input terminal of the first operational amplifier is grounded, the output terminal is connected to the inverting input terminal of the second operational amplifier via a current limiting resistor, the non-inverting input terminal of the second operational amplifier is grounded, and the output terminal corresponds to a column input of the input array.

[0017] Only four pins remain for connection. A scalable array unit is constructed for convolution computation. For input data with n rows and m columns, a d×d convolution kernel is used. The number of columns in the convolution matrix's basic array unit is determined by the kernel size d, and the number of rows is determined by the number of rows n of the input data. All other dimensions can be expanded from this basic array unit with n rows and d columns. The convolution kernel matrix consists of two rows and m×d columns of memristor unit circuits.

[0018] Furthermore, the n-row m×d convolution array is composed of n-row m×d columns of memristor unit circuits, and the operational memristors of each column of memristor unit circuits are connected in parallel to the column output of the corresponding convolution kernel matrix;

[0019] The row memristors of each row of memristor unit circuits are connected to the same row selector;

[0020] The column memristors of each column of memristor unit circuit are connected to the same column selector.

[0021] Furthermore, a d×d convolution kernel is determined, the n×m input array is sparsely stored, and every other column is stored column by column with an interval of d-1 and row by row with an interval of 1, so as to obtain a convolution matrix with n rows and m×d columns, and the corresponding convolution kernel matrix is ​​deformed into 2 rows and m×d columns;

[0022] Basic array units are arranged in an n-row m×d-column convolution matrix, where the number of columns of the basic array unit is d and the number of rows is n, and all basic array units are arranged in sequence to the last column;

[0023] Convolution calculation units are also planned in the convolution matrix. Each product calculation unit is planned according to d rows and d×d columns. It is copied from the first row and column according to the step size s and extended to the nth row and m×d column. F convolution calculation units are arranged in the convolution matrix of n rows and m×d columns, and corresponding F convolution outputs are planned. Each convolution output is connected to an output circuit.

[0024] Furthermore, the n-row m×d convolution matrix is ​​provided with a ground selector, a cell selector, an inter-row selector, and an output selector;

[0025] Ground selector: In each row, the MOS tube sources of all memristor unit circuits are connected together and then grounded uniformly through the ground selector;

[0026] A cell selector is provided for every d memristor cell circuits in each row, and the cell selector is connected between the sources of adjacent MOS tubes;

[0027] In each convolution calculation unit, the source of the MOS tube of each row of memristor unit circuit is connected in parallel to a row output line;

[0028] Inter-row selector: Except for the first row, in each row, an inter-row selector is set on both sides of each d memristor unit circuit. The inter-row selector is used to connect the row output line of the current row with the row above.

[0029] Output selector: In each convolution calculation unit, all row output lines are connected in series through the inter-row selector and then connected to the output line of the convolution calculation unit through an output selector.

[0030] The row selector, inter-row selector, cell selector, column selector and output selector are all NMOS tubes.

[0031] Furthermore, each group of the output circuits includes a group of operational amplifier circuits and a group of integration circuits, wherein the operational amplifier circuit is connected to one output of the input array, the output end of the operational amplifier circuit is connected to the front end of the switch, the first rear end of the switch is connected to the inverting input end of the integration circuit, the second rear end of the switch is connected to the inverting input end of the integration circuit via the inverter, the same-direction input end of the integration circuit is grounded, and the output end outputs the convolution result.

[0032] A convolution method for a full-size convolution calculator, comprising:

[0033] Step 1: Obtain input data through the convolution kernel matrix. The convolution kernel matrix sends a pulse voltage signal lower than the memristor threshold voltage to the positive input terminal of the convolution kernel. After the operation circuit, m data lower than the memristor threshold voltage are obtained.

[0034] Step 2: Each data is connected to the input array and accumulated and summed with the input data stored in the memristor crossbar array in F convolution calculation units;

[0035] Step 3: The F output results are sent to F output circuits. The switches in the output circuits synchronously switch between the positive and negative values ​​of the convolution kernel. A pulse voltage lower than the threshold voltage of the memristor is then sent to the negative value row of the convolution kernel. The inverter takes the absolute value of the negative value to obtain a convolution result. Here, the column vector of the d×d convolution kernel is converted into a row vector and arranged in non-overlapping rows. One row stores positive values, and the other row stores the absolute values ​​of negative values.

[0036] Then, by shifting rightward or downward, find the remaining convolution calculation units of the convolution matrix and repeat steps 1, 2, and 3 to obtain all the convolution results.

[0037] The beneficial effects of the present invention are as follows: by utilizing the high integration and size advantages of the memristor array, convolution calculations are accelerated by increasing the storage area; the convolver can parallelize the convolution calculations of all convolution areas tiled on the convolution kernel matrix, significantly increasing the computational efficiency, and the larger the convolution kernel matrix, the more significant the effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 It is a schematic diagram of the algorithm;

[0039] Figure 2 It is a cross array structure;

[0040] Figure 3 is the circuit diagram of the memristor unit;

[0041] Figure 4 This is the bidirectional pulse trigger waveform of the memristor unit circuit;

[0042] Figure 5 It is the convolution kernel storage and reading circuit

[0043] Figure 6 Schematic diagram of a single computing unit

[0044] Figure 7 This is the convolution kernel reading circuit diagram

[0045] Figure 8 It is a schematic diagram of input data and kernel matrix storage;

[0046] Figure 9 Output circuit diagram

[0047] Figure 10 It is the output waveform of the convolution result.

[0048] The present invention will be further described below with reference to the embodiments and accompanying drawings.

[0049] like Figure 3 、 4 5. A full-scale convolution calculator based on a memristor crossbar array, with:

[0050] A convolution kernel matrix comprising 2 rows and m columns of memristor unit circuits, wherein the 2 rows of memristor unit circuits are used to collect target data, and the column output of each column of memristor unit circuits corresponds to and is connected to a column input of the input array;

[0051] Convolution matrix: includes n rows and m × d columns of memristor unit circuits, forming an n-row m × d convolution array. The n-row m × d convolution array is connected to the F group of output circuits according to the convolution kernel output logic;

[0052] like Figure 9 、 10 As shown, the output circuit outputs the convolution result.

[0053] like Figure 3 As shown, the memristor unit circuit is provided with a MOS tube, the source of the MOS tube is grounded, the drain is connected to the operational memristor, the operational memristor is connected to the data source, the operational memristor is used to calculate and store data, the gate of the MOS tube is connected to the row memristor, and the gate is also connected to the column selection signal source through the column memristor.

[0054] The memristor unit circuit serves as a single storage and computing unit, consisting of one MOS tube and three memristors. The operational memristor M1 is used for calculation or storage, and the row memristor, column memristor and MOS tube together form a functional device for a bidirectional pulse-triggered control switch.

[0055] The row memristor and column memristor are connected in reverse series to control the NMOS to be turned on or off. The voltage divider formula gives Assume that the resistance of the column memristor is R ON , the resistance of the memristor is R OFF , R ON and R OFFThey represent the low resistance state and high resistance state of the memristor respectively. When calculating, Vs maintains the voltage Vs=2V. The v-gate state of M2 under different resistance conditions is shown in Table 1. Assume that the initial state of the row and column memristors M2 is M2 Left =R OFF , M2 Right =R ON , then v gate =1.99v, NMOS is in the On state, if a voltage of -10v with a pulse width of 50ns is applied to the Vs terminal, then M2 Left By R OFF becomes R ON , M2 Right By R ON becomes R OFF , apply voltage Vs=2v to Vs terminal again, v gate =0.013v, which is lower than the threshold voltage of NMOS. NMOS is in the OFF state. If you want to turn it on again, you need to apply a 50ns pulse width of 10v voltage to the Vs end. M2 Left Then R ON becomes R OFF , M2 Right By R OFF becomes R ON , again VS applies voltage Vs=2v, v gate =1.99v, NMOS returns to the On state. The resistor ratio and threshold voltage must meet the following requirements:

[0056] v th ≤Vs·R off / (R off +R on )<v on , Vs·R on / (R off +R on )<v th ≤v off (5)

[0057] where v th Indicates the threshold voltage of NMOS.

[0058] Table 1 Relationship between memristor state, gate voltage and NMOS state

[0059]

[0060] like Figure 4As shown, assuming that the initial state of NMOS is On, first, a voltage of V(Vs) = 2V with a delay of 40ns and a pulse width of 280ns ​​is applied to the Vs terminal, and a 3-cycle square wave signal with a delay of 50ns, V(Vin) = 0.5v, a pulse width of 50ns, and a duty cycle of 50% is input to the Vin terminal of the operational memristor M1, then the current I(mem) will be measured on the memristor; a Switch off signal of -10v with a pulse width of 50ns is applied to the Vs terminal after a delay of 350ns, then the NMOS state becomes OFF, and a 3-cycle square wave signal of 0.5v with a pulse width of 50ns and a duty cycle of 50% is applied to the Vin terminal of the M1 memristor between 450ns and 720ns. Since the NMOS is already in the OFF state, no current will flow through the memristor, and then a Switch off signal of 10v with a pulse width of 50ns is applied to the Vs terminal. On signal, the NMOS state changes to On, and the periodic pulse signal is repeatedly applied to the Vin terminal of the operational memristor M1, and current flows through the memristor again.

[0061] First, encapsulate the memristor unit circuit unit and use a rectangular block to represent it, as shown in the following example: Figure 5 As shown, only four pins are left for connection. Construct an expandable array unit for convolution calculation. For an input data with n rows and m columns and a d×d convolution kernel, the number of columns of the basic array unit of the convolution kernel matrix is ​​determined by the convolution kernel size d, and the number of rows is determined by the number of rows n of the convolution kernel matrix. All other dimensions can be expanded from this basic array unit with n rows and d columns.

[0062] The convolution kernel matrix is ​​a two-row array, wherein the computational memristors of the memristor unit circuits in the first row are connected in parallel to the same initial data source, and the computational memristors of the memristor unit circuits in the second row are connected in parallel to the same delayed data source;

[0063] The row memristors of all memristor unit circuits are grounded;

[0064] The column memristors of the same column memristor unit circuit are connected in parallel to the same column selection signal source;

[0065] The drains of the memristor unit circuits in the same column are connected in parallel to the inverting input terminal of the first operational amplifier, the non-inverting input terminal of the first operational amplifier is grounded, the output terminal is connected to the inverting input terminal of the second operational amplifier via a current limiting resistor, the non-inverting input terminal of the second operational amplifier is grounded, and the output terminal corresponds to a column input of the input array.

[0066] like Figure 7As shown, one row receives and stores the positive value W+ of the core element, while the other row receives and stores the absolute value |W-| of the negative core element. After a 100ns delay, the negative portion of the core element |W-| is stored using a 0.2V read voltage and input into the computation array. Each column is followed by a two-stage operational amplifier circuit that reads the W+ core element using a 0.2V read voltage for 50ns. The output voltage is limited to the threshold voltage of the memristor and input into the convolution array.

[0067] The n×m convolution array is composed of n rows and m columns of memristor unit circuits, and the operational memristors of each column of memristor unit circuits are connected in parallel to the column output of the corresponding convolution kernel matrix;

[0068] The row memristors of each row of memristor unit circuits are connected to the same row selector;

[0069] The column memristors of each column of memristor unit circuit are connected to the same column selector.

[0070] like Figure 5 As shown in the figure, a 5×5 input array and a 2×2 convolution kernel require five 5×2 basic cells in a 5-row, 2-column array. NMOS transistors are used for expansion and selection. Grayscale-filled NMOS transistors are closed, while hollow NMOS transistors are open. Basic cells are cascaded using cell connectors, and rows are connected using inter-row connectors. Output selectors then connect the computation results of the current cell to the output circuit.

[0071] Artificially set a d×d convolution kernel, the n×m input array is sparsely stored, and every other column is stored column by column with an interval of d-1, and row by row with an interval of 1, to obtain a convolution matrix with n rows and m×d columns. The corresponding convolution kernel matrix is ​​deformed into 2 rows and m×d columns;

[0072] Basic array units are arranged in an n-row m×d convolution matrix, the number of columns of the basic array unit is d, the number of rows is n, and all basic array units are arranged in sequence to the last column;

[0073] Convolution kernel output logic: Convolution calculation units are also planned in the convolution matrix. Each product calculation unit is planned according to d rows and d×d columns. It is copied from the first row and column with a step size of s and extended to the nth row and m×d column. F convolution calculation units are arranged in the n rows and m×d columns of the convolution matrix, and corresponding F convolution outputs are planned. Each convolution output is connected to an output circuit.

[0074] The n-row m×d convolution matrix is ​​provided with a ground selector, a unit selector, an inter-row selector, and an output selector;

[0075] Ground selector: In each row, the MOS tube sources of all memristor unit circuits are connected together and then grounded uniformly through the ground selector;

[0076] A cell selector is provided for every d memristor cell circuits in each row, and the cell selector is connected between the sources of adjacent MOS tubes;

[0077] In each convolution calculation unit, the source of the MOS tube of each row of memristor unit circuit is connected in parallel to a row output line;

[0078] Inter-row selector: Except for the first row, in each row, an inter-row selector is set on both sides of each d memristor unit circuit. The inter-row selector is used to connect the row output line of the current row with the row above.

[0079] Output selector: In each convolution calculation unit, all row output lines are connected in series through the inter-row selector and then connected to the output line of the convolution calculation unit through an output selector.

[0080] Assume that the input I is m×m dimensional image data, Figure 5 The first two convolution calculations are shown in the figure. The first convolution calculation is to simultaneously calculate the convolution calculation unit ① in the four solid boxes in the figure. The second convolution calculation moves to the right by 1 step s. One step s corresponds to a pixel point d rows d × d columns, including the area of ​​4 dotted boxes ②. The calculation process of a single calculation unit is as follows Figure 6 As shown, the solid filled NMOS indicates a closed state, the hollow NMOS indicates an open state, the cell connector connects two basic cells, the inter-row selector superimposes the currents of two adjacent rows in the basic cell, and the output selector connects the calculation result of the cell to the output circuit.

[0081] like Figure 9 As shown, each group of the output circuits includes a group of operational amplifier circuits and a group of integration circuits, wherein the operational amplifier circuit is connected to one output of the input array, the output end of the operational amplifier circuit is connected to the front end of the switch, the first rear end of the switch is connected to the inverting input end of the integration circuit, the second rear end of the switch is connected to the inverting input end of the integration circuit via the inverter, the same-direction input end of the integration circuit is grounded, and the output end outputs the convolution result.

[0082] calculate Figure 5The convolution results of all four convolution kernels in the black solid line area ① and the convolution matrix are output to the output circuit. At the same time, the four op amp output circuits on output bus one and output bus three are selected, and the output voltage is integrated with the integration circuit. By adjusting the parameters of R and C in the RC integration circuit, the integration result is linearly related to the input. The processing technique is: when the input is the calculation result of W+ and the convolution kernel, a synchronized pulse signal is used to control the single-pole double-throw switch CL1 to throw to the a end, which is integrated by the integrator and maintains the current value. When the input is the calculation result of |W-| and the convolution kernel, the switch CL1 is controlled to throw to the b path, pass through the inverter, and then pass through the integration circuit to superimpose with the calculation result of W+ to realize the positive and negative convolution kernel calculation. The circuit structure is as follows: Figure 7 After the calculation is completed, CL2 is closed and the capacitor C is reset.

[0083] like Figure 10 As shown, the waveform of the convolution result transmitted to the display: the output channel of the convolution result of W+ and |W-| and the inner product of the matrix is ​​V(V1). Because CL1 is thrown to b when the input is |W-|, the result will be reversed to the output channel V(V2). The output result is integrated, and the output results obtained by W+ and |W-| are superimposed, see the output channel V(output).

[0084] Moving right selects calculation area ②, which in turn selects four new output op amp circuits on output bus 2 and output bus 4. In the calculation after moving downward, the outputs are again connected to the op amp circuits in area ① or area ② using a multiplexing method.

[0085] A convolution method for a full-size convolution calculator, comprising:

[0086] Step 1: Obtain input data through the convolution kernel matrix. The convolution kernel matrix sends a pulse voltage signal lower than the memristor threshold voltage to the positive input terminal of the convolution kernel. After the operation circuit, m data lower than the memristor threshold voltage are obtained.

[0087] Step 2: Each data is connected to the input array and accumulated and summed with the input data stored in the memristor crossbar array in F convolution calculation units;

[0088] Step 3: The F output results are sent to F output circuits. The switches in the output circuits synchronously switch between the positive and negative values ​​of the convolution kernel. A pulse voltage lower than the threshold voltage of the memristor is then sent to the negative value row of the convolution kernel. The inverter takes the absolute value of the negative value to obtain a convolution result. Here, the column vector of the d×d convolution kernel is converted into a row vector and arranged in non-overlapping rows. One row stores positive values, and the other row stores the absolute values ​​of negative values.

[0089] Then, by shifting rightward or downward, find the remaining convolution calculation units of the convolution matrix and repeat steps 1, 2, and 3 to obtain all the convolution results.

[0090] The theoretical basis is as follows: a full-size convolution algorithm is designed. Assuming that the input is m×m dimensional image data, the convolution kernel G is set to d×d, and the sliding step is S. When m≥d+S is satisfied, the full-size input convolution algorithm is expressed by the following formula:

[0091]

[0092] k,l increases in a step-by-step manner, and within the value range, the step length step=d+s-1, m≥d+s, is a rounding function. Here, the convolution calculation does not consider edge filling. The calculation speed of the convolution algorithm is not related to the size of the input image, but only to the convolution kernel size and the sliding step size. The number of fully parallel convolution kernel calculations is

[0093] like Figure 1 、 2 As shown, a 5×5 matrix and a 2×2 convolution kernel are convolved with a sliding step size of 1. In the first convolution calculation, the convolution kernel is flattened on the entire convolution matrix, and the area covered by all convolution kernels is calculated at the same time. Figure 1 In (a), the four kernels are convolved, resulting in output 1. The next operation shifts the kernel to the right, as shown in (b), and the entire area covered by the kernel is computed, resulting in output 2. Next, the kernel is shifted down, as shown in (c), resulting in output 3. Finally, the kernel is shifted right, as shown in (d), resulting in output 4.

[0094] A. Array Configuration

[0095] For an input data with n rows and m columns and a d×d convolution kernel, the basic array unit of the convolution matrix is ​​n×d, and other dimensions can be expanded from this basic array unit.

[0096] B. Store convolution kernel matrix and kernel matrix

[0097] The convolution matrix is ​​stored sparsely row by row from top to bottom, with the interval between elements in each row being d-1. The kernel matrix is ​​stored by transposing each column of the kernel matrix into a row vector and then storing it in two rows, one row storing W+ and the other storing |W-|. Figure 8 shown.

[0098] C. Computing unit initialization

[0099] All NMOS transistors that don't store data are turned off. This number of initializations is equal to the convolution kernel dimension d. For example, to implement a 2×2 convolution kernel, the number of initializations is 2. This is accomplished by selecting the row select pins of all cells in the first column that don't store data, grounding the corresponding column select pins, and applying a switch-off voltage to the row select pins. Because the number of array columns matches the size of the convolution kernel, the number of initializations is d.

[0100] d. Switch configuration during calculation

[0101] The principle of switch configuration is to connect all storage areas of corresponding sizes of the convolution kernel, and use unit connectors to connect the units involved in calculation or storage; the inter-row selector selects the row where the current needs to be conducted, and the output selector connects the output of the current calculation unit to the output circuit.

[0102] According to formula (1) and Figure 1 The entire calculation process is completed by moving the control unit connector to the right and the inter-row selector to the bottom.

Claims

1. A full-scale convolution calculator based on a memristor crossbar array, characterized in that: include: A convolution kernel matrix comprising two rows and m×d columns of memristor unit circuits, wherein the two rows of memristor unit circuits are used to collect target data, and the column output of each column of memristor unit circuits is connected in parallel to a column input of the input array; Convolution matrix: includes n rows and m × d columns of memristor unit circuits, forming an n-row m × d convolution array. The n-row m × d convolution array is connected to the F group of output circuits according to the convolution kernel output logic; The output circuit outputs the convolution result; The n-row m×d convolution array is composed of n-row m×d columns of memristor unit circuits, and the operational memristors of each column of memristor unit circuits are connected in parallel to the column output of the corresponding convolution kernel matrix; The row memristors of each row of memristor unit circuits are connected to the same row selector; The column memristors of each column of memristor unit circuit are connected to the same column selector; Determine the d×d convolution kernel, sparsely store the n×m input array, store every other column with a column-by-column interval of d-1 and a row-by-row interval of 1, and obtain a convolution matrix with n rows and m×d columns. The corresponding convolution kernel matrix is ​​deformed into 2 rows and m×d columns. Basic array units are arranged in an n-row m×d-column convolution matrix, where the number of columns of the basic array unit is d and the number of rows is n, and all basic array units are arranged in sequence to the last column; Convolution calculation units are also planned in the convolution matrix. Each convolution calculation unit is planned according to d rows and d columns. It is copied from the first row and column according to the step size s and extended to the nth row and m×d column. F convolution calculation units are arranged in the n rows and m×d columns convolution matrix, and corresponding F convolution outputs are planned. Each convolution output is connected to an output circuit. The n-row m×d-column convolution matrix is ​​provided with a ground selector, a unit selector, an inter-row selector, and an output selector; Ground selector: In each row, the MOS tube sources of all memristor unit circuits are connected together and then grounded uniformly through the ground selector; A cell selector is provided for every d memristor cell circuits in each row, and the cell selector is connected between the sources of adjacent MOS tubes; In each convolution calculation unit, the source of the MOS tube of each row of memristor unit circuit is connected in parallel to a row output line; Inter-row selector: Except for the first row, in each row, an inter-row selector is set on both sides of each d memristor unit circuit. The inter-row selector is used to connect the row output line of the current row with the row above. Output selector: In each convolution calculation unit, all row output lines are connected in series through the inter-row selector and then connected to the output line of the convolution calculation unit through an output selector.

2. The full-scale convolution calculator based on a memristor crossbar array according to claim 1, characterized in that: The memristor unit circuit is provided with a MOS transistor, the source of the MOS transistor is grounded, the drain is connected to an operational memristor, the operational memristor is connected to a data source, the operational memristor is used to calculate and store data, the gate of the MOS transistor is connected to a row memristor, and the gate is also connected to a column selection signal source through a column memristor.

3. The full-scale convolution calculator based on a memristor crossbar array according to claim 1 or 2, characterized in that: The operational memristors of the first row of memristor unit circuits of the convolution kernel matrix are connected in parallel to the same initial data source, and the operational memristors of the second row of memristor unit circuits are connected in parallel to the same delayed data source; The row memristors of all memristor unit circuits are grounded; The column memristors of the same column memristor unit circuit are connected in parallel to the same column selection signal source; The drains of the memristor unit circuits in the same column are connected in parallel to the inverting input terminal of the first operational amplifier, the non-inverting input terminal of the first operational amplifier is grounded, the output terminal is connected to the inverting input terminal of the second operational amplifier via a current limiting resistor, the non-inverting input terminal of the second operational amplifier is grounded, and the output terminal corresponds to a column input of the input array.

4. The full-scale convolution calculator based on a memristor crossbar array according to claim 1, characterized in that: Each group of output circuits includes a group of operational amplifier circuits and a group of integration circuits, wherein the operational amplifier circuit is connected to one output of the input array, the output end of the operational amplifier circuit is connected to the front end of the switch, the first rear end of the switch is connected to the inverting input end of the integration circuit, the second rear end of the switch is connected to the inverting input end of the integration circuit via the inverter, the same-direction input end of the integration circuit is grounded, and the output end outputs the convolution result.

5. A convolution method, implemented based on the full-size convolution calculator described in weights 1-4, characterized in that: Step 1: Obtain input data through the convolution kernel matrix. The convolution kernel matrix sends a pulse voltage signal lower than the memristor threshold voltage to the positive input terminal of the convolution kernel. After the operation circuit, m data lower than the memristor threshold voltage are obtained. Step 2: Each data is connected to the input array and accumulated and summed with the input data stored in the memristor crossbar array in F convolution calculation units; Step 3: The F output results are sent to F output circuits. The switches in the output circuits synchronously switch between the positive and negative values ​​of the convolution kernel. A pulse voltage lower than the threshold voltage of the memristor is then sent to the negative value row of the convolution kernel. The inverter takes the absolute value of the negative value to obtain a convolution result. Here, the column vector of the d×d convolution kernel is converted into a row vector and arranged in non-overlapping rows. One row stores positive values, and the other row stores the absolute values ​​of negative values. Then, by shifting rightward or downward, find the remaining convolution calculation units of the convolution matrix and repeat steps 1, 2, and 3 to obtain all the convolution results.

Images