Stacked package structure and method of forming the same
By employing a combination of substrate openings, back metal, and encapsulant vias in the stacked packaging structure, stable chip stacking and efficient heat dissipation are achieved, solving the problems of unstable chip stair stacking and high impedance and large size in traditional packaging, and improving current carrying capacity.
CN116110860BActive Publication Date: 2026-07-03SHANGHAI XIANFANG SEMICON CO LTD +1
Patent Information
- Application Number
- CN202310089871.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2023-02-09
- Publication Date
- 2026-07-03
- Estimated Expiration
- 2043-02-09
Smart Images
Figure CN116110860B_ABST
Abstract
This invention relates to a stacked packaging structure, comprising: a substrate having a substrate window on its right side; a first chip mounted on the left side of the substrate, wherein the right side of the back side of the first chip has a back metal; a first molding compound layer; a first molding compound via electrically connected to the substrate window and the back metal of the second chip; a second chip offsetly mounted on the first chip, wherein the right side of the back side of the second chip has a back metal; a second molding compound layer; a second molding compound via electrically connected to the substrate window and the back metal of a third chip; a third chip offsetly mounted on the second chip, wherein the right side of the back side of the third chip has a back metal; a metal pillar disposed on the right side pin of the front side of the third chip; a third molding compound layer; a third molding compound via; a circuit electrically connecting the metal pillar and the third molding compound via; and conductive leads electrically interconnecting the substrate, the first chip, the second chip, and the third chip.
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Citation Information
Patent Citations
Multi-chip stacked packaging structure and packaging method thereof
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