Method and apparatus for optimizing non-volatile memory bit process

Abstract

The application relates to the field of semiconductor wafer testing, and provides a nonvolatile memory bit process optimization method and device, which comprises the following steps: inputting ultra-pure dry air between an etching process and an ion implantation process of a device unit region of a Norflash; wherein, the waiting time from the etching to the ion implantation process is controlled. The above process optimization effectively reduces defects of the Norflash in Celletch-CellIMP, reduces the blocking effect of ions during IMP implantation, improves the VT margin tailing distribution problem, improves the tailing die VT initial value, and thus reduces the VT margin failure.

Description

Technical Field

[0001] This invention relates to the field of semiconductor wafer testing, and more particularly to an optimization method and apparatus for non-volatile memory bit technology. Background Technology

[0002] Sufficient VT margin is one of the main items in the CP (Chip Probing) test of Nor flash products. It is a prerequisite for the normal operation of flash chips. VT margin failure is mainly due to the presence of tailing dies in the VT distribution. Since the VT is relatively low, some of these dies will suffer yield loss during the initial value control, and some will also fail during the residual value control after subsequent recycling or high-temperature baking.

[0003] In existing Nor flash semiconductor processes, a common approach to address the problem of insufficient VT is to adjust the amount of IMP (implant) Dose to expand the VT window. However, this method can only adjust the average VT margin and cannot improve the tailing phenomenon in the overall VT margin distribution.

[0004] Research has found that in Nor flash semiconductor processes, the VT distribution tailing phenomenon is mainly caused by defects generated during the chip cell etch process. The generation of defects will block ion implantation in the subsequent cell IMP process, which will affect the VT margin of the chip in that area and result in tailing distribution. Summary of the Invention

[0005] This invention addresses the weaknesses of the Nor flash process flow and proposes a process flow optimization method to effectively improve VT margin failure by solving the problem of VT distribution tailing.

[0006] The technical solution provided by this invention is as follows: An optimization method for non-volatile memory bit technology includes: Ultra-pure dry air is introduced between the etching process and the ion implantation process in the device cell region of the Nor flash. The waiting time from the etching process to the ion implantation process is controlled.

[0007] In some embodiments, it also includes: When the ultrapure dry air is introduced, defects in the device unit area are removed and the generation of such defects is suppressed.

[0008] In some embodiments, it also includes: By suppressing the defects, the ion input of the ion implantation process is controlled.

[0009] In some embodiments, it also includes: By controlling the ion input in the ion implantation process, the tailing distribution range of the VT margin in the Nor flash is controlled within a preset range.

[0010] In some embodiments, the preset range includes -900 to -550.

[0011] An optimized apparatus for non-volatile memory bit technology, comprising: The air input module is used to supply ultrapure, dry air between the etching and ion implantation processes in the device cell region of Nor flash. The time control module is used to control the waiting time from the etching to entering the ion implantation process.

[0012] In some embodiments, it also includes: The removal module is used to remove defects in the device unit area and suppress the generation of defects after the ultrapure dry air is input.

[0013] In some embodiments, it also includes: A control module is used to control the ion input of the ion implantation process by suppressing the defects.

[0014] In some embodiments, it also includes: The control module controls the ion input of the ion implantation process to keep the tailing distribution range of VTmargin in the Nor flash within a preset range.

[0015] In some embodiments, the preset range includes -900 to -550.

[0016] The optimization method and apparatus for non-volatile memory bit technology provided by this invention can achieve at least the following technical effects: The present invention effectively reduces the defects generated by Nor flash in Cell etch ~ Cell IMP through the above process optimization, reduces the blocking effect on ions during IMP implantation, improves the VT margin tailing distribution problem, and increases the initial value of tailing die VT, thereby reducing VT margin failure. Attached Figure Description

[0017] The preferred embodiments will now be described in a clear and easy-to-understand manner, with reference to the accompanying drawings, to further explain the above-mentioned characteristics, technical features, advantages, and implementation methods of an optimization method and apparatus for non-volatile memory bit technology.

[0018] Figure 1 This is a schematic diagram of an optimization method for non-volatile memory bit technology in this invention; Figure 2 This is a schematic diagram of an embodiment of an optimization method for non-volatile memory bit technology in this invention; Figure 3 This is a schematic diagram of the VT margin tailing distribution before improvement; Figure 4 This is a schematic diagram of the improved VT margin tailing distribution in this invention; Figure 5 This is a comparison diagram of the VT margin tailing distribution in this invention; Figure 6 This is a schematic diagram of an embodiment of an optimized device for non-volatile memory bit technology in this invention. Detailed Implementation

[0019] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that this application can also be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods have been omitted so as not to obscure the description of this application with unnecessary detail.

[0020] It should be understood that, when used in this specification and the appended claims, the term "comprising" indicates the presence of the described features, integrals, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or sets.

[0021] To keep the drawings concise, only the parts relevant to the invention are shown schematically in each figure, and they do not represent the actual structure of the product. Furthermore, for ease of understanding, in some figures, only one of components with the same structure or function is shown schematically, or only one is labeled. In this document, "one" can mean not only "only one" but also "more than one".

[0022] It should also be further understood that the term “and / or” as used in this application specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0023] Furthermore, in the description of this application, the terms "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0024] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the specific implementation methods of the present invention will be described below with reference to the accompanying drawings. Obviously, the drawings described below are merely some embodiments of the present invention. For those skilled in the art, other drawings and other implementation methods can be obtained based on these drawings without any creative effort.

[0025] In one embodiment, such as Figure 1 As shown, the present invention provides an optimization method for non-volatile memory bit technology, comprising: The S100 introduces ultrapure dry air between the etching process and the ion implantation process in the device cell region of the Nor flash.

[0026] Specifically, ultrapure dry air is a type of dry oxygen with extremely high purity, reaching up to 99.999%.

[0027] In this embodiment, ultrapure dry oxygen (99.999%) is first introduced, and then high-temperature heating is carried out for 30 minutes (derived through experimental verification, comparative analysis of effects at different times, and product considerations).

[0028] In this embodiment, this step serves two purposes. First, it reacts with the tiny particles (>1 nm) that may be generated during the oxygen heating and etching process, producing water vapor which is then removed by the vacuum pump, thus eliminating the water vapor. Second, the pure oxygen ensures a clean environment before the subsequent ion implantation process, preventing further particle generation that could affect the manufacturing process.

[0029] In this embodiment, the optimization method for non-volatile memory bit technology is a method for eliminating tiny particles in the Nor flash (non-volatile memory) storage bit technology process.

[0030] For example, adding a layer of clean and dry air between the Etch and IMP cells in the Nor flash cell region can remove defects in the Etch process and reduce the generation of defects.

[0031] S200 wherein the waiting time from the etching to entering the ion implantation process is controlled.

[0032] Specifically, the Q time (waiting time) between Etch and IMP in the Cell region is subject to stricter control.

[0033] The waiting time is the time required to add ultrapure dry air.

[0034] If the specified time is exceeded, the processing system will stop processing that batch of wafers.

[0035] In this embodiment, the connection time between the etching and ion implantation processes is mainly controlled by the equipment MES running system, so as to reduce the time of the condense reaction and the probability of generating condense particles.

[0036] In this embodiment, the above process optimization effectively reduces the defects generated by Nor flash in Cell etch ~ Cell IMP, reduces the blocking effect on ions during IMP implantation, and improves the VT margin tailing distribution problem (e.g. Figure 1 As shown in the figure, the initial value of the tailing die VT was increased, thereby reducing the failure of the VT margin.

[0037] In one embodiment, such as Figure 2 As shown, the present invention provides an optimization method for non-volatile memory bit technology, comprising: When the ultrapure dry air is introduced, defects in the device unit area are removed and the generation of such defects is suppressed.

[0038] In one embodiment, such as Figure 2 As shown, the present invention provides an optimization method for non-volatile memory bit technology, comprising: By suppressing the defects, the ion input of the ion implantation process is controlled.

[0039] In one embodiment, such as Figure 2 As shown, the present invention provides an optimization method for non-volatile memory bit technology, comprising: By controlling the ion input in the ion implantation process, the tailing distribution range of the VT margin in the Nor flash is controlled within a preset range.

[0040] In one embodiment, such as Figures 3-5 As shown, the present invention provides an optimization method for non-volatile memory bit technology, comprising: The preset range includes -900 to -550.

[0041] Specifically, this invention addresses the weaknesses of the Nor flash process flow by optimizing the Nor flash process flow as follows to solve the problem of VT distribution tailing and improve the CP VT margin test item: (1) Add an ultrapure dry air clean and dry between the etch and IMP regions of the Nor flash Cell.

[0042] (2) Stricter control is applied to the Q time between etch and IMP in the Nor flash Cell region.

[0043] For example, such as Figures 3-5 As shown, the tailing distribution range of VT margin changed from -900 to -400 before the improvement to -900 to -550 after the improvement.

[0044] In one embodiment, such as Figure 6 As shown, the present invention provides an optimization apparatus for non-volatile memory bit technology, comprising: The air input module 100 is used to input ultrapure dry air between the etching process and the ion implantation process in the device cell region of Nor flash.

[0045] The time control module 200 is used to control the waiting time from the etching to entering the ion implantation process.

[0046] In one embodiment, it also includes: The removal module is used to remove defects in the device unit area and suppress the generation of defects after the ultrapure dry air is input.

[0047] In one embodiment, it also includes: A control module is used to control the ion input of the ion implantation process by suppressing the defects.

[0048] In one embodiment, it also includes: The control module controls the ion input of the ion implantation process to keep the tailing distribution range of VTmargin in the Nor flash within a preset range.

[0049] In one embodiment, the preset range includes -900 to -550.

[0050] The present invention effectively reduces the defects generated by Nor flash in Cell etch ~ Cell IMP through the above process optimization, reduces the blocking effect on ions during IMP implantation, improves the VT margin tailing distribution problem, and increases the initial value of tailing die VT, thereby reducing VT margin failure.

[0051] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of program modules is merely an example. In practical applications, the above functions can be assigned to different program modules as needed, that is, the internal structure of the device can be divided into different program units or modules to complete all or part of the functions described above. The program modules in the embodiments can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one processing unit. The integrated unit can be implemented in hardware or as a software program unit. Furthermore, the specific names of the program modules are only for easy differentiation and are not intended to limit the scope of protection of this application.

[0052] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0053] Those skilled in the art will recognize that the units of the various examples described in connection with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0054] In the embodiments provided in this application, it should be understood that the disclosed system can be implemented in other ways. For example, the embodiments described above are merely illustrative; the division of modules or units is merely a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interfaces, devices, or units, and may be electrical, mechanical, or other forms.

[0055] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0056] Furthermore, the functional units in the various embodiments of this application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The integrated unit described above can be implemented in hardware or as a software functional unit.

[0057] It should be noted that the above embodiments can be freely combined as needed. The above description is only a preferred embodiment of the present invention. It should be pointed out that for those skilled in the art, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A method for optimizing a non-volatile memory bit process, comprising: include: Between the etching process and the ion implantation process in the device cell region of the Nor flash, ultrapure dry air is introduced and heated at high temperature for a preset time. The preset time is 30 minutes; When the ultrapure dry air is introduced, defects in the device unit area are removed and the generation of tiny condensate particles is suppressed; specifically, the ultrapure dry air reacts with the tiny condensate particles to generate water vapor, which is then removed by a vacuum pump. The waiting time from etching to entering the ion implantation process is controlled; the waiting time is the time for adding ultra-pure dry air; if the specified time is exceeded, the processing system will stop operating the batch of wafers.

2. The optimization method for non-volatile memory bit technology according to claim 1, characterized in that, Also includes: By suppressing the defects, the ion input of the ion implantation process is controlled.

3. The optimization method for non-volatile memory bit technology according to claim 1, characterized in that, Also includes: By controlling the ion input in the ion implantation process, the tailing distribution range of the VT margin in the Nor flash is controlled within a preset range.

4. The optimization method for non-volatile memory bit technology according to claim 3, characterized in that, The preset range includes -900 to -550.

5. An optimization apparatus for non-volatile memory bit technology, characterized in that, include: An air input module is used to input ultrapure dry air and heat it at high temperature for a preset time between the etching process and the ion implantation process in the device cell region of Nor flash. The preset time is 30 minutes; The time control module is used to control the waiting time from the etching to the ion implantation process; specifically, it includes: the ultrapure dry air reacts with micro-particle condense to generate water vapor, which is then removed by a vacuum pump; the waiting time is the time for adding ultrapure dry air; if the specified time is exceeded, the processing system will stop operating the batch of wafers. The removal module is used to remove defects in the device unit area and suppress the generation of defects after the ultrapure dry air is input.

6. The optimization apparatus for non-volatile memory bit technology according to claim 5, characterized in that, Also includes: A control module is used to control the ion input of the ion implantation process by suppressing the defects.

7. The apparatus for optimizing non-volatile memory bit technology according to claim 5, characterized in that, Also includes: The control module controls the ion input of the ion implantation process to keep the tailing distribution range of the VT margin in the Nor flash within a preset range.

8. The optimization apparatus for non-volatile memory bit technology according to claim 7, characterized in that, The preset range includes -900 to -550.

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