Performance matching method of memory, storage device and memory control circuit

Abstract

This invention provides a memory performance matching method, a memory storage device, and a memory control circuit unit. The method includes: receiving a performance matching command from a host system; adjusting the operating settings of the memory storage device in response to the performance matching command to match the performance requirements of the memory storage device with those of the host system; and interacting with the host system based on the adjusted operating settings. This improves the operational performance of the memory storage device and / or avoids compatibility issues between the memory storage device and the host system after it leaves the factory.

Description

Technical Field

[0001] This invention relates to a memory performance matching method, a memory storage device, and a memory control circuit unit. The method includes: receiving a performance matching command from a host system; adjusting the operating settings of the memory storage device in response to the performance matching command to match the performance requirements of the memory storage device with those of the host system; and interacting with the host system based on the adjusted operating settings. This improves the operational performance of the memory storage device and / or avoids compatibility issues between the memory storage device and the host system after the device has left the factory. Background Technology

[0002] The rapid growth of smartphones, tablets, and personal computers in recent years has led to a surge in consumer demand for storage media. Rewritable non-volatile memory modules (e.g., flash memory) are ideally suited for integration into the various portable multimedia devices exemplified above due to their characteristics such as data non-volatility, low power consumption, small size, and lack of mechanical structure.

[0003] Generally, the operating parameters of memory storage devices containing rewritable non-volatile memory modules, or the memory controllers used to control these modules, are preset at the factory. After leaving the factory, the memory storage device or memory controller can perform various operations based on these operating parameters, such as performing internal data access. However, in practice, different types of host systems may have different performance requirements for memory storage devices. Furthermore, when the operating environment changes, the preset operating parameters may no longer meet the current performance requirements of the host system. These situations may not only lead to reduced operating efficiency of the memory storage device, but may also cause compatibility issues between the memory storage device and the host system. Summary of the Invention

[0004] The present invention provides a memory performance matching method, a memory storage device, and a memory control circuit unit, which can improve the above-mentioned problems.

[0005] An exemplary embodiment of the present invention provides a memory performance matching method for a memory storage device. The memory performance matching method includes: receiving a performance matching instruction from a host system; adjusting the operating settings of the memory storage device in response to the performance matching instruction so that the performance of the memory storage device matches the performance requirements of the host system; and interacting with the host system based on the adjusted operating settings.

[0006] An exemplary embodiment of the present invention provides a memory storage device, comprising a connection interface unit, a rewritable non-volatile memory module, and a memory control circuit unit. The connection interface unit is configured to connect to a host system. The memory control circuit unit is connected to the connection interface unit and the rewritable non-volatile memory module. The memory control circuit unit is configured to: receive a performance matching command from the host system; adjust the operating settings of the memory storage device in response to the performance matching command to match the performance requirements of the host system; and interact with the host system based on the adjusted operating settings.

[0007] An exemplary embodiment of the present invention further provides a memory control circuit unit for controlling a rewritable non-volatile memory module. The memory control circuit unit includes a host interface, a memory interface, and a memory management circuit. The host interface is used to connect to a host system. The memory interface is used to connect to the rewritable non-volatile memory module. The memory management circuit is connected to the host interface and the memory interface. The memory management circuit is used to: receive a performance matching command from the host system; adjust the operating settings of the memory storage device in response to the performance matching command so that the performance of the memory storage device matches the performance requirements of the host system; and interact with the host system based on the adjusted operating settings.

[0008] Based on the above, upon receiving a performance matching command from the host system, the operating settings of the memory storage device can be dynamically adjusted in response to this command to match the performance requirements of the memory storage device with those of the host system. Subsequently, the memory storage device can interact with the host system based on the adjusted operating settings. Therefore, regardless of the original factory settings, the performance of the memory storage device can be dynamically adjusted to meet the requirements of the host system, thereby improving the operational performance of the memory storage device and / or preventing compatibility issues between the memory storage device and the host system after the device leaves the factory. Attached Figure Description

[0009] Figure 1 This is a schematic diagram of a host system, memory storage device, and input / output (I / O) device according to an exemplary embodiment of the present invention;

[0010] Figure 2 This is a schematic diagram of a host system, a memory storage device, and an I / O device according to an exemplary embodiment of the present invention;

[0011] Figure 3 This is a schematic diagram of a host system and a memory storage device according to an exemplary embodiment of the present invention;

[0012] Figure 4 This is a schematic diagram of a memory storage device according to an exemplary embodiment of the present invention;

[0013] Figure 5 This is a schematic diagram of a memory control circuit unit according to an exemplary embodiment of the present invention;

[0014] Figure 6 This is a schematic diagram illustrating the management of a rewritable non-volatile memory module according to an exemplary embodiment of the present invention;

[0015] Figure 7 This is a schematic diagram illustrating communication between a memory storage device and a host system according to an exemplary embodiment of the present invention;

[0016] Figure 8 This is a memory performance matching method shown in an embodiment of the present invention. Detailed Implementation

[0017] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same element references are used in the drawings and description to denote the same or similar parts.

[0018] Generally, a memory storage device (also known as a memory storage system) includes a rewritable non-volatile memory module and a controller (also known as a control circuit). The memory storage device can be used with a host system to enable the host system to write data to or read data from the memory storage device.

[0019] Figure 1 This is a schematic diagram of a host system, a memory storage device, and an input / output (I / O) device according to an exemplary embodiment of the present invention. Figure 2 This is a schematic diagram of a host system, a memory storage device, and an I / O device according to an exemplary embodiment of the present invention.

[0020] Please refer to Figure 1 and Figure 2 The host system 11 may include a processor 111, random access memory (RAM) 112, read-only memory (ROM) 113, and a data transfer interface 114. The processor 111, RAM 112, ROM 113, and data transfer interface 114 may be connected to the system bus 110.

[0021] In one exemplary embodiment, the host system 11 can be connected to the memory storage device 10 via a data transmission interface 114. For example, the host system 11 can store data to or read data from the memory storage device 10 via the data transmission interface 114. Furthermore, the host system 11 can be connected to the I / O device 12 via a system bus 110. For example, the host system 11 can transmit output signals to or receive input signals from the I / O device 12 via the system bus 110.

[0022] In one exemplary embodiment, the processor 111, random access memory 112, read-only memory 113, and data transfer interface 114 may be disposed on the motherboard 20 of the host system 11. The number of data transfer interfaces 114 may be one or more. Through the data transfer interface 114, the motherboard 20 may be connected to the memory storage device 10 via wired or wireless means.

[0023] In one exemplary embodiment, the memory storage device 10 may be, for example, a USB flash drive 201, a memory card 202, a solid-state drive (SSD) 203, or a wireless memory storage device 204. The wireless memory storage device 204 may be, for example, a Near Field Communication (NFC) memory storage device, a WiFi wireless fax memory storage device, a Bluetooth memory storage device, or a Bluetooth Low Energy (BLE) memory storage device (e.g., iBeacon), or other memory storage devices based on various wireless communication technologies. Furthermore, the motherboard 20 may also be connected via the system bus 110 to various I / O devices such as a Global Positioning System (GPS) module 205, a network interface card 206, a wireless transmission device 207, a keyboard 208, a screen 209, and a speaker 210. For example, in one exemplary embodiment, the motherboard 20 may access the wireless memory storage device 204 via the wireless transmission device 207.

[0024] In one exemplary embodiment, the host system 11 is a computer system. In another exemplary embodiment, the host system 11 may be any system capable of substantially cooperating with a memory storage device to store data. In one exemplary embodiment, the memory storage device 10 and the host system 11 may each include… Figure 3 The memory storage device 30 and the host system 31.

[0025] Figure 3 This is a schematic diagram of a host system and a memory storage device according to an exemplary embodiment of the present invention. Please refer to... Figure 3The memory storage device 30 can be used in conjunction with the host system 31 to store data. For example, the host system 31 can be a digital camera, camcorder, communication device, audio player, video player, or tablet computer. For example, the memory storage device 30 can be various non-volatile memory storage devices such as a Secure Digital (SD) card 32, a Compact Flash (CF) card 33, or an embedded storage device 34 used by the host system 31. The embedded storage device 34 includes various types of embedded storage devices that directly connect the memory module to the substrate of the host system, such as an embedded Multi Media Card (eMMC) 341 and / or an embedded Multi Chip Package (eMCP) storage device 342.

[0026] Figure 4 This is a schematic diagram of a memory storage device according to an exemplary embodiment of the present invention. Please refer to... Figure 4 The memory storage device 10 includes a connection interface unit 41, a memory control circuit unit 42, and a rewritable non-volatile memory module 43.

[0027] The connection interface unit 41 is used to connect the memory storage device 10 to the host system 11. The memory storage device 10 can communicate with the host system 11 via the connection interface unit 41. In an exemplary embodiment, the connection interface unit 41 is compatible with the Peripheral Component Interconnect Express (PCI Express) standard. However, it must be understood that the present invention is not limited thereto, and the connection interface unit 41 may also conform to the Serial Advanced Technology Attachment (SATA) standard, the Parallel Advanced Technology Attachment (PATA) standard, the Institute of Electrical and Electronics Engineers (IEEE) 1394 standard, the Universal Serial Bus (USB) standard, the SD interface standard, the Ultra High Speed-I (UHS-I) interface standard, the Ultra High Speed-II (UHS-II) interface standard, the Memory Stick (MS) interface standard, the MCP interface standard, the MMC interface standard, the eMMC interface standard, the Universal Flash Storage (UFS) interface standard, the eMCP interface standard, the CF interface standard, the Integrated Device Electronics (IDE) standard, or other suitable standards. The connection interface unit 41 can be packaged in a chip with the memory control circuit unit 42, or the connection interface unit 41 can be disposed outside a chip containing the memory control circuit unit 42.

[0028] The memory control circuit unit 42 is connected to the connection interface unit 41 and the rewritable non-volatile memory module 43. The memory control circuit unit 42 is used to execute multiple logic gates or control instructions implemented in hardware or firmware, and to perform operations such as writing, reading and erasing data in the rewritable non-volatile memory module 43 according to the instructions of the host system 11.

[0029] The rewritable non-volatile memory module 43 is used to store data written by the host system 11. The rewritable non-volatile memory module 43 may include a single-level cell (SLC) NAND flash memory module (i.e., a flash memory module that can store 1 bit in one memory cell), a multi-level cell (MLC) NAND flash memory module (i.e., a flash memory module that can store 2 bits in one memory cell), a triple-level cell (TLC) NAND flash memory module (i.e., a flash memory module that can store 3 bits in one memory cell), a quad-level cell (QLC) NAND flash memory module (i.e., a flash memory module that can store 4 bits in one memory cell), other flash memory modules, or other memory modules with the same characteristics.

[0030] Each memory cell in the rewritable non-volatile memory module 43 stores one or more bits by changing a voltage (hereinafter also referred to as the threshold voltage). Specifically, each memory cell has a charge trapping layer between its control gate and channel. By applying a write voltage to the control gate, the amount of electrons in the charge trapping layer can be changed, thereby changing the threshold voltage of the memory cell. This operation of changing the threshold voltage of the memory cell is also called "writing data to the memory cell" or "programming the memory cell". As the threshold voltage changes, each memory cell in the rewritable non-volatile memory module 43 has multiple storage states. By applying a read voltage, it can be determined which storage state a memory cell belongs to, thereby retrieving the one or more bits stored in that memory cell.

[0031] In one exemplary embodiment, the memory cells of the rewritable non-volatile memory module 43 can constitute multiple physical programming units, and these physical programming units can constitute multiple physical erase units. Specifically, memory cells on the same word line can form one or more physical programming units. If each memory cell can store more than two bits, then physical programming units on the same word line can be classified into lower physical programming units and upper physical programming units at least. For example, the least significant bit (LSB) of a memory cell belongs to the lower physical programming unit, and the most significant bit (MSB) of a memory cell belongs to the upper physical programming unit. Generally, in MLC NAND flash memory, the write speed of the lower physical programming unit is greater than that of the upper physical programming unit, and / or the reliability of the lower physical programming unit is higher than that of the upper physical programming unit.

[0032] In one exemplary embodiment, a physical programming unit is the smallest unit of programming. That is, a physical programming unit is the smallest unit for writing data. For example, a physical programming unit can be a physical page or a physical sector. If the physical programming unit is a physical page, these physical programming units may include data bit areas and redundancy bit areas. The data bit area contains multiple physical sectors for storing user data, while the redundancy bit area is used to store system data (e.g., management data such as error correction codes). In one exemplary embodiment, the data bit area contains 32 physical sectors, and the size of one physical sector is 512 bytes (B). However, in other exemplary embodiments, the data bit area may also contain 8, 16, or more or fewer physical sectors, and the size of each physical sector may also be larger or smaller. On the other hand, a physical erase unit is the smallest unit of erasure. That is, each physical erase unit contains a minimum number of storage units to be erased together. For example, a physical erase unit is a physical block.

[0033] Figure 5 This is a schematic diagram of a memory control circuit unit according to an exemplary embodiment of the present invention. Please refer to... Figure 5 The memory control circuit unit 42 includes a memory management circuit 51, a host interface 52, and a memory interface 53.

[0034] The memory management circuit 51 controls the overall operation of the memory control circuit unit 42. Specifically, the memory management circuit 51 has multiple control instructions, and these control instructions are executed when the memory storage device 10 is operating to perform operations such as writing, reading, and erasing data. The following description of the operation of the memory management circuit 51 is equivalent to the description of the operation of the memory control circuit unit 42.

[0035] In one exemplary embodiment, the control instructions of the memory management circuit 51 are implemented in firmware form. For example, the memory management circuit 51 has a microprocessor unit (not shown) and a read-only memory (not shown), and these control instructions are burned into the read-only memory. When the memory storage device 10 is operating, these control instructions are executed by the microprocessor unit to perform operations such as writing, reading, and erasing data.

[0036] In one exemplary embodiment, the control instructions of the memory management circuit 51 may also be stored in program code form in a specific area of ​​the rewritable non-volatile memory module 43 (e.g., a system area in the memory module dedicated to storing system data). Furthermore, the memory management circuit 51 includes a microprocessor unit (not shown), a read-only memory (not shown), and a random access memory (not shown). Specifically, this read-only memory has a boot code, and when the memory control circuit unit 42 is enabled, the microprocessor unit first executes this boot code to load the control instructions stored in the rewritable non-volatile memory module 43 into the random access memory of the memory management circuit 51. Subsequently, the microprocessor unit executes these control instructions to perform operations such as writing, reading, and erasing data.

[0037] In one exemplary embodiment, the control instructions for the memory management circuit 51 can also be implemented in hardware. For example, the memory management circuit 51 includes a microcontroller, a memory cell management circuit, a memory write circuit, a memory read circuit, a memory erase circuit, and a data processing circuit. The memory cell management circuit, memory write circuit, memory read circuit, memory erase circuit, and data processing circuit are connected to the microcontroller. The memory cell management circuit manages the memory cells or groups of memory cells in the rewritable non-volatile memory module 43. The memory write circuit issues a sequence of write instructions to the rewritable non-volatile memory module 43 to write data into the rewritable non-volatile memory module 43. The memory read circuit issues a sequence of read instructions to the rewritable non-volatile memory module 43 to read data from the rewritable non-volatile memory module 43. The memory erase circuit issues a sequence of erase instructions to the rewritable non-volatile memory module 43 to erase data from the rewritable non-volatile memory module 43. The data processing circuit is used to process data to be written to and read from the rewritable non-volatile memory module 43. The write instruction sequence, read instruction sequence, and erase instruction sequence may each include one or more program codes or instruction codes and are used to instruct the rewritable non-volatile memory module 43 to perform corresponding write, read, and erase operations. In an exemplary embodiment, the memory management circuit 51 may also issue other types of instruction sequences to the rewritable non-volatile memory module 43 to instruct it to perform corresponding operations.

[0038] The host interface 52 is connected to the memory management circuit 51. The memory management circuit 51 can communicate with the host system 11 through the host interface 52. The host interface 52 can be used to receive and identify instructions and data transmitted by the host system 11. For example, instructions and data transmitted by the host system 11 can be transmitted to the memory management circuit 51 through the host interface 52. In addition, the memory management circuit 51 can transmit data to the host system 11 through the host interface 52. In this exemplary embodiment, the host interface 52 is compatible with the PCI Express standard. However, it should be understood that the present invention is not limited thereto, and the host interface 52 may also be compatible with the SATA standard, PATA standard, IEEE 1394 standard, USB standard, SD standard, UHS-I standard, UHS-II standard, MS standard, MMC standard, eMMC standard, UFS standard, CF standard, IDE standard, or other suitable data transmission standards.

[0039] The memory interface 53 is connected to the memory management circuit 51 and is used to access the rewritable non-volatile memory module 43. For example, the memory management circuit 51 can access the rewritable non-volatile memory module 43 through the memory interface 53. That is, data to be written to the rewritable non-volatile memory module 43 is converted into a format acceptable to the rewritable non-volatile memory module 43 via the memory interface 53. Specifically, if the memory management circuit 51 needs to access the rewritable non-volatile memory module 43, the memory interface 53 will transmit a corresponding instruction sequence. For example, these instruction sequences may include write instruction sequences indicating the writing of data, read instruction sequences indicating the reading of data, erase instruction sequences indicating the erasure of data, and corresponding instruction sequences indicating various memory operations (e.g., changing the read voltage level or performing garbage collection operations, etc.). These instruction sequences are generated by the memory management circuit 51 and transmitted to the rewritable non-volatile memory module 43 via the memory interface 53. These instruction sequences may include one or more signals or data on the bus. These signals or data may include instruction codes or program codes. For example, a read instruction sequence may include information such as the read identification code and memory address.

[0040] In one exemplary embodiment, the memory control circuit unit 42 further includes an error checking and correction circuit 54, a buffer memory 55, and a power management circuit 56.

[0041] Error checking and correction circuit 54 is connected to memory management circuit 51 and is used to perform error checking and correction operations to ensure data integrity. Specifically, when memory management circuit 51 receives a write command from host system 11, error checking and correction circuit 54 generates a corresponding error correcting code (ECC) and / or error detecting code (EDC) for the data corresponding to the write command, and memory management circuit 51 writes the data corresponding to the write command and the corresponding error correcting code and / or error detecting code to rewritable non-volatile memory module 43. Subsequently, when memory management circuit 51 reads data from rewritable non-volatile memory module 43, it simultaneously reads the corresponding error correcting code and / or error detecting code for this data, and error checking and correction circuit 54 performs error checking and correction operations on the read data based on the error correcting code and / or error detecting code.

[0042] The buffer memory 55 is connected to the memory management circuit 51 and is used to cache data. The power management circuit 56 is connected to the memory management circuit 51 and is used to control the power supply of the memory storage device 10.

[0043] In one exemplary embodiment, Figure 4 The rewritable non-volatile memory module 43 may include a flash memory module. In one exemplary embodiment, Figure 4 The memory control circuit unit 42 may include a flash memory controller. In one exemplary embodiment, Figure 5 The memory management circuit 51 may include a flash memory management circuit.

[0044] Figure 6 This is a schematic diagram illustrating the management of a rewritable non-volatile memory module according to an exemplary embodiment of the present invention. Please refer to... Figure 6 The memory management circuit 51 can logically group the physical units 610(0) to 610(B) in the rewritable non-volatile memory module 43 into the storage area 601 and the spare area 602. For example, a physical unit may contain one or more physical programmable units.

[0045] Entity cells 610(0) to 610(A) in storage area 601 are used to store user data (e.g., from...) Figure 1 (User data of host system 11). For example, entity units 610(0) to 610(A) in storage area 601 can store valid and invalid data. Entity units 610(A+1) to 610(B) in free area 602 do not store data (e.g., valid data). For example, if an entity unit does not store valid data, this entity unit can be associated (or added) to free area 602. In addition, entity units in free area 602 (or entity units that do not store valid data) can be erased. When new data is written, one or more entity units can be retrieved from free area 602 to store this new data. In an exemplary embodiment, free area 602 is also referred to as a free pool.

[0046] The memory management circuit 51 can configure logic units 612(0) to 612(C) to map physical units 610(0) to 610(A) in memory area 601. In one exemplary embodiment, each logic unit corresponds to a logical address. For example, a logical address may include one or more logical block addresses (LBAs) or other logical management units. In one exemplary embodiment, a logic unit may also correspond to a logical programmable unit or consist of multiple consecutive or non-consecutive logical addresses.

[0047] It should be noted that a logical unit can be mapped to one or more entity units. If an entity unit is currently mapped to a logical unit, it means that the data currently stored in this entity unit includes valid data. Conversely, if an entity unit is not currently mapped to any logical unit, it means that the data currently stored in this entity unit is invalid data.

[0048] The memory management circuit 51 can record mapping information (also known as logic-to-entity mapping information) describing the mapping relationship between logical units and physical units in at least one mapping table (also known as a logic-to-entity mapping table). When the host system 11 wants to read data from the memory storage device 10 or write data to the memory storage device 10, the memory management circuit 51 can access the rewritable non-volatile memory module 43 according to the information in this mapping table (i.e., mapping information).

[0049] Figure 7 This is a schematic diagram illustrating communication between a memory storage device and a host system according to an exemplary embodiment of the present invention.

[0050] Please refer to Figure 7 In one exemplary embodiment, memory management circuitry 51 may receive an instruction (also known as a performance matching instruction) CMD from host system 11. The CMD can be used to provide the performance requirements of host system 11 to memory storage device 10. In response to the CMD, memory management circuitry 51 may adjust certain operating settings within memory storage device 10 to match the performance of memory storage device 10 with the performance requirements of host system 11. Subsequently, memory management circuitry 51 or memory storage device 10 may interact with host system 11 based on the adjusted operating settings. For example, memory management circuitry 51 may receive at least one operating instruction from host system 11 and execute the corresponding operating action (e.g., accessing rewritable non-volatile memory module 43) based on the adjusted operating settings. For example, the operating instruction may include read instructions, write instructions, and / or erase instructions.

[0051] In one exemplary embodiment, the instruction CMD may carry performance requirement information from the host system 11. This performance requirement information may reflect the performance requirements of the host system 11 for the memory storage device 10. For example, this performance requirement may be related to the performance, temperature, and / or input / output latency of the memory storage device 10, and the type of performance requirement of the host system 11 for the memory storage device 10 is not limited to these.

[0052] In one exemplary embodiment, the performance requirement information may reflect the input / output latency required by the host system 11, the storage space forcibly released by the host system 11 in the idle state of the memory storage device 10, and / or the power consumption setting (e.g., current value) of the memory storage device 10 in low-power modes (e.g., sleep, power-saving, or standby modes) required by the host system 11. Furthermore, the content of the performance requirement information may be adjusted according to practical needs, and this invention is not limited thereto.

[0053] In one exemplary embodiment, the memory management circuit 51 can parse the instruction CMD to obtain the performance requirement information. Then, the memory management circuit 51 can adjust some operating settings of the memory storage device 10 based on the performance requirement information. According to the adjusted operating settings, the memory management circuit 51 can interact with the host system 11 while meeting its performance requirements. In one exemplary embodiment, according to the adjusted operating settings, the memory management circuit 51 can also maximize the performance of the memory storage device 10 while meeting the performance requirements of the host system 11.

[0054] In one exemplary embodiment, in response to instruction CMD, memory management circuitry 51 may send a response RS to host system 11. The response RS may reflect whether memory storage device 10 can meet one or more performance requirements specified by host system 11.

[0055] In one exemplary embodiment, assuming that the memory management circuit 51 can meet a certain performance requirement (also referred to as a first performance requirement) specified by the host system 11 by adjusting some operating settings of the memory storage device 10, the response RS may carry response information (also referred to as first response information) corresponding to the first performance requirement. For example, the first response information may include an information bit (also referred to as a first information bit). For example, the bit value of the first information bit may be "1". Based on the first response information in the response RS, the host system 11 can determine that the memory storage device 10 can meet the first performance requirement specified by the host system 11.

[0056] In one exemplary embodiment, assuming that the memory management circuit 51 cannot meet a certain performance requirement (also referred to as a second performance requirement) specified by the host system 11 by adjusting some of the operating settings of the memory storage device 10, the response RS may carry response information corresponding to the second performance requirement (also referred to as second response information). For example, the second response information may include an information bit (also referred to as a second information bit). For example, the bit value of the second information bit may be "0". Based on the second response information in the response RS, the host system 11 can determine that the memory storage device 10 cannot meet the second performance requirement specified by the host system 11.

[0057] In one exemplary embodiment, in response to instruction CMD, memory management circuitry 51 can adjust (e.g., increase or decrease) at least one of the idle time threshold and low-power current value of memory storage device 10 to meet the performance requirements of host system 11. The idle time threshold can be used to control the timing at which memory storage device 10 enters a low-power mode (e.g., sleep, power-saving, or standby mode). For example, assuming the length of time memory storage device 10 is idle exceeds this idle time threshold, memory management circuitry 51 can control memory storage device 10 to enter a low-power mode. Furthermore, the low-power current value can be used to control the current value (or power consumption value) of memory storage device 10 when operating in low-power mode.

[0058] In one exemplary embodiment, in response to instruction CMD, memory management circuitry 51 can adjust the behavior mode of memory storage device 10 corresponding to at least one operating instruction from host system 11 to meet the performance requirements of host system 11.

[0059] Taking garbage collection as an example, during the execution of write instructions from the host system 11 by the memory storage device 10, the garbage collection operation can be performed in the background of the memory storage device 10 to move valid data from at least one physical unit (also called a source physical unit) to another physical unit (also called a target physical unit). If the valid data stored in a source physical unit is completely moved, this source physical unit can be erased and set as a new idle physical unit (e.g., added to a new system). Figure 6 (Idle area 602).

[0060] In one exemplary embodiment, in response to instruction CMD, memory management circuitry 51 can adjust the operation settings of the garbage collection operation to meet the input / output latency required by host system 11. For example, when the input / output latency required by host system 11 is short, memory management circuitry 51 can reduce the amount of valid data collected by the garbage collection operation (equivalent to reducing the total number of source entity units) to reduce the latency caused by the garbage collection operation executed in the background to the write instruction currently executed in the foreground. Alternatively, when the input / output latency required by host system 11 is long, memory management circuitry 51 can increase the amount of valid data collected by the garbage collection operation (equivalent to increasing the total number of source entity units) to increase the execution efficiency of the garbage collection operation executed in the background. Furthermore, the type and method of adjustment of the operation parameters that memory management circuitry 51 can adjust under different operating scenarios can also be set according to practical needs, and the present invention is not limited thereto.

[0061] In one exemplary embodiment, upon receiving the instruction CMD, the memory management circuit 51 determines, through table lookup or algorithmic calculation, whether to adjust specific operational settings in the memory storage device 10. Thus, in subsequent interactions between the memory storage device 10 and the host system 11, the adjusted operational settings can be used to meet the performance requirements of the host system 11 for the memory storage device 10. The relevant lookup tables or algorithms can be configured according to practical needs, and this invention is not limited thereto.

[0062] Figure 8 This is a memory performance matching method shown in an embodiment of the present invention. Please refer to... Figure 8 In step S801, a performance matching command is received from the host system. In step S802, in response to the performance matching command, the operating settings of the memory storage device are adjusted to match the performance of the memory storage device with the performance requirements of the host system. In step S803, the system interacts with the host system based on the adjusted operating settings.

[0063] However, Figure 8 Each step has been explained in detail above and will not be repeated here. It is worth noting that... Figure 8 Each step can be implemented as multiple pieces of code or circuits; this application does not impose any restrictions. Furthermore, Figure 8 The method can be used in conjunction with the above examples and embodiments, or it can be used alone; this case does not impose any restrictions.

[0064] In summary, upon receiving a performance matching command from the host system, the operating settings of the memory device can be dynamically adjusted in response to this command, ensuring that the performance of the memory device matches the performance requirements of the host system. Subsequently, the memory device can interact with the host system based on the adjusted operating settings. Therefore, regardless of the original factory settings, the performance of the memory device can be dynamically adjusted to meet the requirements of the host system, thereby improving the operational performance of the memory device and / or preventing compatibility issues between the memory device and the host system after the device leaves the factory.

[0065] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for matching the performance of a memory, characterized in that, For a memory storage device, the performance matching method of the memory includes: Receive a performance matching instruction from the host system, the performance matching instruction carrying performance requirement information from the host system, wherein the performance requirement information reflects the storage space that the host system requires to be forcibly released when the memory storage device is idle and the input / output latency time required by the host system. Parse the performance matching instruction to obtain the performance requirement information; In response to the performance matching instruction, the operating settings of the memory storage device are adjusted, including adjusting the behavior mode of the garbage collection operation performed by the memory storage device in the background during the execution of a write instruction from the host system by the memory storage device, based on the performance requirement information, so that the performance of the memory storage device matches the performance requirements of the host system. Interacting with the host system based on the adjusted operation settings; and In response to the performance matching command, a response is sent to the host system, wherein the response reflects whether the memory storage device can meet the performance requirements of the host system. The adjustment of the behavior mode of the garbage collection operation performed in the background by the memory storage device during the execution of the write instruction from the host system, based on the performance requirement information, includes: Based on the input / output delay time required by the host system, the total number of source entity units used to collect valid data in the garbage collection operation is dynamically adjusted. Sending the response to the host system in response to the performance matching command includes: If the memory storage device can meet the first performance requirement specified by the host system, the response includes a first information bit reflecting that the memory storage device can meet the first performance requirement specified by the host system; and If the memory storage device cannot meet the second performance requirement specified by the host system, the response includes a second information bit reflecting that the memory storage device cannot meet the second performance requirement specified by the host system.

2. The memory performance matching method according to claim 1, The performance requirement information also reflects at least one of the power consumption settings required by the host system for the memory storage device in low-power mode.

3. The memory performance matching method according to claim 1, wherein the step of adjusting the operating settings of the memory storage device in response to the performance matching instruction includes: Adjust at least one of the idle time threshold and low power current value of the memory storage device to meet the performance requirements of the host system.

4. The memory performance matching method according to claim 1, wherein the step of adjusting the operating settings of the memory storage device in response to the performance matching instruction includes: The behavior mode of the memory storage device is adjusted to correspond to at least one operation instruction from the host system in order to meet the performance requirements of the host system.

5. A memory storage device, characterized in that, include: A connection interface unit for connecting to the host system; Rewritable non-volatile memory module; as well as The memory control circuit unit is connected to the connection interface unit and the rewritable non-volatile memory module. The memory control circuit unit is used to: The host system receives a performance matching instruction, which carries performance requirement information from the host system, wherein the performance requirement information reflects the storage space that the host system requires to be forcibly released when the memory storage device is idle and the input / output latency time required by the host system. Parse the performance matching instruction to obtain the performance requirement information; In response to the performance matching instruction, the operating settings of the memory storage device are adjusted, including adjusting the behavior mode of the garbage collection operation performed by the memory storage device in the background during the execution of a write instruction from the host system by the memory storage device, based on the performance requirement information, so that the performance of the memory storage device matches the performance requirements of the host system. Interacting with the host system based on the adjusted operation settings; as well as In response to the performance matching command, a response is sent to the host system, wherein the response reflects whether the memory storage device can meet the performance requirements of the host system. The adjustment of the behavior mode of the garbage collection operation performed in the background by the memory storage device during the execution of the write instruction from the host system, based on the performance requirement information, includes: Based on the input / output delay time required by the host system, the total number of source entity units used to collect valid data in the garbage collection operation is dynamically adjusted. Sending the response to the host system in response to the performance matching command includes: If the memory storage device can meet the first performance requirement specified by the host system, the response includes a first information bit reflecting that the memory storage device can meet the first performance requirement specified by the host system; and If the memory storage device cannot meet the second performance requirement specified by the host system, the response includes a second information bit reflecting that the memory storage device cannot meet the second performance requirement specified by the host system.

6. The memory storage device according to claim 5, The performance requirement information also reflects at least one of the power consumption settings required by the host system for the memory storage device in low-power mode.

7. The memory storage device of claim 5, wherein the operation of the memory control circuit unit adjusting the operation settings of the memory storage device in response to the performance matching command includes: Adjust at least one of the idle time threshold and low power current value of the memory storage device to meet the performance requirements of the host system.

8. The memory storage device of claim 5, wherein the operation of the memory control circuit unit adjusting the operation settings of the memory storage device in response to the performance matching command includes: The behavior mode of the memory storage device is adjusted to correspond to at least one operation instruction from the host system in order to meet the performance requirements of the host system.

9. A memory control circuit unit, characterized in that, For controlling a memory storage device, the memory control circuit unit includes: Host interface, used to connect to the host system; A memory interface for connecting to a rewritable non-volatile memory module; and The memory management circuit is connected to the host interface and the memory interface. The memory management circuit mentioned above is used for: The host system receives a performance matching instruction, which carries performance requirement information from the host system, wherein the performance requirement information reflects the storage space that the host system requires to be forcibly released when the memory storage device is idle and the input / output latency time required by the host system. Parse the performance matching instruction to obtain the performance requirement information; In response to the performance matching instruction, the operating settings of the memory storage device are adjusted, including adjusting the behavior mode of the garbage collection operation performed by the memory storage device in the background during the execution of a write instruction from the host system by the memory storage device, based on the performance requirement information, so that the performance of the memory storage device matches the performance requirements of the host system. Interacting with the host system based on the adjusted operation settings; and In response to the performance matching command, a response is sent to the host system, wherein the response reflects whether the memory storage device can meet the performance requirements of the host system. The adjustment of the behavior mode of the garbage collection operation performed in the background by the memory storage device during the execution of the write instruction from the host system, based on the performance requirement information, includes: Based on the input / output delay time required by the host system, the total number of source entity units used to collect valid data in the garbage collection operation is dynamically adjusted. Sending the response to the host system in response to the performance matching command includes: If the memory storage device can meet the first performance requirement specified by the host system, the response includes a first information bit reflecting that the memory storage device can meet the first performance requirement specified by the host system; and If the memory storage device cannot meet the second performance requirement specified by the host system, the response includes a second information bit reflecting that the memory storage device cannot meet the second performance requirement specified by the host system.

10. The memory control circuit unit according to claim 9, The performance requirement information also reflects at least one of the power consumption settings required by the host system for the memory storage device in low-power mode.

11. The memory control circuit unit of claim 9, wherein the operation of the memory management circuit adjusting the operation settings of the memory storage device in response to the performance matching command includes: Adjust at least one of the idle time threshold and low power current value of the memory storage device to meet the performance requirements of the host system.

12. The memory control circuit unit of claim 9, wherein the operation of the memory management circuit adjusting the operation settings of the memory storage device in response to the performance matching command includes: The behavior mode of the memory storage device is adjusted to correspond to at least one operation instruction from the host system in order to meet the performance requirements of the host system.

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