A high-efficiency heterojunction solar cell and its manufacturing method

Abstract

This invention relates to a method for fabricating a high-efficiency heterojunction solar cell, comprising forming a first semiconductor film layer with N-type or P-type doping on a first passivation layer of a passivated semiconductor substrate. The specific steps are as follows: Step A, forming a first microcrystalline silicon stack on the first passivation layer of the passivated semiconductor substrate; Step B, forming a first amorphous silicon layer on the first microcrystalline silicon stack. The purpose of this invention is to provide a high-efficiency heterojunction solar cell and its manufacturing method. By employing an N-type semiconductor film layer and / or a P-type semiconductor film layer composed of a microcrystalline silicon stack and an amorphous silicon layer, the effects of short-circuit current, open-circuit voltage, and fill factor can be simultaneously improved, resulting in a significant increase in cell efficiency.

Description

Technical Field

[0001] This invention relates to a high-efficiency heterojunction solar cell and its manufacturing method. Background Technology

[0002] Heterojunction solar cells have simple manufacturing processes and low temperatures. They also offer advantages such as high power generation, high stability, no degradation, and low cost. With continuous technological advancements and policy support in the industry, heterojunction solar cells are showing their cost-effectiveness advantage and may replace crystalline silicon solar cells as the next generation of mainstream photovoltaic cells.

[0003] Traditional heterojunction solar cells use N-type monocrystalline silicon wafers as substrates, with an intrinsic amorphous silicon layer (I-layer) passivating the crystalline silicon surface. A boron-doped P-type amorphous silicon thin film serves as the emitter layer, and a phosphorus-doped N-type amorphous silicon thin film forms the back field. This core process technology is crucial to the efficiency of heterojunction solar cells. Compared to doped amorphous silicon thin films, doped microcrystalline silicon thin films offer advantages such as higher doping efficiency, higher conductivity, and lower light absorption, making their application in heterojunction cells a promising way to further improve cell efficiency. However, the higher potential barrier between the microcrystalline silicon layer and the TCO thin film reduces the cell's open-circuit voltage and also increases the series resistance, leading to a decrease in cell conversion efficiency. Summary of the Invention

[0004] The purpose of this invention is to provide a high-efficiency heterojunction solar cell and its manufacturing method. By using an N-type semiconductor film layer and / or a P-type semiconductor film layer composed of microcrystalline silicon stack and amorphous silicon layer, the effects of short-circuit current, open-circuit voltage and fill factor of the cell can be improved simultaneously, and the cell efficiency is significantly improved.

[0005] The objective of this invention is achieved through the following technical solution:

[0006] A high-efficiency heterojunction solar cell includes a semiconductor substrate, a first passivation layer disposed on a first main surface of the semiconductor substrate, and a first semiconductor film layer disposed on the first passivation layer and having N-type doping or P-type doping; the first semiconductor film layer includes a first microcrystalline silicon stack disposed on the first passivation layer and a first amorphous silicon layer disposed on the first microcrystalline silicon stack and having doping of the same conductivity type as the first microcrystalline silicon stack.

[0007] A method for fabricating a high-efficiency heterojunction solar cell includes forming a first semiconductor film layer with N-type or P-type doping on a first passivation layer of a passivated semiconductor substrate. The specific steps are as follows.

[0008] Step A: A first microcrystalline silicon stack is formed on the first passivation layer of the passivated semiconductor substrate;

[0009] Step B: A first amorphous silicon layer is formed on the first microcrystalline silicon stack.

[0010] Compared with the prior art, the advantages of the present invention are as follows:

[0011] By designing the doped semiconductor film as a composite layer structure, on the one hand, the microcrystalline silicon stack is used to improve the optical bandgap and doping efficiency of the thin film, enabling the battery to obtain high short-circuit current and open-circuit voltage; on the other hand, the thin doped amorphous silicon layer and the conductive film layer form good contact, reducing series resistance and improving the fill factor of the battery, enabling the battery to obtain high conversion efficiency. Attached Figure Description

[0012] Figure 1 This is a schematic diagram of one embodiment of the high-efficiency heterojunction solar cell provided by the present invention.

[0013] Figure 2 This is a schematic diagram of one embodiment of the high-efficiency heterojunction solar cell provided by the present invention.

[0014] Figure 3 This is a schematic diagram of one embodiment of the high-efficiency heterojunction solar cell provided by the present invention.

[0015] Figure 4 A flowchart illustrating the fabrication method of the high-efficiency heterojunction solar cell provided by this invention.

[0016] Figure 5 This is a schematic diagram of one embodiment of the high-efficiency heterojunction solar cell provided by the present invention. Detailed Implementation

[0017] A high-efficiency heterojunction solar cell includes a semiconductor substrate, a first passivation layer disposed on a first main surface of the semiconductor substrate, and a first semiconductor film layer disposed on the first passivation layer and having N-type doping or P-type doping; the first semiconductor film layer includes a first microcrystalline silicon stack disposed on the first passivation layer and a first amorphous silicon layer disposed on the first microcrystalline silicon stack and having doping of the same conductivity type as the first microcrystalline silicon stack.

[0018] The first microcrystalline silicon stack includes a first microcrystalline silicon seed layer, a first microcrystalline silicon oxide layer with N-type doping or P-type doping, and a first microcrystalline silicon layer with the same conductivity type doping as the first microcrystalline silicon oxide layer, arranged sequentially from bottom to top on a first passivation layer as a substrate.

[0019] When the first semiconductor film layer is N-type doped, the thickness of the first microcrystalline silicon seed layer is 1-4 nm, the thickness of the first microcrystalline silicon oxide layer is 4-8 nm, the thickness of the first microcrystalline silicon layer is 1-4 nm, and the thickness of the first amorphous silicon layer is 1-4 nm.

[0020] When the first semiconductor film layer is P-type doped, the thickness of the first microcrystalline silicon seed layer is 1-4 nm, the thickness of the first microcrystalline silicon oxide layer is 2-6 nm, the thickness of the first microcrystalline silicon layer is 8-20 nm, and the thickness of the first amorphous silicon layer is 1-4 nm.

[0021] In one specific embodiment, the high-efficiency heterojunction solar cell further includes a second passivation layer disposed on a second main surface of a semiconductor substrate and a second semiconductor film layer disposed on the second passivation layer and having a different conductivity type doping than the first semiconductor film layer; the second semiconductor film layer includes a second microcrystalline silicon stack disposed on the second passivation layer and a second amorphous silicon layer disposed on the second microcrystalline silicon stack and having the same conductivity type doping as the second microcrystalline silicon stack.

[0022] In one specific embodiment, the first passivation layer is disposed only on a portion of the first main surface of the semiconductor substrate; a second passivation layer and a second semiconductor film layer disposed on the second passivation layer and having a different conductivity type doping than the first semiconductor film layer are disposed on the first main surface not covered by the first passivation layer; the second semiconductor film layer includes a second microcrystalline silicon stack disposed on the second passivation layer and a second amorphous silicon layer disposed on the second microcrystalline silicon stack and having the same conductivity type doping as the second microcrystalline silicon stack.

[0023] A method for manufacturing a high-efficiency heterojunction solar cell includes forming a first semiconductor film layer with N-type or P-type doping on a first passivation layer of a passivated semiconductor substrate. The specific steps are as follows.

[0024] Step A: A first microcrystalline silicon stack is formed on the first passivation layer of the passivated semiconductor substrate;

[0025] Step B: A first amorphous silicon layer is formed on the first microcrystalline silicon stack.

[0026] The specific steps of step A are as follows: a1, depositing a first microcrystalline silicon seed layer on the first passivation layer of the passivated semiconductor substrate; a2, depositing a first microcrystalline silicon oxide layer with N-type doping or P-type doping on the first microcrystalline silicon seed layer; a3, depositing a first microcrystalline silicon layer with doping of the same conductivity type as the first microcrystalline silicon oxide layer on the first microcrystalline silicon oxide layer.

[0027] The specific method of process a1 is as follows: first, the PECVD film formation temperature is preset to 150-250℃, and then a mixed gas of silane and hydrogen is introduced, with a reaction gas pressure of 100-300Pa, to deposit the first microcrystalline silicon seed layer.

[0028] When preparing the N-type doped first semiconductor film, the specific method of step a2 is as follows: first, the PECVD film formation temperature is preset to 150-250℃, and then a mixed gas of silane, phosphine, hydrogen and carbon dioxide is introduced. The reaction gas pressure is 150-500Pa, the ratio of phosphine to silane is 1%-10%, and the ratio of carbon dioxide to silane is 50%-100%, so as to deposit the N-type first microcrystalline silicon oxide layer.

[0029] When preparing the P-type doped first semiconductor film layer, the specific method of step a2 is as follows: first, the PECVD film formation temperature is preset to 150-250℃, and then a mixed gas of silane, diborane, hydrogen and carbon dioxide is introduced. The reaction gas pressure is 150-500Pa, the ratio of diborane to silane is 0.5%-4%, and the ratio of carbon dioxide to silane is 50%-100%, so as to deposit the P-type first microcrystalline silicon oxide layer.

[0030] When preparing the N-type doped first semiconductor film, the specific method of step a3 is as follows: first, preset the PECVD film formation temperature to 150-250℃, then introduce a mixed gas of silane, phosphine, and hydrogen, with a reaction gas pressure of 150-500 Pa and a deposition power density of 0.08-0.3 W / cm³. 2 The ratio of phosphine to silane is 1%-10% to deposit the first N-type microcrystalline silicon layer;

[0031] When preparing the P-type doped first semiconductor film, the specific method of step a3 is as follows: first, the PECVD film formation temperature is preset to 150-250℃, then a mixed gas of silane, diborane, and hydrogen is introduced, the reaction gas pressure is 150-500 Pa, and the deposition power density is 0.1-0.5 W / cm³. 2 The ratio of diborane to silane is 0.5%-4% to deposit a first microcrystalline silicon layer of P-type.

[0032] When preparing the N-type doped first semiconductor film, the specific method of step B is as follows: first, preset the PECVD film formation temperature to 150-250℃, then introduce a mixed gas of silane, phosphine, and hydrogen, with a reaction gas pressure of 30-150 Pa and a deposition power density of 0.01-0.02 W / cm². 2 The ratio of phosphine to silane is 1%-10% to deposit the first N-type amorphous silicon layer;

[0033] When preparing the P-type doped first semiconductor film, the specific method of step B is as follows: first, preset the PECVD film formation temperature to 150-250℃, then introduce a mixed gas of silane, diborane, and hydrogen, with a reaction gas pressure of 30-150 Pa and a deposition power density of 0.01-0.02 W / cm³. 2 The ratio of diborane to silane is 1%-10% to deposit a P-type first amorphous silicon layer.

[0034] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0035] like Figure 1 As shown, the present invention provides a high-efficiency heterojunction solar cell, comprising: an N-type silicon wafer 10, a first intrinsic amorphous silicon layer 20 (i.e., a first passivation layer), an N-type semiconductor film layer 30 (i.e., a first semiconductor film layer) and a front transparent conductive layer 60-1 and a front metal grid line 70-1 sequentially disposed on the front side of the silicon wafer 10, and a second intrinsic amorphous silicon layer 40 (i.e., a second passivation layer), a P-type semiconductor film layer 50 (i.e., a second semiconductor film layer) and a back transparent conductive layer 60-2 and a back metal grid line 70-2 sequentially disposed on the back side of the silicon wafer 10. The N-type semiconductor film 30 and / or the P-type semiconductor film 50 are multilayer composite structures. The N-type semiconductor film 30 includes an N-face microcrystalline silicon seed layer 31, an N-type microcrystalline silicon oxide layer 32, an N-type microcrystalline silicon layer 33, and an N-type amorphous silicon layer 34. The P-type semiconductor film 50 includes a P-face microcrystalline silicon seed layer 51, a P-type microcrystalline silicon oxide layer 52, a P-type microcrystalline silicon layer 53, and a P-type amorphous silicon layer 54.

[0036] The N-type silicon wafer is either a monocrystalline silicon wafer or a polycrystalline silicon wafer.

[0037] The thickness of the N-face microcrystalline silicon seed layer 31 is 1-4 nm; the thickness of the N-type microcrystalline silicon oxide layer 32 is 4-8 nm; the thickness of the N-type microcrystalline silicon layer 33 is 1-4 nm; and the thickness of the N-type amorphous silicon layer 34 is 1-4 nm.

[0038] The thickness of the P-face microcrystalline silicon seed layer 51 is 1-4 nm; the thickness of the P-type microcrystalline silicon oxide layer 52 is 2-6 nm; the thickness of the P-type microcrystalline silicon layer 53 is 8-20 nm; and the thickness of the P-type amorphous silicon layer 54 is 1-4 nm.

[0039] In another implementation, such as Figure 5As shown, a back-contact heterojunction solar cell (HBC) includes an N-type monocrystalline silicon wafer 80, a third intrinsic amorphous silicon layer 97 and an anti-reflection layer 98 sequentially stacked on the front side of the silicon wafer 80, a P-region intrinsic amorphous silicon layer 81 (i.e., a first passivation layer), a P-region semiconductor film layer (i.e., a first semiconductor film layer, including a P-region microcrystalline silicon seed layer 82, a P-type microcrystalline silicon oxide layer 83, a P-type microcrystalline silicon layer 84, and a P-type amorphous silicon layer 85), a P-region transparent conductive film layer 93, and a P-region metal grid line 94 sequentially stacked on the P-region surface of the back side of the silicon wafer, and an N-region intrinsic amorphous silicon layer 87 (i.e., a second passivation layer), an N-region semiconductor film layer (i.e., a second semiconductor film layer, including an N-region microcrystalline silicon seed layer 88, an N-type microcrystalline silicon oxide layer 89, an N-type microcrystalline silicon layer 90, and an N-type amorphous silicon layer 91), an N-region transparent conductive layer 92, and an N-region metal grid line 95 sequentially stacked on the N-region surface of the back side of the silicon wafer. At the junction of the N-region and the P-region, the intrinsic amorphous silicon layer 87 (i.e., the second passivation layer) and the semiconductor film layer of the N-region are stacked on the semiconductor film layer of the P-region through an insulating film layer 86. An insulating groove 96 is provided between the transparent conductive film layer 93 of the P-region and the transparent conductive layer 92 of the N-region for separation.

[0040] like Figure 1 and 4 As shown, the method for fabricating the high-efficiency heterojunction solar cell includes the following steps:

[0041] S01 provides texturized and cleaned N-type silicon wafers;

[0042] S02, a second intrinsic amorphous silicon layer is deposited on the back side of the silicon wafer by PECVD;

[0043] S03, depositing the first intrinsic amorphous silicon layer on the front side of the silicon wafer by PECVD;

[0044] S04, deposit an N-type semiconductor film layer on the first intrinsic amorphous silicon layer on the front side of the silicon wafer by PECVD; specifically, deposit an N-type doped layer or sequentially deposit an N-side seed layer, an N-type microcrystalline silicon oxide layer, an N-type microcrystalline silicon layer and an N-type amorphous silicon layer to form a multilayer composite N-type semiconductor film layer 30.

[0045] S05, deposit a P-type semiconductor film layer on the second intrinsic amorphous silicon layer on the back side of the silicon wafer by PECVD; specifically, deposit a P-type doped layer or sequentially deposit a P-face microcrystalline silicon seed layer, a P-type microcrystalline silicon oxide layer, a P-type microcrystalline silicon layer, and a P-type amorphous silicon layer to form a multilayer composite P-type semiconductor film layer 50.

[0046] S06, by PVD magnetron sputtering, a front transparent conductive layer 60-1 is deposited on the front of the silicon wafer, and a back transparent conductive layer 60-2 is deposited on the back of the silicon wafer;

[0047] S07, fabricate front metal gate line 70-1 and back metal gate line 70-2 on the front and back sides of the silicon wafer, respectively;

[0048] The process of depositing the N-plane microcrystalline silicon seed layer in step S04 and the process of depositing the P-plane microcrystalline silicon seed layer in step S05 involves introducing a mixed gas of silane and hydrogen, with a reaction gas pressure of 100-300 Pa.

[0049] The process of depositing the N-type microcrystalline silicon oxide layer in step S04 involves introducing a mixed gas of silane, phosphine, hydrogen, and carbon dioxide. The reaction gas pressure is 150-500 Pa, the ratio of phosphine to silane is 1%-10%, and the ratio of carbon dioxide to silane is 50%-100%.

[0050] The process of depositing the N-type microcrystalline silicon layer in step S04 involves introducing a mixed gas of silane, phosphine, and hydrogen, with a reaction gas pressure of 150-500 Pa and a deposition power density of 0.08-0.3 W / cm³. 2 The ratio of phosphine to silane is 1%-10%;

[0051] The process of depositing the N-type amorphous silicon layer in step S04 involves introducing a mixed gas of silane, phosphine, and hydrogen at a pressure of 30-150 Pa and a deposition power density of 0.01-0.02 W / cm³. 2 The ratio of phosphine to silane is 1%-10%.

[0052] In step S04, the preset film-forming temperature for PECVD is 150-250℃.

[0053] The process of depositing the P-type microcrystalline silicon oxide layer in step S05 involves first setting the PECVD film formation temperature to 150-250℃, and then introducing a mixed gas of silane, diborane, hydrogen, and carbon dioxide. The reaction gas pressure is 150-500 Pa, the ratio of diborane to silane is 0.5%-4%, and the ratio of carbon dioxide to silane is 50%-100%.

[0054] The process of depositing the P-type microcrystalline silicon layer in step S05 involves first setting the PECVD film formation temperature to 150-250℃, then introducing a mixed gas of silane, diborane, and hydrogen at a reaction gas pressure of 150-500 Pa and a deposition power density of 0.1-0.5 W / cm³. 2 The ratio of diborane to silane is 0.5%-4%.

[0055] In step S05, the deposition of the P-type amorphous silicon layer involves introducing a mixed gas of silane, diborane, and hydrogen. The reaction gas pressure is 30-150 Pa, and the deposition power density is 0.01-0.02 W / cm³. 2The ratio of diborane to silane is 1%-10%.

[0056] Example 1

[0057] A high-efficiency heterojunction solar cell (e.g.) Figure 1 The manufacturing method shown is as follows:

[0058] S01, providing an N-type silicon wafer 10 that has been texturized and cleaned; the specific process is to form a pyramidal textured surface on the surface of the N-type silicon wafer 10 through a texturizing and cleaning method, and keep it clean; the N-type silicon wafer 10 is a monocrystalline silicon wafer.

[0059] S02, a second intrinsic amorphous silicon layer 40 is deposited on the back side of the silicon wafer 10 after S01 treatment by PECVD; the specific process is to introduce silane and hydrogen into the reaction chamber; the preset film formation temperature is 150-250℃; the reaction gas pressure is 30-150Pa; the deposition thickness is 5-10nm.

[0060] S03, depositing the first intrinsic amorphous silicon layer 20 on the front side of the silicon wafer 10 after SO2 treatment by PECVD; the specific process is to introduce silane and hydrogen into the reaction chamber; the preset film formation temperature is 150-250℃; the reaction gas pressure is 30-150Pa; the deposition thickness is 4-7nm.

[0061] S04, on the first intrinsic amorphous silicon layer 20 on the front side of the silicon wafer 10 after S03 treatment, an N-face microcrystalline silicon seed layer 31, an N-type microcrystalline silicon oxide layer 32, an N-type microcrystalline silicon layer 33, and an N-type amorphous silicon layer 34 are sequentially deposited by PECVD to form a multilayer composite structure N-type doped layer; the specific process is as follows: the preset film deposition temperature is 150-250℃; a mixture of silane and hydrogen gas is first introduced into the reaction chamber at a pressure of 100-300Pa to deposit the first layer as the N-face microcrystalline silicon seed layer 31, with a thickness of 1-4nm; then silane and phosphorus are introduced into the reaction chamber. A mixture of phosphine, hydrogen, and carbon dioxide is deposited, with a phosphine to silane ratio of 1%-10% and a carbon dioxide to silane ratio of 50%-100%. The reaction gas pressure is 150-500 Pa. A second layer, N-type microcrystalline silicon oxide layer 32, with a thickness of 4-8 nm, is deposited. Finally, a mixture of silane, phosphine, and hydrogen is introduced into the reaction chamber, with a phosphine to silane ratio of 1%-10% and a reaction gas pressure of 150-500 Pa. A third layer, N-type microcrystalline silicon layer 33, with a thickness of 1-4 nm, is deposited. A fourth layer, N-type amorphous silicon layer 34, with a thickness of 1-4 nm, is deposited.

[0062] S05, on the second intrinsic amorphous silicon layer on the back side of the silicon wafer 10 after S04 treatment, a P-face microcrystalline silicon seed layer 51, a P-type microcrystalline silicon oxide layer 52, a P-type microcrystalline silicon layer 53, and a P-type amorphous silicon layer 54 are deposited by PECVD to form a multilayer composite structure P-type doped layer; the specific process is as follows: the preset film deposition temperature is 150-250℃; a mixture of silane and hydrogen gas is first introduced into the reaction chamber at a pressure of 100-300Pa to deposit the first layer as the P-face microcrystalline silicon seed layer 51, with a thickness of 1-4nm; then silane, diborane, and hydrogen gas are introduced into the reaction chamber to... A mixture of silane, diborane, and hydrogen is introduced into the reaction chamber, with diborane to silane ratio of 0.5%-4% and carbon dioxide to silane ratio of 50%-100%. The reaction gas pressure is 150-500 Pa. A second layer, P-type microcrystalline silicon oxide layer 52, with a thickness of 2-6 nm, is deposited. Finally, a mixture of silane, diborane, and hydrogen is introduced into the reaction chamber, with diborane to silane ratio of 0.5%-4% and reaction gas pressure of 150-500 Pa. A third layer, P-type microcrystalline silicon layer 53, with a thickness of 8-20 nm, is deposited. A fourth layer, P-type amorphous silicon layer 54, with a thickness of 1-4 nm, is deposited.

[0063] In S06, a transparent conductive layer 60-1 (ITO) is deposited on the front side of the silicon wafer 10 after S05 by PVD magnetron sputtering, and a transparent conductive layer 60-2 (ITO) is deposited on the back side of the silicon wafer 10 after S05 by PVD magnetron sputtering; the deposition thickness is 90-110nm.

[0064] S07, front metal grid lines 70-1 (silver grid) are fabricated on the front transparent conductive layer 60-1 of the silicon wafer 10 after processing in S06 by screen printing, and back metal grid lines 70-2 (silver grid) are fabricated on the back transparent conductive layer 60-2 of the silicon wafer 10 by screen printing.

[0065] Example 2

[0066] A high-efficiency heterojunction solar cell (e.g.) Figure 2 The manufacturing method shown is different from that of Example 1 only in the following aspects:

[0067] S05, depositing a P-type semiconductor film 50 on the second intrinsic amorphous silicon layer 40 on the back side of the silicon wafer after S04 treatment by PECVD; the specific process is to introduce diborane, silane and hydrogen into the reaction chamber; the preset film formation temperature is 150-250℃; the reaction gas pressure is 30-150Pa; the deposition thickness is 6-14nm.

[0068] Example 3

[0069] A high-efficiency heterojunction solar cell (e.g.) Figure 3 The manufacturing method shown is different from that of Example 1 only in the following aspects:

[0070] S04, depositing an N-type semiconductor film 30 on the first intrinsic amorphous silicon layer 20 on the front side of the silicon wafer after S03 treatment by PECVD; the specific process is to introduce phosphine, silane and hydrogen into the reaction chamber; the preset film formation temperature is 150-250℃; the reaction gas pressure is 30-150Pa; the deposition thickness is 4-7nm.

[0071] Table 1 lists a comparison of the efficiency of the heterojunction solar cell provided by this invention and conventional heterojunction solar cells. The results show that the heterojunction solar cell provided by this invention performs better in terms of electrical performance, as detailed below:

[0072]

Claims

1. A high-efficiency heterojunction solar cell, characterized in that: It includes a semiconductor substrate, a first passivation layer disposed on a first main surface of the semiconductor substrate, and a first semiconductor film layer disposed on the first passivation layer and having N-type doping; the first semiconductor film layer includes a first microcrystalline silicon stack disposed on the first passivation layer and an N-type amorphous silicon layer disposed on the first microcrystalline silicon stack and having the same conductivity type doping as the first microcrystalline silicon stack; the first microcrystalline silicon stack includes an N-type microcrystalline silicon seed layer, an N-type microcrystalline silicon oxide layer, and an N-type microcrystalline silicon layer disposed sequentially from bottom to top on the first passivation layer as a substrate; the thickness of the N-type microcrystalline silicon seed layer is 1-4 nm; the thickness of the N-type microcrystalline silicon oxide layer is 4-8 nm; the thickness of the N-type microcrystalline silicon layer is 1-4 nm; and the thickness of the N-type amorphous silicon layer is 1-4 nm. It also includes a second passivation layer disposed on the second main surface of the semiconductor substrate and a P-type semiconductor film layer disposed on the second passivation layer and doped with a different conductivity type than the first semiconductor film layer; the P-type semiconductor film layer includes a P-face microcrystalline silicon seed layer, a P-type microcrystalline silicon oxide layer, a P-type microcrystalline silicon layer, and a P-type amorphous silicon layer, wherein the thickness of the P-type microcrystalline silicon seed layer is 1-4 nm; the thickness of the P-type microcrystalline silicon oxide layer is 2-6 nm; the thickness of the P-type microcrystalline silicon layer is 8-20 nm; and the thickness of the P-type amorphous silicon layer is 1-4 nm. The first main side is the front, and the second main side is the back.

2. The method for fabricating a high-efficiency heterojunction solar cell according to claim 1, characterized in that: It includes forming a first semiconductor film layer with N-type doping or P-type doping on a first passivation layer of a passivated semiconductor substrate, and the specific steps are as follows: Step A, forming a first microcrystalline silicon stack on the first passivation layer of the passivated semiconductor substrate; Step B, forming a first amorphous silicon layer on the first microcrystalline silicon stack.

3. The method for fabricating a high-efficiency heterojunction solar cell according to claim 2, characterized in that: The specific steps of step A are as follows: a1, depositing a first microcrystalline silicon seed layer on the first passivation layer of the passivated semiconductor substrate; a2, depositing a first microcrystalline silicon oxide layer with N-type doping or P-type doping on the first microcrystalline silicon seed layer. a3, depositing a first microcrystalline silicon layer on the first microcrystalline silicon oxide layer having doping with the same conductivity type as the first microcrystalline silicon oxide layer.

4. The method for fabricating a high-efficiency heterojunction solar cell according to claim 3, characterized in that: The specific method of process a1 is as follows: first, the PECVD film formation temperature is preset to 150-250℃, and then a mixed gas of silane and hydrogen is introduced, with a reaction gas pressure of 100-300Pa, to deposit the first microcrystalline silicon seed layer.

5. The method for fabricating a high-efficiency heterojunction solar cell according to claim 3, characterized in that: When preparing the N-type doped first semiconductor film, the specific method of step a2 is as follows: first, the PECVD film formation temperature is preset to 150-250℃, and then a mixed gas of silane, phosphine, hydrogen and carbon dioxide is introduced. The reaction gas pressure is 150-500Pa, the ratio of phosphine to silane is 1%-10%, and the ratio of carbon dioxide to silane is 50%-100%, so as to deposit the N-type first microcrystalline silicon oxide layer. When preparing the P-type doped first semiconductor film layer, the specific method of step a2 is as follows: first, the PECVD film formation temperature is preset to 150-250℃, and then a mixed gas of silane, diborane, hydrogen and carbon dioxide is introduced. The reaction gas pressure is 150-500Pa, the ratio of diborane to silane is 0.5%-4%, and the ratio of carbon dioxide to silane is 50%-100%, so as to deposit the P-type first microcrystalline silicon oxide layer.

6. The method for fabricating a high-efficiency heterojunction solar cell according to claim 3, characterized in that: When preparing the N-type doped first semiconductor film layer, the specific method of step a3 is as follows: first, the PECVD film formation temperature is preset to 150-250℃, then a mixed gas of silane, phosphine, and hydrogen is introduced, the reaction gas pressure is 150-500Pa, the deposition power density is 0.08-0.3W / cm2, and the ratio of phosphine to silane is 1%-10%, so as to deposit the N-type first microcrystalline silicon layer; When preparing the P-type doped first semiconductor film layer, the specific method of step a3 is as follows: first, the PECVD film formation temperature is preset to 150-250℃, then a mixed gas of silane, diborane, and hydrogen is introduced, the reaction gas pressure is 150-500Pa, the deposition power density is 0.1-0.5W / cm2, and the ratio of diborane to silane is 0.5%-4%, so as to deposit the P-type first microcrystalline silicon layer.

7. The method for fabricating a high-efficiency heterojunction solar cell according to claim 3, characterized in that: When preparing the N-type doped first semiconductor film layer, the specific method of step B is as follows: first, preset the PECVD film formation temperature to 150-250℃, then introduce a mixed gas of silane, phosphine, and hydrogen, with a reaction gas pressure of 30-150Pa, a deposition power density of 0.01-0.02W / cm2, and a phosphine to silane ratio of 1%-10%, to deposit the N-type first amorphous silicon layer; When preparing the P-type doped first semiconductor film layer, the specific method of step B is as follows: first, preset the PECVD film formation temperature to 150-250℃, then introduce a mixed gas of silane, diborane, and hydrogen, with a reaction gas pressure of 30-150Pa, a deposition power density of 0.01-0.02W / cm2, and a diborane to silane ratio of 1%-10%, to deposit the P-type first amorphous silicon layer.

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