A gate tunneling field effect transistor and its manufacturing method

Abstract

The present invention provides a gate-all-around tunneling field-effect transistor, comprising: a substrate; the substrate comprising: a first epitaxial region, a second epitaxial region, a first channel region, a second channel region and a third channel region; a first epitaxial layer formed in the first epitaxial region; a second epitaxial layer formed in the second epitaxial region; a plurality of first channel layers stacked in a direction away from the substrate, and two adjacent first channel layers are separated by a channel cavity; wherein the first channel layer comprises a first channel portion, a second channel portion and a third channel portion; an inner sidewall filled in the channel cavity of the first channel region and the third channel region; a second channel layer, a gate dielectric layer and a control gate; all formed in the second channel region; wherein the first channel portion is doped with a first ion, and the second channel layer is doped with a second ion; the types of the first ion and the second ion are different; so as to solve the problem of how to increase the on-state current of the gate-all-around tunneling field-effect transistor.

Description

Technical Field

[0001] The present invention relates to the field of semiconductors, and in particular to a wrap-gate tunneling field-effect transistor and a manufacturing method thereof. Background Art

[0002] As transistor sizes shrink, reducing device power consumption has become one of the most important challenges in integrated circuit technology. Reducing the supply voltage (VDD) is one of the most effective methods for reducing power consumption. However, maintaining a sufficiently high on-state current requires a sufficiently high overdrive voltage, which requires the device threshold voltage to decrease simultaneously with the supply voltage. However, the subthreshold swing of traditional MOSFET devices has a theoretical limit due to the kT / q thermodynamic constraint. Reducing the device threshold voltage directly leads to an exponential increase in the off-state leakage current of CMOS devices, making it increasingly difficult to reduce the supply voltage and power consumption of traditional MOSFETs. The device operating voltage (VDD) remains relatively constant in the latest CMOS technology nodes. In this context, devices with ultra-steep subthreshold swings hold great potential for ultra-low power applications. Tunneling field-effect transistors (TFETs), due to their excellent subthreshold characteristics, low off-state leakage current, and low switching power consumption, are promising devices for future ultra-low power integrated circuit applications.

[0003] Although TFETs have great advantages in the field of low power consumption, their low on-state current has always been a major factor limiting their large-scale industrial application. In TFETs, increasing the on-state tunneling current is mainly achieved by increasing the quantum band-to-band tunneling probability and increasing the tunneling junction area. Therefore, how to develop a new tunneling field-effect transistor with a larger tunneling junction area to increase the on-state current has become a technical focus that technicians in this field urgently need to solve. Summary of the Invention

[0004] The present invention provides a gate-all-around tunneling field effect transistor and a manufacturing method thereof, so as to solve the problem of how to increase the on-state current of the gate-all-around tunneling field effect transistor.

[0005] According to a first aspect of the present invention, there is provided a gate-all-around tunneling field-effect transistor, comprising:

[0006] A substrate; the substrate comprising: a first epitaxial region, a second epitaxial region, a first channel region, a second channel region, and a third channel region; wherein the first channel region, the second channel region, and the third channel region are arranged in sequence along a first direction; the first direction represents a direction from the first epitaxial region to the second epitaxial region;

[0007] a first epitaxial layer formed in the first epitaxial region;

[0008] a second epitaxial layer formed in the second epitaxial region;

[0009] a plurality of first channel layers; the plurality of first channel layers covering the first channel region, the second channel region, and the third channel region; both ends of each first channel layer contact the first epitaxial layer and the second epitaxial layer, respectively; the plurality of first channel layers are stacked in a direction away from the substrate, and two adjacent first channel layers are separated by a channel cavity; wherein each first channel layer includes a first channel portion, a second channel portion, and a third channel portion; the first channel portion covers the first channel region and a portion of the second channel region, the second channel portion is formed in the remaining portion of the second channel region, and the third channel portion is formed in the third channel region;

[0010] Inner sidewalls filled in the channel cavities of the first channel region and the third channel region;

[0011] A second channel layer, a gate dielectric layer, and a control gate are all formed in the second channel region; wherein the second channel layer partially surrounds the first channel portion and the second channel portion; the gate dielectric layer surrounds the second channel layer; and the control gate surrounds the gate dielectric layer;

[0012] The first channel portion is doped with first ions, and the second channel layer is doped with second ions; the first ions and the second ions are of different types; the first epitaxial layer is a source region or a drain region, and the second epitaxial layer is a drain region or a source region correspondingly.

[0013] In one embodiment, the wrap-gate tunneling field-effect transistor further includes:

[0014] an ohmic contact layer formed on the surfaces of the first epitaxial layer, the second epitaxial layer and the control gate;

[0015] An interlayer dielectric layer formed on the ohmic contact layer and the inner sidewall surface;

[0016] A metal plug penetrates the interlayer dielectric layer and connects the ohmic contact layer.

[0017] Optionally, the third channel portion is doped with the second ions.

[0018] Optionally, only a partial region of the third channel portion is doped with the second ions, and the partial region is a portion close to the second epitaxial region.

[0019] Optionally, a width of the second channel layer along the first direction is 5 nm to 200 nm, and a thickness of the second channel layer along the stacking direction of the first channel layer is 3 nm to 20 nm.

[0020] Optionally, a first overlapping length between the second channel layer and the first channel portion is 5 nm-50 nm; the first length represents a length of the overlapping portion between the second channel layer and the first channel portion along the channel direction.

[0021] Optionally, a thickness of the first channel layer along a stacking direction of the first channel layer is 3 nm-20 nm.

[0022] Optionally, the material of the second channel layer is a binary or ternary compound of II-VI, III-V and IV-IV groups.

[0023] Optionally, the material of the second channel layer is Si, SiGe or Ge.

[0024] Optionally, the first epitaxial region is a source region, the second epitaxial region is a drain region; the first ions are P-type ions; and the second ions are N-type ions.

[0025] Optionally, the first epitaxial region is a drain region, the second epitaxial region is a source region, the first ions are N-type ions, and the second ions are P-type ions.

[0026] According to a second aspect of the present invention, a method for manufacturing a gate-all-around tunneling field-effect transistor is provided, comprising:

[0027] A substrate is provided; the substrate comprises: a first epitaxial region, a first channel region, a second channel region, a third channel region and a second epitaxial region arranged in sequence along a first direction;

[0028] A fin structure and an isolation layer are formed on the substrate; the fin structure is formed in the first channel region, the second channel region, and the third channel region, and the fin structure extends along the first direction; the isolation layer is formed on both sides of the fin structure along the second direction; the fin structure includes a plurality of sacrificial layers and a plurality of first channel layers stacked at intervals; the second direction is perpendicular to the first direction on the plane of the substrate; wherein the first channel layer includes: a first channel portion, a second channel portion, and a third channel portion;

[0029] doping first ions in the first channel portion;

[0030] A gate-all-around tunneling field-effect transistor structure is formed; the gate-all-around tunneling field-effect transistor comprises: the substrate, the plurality of first channel layers, inner sidewalls, a first epitaxial layer, and a second epitaxial layer; two adjacent first channel layers are separated by a channel cavity; wherein the plurality of channel cavities are formed between the plurality of first channel layers; the inner sidewalls are formed in the channel cavities in the first channel region and the second channel region; the first epitaxial layer is formed in the first epitaxial region; and the second epitaxial layer is formed in the second epitaxial region.

[0031] forming a second channel layer; the second channel layer partially encapsulating the first channel portion and the second channel portion; the second channel layer being doped with second ions; the first ions and the second ions being of different types;

[0032] A gate dielectric layer and a control gate are formed; the second channel layer partially wraps the first channel portion and the second channel portion; the gate dielectric layer wraps the second channel layer; and the control gate wraps the gate dielectric layer.

[0033] Optionally, the method further includes forming an ohmic contact layer, an interlayer dielectric layer, and a metal plug.

[0034] Optionally, forming a gate-all-around tunneling field-effect transistor structure specifically includes:

[0035] forming a dummy gate; wherein the dummy gate spans the fin structure of the second channel region;

[0036] releasing the first channel layers to form a plurality of channel cavities between the first channel layers;

[0037] forming the inner sidewalls; the inner sidewalls are formed in the channel cavities of the first channel region and the second channel region;

[0038] forming a first epitaxial layer and a second epitaxial layer;

[0039] The dummy gate is removed to form the gate-all-around tunneling field effect transistor structure.

[0040] Optionally, after doping the first ions into the first channel portion, the method further includes:

[0041] The second ions are doped into the third channel portion.

[0042] Optionally, after doping the first ions into the first channel portion, the method further includes:

[0043] Ion doping is performed on a portion of the third channel portion close to the second epitaxial region; wherein the ions doped in the third channel are the second ions.

[0044] According to a third aspect of the present invention, there is provided an electronic device comprising the all-around-gate tunneling field-effect transistor according to any one of the first aspects of the present invention.

[0045] According to a fourth aspect of the present invention, a method for preparing an electronic device is provided, comprising: a method for manufacturing a gate-all-around tunneling field-effect transistor according to any one of the second aspects of the present invention.

[0046] In the gate-all-around tunneling field-effect transistor provided by the present invention, the second channel layer doped with the second ions wraps around the portion of the first channel doped with the first ions, thereby forming an additional steep tunnel junction, which greatly increases the tunneling area and the tunneling probability. At the same time, because the electric field of the control gate is parallel to the tunneling path, tunneling perpendicular to the control gate surface will occur. In addition, there is a gate-all-around composite electric field effect at the device tunnel junction, and the gate electric fields in multiple gate directions are combined into a stronger electric field intensity at the tunnel junction, which increases the electric field intensity at the tunnel junction and significantly increases the tunneling current. It can be seen that the technical solution provided by the present invention solves the problem of how to increase the on-state current of the gate-all-around tunneling field-effect transistor, and further improves the device performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0048] Figure 1 1 is a schematic diagram of the device structure of a wrap-gate tunneling field-effect transistor provided in a preferred embodiment of the present invention;

[0049] Figure 2 1 is a flow chart of a method for manufacturing a gate-all-around tunneling field-effect transistor according to an embodiment of the present invention;

[0050] Figure 3-9 Schematic diagram of a device structure at different process stages of a method for manufacturing a gate-all-around tunneling field-effect transistor according to a preferred embodiment of the present invention;

[0051] Figure 10 This is a schematic diagram of a device structure after a control gate is manufactured according to a method for manufacturing a wrap-gate tunneling field-effect transistor, provided in a preferred embodiment of the present invention;

[0052] Figure 11 is a schematic diagram of a device structure after a control gate is manufactured according to a method for manufacturing a wrap-gate tunneling field-effect transistor, provided in another specific embodiment of the present invention;

[0053] Figure 12 This is a schematic diagram of a device structure after a control gate is manufactured according to a method for manufacturing a wrap-gate tunneling field-effect transistor according to another specific embodiment of the present invention;

[0054] Description of reference numerals:

[0055] 101-substrate;

[0056] 102-first channel portion;

[0057] 103-body channel layer;

[0058] 104-first channel layer;

[0059] 105-inner wall;

[0060] 106-first epitaxial region;

[0061] 107-second epitaxial region;

[0062] 108-second channel layer;

[0063] 109-gate dielectric layer;

[0064] 110-control grid;

[0065] 111-Ohmic contact layer;

[0066] 112-interlayer dielectric layer;

[0067] 113-Metal plug;

[0068] 114-photoresist;

[0069] 115-sacrificial layer;

[0070] 116-False fence. DETAILED DESCRIPTION

[0071] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0072] The terms "first," "second," "third," "fourth," and so on (if any) in the description and claims of the present invention and in the accompanying drawings are used to distinguish similar objects and are not necessarily used to describe a particular order or precedence. It should be understood that the terms used in this manner are interchangeable where appropriate, so that the embodiments of the present invention described herein can be implemented in orders other than those illustrated or described herein. In addition, the terms "including" and "having," as well as any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or apparatus that includes a series of steps or elements is not necessarily limited to those steps or elements explicitly listed, but may include other steps or elements not explicitly listed or inherent to such processes, methods, products, or apparatuses.

[0073] Although TFETs have great advantages in the field of low power consumption, their low on-state current has always been a major factor limiting their large-scale industrial application. In TFETs, increasing the on-state tunneling current is mainly achieved by increasing the quantum band-to-band tunneling probability and increasing the tunneling junction area.

[0074] In view of this, the inventors of the present application set an epitaxial channel layer between the channel layer and the gate dielectric layer, and injected N-type or P-type ions, and heavily doped N-type ions or P-type ions in the channel layer between the inner side walls and part of the channel layer in the channel area, wherein the type of ions heavily doped in the channel layer is different from the type of ions doped in the newly added epitaxial channel layer, thereby forming an additional steep tunnel junction in part of the channel area close to the source area. The tunneling field-effect transistor can significantly increase the on-state current of the tunneling transistor, enhance the current switching ratio of the device, and at the same time help to further reduce the subthreshold slope in the transfer characteristics of the tunneling transistor device.

[0075] The following specific embodiments are used to describe the technical solution of the present invention in detail. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described in detail in some embodiments.

[0076] Please refer to Figures 1-12 According to a first aspect of the present invention, there is provided a gate-all-around tunneling field-effect transistor, comprising:

[0077] A substrate 101; the substrate 101 includes: a first epitaxial region 106, a second epitaxial region 107, a first channel region, a second channel region, and a third channel region; wherein the first channel region, the second channel region, and the third channel region are arranged in sequence along a first direction; the first direction represents the direction from the first epitaxial region 106 to the second epitaxial region 107; Figure 1In 3-12, the first epitaxial region 106 is between the dotted lines ab, the second epitaxial region 107 is between the dotted lines ef, the first channel region is between the dotted lines bc, the second channel region is between the dotted lines cd, and the third channel region is between the dotted lines de;

[0078] a first epitaxial layer formed in the first epitaxial region 106;

[0079] A second epitaxial layer formed in the second epitaxial region 107;

[0080] a plurality of first channel layers 104; the plurality of first channel layers 104 covering the first channel region, the second channel region, and the third channel region, with both ends of each first channel layer 104 contacting the first epitaxial layer and the second epitaxial layer, respectively, and the plurality of first channel layers 104 being stacked in a direction away from the substrate 101, with two adjacent first channel layers 104 separated by a channel cavity; wherein each first channel layer 104 includes a first channel portion 102, a second channel portion, and a third channel portion; the first channel portion 102 covering the first channel region and a portion of the second channel region, the second channel portion being formed in the remaining portion of the second channel region, and the third channel portion being formed in the third channel region; wherein the first channel portion 102, the second channel portion, and the third channel portion are all named for convenience of description;

[0081] Inner sidewalls 105 are filled in the channel cavities of the first channel region and the third channel region;

[0082] The second channel layer, the gate dielectric layer 109 and the control gate 110 are all formed in the second channel region; wherein the second channel layer wraps part of the first channel portion 102 and the second channel portion; the gate dielectric layer 109 surrounds the second channel layer; the control gate 110 surrounds the gate dielectric layer 109; in a specific embodiment, the gate-all-around tunneling field effect transistor is as follows Figure 1 As shown;

[0083] The first channel portion 102 is doped with first ions, and the second channel layer is doped with second ions; the first ions and the second ions are of different types; the first epitaxial layer is a source region or a drain region, and the second epitaxial layer is a drain region or a source region correspondingly, and the ions doped in the first epitaxial layer are different from the ions doped in the second epitaxial layer;

[0084] The first ions and the second ions are both heavily doped into the corresponding structural layers; the undoped or lightly doped portion of the first channel portion 102 is the body channel layer 103;

[0085] The first channel layer 104 is a nanowire or a nanosheet, and the channel length of the device (the length along the first direction) is about 5 nm-200 nm.

[0086] In the gate-all-around tunneling field-effect transistor provided by the present invention, the first channel portion 102 is heavily doped with first ions, and a second channel layer is epitaxially grown on the surface of the first channel layer 104 in the second channel region; wherein the second channel layer is doped with second ions; it can be seen that the second channel layer doped with the second ions wraps around the portion of the first channel portion 102 doped with the first ions, thereby forming an additional steep tunnel junction, which greatly increases the tunneling area and the tunneling probability; at the same time, since the electric field of the control gate 110 is parallel to the tunneling path, tunneling perpendicular to the surface of the control gate 110 will occur; and there is a gate-all-around synthetic electric field effect at the device tunnel junction, and the gate electric fields in multiple gate directions are synthesized into a stronger electric field strength at the tunnel junction, which increases the electric field strength at the tunnel junction and significantly increases the tunneling current.

[0087] Therefore, the technical solution provided by the present invention solves the problem of how to increase the on-state current of the gate-all-around tunneling field-effect transistor, thereby achieving further improvement in device performance.

[0088] In one embodiment, the wrap-gate tunneling field-effect transistor further includes:

[0089] an ohmic contact layer 111 formed on the surfaces of the first epitaxial layer 106 , the second epitaxial layer 107 , and the control gate 110 ;

[0090] An interlayer dielectric layer 112 is formed on the surface of the ohmic contact layer 111 and the inner sidewall 105;

[0091] The metal plug 113 penetrates the interlayer dielectric layer 112 and connects to the ohmic contact layer 111 .

[0092] In one embodiment, a partial structural diagram of a gate-all-around tunneling field effect transistor is shown in FIG. Figure 11 As shown, the first channel portion 102 is doped with first ions, and the second channel portion and the third channel portion are body regions.

[0093] In a specific embodiment, Figure 12 As shown, in order to reduce the device resistance and thus further increase the current, the third channel portion is further doped with the second ions, wherein the first channel portion 102 is doped with the first ions, and the second channel portion is the body region.

[0094] Among them, although the device resistance can be reduced when the third channel portion is doped with the second ion, the gate-all-around tunneling field-effect transistor provided in this specific embodiment will produce a significant bipolar effect because the body region, i.e., the second channel portion, (i.e., the body region) is completely covered by the control gate 110.

[0095] In order to suppress the bipolar effect, in another specific embodiment, as Figure 10 As shown, only a portion of the third channel portion is doped with the second ions, and the portion is located near the second epitaxial region 107. Since the body region includes the second channel portion and a portion of the third channel portion, and the portion of the third channel portion that constitutes the body region is not covered by the control gate 110, the body region not covered by the control gate 110 forms a high-resistance region, effectively suppressing the effect of the drain voltage on the source tunneling junction width, while also suppressing the bipolar effect of the transistor and facilitating improved output characteristics of the device.

[0096] The thickness of the second channel layer along the first direction is an important parameter in device design.

[0097] If the thickness of the second channel layer is too large, the gate electric field strength at the interface between the first channel portion 102 / the second channel layer is weak, and the fully enclosed gate synthetic electric field effect at the interface between the first channel portion 102 / the second channel layer is weakened, resulting in an increase in the tunneling length of the band-to-band tunneling junction and a decrease in current, and the purpose of effectively increasing the tunneling current through the enclosed gate synthetic electric field effect cannot be achieved; if the thickness of the second channel layer is too small, the tunneling path between the first channel portion 102 / the second channel layer is difficult to form, and the purpose of increasing the tunneling current by increasing the effective tunneling area cannot be achieved; at the same time, in the case of extremely small size, the quantum confinement effect will cause the band gap width of the second channel layer to increase, and the effective mass of the carriers to increase, which not only reduces the probability of carrier band-to-band tunneling but also reduces the carrier mobility, which is not conducive to increasing the on-state current of the device.

[0098] Therefore, in a preferred embodiment, the width of the second channel layer along the first direction is 5 nm to 200 nm. The thickness of the second channel layer along the stacking direction of the first channel layer is 3 nm to 20 nm. In one embodiment, the material of the second channel layer is a binary or ternary compound of II-VI, III-V, and IV-IV groups. Specifically, the material of the second channel layer is Si, SiGe, or Ge.

[0099] In a preferred embodiment, the second channel layer is made of a narrow bandgap material such as SiGe, which will further reduce the tunneling length and increase the on-state current.

[0100] In order to further increase the tunneling area and increase the on-state current, in a preferred embodiment, the first length of the overlap between the second channel layer and the first channel portion 102 is 5nm-50nm; the first length represents the length of the overlapping portion between the second channel layer and the first channel portion 102 along the channel direction after the second channel layer wraps the first channel portion 102.

[0101] In one embodiment, the thickness of the first channel layer 104 along the stacking direction of the first channel layer 104 is 3 nm-20 nm.

[0102] In a specific embodiment, when the all-around tunneling field-effect transistor is an N-type device, the first epitaxial region 106 is a source region, the second epitaxial region 107 is a drain region; the first ions are P-type ions; and the second ions are N-type ions.

[0103] In another specific embodiment, when the gate-all-around tunneling field-effect transistor is a P-type device, the first epitaxial region 106 is a drain region, the second epitaxial region 107 is a source region, the first ions are N-type ions, and the second ions are P-type ions.

[0104] Secondly, according to an embodiment of the present invention, a method for manufacturing a gate-all-around tunneling field effect transistor is also provided. The process flow chart of the method for manufacturing a gate-all-around tunneling field effect transistor is as follows: Figure 2 As shown, the method includes:

[0105] S11: providing a substrate 101; for the convenience of description, the substrate 101 is specified to include: a first epitaxial region 106, a first channel region, a second channel region, a third channel region and a second epitaxial region 107 arranged in sequence along a first direction;

[0106] S12: forming a fin structure and an isolation layer on the substrate 101; the fin structure is formed in the first channel region, the second channel region and the third channel region, and the fin structure extends along the first direction; the isolation layer is formed on both sides of the fin structure along the second direction; the fin structure includes a plurality of sacrificial layers 115 and a plurality of first channel layers 104 stacked at intervals; the second direction is perpendicular to the first direction on the plane of the substrate 101; wherein the first channel layer 104 includes: a first channel portion 102, a second channel portion and a third channel portion; wherein the first channel layer 104 and the sacrificial layer 115 are lightly doped with a doping concentration of 1E12cm-3-1E16cm-3; specifically, the material of the channel layer is Si, the material of the sacrificial layer 115 is SiGe, the material of the first channel layer 104 is Si; the material of the isolation layer (STI) is SiO2; the fin structure has a crystal orientation of <100> , the thickness of each sacrificial layer 115 or the first channel layer 104 is about 3-20 nm;

[0107] S13: doping the first channel portion 102 with first ions; Figure 3 As shown; wherein, the arrow points to the portion of the fin structure into which ions are implanted; the direction perpendicular to the arrow is the channel direction, and when ion doping is performed, the portion of the fin structure not pointed to by the other arrows is covered with a photoresist 114;

[0108] S14: forming a gate-all-around tunneling field effect transistor structure; the gate-all-around tunneling field effect transistor comprises: the substrate 101, the plurality of first channel layers 104, the inner sidewalls 105, the first epitaxial layer and the second epitaxial layer; two adjacent first channel layers 104 are separated by a channel cavity; wherein the plurality of channel cavities are formed between the plurality of first channel layers 104; the inner sidewalls 105 are formed in the channel cavities in the first channel region and the second channel region; the first epitaxial layer is formed in the first epitaxial region 106; the second epitaxial layer is formed in the second epitaxial region 107; the device formed after step S14 (excluding the second channel layer in the figure) is as follows Figure 9 As shown,

[0109] S15: forming a second channel layer; the second channel layer partially wraps the first channel portion 102 and the second channel portion; the second channel layer is doped with second ions; the device structure after forming the second channel layer is as follows Figure 9 As shown;

[0110] S16: forming a gate dielectric layer 109 and a control gate 110; the second channel layer partially wraps the first channel portion 102 and the second channel portion; the gate dielectric layer 109 wraps the second channel layer; the control gate 110 wraps the gate dielectric layer 109. Specifically, the material forming the gate dielectric layer 109 is SiO2, Si3N4 or a high-K gate dielectric material; the material forming the control gate 110 is doped polysilicon, metal cobalt, nickel and other metals or metal silicides; wherein, the method for forming the gate dielectric layer 109 adopts: conventional thermal oxidation, nitrogen-doped thermal oxidation, atomic layer deposition or chemical vapor deposition; in a specific embodiment, when the material of the gate dielectric layer 109 is HfO2, the thickness is 1-5 nm, and when the material of the control gate 110 is a TiN layer, the thickness is 5-100 nm; as Figure 10 、 Figure 11 or Figure 12 As shown;

[0111] The fabrication method of the gate-all-around tunneling field-effect transistor provided by the present invention increases the on-state current by forming a new tunneling junction. Specifically, the second channel layer encapsulates a portion of the first channel portion 102 and a portion of the body region, which not only increases the tunneling area but also increases the electric field strength at the tunneling junction through the composite electric field effect, significantly improving the on-state current of the device.

[0112] In a preferred embodiment, in order to reduce device resistance, in step S13, after doping the first channel portion 102 with the first ions, the following steps are further included:

[0113] The second ions are doped into the third channel portion.

[0114] In a more preferred embodiment, Figure 4 As shown, the arrows point to the ion doping sites. When ion doping is performed, the portions of the fin structure not pointed to by the arrows are covered with a photoresist 114. In order to further suppress the bipolar effect, after doping the first ions in the first channel portion 102, the following steps are further included:

[0115] Only the portion of the third channel portion close to the second epitaxial region 107 is ion doped, while the other portions of the third channel layer and the second channel portion are not doped or are lightly doped; wherein the ions doped in the third channel are the second ions, and the device structure after doping the third channel portion with the second ions is as follows Figure 5 Taking this embodiment as an example, the ion concentrations doped in each structural layer when the first channel layer 104 is a nanowire are described in detail below:

[0116] When the all-around tunneling field-effect transistor is an N-type device, the first epitaxial region 106 is a source region, and the second epitaxial region 107 is a drain region; the first ions are P-type ions; the second ions are N-type ions; and the ion concentrations doped in each structural layer specifically include:

[0117] The first channel portion 102 is heavily doped with P-type, and its doping concentration is about 1E18cm-3-1E22cm-3.

[0118] The portion of the third channel portion close to the second epitaxial region 107 is heavily N-type doped, with a doping concentration of approximately 1E16 cm-3 to 1E21 cm-3.

[0119] The second channel layer is heavily N-type doped, with a doping concentration of approximately 1E18cm-3-1E22cm-3;

[0120] The source region is doped with B ions, the drain region is doped with As ions, and the ions doped in the second channel layer are As ions.

[0121] When the all-around tunneling field-effect transistor is a P-type device, the first epitaxial region 106 is a drain region, the second epitaxial region 107 is a source region, the first ions are N-type ions, and the second ions are P-type ions. The ion concentrations doped in each structural layer specifically include:

[0122] The first channel portion 102 is heavily N-type doped, with a doping concentration of approximately 1E18 cm-3 to 1E22 cm-3.

[0123] The portion of the third channel portion close to the second epitaxial region 107 is heavily doped with P-type, and its doping concentration is about 1E16cm-3-1E21cm-3.

[0124] The second channel layer is heavily doped with P-type, and its doping concentration is about 1E18cm-3-1E22cm-3.

[0125] In one embodiment, ions are doped into the first channel portion 102 and / or the third channel portion by ion implantation, solid-state source doping, or in-situ doping.

[0126] In one embodiment, step S13, after doping the first ion and / or the second ion, further includes: performing an annealing treatment; specifically including: performing a rapid high-temperature annealing and activating the injected impurities; wherein the temperature is: 1050° C., and the time is: 10s.

[0127] In one embodiment, step S14, forming a gate-all-around tunneling field effect transistor structure specifically includes steps S141-S145:

[0128] S141: forming a dummy gate 116; the dummy gate 116 spans the fin structure of the second channel region; specifically, the material forming the dummy gate 116 is polysilicon, such as Figure 6 As shown;

[0129] In one embodiment, the dummy gate 116 is formed by atomic layer deposition, chemical vapor deposition, or physical vapor deposition. In a specific example, the thickness of the dummy gate 116 is 50 nm.

[0130] S142: releasing the first channel layers 104 to form a plurality of channel cavities between the first channel layers 104;

[0131] S143: forming the inner sidewall 105; the inner sidewall 105 is formed in the channel cavity of the first channel region and the second channel region; specifically, the material forming the inner sidewall 105 is SiO2, Si3N4 or other low-K dielectric materials; Figure 7 As shown;

[0132] S144: forming a first epitaxial layer and a second epitaxial layer; the first epitaxial layer is a source region or a drain region, the second epitaxial layer is a source region or a drain region, the first epitaxial layer and the second epitaxial layer are of different types; the material of the first epitaxial layer is: SiGe or Si:C; the material of the second epitaxial layer is SiGe or Si:C; Figure 8 As shown;

[0133] Among them, since the source / drain regions of the device are grown using SiGe / Si:C epitaxy, stress will be further applied to the first channel layer 104 of the gate nanowire / nanosheet, which is beneficial to increasing the band-to-band tunneling probability and carrier mobility of the channel material;

[0134] S145: removing the dummy gate 116 to form the surround-gate tunneling field effect transistor structure, as shown in FIG. Figure 9 shown.

[0135] In one embodiment, the process further includes: step S17: forming an ohmic contact layer 111, an interlayer dielectric layer 112, and a metal plug 113. Figure 1 shown.

[0136] The all-around gate tunneling field-effect transistor provided by the present invention can effectively enhance the gate control capability of the device, significantly and effectively increase the on-state current of the device, while maintaining a steep subthreshold slope.

[0137] In addition, according to an embodiment of the present invention, an electronic device is provided, comprising the gate-all-around tunneling field-effect transistor according to any one of the aforementioned embodiments of the present invention.

[0138] According to an embodiment of the present invention, a method for manufacturing an electronic device is further provided, comprising: a method for manufacturing a gate-all-around tunneling field-effect transistor according to any one of the aforementioned embodiments of the present invention.

[0139] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A gate-all-around tunneling field-effect transistor, characterized in that: include: substrate; The substrate comprises: a first epitaxial region, a second epitaxial region, a first channel region, a second channel region, and a third channel region; wherein the first channel region, the second channel region, and the third channel region are arranged in sequence along a first direction; the first direction represents a direction from the first epitaxial region to the second epitaxial region; a first epitaxial layer formed in the first epitaxial region; a second epitaxial layer formed in the second epitaxial region; a plurality of first channel layers; the plurality of first channel layers covering the first channel region, the second channel region, and the third channel region; both ends of each first channel layer contact the first epitaxial layer and the second epitaxial layer, respectively; the plurality of first channel layers are stacked in a direction away from the substrate, and two adjacent first channel layers are separated by a channel cavity; wherein each first channel layer includes a first channel portion, a second channel portion, and a third channel portion; the first channel portion covers the first channel region and a portion of the second channel region, the second channel portion is formed in the remaining portion of the second channel region, and the third channel portion is formed in the third channel region; Inner sidewalls filled in the channel cavities of the first channel region and the third channel region; A second channel layer, a gate dielectric layer, and a control gate are all formed in the second channel region; wherein the second channel layer partially surrounds the first channel portion and the second channel portion; the gate dielectric layer surrounds the second channel layer; and the control gate surrounds the gate dielectric layer; The first channel portion is doped with first ions, and the second channel layer is doped with second ions; the first ions and the second ions are of different types; the first epitaxial layer is a source region or a drain region, and the second epitaxial layer is a drain region or a source region correspondingly.

2. The all-around-gate tunneling field-effect transistor according to claim 1, wherein: The surround-gate tunneling field-effect transistor further comprises: an ohmic contact layer formed on the surfaces of the first epitaxial layer, the second epitaxial layer and the control gate; An interlayer dielectric layer formed on the ohmic contact layer and the inner sidewall surface; A metal plug penetrates the interlayer dielectric layer and connects the ohmic contact layer.

3. The all-around-gate tunneling field-effect transistor according to claim 2, wherein: The third channel portion is doped with the second ions.

4. The all-around-gate tunneling field-effect transistor according to claim 2, wherein: Only a partial region of the third channel portion is doped with the second ions, and the partial region is a portion close to the second epitaxial region.

5. The all-around-gate tunneling field-effect transistor according to claim 3 or 4, characterized in that: The width of the second channel layer along the first direction is 5 nm to 200 nm; the thickness of the second channel layer along the stacking direction of the first channel layer is 3 nm to 20 nm.

6. The all-around-gate tunneling field-effect transistor according to claim 5, characterized in that: A first overlapping length between the second channel layer and the first channel portion is 5 nm-100 nm; the first length represents a length of the overlapping portion between the second channel layer and the first channel portion along the channel direction.

7. The all-around-gate tunneling field-effect transistor according to claim 6, wherein: The thickness of the first channel layer along the stacking direction of the first channel layer is 3 nm-20 nm.

8. The all-around-gate tunneling field-effect transistor according to claim 7, wherein: The material of the second channel layer is a binary or ternary compound of II-VI, III-V and IV-IV groups.

9. The all-around-gate tunneling field-effect transistor according to claim 8, wherein: The material of the second channel layer is Si, SiGe or Ge.

10. The all-around-gate tunneling field-effect transistor according to claim 9, wherein: The first epitaxial region is a source region, and the second epitaxial region is a drain region; the first ions are P-type ions; and the second ions are N-type ions.

11. The all-around-gate tunneling field-effect transistor according to claim 10, wherein: The first epitaxial region is a drain region, the second epitaxial region is a source region, the first ions are N-type ions, and the second ions are P-type ions.

12. A method for manufacturing a gate-all-around tunneling field effect transistor, characterized in that: include: A substrate is provided; the substrate comprises: a first epitaxial region, a first channel region, a second channel region, a third channel region and a second epitaxial region arranged in sequence along a first direction; A fin structure and an isolation layer are formed on the substrate; the fin structure is formed in the first channel region, the second channel region, and the third channel region, and the fin structure extends along the first direction; the isolation layer is formed on both sides of the fin structure along the second direction; the fin structure includes a plurality of sacrificial layers and a plurality of first channel layers stacked at intervals; the second direction is perpendicular to the first direction on the plane of the substrate; wherein the first channel layer includes: a first channel portion, a second channel portion, and a third channel portion; doping first ions in the first channel portion; A gate-all-around tunneling field effect transistor structure is formed; the gate-all-around tunneling field effect transistor comprises: the substrate, the plurality of first channel layers, inner sidewalls, a first epitaxial layer, and a second epitaxial layer; two adjacent first channel layers are separated by a channel cavity; Wherein, a plurality of channel cavities are formed between the plurality of first channel layers; the inner sidewalls are formed in the channel cavities in the first channel region and the second channel region; the first epitaxial layer is formed in the first epitaxial region; and the second epitaxial layer is formed in the second epitaxial region; forming a second channel layer; wherein the second channel layer partially encapsulates the first channel portion and the second channel portion; and the second channel layer is doped with second ions, wherein the first ions and the second ions are of different types; A gate dielectric layer and a control gate are formed; the second channel layer partially wraps the first channel portion and the second channel portion; the gate dielectric layer wraps the second channel layer; and the control gate wraps the gate dielectric layer.

13. The method for manufacturing a gate-all-around tunneling field effect transistor according to claim 12, wherein: Also includes: An ohmic contact layer, an interlayer dielectric layer and a metal plug are formed.

14. The method for manufacturing a gate-all-around tunneling field effect transistor according to claim 13, wherein: Forming a gate-all-around tunneling field effect transistor structure specifically includes: forming a dummy gate; wherein the dummy gate spans the fin structure of the second channel region; releasing the first channel layers to form a plurality of channel cavities between the first channel layers; forming the inner sidewalls; the inner sidewalls are formed in the channel cavities of the first channel region and the second channel region; forming a first epitaxial layer and a second epitaxial layer; The dummy gate is removed to form the gate-all-around tunneling field effect transistor structure.

15. The method for manufacturing a gate-all-around tunneling field effect transistor according to claim 14, wherein: After doping the first ions into the first channel portion, the method further includes: The second ions are doped into the third channel portion.

16. The method for manufacturing a gate-all-around tunneling field effect transistor according to claim 14, wherein: After doping the first ions into the first channel portion, the method further includes: Ion doping is performed on a portion of the third channel portion close to the second epitaxial region; wherein the ions doped in the third channel are the second ions.

17. An electronic device, characterized in that: The all-around gate tunneling field effect transistor comprises the one described in any one of claims 1 to 11.

18. A method for preparing an electronic device, characterized in that: include: A method for manufacturing a gate-all-around tunneling field-effect transistor according to any one of claims 12 to 16.

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