Differential hysteresis comparison circuit and method

Abstract

The present disclosure provides a differential hysteresis comparison circuit and method, which comprises: a differential input circuit for inputting a first differential signal and a second differential signal; a positive feedback hysteresis circuit connected with the differential input circuit, for comparing the first differential signal and the second differential signal to obtain a differential comparison result, outputting a first comparison result signal when the differential comparison result is greater than a first threshold voltage, outputting a second comparison signal when the differential comparison result is less than a second threshold voltage, the first threshold voltage being greater than the second threshold voltage; and an output stage circuit connected with the positive feedback hysteresis circuit, for converting the first comparison result signal or the second comparison result signal into a single-ended signal output.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuit technology, and in particular to a differential hysteresis comparator circuit and method. Background Technology

[0002] During signal generation and transmission, noise from the power supply voltage and environmental noise can introduce noise into the signal, affecting its accuracy and leading to problems such as bit errors. When a noisy signal is input into a comparator, especially when the noise amplitude is large near the comparator's threshold voltage, the comparator's output will flip multiple times, resulting in bit errors and affecting signal accuracy. Although traditional hysteresis comparators can reduce the bit error rate to some extent, hysteresis comparison for differential signals is difficult to implement. Summary of the Invention

[0003] In view of the above problems, the present invention provides a differential hysteresis comparator circuit to solve the above technical problems.

[0004] One aspect of this disclosure provides a differential hysteresis comparator circuit, comprising: a differential input circuit for inputting a first differential signal and a second differential signal; a positive feedback hysteresis circuit connected to the differential input circuit for comparing the first differential signal and the second differential signal to obtain a differential comparison result, outputting a first comparison result signal when the differential comparison result is greater than a first threshold voltage, and outputting a second comparison signal when the differential comparison result is less than a second threshold voltage, wherein the first threshold voltage is greater than the second threshold voltage; and an output stage circuit connected to the positive feedback hysteresis circuit for converting the first comparison result signal or the second comparison result signal into a single-ended signal output.

[0005] Optionally, the differential input circuit includes: a first differential input circuit, including a first transistor M1 and a second transistor M2, wherein the gate of the first transistor M1 is connected to a first voltage signal, and the gate of the second transistor M2 is connected to a second voltage signal, the first voltage signal and the second voltage signal constituting a first differential signal; a second differential input circuit, including a third transistor M3 and a fourth transistor M4, wherein the gate of the third transistor M3 is connected to a third voltage signal, and the gate of the fourth transistor M4 is connected to a fourth voltage signal, the third voltage signal and the fourth voltage signal constituting a second differential signal; the drains of the first transistor M1 and the second transistor M2 are respectively connected to the positive feedback hysteresis circuit, inputting the first differential signal to the positive feedback hysteresis circuit; the drains of the third transistor M3 and the fourth transistor M4 are respectively connected to the positive feedback hysteresis circuit, inputting the second differential signal to the positive feedback hysteresis circuit.

[0006] Optionally, the positive feedback hysteresis circuit includes: a fifth transistor M5, whose gate and drain are connected to form a diode connection, and whose drain is connected to the drain of the first transistor M1 and the drain of the third transistor M3; a sixth transistor M6, whose gate is connected to the gate of the fifth transistor M5 and connected to the first output terminal, and whose drain is connected to the drain of the second transistor M2 and the drain of the fourth transistor M4; a seventh transistor M7, whose gate is connected to the gate of the eighth transistor M8 and connected to the second output terminal, and whose drain is connected to the drain of the third transistor M3 and the drain of the fourth transistor M4; and a seventh transistor M7, whose gate is connected to the gate of the eighth transistor M8 and connected to the second output terminal, and whose drain is connected to the drain of the third transistor M3 and the drain of the fifth transistor M5. The drain of the first transistor M1; the eighth transistor M8, whose gate and drain are connected to form a diode connection, and whose drain is connected to the drain of the fourth transistor M4 and the drain of the second transistor M2; the ninth transistor M9, whose drain is connected to the source of the first transistor M1, the second transistor M2, the third transistor M3 and the fourth transistor M4, whose source is grounded, and whose gate is biased by a voltage Vbias; the source of the fifth transistor M5, the sixth transistor M6, the seventh transistor M7 and the eighth transistor M8 is biased by a voltage V. DD The drains of the fifth transistor M5 and the seventh transistor M7 are connected, and the drains of the sixth transistor M6 and the eighth transistor M8 are connected.

[0007] Optionally, the threshold voltage V TH The voltage value is either the first threshold voltage or the second threshold voltage; wherein, when the differential comparison result is greater than the first threshold voltage, the threshold voltage V TH The threshold voltage becomes the second threshold voltage; when the differential comparison result is less than the second threshold voltage, the threshold voltage becomes the second threshold voltage.

[0008] Optionally, the output stage circuit includes: a tenth transistor M10, whose drain is connected to a single-ended output terminal, whose source is grounded, and whose gate is connected to the gate of an eleventh transistor M11; an eleventh transistor M11, whose gate and drain are connected to form a diode connection, and whose source is grounded; and a twelfth transistor M12, whose gate is connected to the first output terminal, and whose source receives the operating voltage V. DD Its drain is connected to the single-ended output terminal; the thirteenth transistor M13 has its gate connected to the second output terminal, and its source is input with the operating voltage V. DD Its drain is connected to the drain of the eleventh transistor M11.

[0009] Optionally, the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the ninth transistor M9, the tenth transistor M10, and the eleventh transistor M11 are NMOS transistors; the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, the eighth transistor M8, the twelfth transistor M12, and the thirteenth transistor M13 are PMOS transistors.

[0010] This disclosure also provides a differential hysteresis comparison method applied to the differential hysteresis comparison circuit as described in the first aspect. The method includes: inputting a first differential signal and a second differential signal using a differential input circuit; comparing the first differential signal and the second differential signal using a positive feedback hysteresis circuit to obtain a differential comparison result; outputting a first comparison result signal when the differential comparison result is greater than a first threshold voltage; and outputting a second comparison signal when the differential comparison result is less than a second threshold voltage, wherein the first threshold voltage is greater than the second threshold voltage; and converting the first comparison result signal or the second comparison result signal into a single-ended signal output using an output stage circuit.

[0011] Optionally, it includes: when the differential comparison result is greater than a first threshold voltage, reducing the threshold voltage V of the positive feedback hysteresis circuit. TH The voltage is changed to the second threshold voltage; when the differential comparison result is less than the second threshold voltage, the threshold voltage V of the positive feedback hysteresis circuit is changed. TH It becomes the first threshold voltage.

[0012] Optionally, the first threshold voltage is:

[0013]

[0014] The second threshold voltage is:

[0015]

[0016] Among them, n=(W / L)6 / (W / L)5=(W / L)8 / (W / L)7, β=μ0C ox (W / L) 1，2，3，4 μ0C ox The parameters are the device model parameters for the first transistor M1, the second transistor M2, the third transistor M3, and the fourth transistor M4. W / L is the device width-to-length ratio for the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, and the eighth transistor M8. I9 represents the current of the ninth transistor M9.

[0017] The above-described at least one technical solution adopted in the embodiments of this disclosure can achieve the following beneficial effects:

[0018] This disclosure provides a differential hysteresis comparator circuit. By performing a differential input circuit, the influence of common-mode noise in the input signal can be reduced. When the input signal of the hysteresis comparator circuit rises from low to high and exceeds a first threshold voltage V... T + When the input signal is high, the single-ended output of the hysteresis comparator circuit is high. Since the first threshold voltage and the second threshold voltage of the hysteresis comparator circuit are different, even if the noise amplitude of the input signal is large near the first threshold voltage, as long as it does not fall below the second threshold voltage, the output will not flip positively, ensuring signal accuracy. Similarly, when the input signal of the hysteresis comparator circuit drops from high to low and falls below the first threshold voltage V... T - When the single-ended output terminal outputs a low level, and due to the hysteresis characteristic, the accuracy of the signal is guaranteed, and the anti-interference capability of the circuit is improved. Attached Figure Description

[0019] To gain a more complete understanding of this disclosure and its advantages, reference will now be made to the following description taken in conjunction with the accompanying drawings, wherein:

[0020] Figure 1 This schematically illustrates a differential hysteresis comparator circuit diagram provided in an embodiment of the present disclosure;

[0021] Figure 2 The schematic illustration shows an equivalent circuit of a hysteresis comparator circuit provided in an embodiment of this disclosure;

[0022] Figure 3 The diagram illustrates the signal waveform of a differential hysteresis comparator circuit provided in an embodiment of the present disclosure. Detailed Implementation

[0023] The embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. In the following detailed description, numerous specific details are set forth to provide a thorough understanding of the embodiments of the present disclosure for ease of explanation. However, it will be apparent that one or more embodiments may be practiced without these specific details. Furthermore, descriptions of well-known structures and techniques are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.

[0024] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. The terms “comprising,” “including,” etc., as used herein indicate the presence of the stated features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.

[0025] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art, unless otherwise defined. It should be noted that the terms used herein are to be interpreted in a manner consistent with the context of this specification, and not in an idealized or overly rigid way.

[0026] This disclosure provides a differential hysteresis comparator circuit, comprising a differential input circuit, a positive feedback hysteresis circuit, and an output stage circuit. The differential input circuit is used to input a first differential signal and a second differential signal. The positive feedback hysteresis circuit, connected to the differential input circuit, is used to compare the first differential signal and the second differential signal to obtain a differential comparison result. When the differential comparison result is greater than a first threshold voltage, a first comparison result signal is output; when the differential comparison result is less than a second threshold voltage, a second comparison signal is output. The first threshold voltage is greater than the second threshold voltage. The output stage circuit, connected to the positive feedback hysteresis circuit, is used to convert either the first comparison result signal or the second comparison result signal into a single-ended signal output.

[0027] Figure 1 The diagram illustrates a differential hysteresis comparator circuit provided in an embodiment of the present disclosure.

[0028] like Figure 1 As shown in this embodiment, the differential input circuit includes a first differential input circuit and a second differential input circuit. The first differential input circuit includes a first transistor M1 and a second transistor M2, with the gate of the first transistor M1 connected to a first voltage signal V. a The gate of the second transistor M2 is connected to the second voltage signal V. c The first voltage signal V a Second voltage signal V c The first differential signal V is formed a -V c and the first differential signal V a -V c Converted to current signal I a -I c The second differential input circuit includes a third transistor M3 and a fourth transistor M4, with the gate of the third transistor M3 connected to a third voltage signal V. d The gate of the fourth transistor M4 is connected to the fourth voltage signal V. b The third voltage signal V d and the fourth voltage signal V b Constitutes the second differential signal V d -V b and the voltage signal V d -V b Converted to current signal I d -I bThe drains of the first transistor M1 and the second transistor M2 are connected to a positive feedback hysteresis circuit, and a first differential signal V is input to the positive feedback hysteresis circuit. a -V c The drains of the third transistor M3 and the fourth transistor M4 are connected to a positive feedback hysteresis circuit, and the second differential signal V is input to the positive feedback hysteresis circuit. d -V b The first transistor M1, the second transistor M2, the third transistor M3, and the fourth transistor M4 are NMOS transistors.

[0029] In this embodiment, the positive feedback hysteresis circuit includes: a fifth transistor M5, whose gate and drain are connected to form a diode connection, and whose drain is connected to the drain of the first transistor M1 and the drain of the third transistor M3; and a sixth transistor M6, whose gate is connected to the gate of the fifth transistor M5 and connected to the first output terminal V. o1 Its drain is connected to the drain of the second transistor M2 and the drain of the fourth transistor M4; the seventh transistor M7 has its gate connected to the gate of the eighth transistor M8 and connected to the second output terminal V. o2 The drain of transistor M1 is connected to the drain of transistor M3 and the drain of transistor M1; the gate and drain of transistor M8 are connected to form a diode connection, and its drain is connected to the drain of transistor M4 and the drain of transistor M2; the drain of transistor M9 is connected to the source of transistors M1, M2, M3 and M4, its source is grounded, and its gate is biased by voltage Vbias; the source of transistors M5, M6, M7 and M8 is biased by operating voltage V. DD The drains of the fifth transistor M5 and the seventh transistor M7 are connected, and the drains of the sixth transistor M6 and the eighth transistor M8 are connected. The ninth transistor M9 is an NMOS transistor, and the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, and the eighth transistor M8 are PMOS transistors.

[0030] Specifically, the threshold voltage V TH The voltage value is either a first threshold voltage or a second threshold voltage; where, when the differential comparison result is greater than the first threshold voltage V... T + At that time, the threshold voltage V TH It becomes the second threshold voltage V T - When the differential comparison result is less than the second threshold voltage V T - At that time, the threshold voltage V TH It becomes the second threshold voltage V T - V T - <VT + .

[0031] In this embodiment, the first threshold voltage is:

[0032]

[0033] The second threshold voltage is:

[0034]

[0035] Among them, n=(W / L)6 / (W / L)5=(W / L)8 / (W / L)7, β=μ0C ox (W / L) 1，2，3，4 μ0C ox The parameters are the device model parameters for the first transistor M1, the second transistor M2, the third transistor M3, and the fourth transistor M4. W / L is the device width-to-length ratio for the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, and the eighth transistor M8. I9 represents the current of the ninth transistor M9.

[0036] Figure 2 The illustration schematically shows an equivalent circuit of a hysteresis comparator circuit provided in an embodiment of the present disclosure.

[0037] like Figure 2 As shown, the current flowing through transistor M1 is I. a The current flowing through transistor M2 is I. c The current flowing through transistor M3 is I. d The current flowing through transistor M4 is I. b The current flowing through transistor M5 is I5, the current flowing through transistor M6 is I6, the current flowing through transistor M7 is I7, the current flowing through transistor M8 is I8, and NMOS transistor M9 provides current I9 to the circuit. The first differential input circuit and the second differential input circuit are superimposed to achieve (V a -V c )+(V d -V b ), that is (V a -V c )-(V c -V d ), and the voltage signal (V a -V b )-(V c -V d ) transformed into (I a -I b )-(I c -I d ).

[0038] When (V) a +Vd )-(V c +V b The value of (V) is... a -V b )-(V c -V d The value of ) is much smaller than V. T - When M1 and M3 are off, M2 and M4 are on, so M7 and M8 will be on, and M5 and M6 will be off. I9 flows entirely through M2, M4, and M8, and the second output of the hysteresis comparator circuit, V... o2 Output low level, first output terminal V o 1. Output high level. (V) a -V b )-(V c -V d As the value of I9 gradually increases, the current of I9 begins to flow through M1 and M3. When the sum of the currents of M1 and M3 is I... a +I d When =I7, (V a -V b )-(V c -V d The value of ) reaches the threshold voltage V T + .

[0039] When this state is exceeded, that is, (V a -V b )-(V c -V d )>V T + At this time, most of the current I9 flows through M1, M3, and M5, and the second output terminal V of the hysteresis comparator circuit... o2 The first output terminal V transitions from a low level to a high level. o1 The signal transitions from high to low. At this time, the threshold voltage of the hysteresis comparator switches to V. T - , and V T - <V T + Even if (V a -V b )-(V c -V d ) decreases to less than V T + But as long as it is greater than V T - The output will not be flipped.

[0040] Similarly, when (V a +V d)-(V c +V b The value of (V) is... a -V b )-(V c -V d The value of ) is much greater than V. T + M2 and M4 are cut off, M1 and M3 are turned on, so M5 and M6 will turn on, and M7 and M8 will be cut off. I9 flows entirely through M1, M3, and M5, and the second output of the hysteresis comparator circuit, V... o2 Output high level, first output terminal V o1 Output low level. (V) a -V b )-(V c -V d As the value of I9 gradually decreases, the current of I9 begins to flow through M2 and M4. When the sum of the currents of M2 and M4 is I... c +I b When =I6, (V a -V b )-(V c -V d The value of ) reaches the threshold voltage V T - .

[0041] When this state is exceeded, that is, (V a -V b )-(V c -V d ) < V T - At this time, most of the current I9 flows through M2, M4, and M8, and the second output terminal V of the hysteresis comparator circuit... o2 The first output terminal V transitions from a high level to a low level. o1 The signal transitions from low to high. At this time, the threshold voltage of the hysteresis comparator switches to V. T + And even if (V a -V b )-(V c -V d Rise to greater than V T - But as long as it is less than V T + The output will not be flipped.

[0042] like Figure 1 As shown, in this embodiment of the disclosure, the output stage circuit includes: a tenth transistor M10, the drain of which is connected to the single-ended output terminal V. outIts source is grounded, and its gate is connected to the gate of the eleventh transistor M11; the eleventh transistor M11 has its gate and drain connected to form a diode connection, and its source is grounded; the twelfth transistor M12 has its gate connected to the first output terminal V. o1 Its source input operating voltage V DD Its drain is connected to the single-ended output terminal V. out The thirteenth transistor, M13, has its gate connected to the second output terminal V. o2 Its source input operating voltage V DD Its drain is connected to the drain of the eleventh transistor M11. The tenth transistor M10 and the eleventh transistor M11 are NMOS transistors; the twelfth transistor M12 and the thirteenth transistor M13 are PMOS transistors.

[0043] In this embodiment, when the second output terminal V of the hysteresis comparator circuit o2 Low level, first output terminal V o1 When the voltage is high, M12 is off, and M13 is on, transferring VDD to the drain and gate of M11 and the gate of M10, turning on M10 and pulling the output Vout low to VSS; when the second output of the hysteresis comparator circuit V... o2 High level, first output terminal V o1 When the signal is low, M13, M11, and M10 are off, and M12 is on, resulting in an output V. out Pull it down to VDD. The output stage circuit can convert the differential output of the hysteresis comparator circuit into a single-ended output, and at the same time, it forms a push-pull structure through PMOS transistor M12 and NMOS transistor M10 to provide a reasonable output voltage swing.

[0044] A differential hysteresis comparator circuit according to an embodiment of this disclosure compares differential signals using two sets of differential input pairs. The hysteresis comparator circuit performs a hysteresis comparison of the differential signals, and then the output stage circuit converts the differential result into a single-ended signal and outputs it. This reduces the impact of noise on signal accuracy and enables simple and effective hysteresis comparison of differential signals.

[0045] This disclosure, in another aspect, provides a differential hysteresis comparison method, applicable to, for example... Figure 1 The differential hysteresis comparator circuit shown includes S1 to S3.

[0046] S1, using a differential input circuit to input the first differential signal and the second differential signal.

[0047] S2, compare the first differential signal V using a positive feedback hysteresis circuit. a -V c Second differential signal V d -V b The difference comparison result (V) is obtained. a-V b )-(V c -V d When the difference comparison result (V) a -V b )-(V c -V d () greater than the first threshold voltage V T + When the first comparison result signal is output, i.e., the first output terminal V... o1 Output low level, second output terminal V o2 When the output is high, M13, M11, and M10 are cut off, while M12 is turned on, resulting in an output V. out The output will be VDD; when the differential comparison result is less than the second threshold voltage V... T - When the first output terminal V is reached, a second comparison signal is output, i.e., the first output terminal V. o1 Output high level, second output terminal V o2 When the output is low, M12 is off and M13 is on, transferring VDD to the drain and gate of M11 and the gate of M10, turning on M10 and pulling the output Vout low to VSS.

[0048] S3 uses the output stage circuit to convert the first comparison result signal or the second comparison result signal into a single-ended signal output.

[0049] In this method, when the differential comparison result is greater than the first threshold voltage V T + At that time, the threshold voltage V of the positive feedback hysteresis circuit will be... TH It becomes the second threshold voltage V T - When the differential comparison result is less than the second threshold voltage V T - At that time, the threshold voltage V of the positive feedback hysteresis circuit will be... TH It becomes the first threshold voltage V T + .

[0050] Figure 3 The diagram illustrates the signal waveform of a differential hysteresis comparator circuit provided in an embodiment of the present disclosure.

[0051] like Figure 3 As shown, the differential hysteresis comparator circuit provided in this embodiment converts the differential output of the hysteresis comparator circuit into a single-ended output. A push-pull structure is formed using PMOS transistor M12 and NMOS transistor M10 to provide a reasonable output voltage swing. This method reduces the impact of noise on signal accuracy and enables simple and effective hysteresis comparison of differential signals.

[0052] Those skilled in the art will understand that the features described in the various embodiments and / or claims of this disclosure can be combined or combined in various ways, even if such combinations or combinations are not explicitly described in this disclosure. In particular, the features described in the various embodiments and / or claims of this disclosure can be combined or combined in various ways without departing from the spirit and teachings of this disclosure. All such combinations and / or combinations fall within the scope of this disclosure.

[0053] Although this disclosure has been shown and described with reference to specific exemplary embodiments thereof, those skilled in the art will understand that various changes in form and detail may be made to this disclosure without departing from the spirit and scope of the disclosure as defined by the appended claims and their equivalents. Therefore, the scope of this disclosure should not be limited to the above embodiments, but should be defined not only by the appended claims, but also by their equivalents.

Claims

1. A differential hysteresis comparator circuit, characterized in that, include: The differential input circuit is used to input the first differential signal and the second differential signal; A positive feedback hysteresis circuit, connected to the differential input circuit, is used to compare the first differential signal and the second differential signal to obtain a differential comparison result. When the differential comparison result is greater than the first threshold voltage, a first comparison result signal is output. When the differential comparison result is less than the second threshold voltage, a second comparison result signal is output. The first threshold voltage is greater than the second threshold voltage. An output stage circuit, connected to the positive feedback hysteresis circuit, is used to convert the first comparison result signal or the second comparison result signal into a single-ended signal output. The differential input circuit includes: The first differential input circuit includes a first transistor M1 and a second transistor M2. The gate of the first transistor M1 is connected to a first voltage signal, and the gate of the second transistor M2 is connected to a second voltage signal. The first voltage signal and the second voltage signal constitute a first differential signal. The second differential input circuit includes a third transistor M3 and a fourth transistor M4. The gate of the third transistor M3 is connected to a third voltage signal, and the gate of the fourth transistor M4 is connected to a fourth voltage signal. The third voltage signal and the fourth voltage signal constitute the second differential signal. The drains of the first transistor M1 and the second transistor M2 are respectively connected to the positive feedback hysteresis circuit, and the first differential signal is input to the positive feedback hysteresis circuit; the drains of the third transistor M3 and the fourth transistor M4 are also respectively connected to the positive feedback hysteresis circuit, and the second differential signal is input to the positive feedback hysteresis circuit. The positive feedback hysteresis circuit includes: The fifth transistor M5 has its gate and drain connected to form a diode connection, and its drain is connected to the drain of the first transistor M1 and the drain of the third transistor M3. The sixth transistor M6 has its gate connected to the gate of the fifth transistor M5 and connected to the first output terminal, and its drain is connected to the drain of the second transistor M2 and the drain of the fourth transistor M4. The seventh transistor M7 has its gate connected to the gate of the eighth transistor M8 and connected to the second output terminal, and its drain is connected to the drain of the third transistor M3 and the drain of the first transistor M1. The eighth transistor M8 has its gate and drain connected to form a diode connection, and its drain is connected to the drain of the fourth transistor M4 and the drain of the second transistor M2. The ninth transistor M9 has its drain connected to the source of the first transistor M1, the second transistor M2, the third transistor M3 and the fourth transistor M4, its source is grounded, and its gate is biased by a voltage Vbias. The source input operating voltage V of the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, and the eighth transistor M8 DD The drains of the fifth transistor M5 and the seventh transistor M7 are connected, and the drains of the sixth transistor M6 and the eighth transistor M8 are connected. When the differential comparison result is greater than the first threshold voltage, the threshold voltage V of the positive feedback hysteresis circuit is set. TH It becomes the second threshold voltage; When the differential comparison result is less than the second threshold voltage, the threshold voltage V of the positive feedback hysteresis circuit is set. TH It becomes the first threshold voltage.

2. The differential hysteresis comparator circuit according to claim 1, characterized in that, The output stage circuit includes: The tenth transistor M10 has its drain connected to the single-ended output terminal, its source grounded, and its gate connected to the gate of the eleventh transistor M11. The eleventh transistor, M11, has its gate and drain connected to form a diode connection, and its source is grounded. The twelfth transistor M12 has its gate connected to the first output terminal, and its source is input with the operating voltage V. DD Its drain is connected to the single-ended output terminal; The thirteenth transistor M13 has its gate connected to the second output terminal, and its source is input with the operating voltage V. DD Its drain is connected to the drain of the eleventh transistor M11.

3. The differential hysteresis comparator circuit according to claim 2, characterized in that, The first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the ninth transistor M9, the tenth transistor M10, and the eleventh transistor M11 are NMOS transistors; the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, the eighth transistor M8, the twelfth transistor M12, and the thirteenth transistor M13 are PMOS transistors.

4. A differential hysteresis comparison method, applied to the differential hysteresis comparison circuit as described in any one of claims 1 to 3, characterized in that, The method includes: The first differential signal and the second differential signal are input using a differential input circuit; A positive feedback hysteresis circuit is used to compare the first differential signal and the second differential signal to obtain a differential comparison result. When the differential comparison result is greater than the first threshold voltage, the first comparison result signal is output. When the differential comparison result is less than the second threshold voltage, the second comparison result signal is output. The first threshold voltage is greater than the second threshold voltage. The first comparison result signal or the second comparison result signal is converted into a single-ended signal output using an output stage circuit. When the differential comparison result is greater than the first threshold voltage, the threshold voltage V of the positive feedback hysteresis circuit is set. TH It becomes the second threshold voltage; When the differential comparison result is less than the second threshold voltage, the threshold voltage V of the positive feedback hysteresis circuit is set. TH It becomes the first threshold voltage.

5. The differential hysteresis comparison method according to claim 4, characterized in that, The first threshold voltage is: ； The second threshold voltage is: ； Among them, n=(W / L)6 / (W / L)5=(W / L)8 / (W / L)7, β=μ0C ox (W / L) 1,2,3,4 μ0C ox The parameters are the device model parameters for the first transistor M1, the second transistor M2, the third transistor M3, and the fourth transistor M4. W / L is the device width-to-length ratio for the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, and the eighth transistor M8. I9 represents the current of the ninth transistor M9.

Images