Capacitor structure with vias embedded in porous medium

Abstract

A capacitor structure is disclosed. The capacitor structure includes a substrate (102), a conductive layer (104) over the substrate (102), and a porous layer over the conductive layer (104), the porous layer having pores extending vertically from a top surface of the porous layer toward the conductive layer (104). The porous layer includes a first region (110) and a second region (120), the pores of the first region (110) being provided with conductive lines, and the pores of the second region (120) being provided with metal-insulator-metal (MIM) structures. The first region (110) can be used as a via for contacting a bottom electrode of the capacitor structure.

Description

Technical Field

[0001] This invention relates to the field of integration, and more specifically, to electronic products, related semiconductor products, and methods of manufacturing the same. Background Technology

[0002] Silicon passive integration technology is now available for industrial design. For example, PICS technology, developed by Murata Integrated Passive Solutions, allows for the integration of high-density capacitor components into silicon substrates. This technology enables the efficient integration of dozens or even hundreds of passive components into a silicon die.

[0003] For example, in P. Banerjee et al.'s paper entitled "Nanotubular metal-insulator-metalcapacitor arrays for energy storage" (published in Natural Technology in May 2009), a metal-insulator-metal (MIM) structure formed in porous anodic materials such as porous anodic alumina (PAA) is described. Successive layers of metal, insulator, and then metal follow the contour of the porous material, causing the MIM structure to be embedded within the pores of the porous material. However, due to the thickness of the PAA that can be deposited by atomic layer deposition (ALD), Banerjee's PAA embedded structure is affected by high equivalent series resistance (ESR) and limited capacitance density.

[0004] International application publication WO 2015 / 063420 A1 describes an improved ESR and capacitor structure by F. Voiron et al. Voiron's structure produces a highly integrated capacitor suitable for a variety of applications. In this structure, the bottom of the aperture is opened, and the lower metal layer of the MIM structure contacts a conductive layer located beneath the porous region, thereby providing electrical contact and reducing ESR.

[0005] Typically, the PAA embedding structure described above is created by embedding a structure (e.g., a MIM capacitor stack) within a porous region above a substrate, such as a silicon wafer. The porous region is typically created by anodizing a layer of metal, such as aluminum, deposited above the substrate. Anodizing transforms the aluminum layer into porous anodic aluminum oxide. The porous region is typically formed in any shape (when viewed from above) and extends through the aluminum oxide layer in a direction perpendicular to the wafer surface.

[0006] Figure 1A conventional layout 100 for embedding a capacitor structure in a porous region is shown in cross-sectional view. The underlying structure may include a substrate 102, a conductive layer 104 above the substrate 102, and a metal layer 106 above the conductive layer 104.

[0007] According to the conventional layout 100, the metal layer 106 is anodized in the defined region 106b, leaving region 106a unanodized. Typically, this is achieved by applying a hard mask layer (not shown) on top of the metal layer 106 to mask the region corresponding to region 106a. The mask protects these regions from contact with the anodized electrolyte. Therefore, porous regions are formed in the regions 106b where the hard mask layer opens. A capacitor structure is then embedded in one or more regions 106b as needed.

[0008] However, in fact, the production Figure 1 The effective structure of a conventional layout is different. In fact, as... Figure 2 As shown, and in more detail as Figure 3 As shown, each of regions 106b is actually composed of region 106c and two transverse regions 106d.

[0009] Region 106c corresponds to a region with well-formed vias (i.e., the vias are substantially uniform and extend downwards to the conductive layer 104). In fact, some vias in region 106c may need to be etched at the bottom to ensure they are fully open, but typically these vias are sufficient to deposit the MIM stack therein.

[0010] In contrast, region 106d corresponds to the region where the aperture is highly likely to deform and therefore insufficient to accommodate the MIM stack.

[0011] The hole deformation in region 106d is due to the adjacency of these regions with the interface between each region 106d and its surrounding region 106a. In fact, as mentioned above, during anodizing, a hard mask is formed on the defined regions 106a to protect these regions from anodizing. The proximity of region 106d to this hard mask results in a gradually decreasing anodizing electric field in these regions. The closer to the edge of the hard mask, the weaker the anodizing electric field, and the fewer holes are formed.

[0012] The effect of this phenomenon is that the holes in region 106d stop at the residual aluminum flange 302 instead of extending downwards to the conductive layer 104. The fact that the holes in region 106d terminate at flange 302 is another reason why these holes are insufficient to accommodate the MIM stack. In fact, the MIM deposition, and specifically the deposition of the conductive layer, is accomplished using thermal atomic layer deposition (ALD). The precursors used for such conductive layer deposition (e.g., for conductive materials like TiN, MoN, WN, etc.) are chlorine-based and cause corrosion of the aluminum.

[0013] In fact, the width of region 106d is related to the thickness of the anodized metal layer 106 (the thicker the metal layer, the wider region 106d). Approximately, the width of region 106d is three times the thickness of the metal layer 106.

[0014] The width of flange 302 (and region 106d) can be reduced by adding additional control to the anodizing process. For example, the process can be allowed to continue for a longer period of time. However, this introduces the risk of weakening the interface between layers 104 and 106, leading to partial delamination of layer 106. Specifically, when the anodizing process is allowed to run for a longer period of time, it becomes difficult to control the oxidation of layer 104, and particularly difficult to limit the oxidation of layer 104 in the horizontal direction between the holes. When the holes are subsequently etched (during the step of opening the bottom of the holes), the interface between layers 104 and 106 weakens, thus causing delamination of layer 106.

[0015] In one implementation, regions 106a can be provided in structure 100 to form vias for contacting the bottom electrode of the capacitor structure embedded in region 106b from the top. Additionally, regions 106a can be provided near the edge of the dicing channel of the wafer (in the region of the wafer where the capacitor structure is not constructed).

[0016] It is generally desirable to provide contact redundancy by providing several vias to contact a given bottom electrode. Additionally, in some cases, it may be necessary to add vias to improve electrical performance. For example, it is desirable to reduce the equivalent series resistance (ESR) and equivalent series inductance (ESL) of the capacitor structure. Adding vias can help reduce both ESR and ESL. This is especially beneficial for smaller capacitors (e.g., less than 1 / 4 mm²). 2 In particular, the parallelization of capacitors is lower than that of larger capacitor structures.

[0017] However, the presence of flange 302 (and region 106d) is problematic when a large number of vias are required in the capacitor structure. In fact, as... Figure 4 As shown, whenever there is an effective width d1 between two porous regions 106b, a much larger width d2 is required due to the loss of region 106d. In fact, the inventors of this invention have observed that achieving an effective width d1 of 15 micrometers for a via may require a lateral coverage area of ​​up to 100 micrometers, since regions 106d may each be up to 30 micrometers (and where the process stacking rules require further spacing).

[0018] Figure 5 It is shown by Figure 1A top view 500 of the effective capacitance region generated by the conventional structure 100. Specifically, region 502 corresponds to the wafer region where the capacitor structure is constructed. Region 502 may correspond to region 106c described above. Conversely, region 504 is the wafer region not used for the capacitor structure. Region 504 may correspond to regions 106a and 106d described above. Region 506 corresponds to the wafer dicing region.

[0019] like Figure 5 As shown, the effective capacitance area is much smaller than the total area of ​​the wafer according to the conventional structure 100. This is in Figure 6 The text further illustrates that, Figure 6 The ratio of the effective capacitance area to the total area as a function of the capacitor surface area is shown according to the example implementation. The example implementation assumes that the effective via width (d1) is 15 micrometers and the width of each of regions 106d is 30 micrometers.

[0020] As shown, for sizes smaller than 0.25 mm 2 For capacitors with an effective area / total area ratio of less than 80%, this is particularly true for capacitors in 0.1 mm² regions. 2 For the following capacitors, the ratio drops below 70%, and for those in 0.04 mm²... 2 For the following capacitors, the ratio drops to below 50%.

[0021] The present invention was made in view of the above-mentioned problems. Summary of the Invention

[0022] This invention provides a capacitor structure, comprising:

[0023] substrate;

[0024] A conductive layer above the substrate; and

[0025] A porous layer above the conductive layer, the porous layer having pores extending vertically from the top surface of the porous layer toward the conductive layer.

[0026] The porous layer includes a first region and a second region. Conductive lines are disposed in the pores of the first region, and a metal-insulator-metal (MIM) structure is disposed in the pores of the second region.

[0027] Conductive lines form through-holes that pass through the capacitor structure. Therefore, the capacitor structure in the porous layer includes both regions for forming capacitance and regions for providing through-holes that pass through the capacitor structure.

[0028] Through holes can be used to contact the conductive layer, which can then be used as the bottom of the electrodes in a capacitor structure.

[0029] The fact that both the MIM structure and the vias are located in the same porous layer reduces the lateral coverage area of ​​the vias within the capacitor structure. Therefore, it increases the effective utilization of the porous layer and the effective capacitance area within the capacitor structure.

[0030] Furthermore, as the transition from porous to non-porous regions (e.g., non-anodic oxide metal) within the capacitor structure decreases, the porous regions with residual underlying metal also decrease. Since such porous regions can be susceptible to corrosion, their reduction improves the reliability of the capacitor structure.

[0031] In one embodiment, the porous layer includes a third region with empty pores, which separates the first and second regions. The third region can help maintain electrical isolation between the MIM structure and the conductive lines. The third region with its empty pores can also reduce mechanical stress within the capacitor structure.

[0032] The third region can be closely adjacent to the first region and also closely adjacent to the second region. Therefore, the third region can help satisfy the superposition manufacturing rules.

[0033] In one implementation, the bottom ends of the pores in the porous layer open onto the conductive layer. This allows contact between components embedded in the pores and the conductive layer beneath the porous layer.

[0034] In one embodiment, the MIM structure disposed in the holes in the second region includes a first metal layer conformally disposed in the second region, an insulating layer conformally disposed on the first metal layer, and a second metal layer conformally disposed on the insulating layer. The first metal layer contacts the conductive layer at the bottom of each hole in the second region.

[0035] In one embodiment, the bottom end of the conductive wire contacts the conductive layer at the bottom of the hole in the first region. The conductive layer can form the bottom electrode of the capacitor structure. Therefore, the conductive wire forms a through-hole through the capacitor structure for contacting the bottom electrode of the capacitor structure.

[0036] In one embodiment, the conductive layer includes a first layer and a second layer, with the second layer disposed between the first layer and the porous layer.

[0037] In this implementation, the first layer is made of aluminum, but other metals can be used.

[0038] In one embodiment, the second layer is made of tungsten or titanium. In another embodiment, the second layer serves as an etching barrier layer to protect the first layer during anodizing formation through the porous layer. This ensures that the first layer is not anodized, thereby ensuring that it maintains its high conductivity.

[0039] In this implementation, the second layer is discontinuous and has an opening beneath the first and / or second regions of the porous layer. This opening beneath the first and / or second regions can be implemented to ensure direct contact between the first metal layer and the conductive layer of the MIM structure, and / or between the conductive lines and the conductive layer.

[0040] In this embodiment, the porous layer is made of anodic aluminum oxide (AAO).

[0041] In some embodiments, the substrate may be made of silicon, glass, or a polymer.

[0042] In another embodiment, the substrate may be made of silicon and may have a field oxide layer between itself and the conductive layer. The conductive layer may be a composite layer of an aluminum or copper layer and a barrier layer (such as titanium or tungsten).

[0043] In one embodiment, the capacitor structure includes a metal layer on top of the conductive layer, surrounding the porous layer from the sides. The metal layer may be a residual portion of an initial metal layer formed by anodizing to create the porous layer. The metal layer may surround the edges of the porous layer.

[0044] In another embodiment, the metal layer may further include islands within the porous layer. The number and location of the metal islands can be selected by design prior to anodizing to form the porous layer. Specifically, the metal islands are selected to ensure the most uniform anodizing possible.

[0045] In an embodiment, the capacitor structure includes:

[0046] The first conductive layer in contact with the MIM structure; and

[0047] The second conductive layer is isolated from the first conductive layer and is in contact with the top of the conductive wire.

[0048] The first conductive layer can be used as the top electrode of the capacitor structure. The second conductive layer can be used as a contact to the bottom electrode of the capacitor structure.

[0049] In another aspect, the present invention also provides a method for manufacturing a capacitor structure, comprising:

[0050] A porous layer is formed above the conductive layer, the porous layer having pores that extend vertically from the top surface of the porous layer toward the conductive layer;

[0051] Conductive lines are formed in the pores of the first region of the porous layer, and the bottom end of the conductive lines contacts the conductive layer at the bottom of the pores in the first region.

[0052] A metal-insulator-metal (MIM) structure is formed in the pores of the second region of the porous layer.

[0053] In one embodiment, forming a conductive line in the hole in the first region includes:

[0054] A first hard mask is deposited on a porous layer, the first hard mask having an opening in a first region;

[0055] Conductive lines are grown in the holes of the first region by electrochemical deposition (ECD).

[0056] In this implementation, the conductive wire may be made of nickel or copper.

[0057] In this embodiment, forming the MIM structure in the hole in the second region includes:

[0058] Remove the first hard mask;

[0059] A second hard mask is deposited, which covers the first region of the porous layer and the adjacent third region (130); and

[0060] The MIM structure is deposited into a porous layer and a second hard mask.

[0061] In an implementation method, the method further includes:

[0062] A first conductive layer is formed on the MIM structure;

[0063] Etch a MIM structure and a second hard mask on at least a portion of the first region to expose the tips of at least some conductive lines;

[0064] An insulating layer is formed on the first conductive layer, and the insulating layer completely covers the first conductive layer; and

[0065] A second conductive layer is formed on at least a portion of the exposed conductive wires and insulating layer at the top, and the second conductive layer is in contact with the top of the at least some of the conductive wires. Attached Figure Description

[0066] Referring to the accompanying drawings, further features and advantages of the invention will become apparent from the following description of certain embodiments of the invention, given by way of illustration only and not limitation, in which:

[0067] Figure 1 A cross-sectional view shows a conventional layout for embedding a capacitor structure in a porous template;

[0068] Figure 2 The cross-sectional view shows the composition of Figure 1 The effective structure generated by the conventional structure;

[0069] Figure 3 It shows Figure 2 An enlarged view of a portion of the effective structure;

[0070] Figure 4The cross-sectional view shows that in Figure 2 Through-holes formed in the effective structure;

[0071] Figure 5 It is shown by Figure 1 A top view of the effective capacitance region generated by the conventional structure;

[0072] Figure 6 It shows that for Figure 1 The conventional structure of a capacitor is defined as the ratio of the effective capacitance region to the total capacitance region, which is a function of the surface area of ​​the capacitor.

[0073] Figures 7A to 7C A cross-sectional view illustrates a proposed layout for embedding a capacitor structure in a porous template according to an embodiment;

[0074] Figure 8 The effective capacitance area generated by the suggested layout based on the environment is shown;

[0075] Figure 9 The effect of the suggested layout on the ratio of net capacitance to original capacitance is shown.

[0076] Figures 10A to 10K The process for producing a capacitor structure according to a suggested layout, according to an embodiment, is shown.

[0077] Figure 11 An example capacitor structure is shown depending on the environment. Detailed Implementation

[0078] Figure 7A A cross-sectional view shows a proposed layout 700 for embedding a capacitor structure in a porous region according to an embodiment. As described above, it is assumed that the underlying structure includes a substrate 102, a conductive layer 104 above the substrate 102, and a metal layer 106 above the conductive layer 104.

[0079] like Figure 7A As shown, the metal layer 106 can be anodized to form a continuous porous layer 702, rather than defining staggered anodized and non-anodized regions within the metal layer 106.

[0080] In implementations, the continuous porous layer 702 can be designed to extend across the entire wafer surface. For example, in one implementation, the porous layer 702 can be obtained using wafer-level anodizing. Such an implementation may be suitable where uniform anodizing on the wafer can be ensured. This can be accomplished by selecting layer 104 such that it enables a uniform charge distribution on the wafer. In an example experiment, a 300 nm tungsten layer was used as layer 104, and a uniform charge distribution on the wafer was obtained.

[0081] In another embodiment, such as Figure 7A As shown, certain regions 106a of the metal layer 106 may not be anodized. Regions 106a may be located at the edge of the die and / or in the dicing (beyond the edge of the die or at the edge of the wafer).

[0082] In another setting, metal layer 106 may be unanodized in a few islands within porous layer 702. These unanodized metal islands can be in the form of a sparse metal mesh within porous layer 702. Such an implementation may be suitable when the die is isolated from the wafer backside (e.g., via field oxide). The unanodized metal islands help ensure a uniform anode voltage is applied across the wafer.

[0083] like Figure 7B As shown, the porous layer 702 is then divided between a region 702a designed to accommodate a capacitor structure and a region 702b designed to serve as a via in the capacitor structure. In region 702a, MIM stacks can be deposited in the vias. In region 702b, conductive lines can be formed in the vias to provide vias that pass vertically through the structure. In an embodiment, electrochemical deposition (ECD) can be used to grow the conductive lines within the vias of region 702b.

[0084] By using layout 700, the effective utilization of the wafer area is significantly increased. In fact, since a transition from vias to via-less structures is no longer required to implement vias, vias can now be placed closer to adjacent functional MIM structures. Therefore, the lateral coverage area of ​​the vias can be significantly reduced.

[0085] In fact, for example, due to process stacking rules, some isolation may be required between regions 702a and 702b. In the implementation, such as Figure 7C As shown, when region 702a is adjacent to region 702b in which vias will be constructed, a small portion 702c of region 702a (e.g., 5 to 10 micrometers) can be designated as an isolation region. In this isolation region, neither MIM structures nor conductive lines are constructed. In an embodiment, the via in the small portion 702c of region 702a can be empty.

[0086] However, the lateral coverage area of ​​the via remains very small. In experiments, the inventors have observed that a via with an effective width of 15 micrometers may only require a lateral coverage area of ​​27 micrometers. This can be further reduced through better photolithographic alignment.

[0087] As mentioned above, a large number of vias may be required in capacitor structures to provide contact redundancy and / or for ESR / ESL control. By significantly reducing the lateral coverage area of ​​the vias, the proposed layout can therefore have a significant impact on the effective capacitance generated by the structure.

[0088] Figure 8 This is a top view 800 showing the effective capacitance region generated by the proposed layout according to an embodiment. Specifically, region 802 corresponds to the wafer region where the capacitor structure is constructed. Region 802 may correspond to the above... Figure 7B Region 702a is shown. Conversely, region 804 is a wafer region with vias. Region 804 can correspond to the above. Figure 7B The area shown is 702b. In another embodiment, area 804 may correspond to the area shown above. Figure 7C Regions 702b and 702c are shown. Region 808 corresponds to the dicing area of ​​the wafer.

[0089] Optionally, region 806 may be provided corresponding to a region of non-anodized metal. As mentioned above, these regions may be provided for the purpose of enhancing the anodizing process on the wafer. Alternatively, similar to region 804, region 806 may correspond to a wafer region with vias formed.

[0090] like Figure 8 As shown, with Figure 5 Compared to the conventional layout shown, the effective capacitance area is significantly increased relative to the total wafer area. This is in Figure 9 The text further illustrates that, Figure 9 The ratio of effective capacitance area to total wafer area as a function of capacitor surface area is shown according to an example implementation. Specifically, in Figure 9 In the diagram, line 902 corresponds to the performance using the layout of the present invention, while line 904 corresponds to the performance using a conventional layout. As shown, utilization is significantly increased for all capacitor values. For smaller structures, the increase can be as high as 100%, thus doubling the capacitance density. This improvement can also be observed in structures with high contact redundancy.

[0091] Figures 10A to 10K An example process for producing a capacitor structure according to a suggested layout is shown according to an embodiment. This example process is provided for illustrative purposes only and does not limit the embodiments of the invention.

[0092] like Figure 10A As shown, the process begins with the formation of a stack including a substrate 102, a conductive layer 104 above the substrate, and a metal layer 106 above the conductive layer 104.

[0093] In one embodiment, the conductive layer 104 includes a first layer and a second layer, wherein the second layer is disposed between the first layer and the metal layer 106. In another embodiment, the first layer is made of aluminum, and the second layer is made of tungsten. The metal layer 106 may be made of aluminum.

[0094] Next, as Figure 10B As shown, the process includes anodizing some or all of the metal layers 106 to form a porous layer 108 over the conductive layer 104. The porous layer 108 has pores extending perpendicularly from the top surface of the porous layer 108 toward the conductive layer 104. When the metal layers 106 are made of aluminum, the porous layer 108 is made of anodized aluminum (AAO).

[0095] exist Figure 10B The image shows metal layer 106 being anodized entirely. While this implementation is possible, in reality, a small portion of metal layer 106 may not be anodized at the edge of the die and / or in the cut channels.

[0096] Due to the proposed layout, uniform anodizing can be achieved on the wafer. Therefore, the porous layer 108 has well-formed pores, meaning these pores are substantially uniform and extend downwards, substantially vertically, into the conductive layer 104. In fact, additional etching steps can be used to ensure that the pores are fully open in the conductive layer 104.

[0097] Next, as Figure 10C As shown, a first hard mask layer 132 is applied to the porous layer 108. The first hard mask layer 132 is patterned to have openings in a first region 110 defined by the porous layer 108.

[0098] Preferably, the material used for the first hard mask layer 132 can be selected to be highly nonconformal to prevent it from entering the pores of the porous layer 108.

[0099] Subsequently, as Figure 10D As shown, a conductive wire is formed in the hole of the first region 110. In an embodiment, the conductive wire is grown by electrochemical deposition (ECD). For example, the conductive wire may be made of nickel or copper. In an embodiment, the bottom end of the conductive wire contacts the conductive layer 104 at the bottom of the hole in the first region 110.

[0100] Then remove the first hard mask layer 132, apply the second hard mask layer 112, and pattern it, as follows. Figure 10E As shown. Specifically, the second hard mask layer 112 is patterned to cover the first region 110 of the porous layer and the adjacent third region 130 of the porous region. As further described below, according to this embodiment, the third region 130 will be used as an isolation region.

[0101] Next, as Figure 10F As shown, a MIM structure is formed in the pores of the second region 120 of the porous layer 108. According to this embodiment, the second region 120 corresponds to the region of the porous layer 108 that is not covered by the second hard mask layer 112, that is, the region outside the first region 110 and the third region 130.

[0102] In one implementation, this includes depositing the MIM structure onto the porous layer 108 and the second hard mask layer 112. In another implementation, the top metal layer of the MIM structure can be etched onto the first region 110 and the third region 130, such as... Figure 10F As shown.

[0103] The deposition of the MIM structure in the holes of the second region 120 is highly conformal. In one embodiment, the MIM structure includes a first metal layer (114) conformally disposed in the second region (120), an insulating layer (116) conformally disposed on the first metal layer (114), and a second metal layer (118) conformally disposed on the insulating layer (116). In one embodiment, the first metal layer contacts the conductive layer 104 at the bottom of each hole in the second region 120.

[0104] Next, as Figure 10G As shown, a first conductive layer 122 can be formed on the MIM structure. The first conductive layer 122 can be etched onto the first region 110 and the third region 130, as shown. Figure 10G As shown. In an embodiment, the first conductive layer 122 can be used as the top electrode of a capacitor structure.

[0105] Subsequently, as Figure 10H As shown, a MIM structure (a first metal layer 114 and an insulating layer 116) and a second hard mask layer 112 are etched on at least a portion of a first region 110 of the porous layer. This exposes the tips of at least some of the conductive lines constructed in the first region 110 of the porous layer.

[0106] Next, as Figure 10I As shown, an insulating layer 124 is formed on the first conductive layer 122. The insulating layer 124 completely covers (encapsulates) the first conductive layer 122.

[0107] Then, as Figure 10J As shown, a second conductive layer 126 is formed. The second conductive layer 126 covers the exposed portion of the first region 110 and at least a portion of the insulating layer 124. The second conductive layer 126 contacts the exposed tips of at least some conductive wires. In an embodiment, the second conductive layer can be used as a contact to the bottom electrode of a capacitor structure.

[0108] Finally, as Figure 10K As shown, a passivation layer 128 can be formed on this structure.

[0109] Figure 11 An example capacitor structure 1100 according to an embodiment is shown. The example capacitor structure 1100 is provided for illustrative purposes and is not intended to limit the implementation. The capacitor structure 1100 can be obtained using the process described above.

[0110] As shown, the capacitor structure 1100 includes a porous layer comprising a first region 110, a second region 120, and a third region 130.

[0111] In the first region 110, conductive wires are disposed in the pores of the porous layer, thereby providing vertical through-holes through the structure. The bottom end of the conductive wire contacts the conductive layer 104 at the bottom of the pores in the first region 110.

[0112] In the second region 120, a MIM structure is formed in the pores of the porous layer, thereby providing a capacitor in the structure.

[0113] The third region 130 separates the first region 110 and the second region 120. In one embodiment, the third region 130 isolates the first region 110 and the second region 120. In another embodiment, the opening in the third region 130 is empty.

[0114] In one embodiment, the conductive layer 104 includes a first layer and a second layer, the second layer being disposed between the first layer and the porous layer. In another embodiment, the second layer is discontinuous and has an opening below the first region 110 and / or the second region 120 of the porous layer.

[0115] Other variations

[0116] Although the present invention has been described above with reference to certain specific embodiments, it should be understood that the present invention is not limited to the particularities of these specific embodiments. Many changes, modifications, and developments can be made to the above embodiments within the scope of the appended claims.

Claims

1. A capacitor structure (1100), comprising: substrate(102); A first conductive layer (104) above the substrate (102); as well as A porous layer made of anodized aluminum oxide (AAO) is positioned above the first conductive layer (104), the porous layer having pores extending vertically from the top surface of the porous layer toward the first conductive layer (104). The porous layer is characterized in that it includes a first region (110), in which a conductive wire is disposed in a hole of the first region (110), the bottom end of the conductive wire contacts the first conductive layer (104) at the bottom of the hole of the first region (110), and the top end of the conductive wire contacts the second conductive layer (126) on the top surface of the porous layer in the first region (110), thereby the conductive wire forms a conductive via through the porous layer, the conductive via interconnecting the first conductive layer (104) and the second conductive layer (126), and the porous layer includes a second region (120), in which a metal-insulator-metal (MIM) structure is disposed in a hole of the second region (120).

2. The capacitor structure (1100) according to claim 1, wherein, The porous layer includes a third region (130) with empty pores, which separates the first region (110) and the second region (120).

3. The capacitor structure (1100) according to claim 2, wherein, The third region (130) is closely adjacent to the first region (110) and also closely adjacent to the second region (120).

4. The capacitor structure (1100) according to any one of claims 1 to 3, wherein, The MIM structure disposed in the holes of the second region (120) includes a first metal layer conformally disposed in the second region (120), an insulating layer conformally disposed on the first metal layer, and a second metal layer conformally disposed on the insulating layer, wherein the first metal layer contacts the first conductive layer (104) at the bottom of each hole of the second region (120).

5. The capacitor structure (1100) according to any one of claims 1 to 3, wherein, The first conductive layer (104) includes a first layer and a second layer, wherein the second layer is disposed between the first layer and the porous layer.

6. The capacitor structure (1100) according to claim 5, wherein, The first layer is made of aluminum, and the second layer is made of tungsten.

7. The capacitor structure (1100) according to claim 5, wherein, The second layer is discontinuous and has an opening below the first region (110) and / or the second region (120) of the porous layer.

8. The capacitor structure (1100) according to any one of claims 1 to 3, comprising: A metal layer (106a) is located above the first conductive layer (104) and surrounds the porous layer from the side.

9. The capacitor structure (1100) according to any one of claims 1 to 3, comprising: An additional conductive layer (122) is in contact with the MIM structure; The second conductive layer (126) is isolated from the additional conductive layer (122).

10. A method for manufacturing a capacitor structure, comprising: A porous layer (108) made of anodic aluminum oxide (AAO) is formed above the first conductive layer (104), the porous layer (108) having pores extending vertically from the top surface of the porous layer (108) toward the first conductive layer (104); Conductive lines are formed in the holes of the first region (110) of the porous layer, the bottom end of the conductive lines contacts the first conductive layer (104) at the bottom of the holes in the first region (110), and the conductive lines extend to the top of the porous layer. A second conductive layer (126) is formed on the top surface of the porous layer in the first region (110), and the tip of the conductive wire contacts the second conductive layer (126), thereby forming a conductive via through the porous layer, the conductive via interconnecting the first conductive layer (104) and the second conductive layer (126); and A metal-insulator-metal (MIM) structure is formed in the pores of the second region (120) of the porous layer.

11. The method according to claim 10, wherein, Forming the conductive line in the hole in the first region (110) includes: A first hard mask layer (132) is deposited on the porous layer (108), the first hard mask layer (132) having an opening in the first region (110); The conductive wires are grown in the holes of the first region (110) by electrochemical deposition (ECD).

12. The method according to claim 11, wherein, Forming the MIM structure in the hole of the second region (120) includes: Remove the first hard mask layer (132); A second hard mask layer (112) is deposited, which covers the first region (110) and the adjacent third region (130) of the porous layer (108); and The MIM structure is deposited into the porous layer (108) and onto the second hard mask layer (112).

13. The method of claim 12, comprising: An additional conductive layer (122) is formed on the MIM structure. The MIM structure and the second hard mask layer (112) are etched on a portion of the first region (110) to expose the first region (110) in the portion; An insulating layer (124) is formed on the additional conductive layer (122), the insulating layer (124) completely covering the additional conductive layer (122); and A second conductive layer (126) is formed on the exposed portion of the first region (110) and at least a portion of the insulating layer (124), the second conductive layer (126) being in contact with the tips of at least some of the conductive lines.

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