Field effect transistor and method of manufacturing the same

Abstract

A field effect transistor and a manufacturing method thereof, wherein the field effect transistor comprises: a source (13), a drain (14) and a gate (12); a channel region (11) is provided between the source (13) and the drain (14); an inner isolation layer (110) is provided between the gate (12) and the source (13) and between the gate (12) and the drain (14); the inner isolation layer (110) covers a portion of the channel region (11), wherein the inner isolation layer (110) includes donor impurities or acceptor impurities. The structure can reduce the on-resistance of the channel region (11) of the field effect transistor and maintain high carrier mobility in the channel region (11), thereby improving the performance of the field effect transistor.

Description

Technical Field

[0001] The present application relates to the field of semiconductor manufacturing, and in particular to field effect transistors and methods for manufacturing the same. Background Art

[0002] For the past few decades, semiconductor technology has consistently followed Moore's Law, with transistor feature sizes shrinking continuously. Today, semiconductor chips have entered the 5-nanometer (nm) technology node. Starting at the 22-nm node, the fin field-effect transistor (FinFET) has become the mainstream semiconductor device structure. However, after the 5-nm node, FinFETs have struggled to meet the required electrostatic control requirements, and leakage has rapidly worsened with shrinking dimensions. In this context, the gate-all-around field-effect transistor (GAAFET) is widely considered the next-generation semiconductor transistor successor to the FinFET.

[0003] During the manufacturing process of FinFET and GAAFET, an inner spacer needs to be grown outside the gate to separate the gate and the source / drain. However, due to the existence of the inner spacer, the channel area covered by the inner spacer cannot be directly covered and controlled by the gate. This area is called the ineffective gate control area. When the transistor is turned on, the resistance of the ineffective gate control area will not decrease with the increase of the gate voltage, so the resistance of this area will become the resistance bottleneck from the source to the drain.

[0004] One solution is to use a highly doped, low-resistance material in the channel region between the source and drain to reduce the resistance of the channel region. However, this approach increases carrier scattering in the gate-covered channel region (also known as the effective gate region), reducing carrier mobility and sacrificing transistor performance. Furthermore, random fluctuations in impurities in the channel at small dimensions can also lead to more erratic variations in device performance. Therefore, the industry urgently needs a solution to the problem of increased on-resistance in the channel region caused by the ineffective gate region. Summary of the Invention

[0005] The present application provides a field effect transistor and a manufacturing method thereof, which can reduce the on-resistance of the channel region of the field effect transistor and maintain high carrier mobility in the channel region, thereby improving the performance of the field effect transistor.

[0006] In a first aspect, a field effect transistor is provided, comprising: a source, a drain and a gate; a channel region is provided between the source and the drain; an inner isolation layer is provided between the gate and the source and between the gate and the drain, the inner isolation layer covering a portion of the channel region; wherein the inner isolation layer includes donor impurities or acceptor impurities.

[0007] Optionally, the portion of the area covered by the inner isolation layer can be referred to as the inactive gate region. The inner isolation layer is composed of an insulating material and is used to isolate the gate from the drain, and the gate from the source. The inner isolation layer can be a mixture (e.g., phosphosilicate glass or borosilicate glass) or a compound composed of donor or acceptor impurities and other elements (e.g., silicon, oxygen, nitrogen, etc.).

[0008] The present application provides a field-effect transistor, wherein an inner isolation layer of the transistor includes donor impurities or acceptor impurities. During a subsequent high-temperature process, the donor impurities or acceptor impurities can diffuse into the ineffective gate-controlled region covered by the inner isolation layer, forming a low-resistance state under high doping, and precisely modulating the semiconductor doping of the ineffective gate-controlled region covered by the inner isolation layer to reduce the resistance of the region. The remaining portion of the channel region (or, the effective gate-controlled region) can still maintain a high-resistance state under low doping, thereby maintaining high carrier mobility in the channel and improving the performance of the field-effect transistor.

[0009] In combination with the first aspect, in a possible implementation, the donor impurities include at least one of the following: phosphorus, arsenic, and antimony.

[0010] In combination with the first aspect, in a possible implementation, the acceptor impurities include at least one of the following: boron, indium, and aluminum.

[0011] In combination with the first aspect, in a possible implementation, the inner isolation layer includes at least one of the following: phosphosilicate glass, borosilicate glass, and arsenic silicate glass.

[0012] In combination with the first aspect, in a possible implementation, the field effect transistor includes a full-ring gate field effect transistor GAAFET, the channel region is a first channel region, a plurality of stacked channel regions are arranged between the source and the drain, and the first channel region is any channel region among the plurality of stacked channel regions; and the inner isolation layer is a first inner isolation layer, a plurality of stacked inner isolation layers are arranged between the gate and the source and between the gate and the drain, and the first inner isolation layer is any inner isolation layer among the plurality of stacked inner isolation layers.

[0013] With reference to the first aspect, in a possible implementation, the field effect transistor includes a fin field effect transistor (FinFET).

[0014] In a second aspect, a method for manufacturing a field effect transistor is provided, comprising: obtaining a silicon-based original wafer; generating an inner isolation layer of the field effect transistor on the silicon-based original wafer, wherein the inner isolation layer is used to isolate the gate and source, as well as the gate and drain, of the field effect transistor, and covers a portion of the channel region, wherein the inner isolation layer includes donor impurities or acceptor impurities.

[0015] The portion of the area covered by the inner isolation layer may be referred to as a non-effective gate control area.

[0016] The present application provides a method for manufacturing a field-effect transistor, wherein the method uses a material containing donor impurities or acceptor impurities to form an inner isolation layer. During a subsequent high-temperature process, the donor impurities or acceptor impurities can diffuse into the ineffective gate-controlled region covered by the inner isolation layer, forming a low-resistance state under high doping. The semiconductor doping of the ineffective gate-controlled region covered by the inner isolation layer is precisely modulated to reduce the resistance of the region. The remaining portion of the channel region (or, the effective gate-controlled region) can still maintain a high-resistance state under low doping, thereby maintaining high carrier mobility in the channel and improving the performance of the field-effect transistor.

[0017] In combination with the second aspect, in a possible implementation, the donor impurities include at least one of the following: phosphorus, arsenic, and antimony.

[0018] In combination with the second aspect, in a possible implementation, the acceptor impurities include at least one of the following: boron, indium, and aluminum.

[0019] In combination with the second aspect, in a possible implementation, the dielectric material includes at least one of the following: phosphosilicate glass, borosilicate glass, and arsenic silicate glass.

[0020] In combination with the second aspect, in a possible implementation, the field effect transistor includes a full-ring gate field effect transistor GAAFET, the channel region is a first channel region, a plurality of stacked channel regions are arranged between the source and the drain, and the first channel region is any one of the plurality of stacked channel regions; and the inner isolation layer is a first inner isolation layer, a plurality of stacked inner isolation layers are arranged between the gate and the source and between the gate and the drain, and the first inner isolation layer is any one of the plurality of stacked inner isolation layers.

[0021] In combination with the second aspect, in a possible implementation, the field effect transistor includes a fin field effect transistor (FinFET).

[0022] In a third aspect, an electronic device is provided, comprising the field effect transistor as described in the first aspect and any possible implementation manner of the first aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 FIG. 1 is a schematic structural diagram of a FinFET 10 according to an embodiment of the present application.

[0024] Figure 2 2 is a schematic structural diagram of a GAAFET 20 according to an embodiment of the present application.

[0025] Figure 3 FIG. 1 is a schematic structural diagram of a GAAFET 30 according to an embodiment of the present application.

[0026] Figure 4 FIG. 4 is a schematic cross-sectional view of a FinFET 40 according to an embodiment of the present application.

[0027] Figure 5 FIG. 5 is a schematic cross-sectional view of a GAAFET 50 according to an embodiment of the present application.

[0028] Figure 6 FIG. 5 is a schematic cross-sectional view of a FinFET 60 according to another embodiment of the present application.

[0029] Figure 7 FIG. 1 is a schematic cross-sectional view of a GAAFET 70 according to an embodiment of the present application.

[0030] Figure 8 FIG. 1 is a flow chart of a method for manufacturing a field effect transistor according to an embodiment of the present application. DETAILED DESCRIPTION

[0031] The technical solution in this application will be described below with reference to the accompanying drawings.

[0032] For ease of understanding, the following first introduces the structures of FinFET and GAAFET with reference to the accompanying drawings.

[0033] Figure 1 FIG. 1 is a schematic diagram of the structure of the FinFET 10 according to an embodiment of the present application. Figure 1 As shown, in the FinFET 10 design, the channel region 11 is a fin-shaped semiconductor wrapped by a gate (G) 12, that is, the gate surrounds three sides of the channel region 11. The two ends of the channel region 11 are the source (S) and the drain (D) (not shown in the figure). The structure of the gate 12 wrapping the channel region 11 enhances the control capability of the gate, provides better electrical control of the channel region 11, and suppresses the short channel effect. However, since one side of the channel region 11 is also connected to the silicon substrate 16, there will be an additional leakage current path when the transistor is in the off state.

[0034] It should also be noted that, those skilled in the art will understand that in order to more clearly illustrate the shape of the channel region 11, Figure 1 The source, drain, dielectric and other components are not shown. The construction of the above components can be found in Figure 4 The dielectric may include the inner isolation layer 110 hereinafter.

[0035] Since the semiconductor process node has developed to below 5 nanometers, the industry is in urgent need of a new solution to replace the FinFET structure in future process nodes. Although various new transistor solutions have been proposed, in order to save production costs, the industry prefers solutions that can continue to use existing equipment and technological achievements. For this reason, GAAFET is widely considered to be the development direction of the next generation of transistors. The production process of GAAFET is similar to that of FinFET, and the key process steps are basically the same. In addition, GAAFET realizes the gate surrounding the channel area on all four sides, thereby enhancing the gate control capability and further reducing the leakage current.

[0036] Figure 2 and Figure 3 They are schematic diagrams of the structure of GAAFET (20, 30) according to an embodiment of the present application. Figure 2 The channel region 11 in the embodiment is a nanowire structure. Figure 3 The channel region 11 in the embodiment is a nanosheet structure.

[0037] like Figure 2 and Figure 3 As shown, GAAFETs can be divided into nanowire and nanosheet structures, depending on the aspect ratio of the channel region between the source (S) and drain (D). Multiple nanowires or nanosheets are stacked and serve as the channel region 11 connecting the source and drain (not shown in the figure). This allows the gate (G) 12 to surround all sides of the channel region 11, achieving the goal of the gate 12 completely encompassing the channel region 11. This structure allows for better control of the channel region 11, further reducing leakage current, and improving parasitic capacitance and resistance issues.

[0038] It should also be noted that, those skilled in the art will understand that in order to more clearly illustrate the shape of the channel region 11, Figure 2 and Figure 3 The source, drain, dielectric and other components are not shown. The construction of the above components can be found in Figure 5 or Figure 6 The content shown.

[0039] Figure 4 FIG is a schematic cross-sectional view of a FinFET 40 according to an embodiment of the present application. Figure 4As shown, the FinFET 40 includes a source 13, a drain 14 and a gate 12. A channel region 11 is provided between the source 13 and the drain 14.

[0040] To prevent direct conduction between the gate 12 and the source / drain (13, 14), an inner spacer 110 is provided between the source / drain (13, 14) and the gate 12. The inner spacer 110 is made of a dielectric material and is used to isolate the source / drain (13, 14) from the gate 12. Due to the presence of the inner spacer 110, the channel region 11 is divided into an inactive gate control region 120 and an active gate control region 130. The channel region 11 covered by the inner spacer 110 is referred to as the inactive gate control region 120, which cannot be directly covered and controlled by the gate 12. The region directly covered by the gate 12 is referred to as the active gate control region 130, which can be directly covered and controlled by the gate 12. A gate dielectric layer 140 is also provided between the gate 12 and the channel region 11. The gate dielectric layer 140 is used to isolate the gate 12 from the channel region 11. Below the channel region 11 is a silicon substrate 16.

[0041] Figure 5 FIG is a cross-sectional view of a GAAFET 50 according to an embodiment of the present application. Figure 5 As shown in FIG. 5 , the GAAFET 50 includes a source 13, a drain 14, and a gate 12. Figure 4 The difference between the FinFET 40 in FIG. 1 and FIG. 2 is that the channel region 11 in the GAAFET 50 is composed of a plurality of stacked nanosheets or nanowires. Figure 5 As shown, a plurality of stacked channel regions 11 are provided between the source 13 and the drain 14 .

[0042] Correspondingly, in the cross-sectional direction of the GAAFET, a plurality of stacked inner isolation layers 110 and a plurality of stacked gate dielectric layers 140 are also provided between the source 13 and the drain 14 .

[0043] In the FinFET and GAAFET manufacturing process, in order to suppress the attenuation of carrier mobility in the channel and reduce the influence of channel impurity fluctuations, the channel material is generally prepared using low-doped high-resistance semiconductor materials, while the source / drain (13, 14) is usually made of highly doped semiconductor materials with low resistance.

[0044] When the transistor is turned on, based on the modulation of the gate voltage, ideally the entire channel region 11 should be in a low-resistance state. However, since the gate 12 does not cover the ineffective gate-controlled region 120, the gate voltage can only effectively control the effective gate-controlled region 130, but cannot effectively control the ineffective gate-controlled region 120. When the transistor is turned on, the resistance of the ineffective gate-controlled region 120 will not completely decrease with the increase of the gate voltage, so the resistance of the ineffective gate-controlled region 120 will become the resistance bottleneck between the source 13 and the drain 14, affecting the device performance of the GAAFET.

[0045] One solution to this problem is to use highly doped, low-resistance materials throughout the entire channel region 11 of FinFETs and GAAFETs to reduce the resistance of the entire channel region 11. While this approach reduces the resistance in the inactive gate region 120, the high concentration of impurities in the material increases carrier scattering in the active gate region 130, reducing carrier mobility and sacrificing transistor performance. Furthermore, random fluctuations in impurities in the channel at small dimensions can also lead to more pronounced, irregular variations in device performance.

[0046] To address the above issues, embodiments of the present application provide a manufacturing solution for a field-effect transistor (FET). This solution precisely modulates the semiconductor doping in the non-active gate region 120 covered by the inner isolation layer 110, thereby reducing the resistance of this region. Furthermore, the remainder of the channel region (i.e., the active gate region 130) can still maintain a high-resistance state under low doping conditions, thereby maintaining high carrier mobility in the channel region. Such FETs include, but are not limited to, FinFETs and GAAFETs.

[0047] Next, taking FinFET and GAAFET as examples, the field effect transistor and the manufacturing method thereof in the embodiments of the present application will be introduced in conjunction with the accompanying drawings.

[0048] Figure 6 FIG is a schematic cross-sectional view of a FinFET 60 according to an embodiment of the present application. Figure 6 As shown, the FinFET 60 includes a source 13, a drain 14, and a gate 12, with a channel region 11 disposed between the source 13 and the drain 14. An inner isolation layer 110 is disposed between the gate 12 and the source 13, and between the gate 12 and the drain 14. The channel region 11 includes an effective gate-controlled region 130 and an ineffective gate-controlled region 120. The ineffective gate-controlled region 120 is the region of the channel region 11 covered by the inner isolation layer 110; the effective gate-controlled region 130 is the region of the channel region 11 covered by the gate 12.

[0049] When forming the inner isolation layer 110 in the FinFET 60, a material containing donor or acceptor impurities can be used to form the inner isolation layer 110. The inner isolation layer is composed of an insulating material and is used to isolate the gate from the drain, and the gate from the source. The inner isolation layer can be a mixture (e.g., phosphosilicate glass or borosilicate glass) or a compound composed of donor or acceptor impurities and other elements (e.g., silicon, oxygen, nitrogen, etc.).

[0050] Donor impurities typically refer to Group V elements (e.g., phosphorus, arsenic, antimony, etc.). After being doped into semiconductor silicon, donor impurities can replace some silicon atoms, and each replacement of a silicon atom will produce an additional valence electron, forming an N-type semiconductor. Acceptor impurities typically refer to Group III elements (e.g., boron, indium, aluminum). After being introduced into semiconductor silicon, acceptor impurities can replace some silicon atoms, and each replacement of a silicon atom will produce an additional hole.

[0051] During the subsequent high-temperature preparation process, the above-mentioned donor impurities or acceptor impurities can diffuse into the adjacent semiconductor materials. Since the inner isolation layer 110 is closely adjacent to the non-effective gate-controlled region 120, the donor impurities or acceptor impurities can accurately diffuse into the non-effective gate-controlled region 120, thereby reducing the resistance of the non-effective gate-controlled region 120 by increasing the doping degree in the non-effective gate-controlled region 120, thereby reducing the resistance of the non-effective gate-controlled region 120, and further reducing the resistance of the non-effective gate-controlled portion 130 in the channel region 11.

[0052] In addition, since the inner isolation layer 110 is not adjacent to the effective gate control region 130, the diffusion range of donor impurities or acceptor impurities into the effective gate control region 130 is limited, and will not affect the doping degree of the effective gate control region 130, thereby not causing the decline of carrier mobility in the effective gate control region 130, and maintaining the conductive performance of the effective gate control region 130.

[0053] In some examples, the subsequent high-temperature preparation processes include but are not limited to: a high-temperature process for source and drain epitaxial growth; a high-temperature process for source and drain impurity activation; and post-metallization annealing (PMA) after completion of the high-K metal gate.

[0054] As an example, the donor impurities include but are not limited to at least one of the following: phosphorus, arsenic, and antimony.

[0055] As examples, the above-mentioned acceptor impurities include but are not limited to: boron, indium, and aluminum.

[0056] As an example, the inner isolation layer 110 may include, but is not limited to, phosphosilicate glass, borosilicate glass, and arsenic silicate glass. Phosphosilicate glass, borosilicate glass, and arsenic silicate glass refer to silicon dioxide doped with phosphorus, boron, or arsenic, respectively. Phosphosilicate glass and arsenic silicate glass can provide donor impurities such as phosphorus and arsenic, while borosilicate glass can provide acceptor impurities such as boron.

[0057] It should be understood that the above-mentioned inner isolation layer can also be made of other materials, as long as it is a dielectric material containing donor impurities or acceptor impurities, and they will not be listed one by one here.

[0058] The present application provides a method for manufacturing a field-effect transistor, wherein the method uses a material containing donor impurities or acceptor materials to form an inner isolation layer. During a subsequent high-temperature process, the donor impurities or acceptor impurities can diffuse into the ineffective gate-controlled region covered by the inner isolation layer, forming a low-resistance state under high doping. The semiconductor doping of the ineffective gate-controlled region covered by the inner isolation layer is precisely modulated to reduce the resistance of the region. The remaining portion of the channel region (or, the effective gate-controlled region) can still maintain a high-resistance state under low doping, thereby maintaining high carrier mobility in the channel and improving the performance of the field-effect transistor.

[0059] Figure 7 Schematic diagram of the structure of GAAFET 70 according to one embodiment of the present application. Figure 7 As shown, the GAAFET 70 includes a source 13, a drain 14, and a gate 12. A plurality of stacked channel regions 11 are provided between the source 13 and the drain 14. A plurality of inner isolation layers 110 are provided between the gate 12 and the source 13, and between the gate 12 and the drain 14. Each channel region 11 includes an effective gate control region 130 and an ineffective gate control region 120. The ineffective gate control region 120 is the region of the channel region 11 covered by the inner isolation layer 110; the effective gate control region 130 is the region of the channel region 11 covered by the gate 12.

[0060] Optionally, the plurality of stacked channel regions 11 may be a nanowire structure or a nanosheet structure.

[0061] and Figure 6 Similarly, when preparing the inner isolation layer 110 in the GAAFET 70, a material containing donor impurities or acceptor impurities can be used to prepare the inner isolation layer 110. During the subsequent high-temperature preparation process, the donor impurities or acceptor impurities can diffuse into the adjacent semiconductor material. Since the inner isolation layer 110 is closely adjacent to the inactive gate region 120, the donor impurities or acceptor impurities can diffuse into the inactive gate region 120, thereby reducing the resistance of the inactive gate region 120 by increasing the doping level in the inactive gate region 120, thereby reducing the resistance of the entire channel region.

[0062] For the sake of brevity, Figure 7 Zhongyu Figure 6 The same or similar content will not be repeated here.

[0063] like Figure 6 and Figure 7 As shown, a gate dielectric layer 140 is further provided between the gate 12 and the channel region 11. The gate dielectric layer 140 is used to isolate the gate from the channel region.

[0064] As an example, gate 12 may be a high-k metal gate (HKMG). HKMG is a gate manufacturing process used as transistor feature sizes continue to shrink. During transistor manufacturing, a high-k gate dielectric layer and a metal gate (MG) are combined. The high-k process partially replaces traditional silicon dioxide (SiO2) as the gate dielectric layer 140 with a material having a high dielectric constant. The MG process uses metal materials instead of polysilicon as the gate. HKMG technology effectively suppresses the traditional gate polysilicon depletion effect, enhancing the gate's ability to control the channel while reducing gate leakage current.

[0065] like Figure 6 and Figure 7 As shown, field-effect transistors can be placed in wells 17 implanted in silicon substrate 16. Wells 17 refer to regions doped with N-type or P-type impurities in silicon substrate 16, and are referred to as N-wells and P-wells, respectively. Shallow trench isolation (STI) 18 is also provided in well 17. STI 18 is typically made of an insulating material, such as SiO2, and serves to separate two adjacent transistors.

[0066] Figure 8 FIG. 1 is a flow chart of a method for manufacturing a field effect transistor according to an embodiment of the present application. Figure 8 As shown, the method includes:

[0067] S801. Obtain a silicon-based original wafer.

[0068] S802. Fabricate an inner isolation layer of the field effect transistor on the silicon-based original wafer, wherein the inner isolation layer is used to isolate the gate and source, as well as the gate and drain, of the field effect transistor and covers a portion of the channel region, and the inner isolation layer includes donor impurities or acceptor impurities.

[0069] Those skilled in the art will appreciate that, before forming the inner isolation layer on the silicon-based wafer, other processes for manufacturing field-effect transistors can be performed on the silicon-based wafer. These processes include, but are not limited to, epitaxial growth of stacked materials, photolithographic etching of fin patterns, STI material filling, polysilicon deposition, and etching of polysilicon dummy gates.

[0070] After the inner isolation layer is formed on the silicon substrate, other processes for manufacturing field-effect transistors can be performed on the silicon substrate. These processes include, but are not limited to, source and drain growth, polysilicon dummy gate removal, gate oxidation, and the formation of a high-K dielectric metal gate.

[0071] The present application provides a method for manufacturing a field-effect transistor, wherein an inner isolation layer is made of a material containing donor impurities or acceptor materials. During a subsequent high-temperature process, the donor impurities or acceptor impurities can diffuse into the ineffective gate-controlled region covered by the inner isolation layer, forming a low-resistance state under high doping. The semiconductor doping of the ineffective gate-controlled region covered by the inner isolation layer is precisely modulated to reduce the resistance of the region. The remaining portion of the channel region (i.e., the effective gate-controlled region) can still maintain a high-resistance state under low doping, thereby maintaining high carrier mobility in the channel and improving the performance of the field-effect transistor.

[0072] Next, a specific manufacturing method 900 of the GAAFET is described by taking the GAAFET as an example.

[0073] S901. Obtain a silicon-based original wafer.

[0074] S902. Epitaxially grow SiGe (silicon germanium) / Si (silicon) stacked material on the semiconductor substrate of the silicon-based original wafer.

[0075] S903, using a mask to photolithographically etch a fin-shaped pattern.

[0076] S904: Filling the STI material.

[0077] S905 , depositing polysilicon, and using a mask to photoetch a polysilicon dummy gate on the polysilicon.

[0078] S906: Generate an inner isolation layer.

[0079] Wherein, the inner isolation layer includes donor impurities or acceptor impurities. The detailed description of the inner isolation layer can be found in the above text, and will not be repeated here for the sake of brevity.

[0080] S907 , growing embedded source and drain layers, and performing source and drain ion implantation.

[0081] S908 , removing the polysilicon dummy gate.

[0082] S909, selectively etching the trench and leaving the trench material.

[0083] S910 , performing gate oxidation, high-K dielectric metal gate formation, and work function metal deposition.

[0084] S911, open the source and drain gates for extraction.

[0085] Optionally, after S911, the subsequent manufacturing process of GAAFET may be continued. For the sake of brevity, the subsequent manufacturing process will not be described in detail.

[0086] Those skilled in the art will appreciate that the above method 900 is merely an example for describing the manufacturing process of GAAFET, and in practice, some steps may be appropriately added or reduced.

[0087] It should be understood that the production processes and key steps of FinFETs and GAAFETs are similar, and only some steps need to be adjusted. For example, in the process of manufacturing FinFETs, steps S903 and S909 in method 900 can be omitted. For the sake of brevity, the FinFET manufacturing method will not be described here.

[0088] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0089] Those skilled in the art will clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0090] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A field effect transistor, characterized in that: include: source, drain, and gate; A channel region is provided between the source electrode and the drain electrode; An inner isolation layer is provided between the gate and the source and between the gate and the drain, and the inner isolation layer covers a portion of the channel region, wherein the inner isolation layer includes donor impurities or acceptor impurities, and the donor impurities or acceptor impurities diffuse into the portion of the channel region covered by the inner isolation layer.

2. The field effect transistor according to claim 1, wherein The donor impurities include at least one of the following: phosphorus, arsenic, and antimony.

3. The field effect transistor according to claim 1 or 2, characterized in that The acceptor impurities include at least one of the following: boron, indium, and aluminum.

4. The field effect transistor according to any one of claims 1 to 3, wherein The inner isolation layer includes at least one of the following: phosphosilicate glass, borosilicate glass, and arsenic silicate glass.

5. The field effect transistor according to any one of claims 1 to 4, characterized in that The field effect transistor includes a gate-all-around field effect transistor (GAAFET), the channel region is a first channel region, a plurality of stacked channel regions are provided between the source and the drain, and the first channel region is any channel region of the plurality of stacked channel regions; as well as, The inner isolation layer is a first inner isolation layer, a plurality of stacked inner isolation layers are provided between the gate and the source and between the gate and the drain, and the first inner isolation layer is any one of the plurality of stacked inner isolation layers.

6. The field effect transistor according to any one of claims 1 to 5, characterized in that The field effect transistor includes a fin field effect transistor FinFET.

7. A method for manufacturing a field effect transistor, characterized in that: include: Obtain silicon-based original wafers; An inner isolation layer of the field effect transistor is generated on the silicon-based original wafer, wherein the inner isolation layer is used to isolate the gate and source, as well as the gate and drain, of the field effect transistor and covers a portion of the channel region. The inner isolation layer includes donor impurities or acceptor impurities, and the donor impurities or acceptor impurities diffuse into the portion of the channel region covered by the inner isolation layer.

8. The method according to claim 7, wherein The donor impurities include at least one of the following: phosphorus, arsenic, and antimony.

9. The method according to claim 7 or 8, wherein The acceptor impurities include at least one of the following: boron, indium, and aluminum.

10. The method according to any one of claims 7 to 9, characterized in that The inner isolation layer includes at least one of the following: phosphosilicate glass, borosilicate glass, and arsenic silicate glass.

11. The method according to any one of claims 7 to 10, characterized in that The field effect transistor includes a gate-all-around field effect transistor (GAAFET), the channel region is a first channel region, a plurality of stacked channel regions are provided between the source and the drain, and the first channel region is any channel region of the plurality of stacked channel regions; as well as, The inner isolation layer is a first inner isolation layer, a plurality of stacked inner isolation layers are provided between the gate and the source and between the gate and the drain, and the first inner isolation layer is any one of the plurality of stacked inner isolation layers.

12. The method according to any one of claims 7 to 11, characterized in that The field effect transistor includes a fin field effect transistor FinFET.

13. An electronic device, characterized in that: The method comprises the field effect transistor according to any one of claims 1 to 5.

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