Systems and methods using non-ideal polarization bit channels in parallel polar codes

Abstract

The disclosed systems, structures, and methods relate to encoding and decoding information for transmission over a communication channel. The encoding method includes: distributing the information bits among m parallel polar codes such that each of the m parallel polar codes includes a subset of the information bits; dividing the subset of information bits in each of the m parallel polar codes into a guard information portion and a full-rate information portion; guarding the information bits within the guard information portion of each of the m parallel polar codes; setting multiple freeze bits in each of the m parallel polar codes; and generating a polar codeword for each of the m parallel polar codes.

Description

[0001] Cross-references

[0002] This application claims the benefit and priority of U.S. nonprovisional patent application No. 17 / 163,100, filed January 29, 2021, entitled “Systems and methods for using notperfectly polarized bit channels in parallel polar codes,” the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure generally relates to the field of encoding and decoding information for transmission over noisy media, and more specifically to systems and methods for using polar codes to enhance the reliability of data transmission. Background Technology

[0004] In data communication systems, data is transmitted from a transmitter to a receiver via a channel. Due to noise in the channel, the quality of the transmitted data degrades, potentially causing the received data to be inconsistent with the transmitted data. The implementation of the transmitter and receiver depends on the channel through which the data is being transmitted; for example, whether the channel is wireless, cable, or fiber optic.

[0005] Forward error correction (FEC) codes provide reliable communication in one-way channels by enabling the receiver to detect and correct a limited number of errors. FEC techniques can be used to reduce the bit error rate (BER). Messages can be transmitted using FEC-coded bits, which include redundant information, such as parity bits or check bits. The bit estimates recovered at the receiver are estimates of the FEC-coded bits generated at the transmitter. These estimates can be FEC-decoded at the receiver according to the selected FEC scheme. FEC decoding utilizes the redundant information included in the FEC-coded bits to detect and correct bit errors. Ultimately, the estimates of the original message bits can be recovered from the FEC-decoded bit estimates.

[0006] The two basic types of FEC are block FEC and convolutional FEC. Block FEC divides data into blocks, each of which is independently encoded before being sent (i.e., independent of other blocks). In convolutional FEC, the encoded data depends on the current data and previous data in the digital communication scheme.

[0007] Forward error correction (FEC) is crucial in data transmission systems. For example, in high-throughput optical transmission systems, it is not uncommon for FEC to consume more than half of the power of optical digital signal processing (oDSP). Therefore, it is desirable to design FECs with high coding gain, low latency, and low power consumption.

[0008] There are many techniques for designing FECs, and many types of FECs are known in the field (e.g., algebraic codes, convolutional turbo codes, low-density parity-check (LDPC) codes, turbo product codes (TPC), etc.). In 2009, Arikan introduced a block FEC called "polar codes" in the following paper: "Channel Polarization: A method for Constructing Capacity Achieving Codes for Symmetric Binary-Input Memoryless Channels" published by E. Arikan in Volume 55, Issue 7 (July 2009), pp. 3051-3073. Polar codes are linear block codes that can "polarize" the capacity of a bit channel. That is, after the bit channel is polarized by polarized block codes, the capacity of the bit channel is close to 1 (i.e., an ideal channel) or 0 (a completely noisy channel). Data is then transmitted through bit channels with a capacity close to 1, while predetermined (e.g., constant) bit values ​​are transmitted through bit channels with a capacity close to 0 (these bits are called "frozen" bits because their values ​​do not change). Arikan was able to prove that when the code length (i.e., the number of bit channels) approaches infinity, the number of bit channels with a capacity of 1 divided by the total number of bit channels approximates the channel capacity, i.e., the theoretical maximum data rate of the channel (also known as "Shannon capacity").

[0009] Arikan's proposed polar code decoding algorithm is called "successive-cancellation (SC)" decoding, which can be efficiently represented as a binary tree search. While SC decoding exhibits excellent performance with code lengths approaching infinity, its performance is unsatisfactory with small to medium code lengths. Therefore, many alternative decoding algorithms have been proposed. One of the most frequently cited alternatives is called "successive-cancellation-list (SCL)" decoding, described in "List Decoding of Polar Codes" by I. Tal and A. Vardy, Vol. 61, No. 5, pp. 2213-2226 (May 2015). SCL decoding combines list decoding (a decoding technique known since the 1950s) with SC decoding of polar codes, resulting in an algorithm that does not examine individual candidate codewords (as in SC decoding), but instead examines a "list" containing Lm most likely candidate codewords. It has been demonstrated that SCL decoding of polar codes combined with cyclic redundancy check (CRC) (a type of error detection code known since 1961) has error correction performance comparable to low-density parity check codes. However, both SC and SCL decoders suffer from high latency, making them difficult to implement in high-throughput applications.

[0010] Polar codes are the first, and currently the only, class of codes that have been proven through analysis to achieve channel capacity with achievable complexity. While polar codes possess this theoretical advantage over other known FECs, many challenges remain in practical implementation. Therefore, there is a desire to improve methods using polar coding techniques that utilize increased coding gain and high throughput. Summary of the Invention

[0011] This disclosure provides an encoder and a decoder that use multiple polar codes in parallel and cooperate with each other. Compared to traditional polar codes, this cooperation improves gain, and the use of parallel polar codes increases overall throughput. Therefore, the disclosed technique improves the reliability and throughput of digital communication.

[0012] According to one aspect of this disclosure, the above-described technology is implemented as a method for encoding information bits for transmission via a communication channel. The method may include: distributing the information bits among m parallel polar codes, such that each of the m parallel polar codes includes a subset of the information bits; dividing the subset of information bits in each of the m parallel polar codes into a protection information portion and a full-rate information portion; protecting the information bits in the protection information portion of each of the m parallel polar codes; setting a plurality of freeze bits in each of the m parallel polar codes; and generating a polar codeword for each of the m parallel polar codes.

[0013] According to some other and any of the above embodiments, the information bits in the protection information portion of each of the m parallel polar codes are positioned in the non-ideal polarization bit channel of the corresponding parallel polar code among the m parallel polar codes.

[0014] According to some other and any of the above embodiments, for each of the m parallel polar codes, the positions in the non-ideal polarized bit channel are grouped into L blocks, wherein each of the L blocks includes a subset of the information bits within the protection information portion.

[0015] According to some other and any of the above embodiments, the total number of blocks in the non-ideal polarized bit channel of each of the m parallel polarized codes is determined based on the total number of factors of m greater than 1.

[0016] According to some other and any of the above embodiments, the information bits in the protection information portion of each of the m parallel polar codes are protected using a repetition code.

[0017] According to some other and any of the above embodiments, the information bits in one block of the L blocks of the first parallel polar code of the m parallel polar codes are repeated in one block of the L blocks of the second parallel polar code of the m parallel polar codes.

[0018] According to some other and any of the above embodiments, the information bits in one block of one of the L blocks of the first parallel polar code in the m parallel polar codes are repeated d times in the m parallel polar codes. i Next, among which, d i It is a factor of m and is greater than 1.

[0019] According to some other and any of the above embodiments, the information bits in the protection information portion of each of the m parallel polar codes are protected using Bose-Chaudhuri-Hocquenghem (BCH) or Reed-Muller codes.

[0020] According to another aspect of this disclosure, there is a method for decoding m polar-coded codewords received through a communication channel. Each of the m polar-coded codewords is used to encode information bits in a plurality of nodes, and the method includes: for each node in each of the m polar-coded codewords: when the node is in a full-rate information portion, decoding the node according to a log-likelihood ratio (LLR) decoding algorithm to generate a first part of a decoded message; when the node is in a protection information portion, decoding the node according to an average LLR decoding algorithm to generate a second part of the decoded message.

[0021] According to some other and any of the above embodiments, the SC or SCL decoder is used to decode nodes in a codeword.

[0022] According to some other and any of the above embodiments, the method further includes: for each of the m polarized codewords, when the bits in the corresponding codeword are frozen bits, generating decoded bits in the decoded message according to a predetermined value.

[0023] According to some other and any of the above embodiments, the average LLR decoding algorithm is based on:

[0024]

[0025] in, d i It is the total number of repetitions of the node in the m polar-coded codewords. It is the LLR of the node in the corresponding codeword j among the m polarized codewords, j = 1...m.

[0026] According to one aspect of this disclosure, there exists an encoder for encoding information bits for transmission via a communication channel. The encoder includes circuitry configured to: distribute the information bits among m parallel polar codes, such that each of the m parallel polar codes includes a subset of the information bits; divide the subset of information bits in each of the m parallel polar codes into a protection information portion and a full-rate information portion; protect the information bits within the protection information portion of each of the m parallel polar codes; set a plurality of freeze bits in each of the m parallel polar codes; and generate polar codewords for each of the m parallel polar codes.

[0027] According to some other and any of the above embodiments, the circuit includes at least one processor and a memory storing programming instructions, wherein the programming instructions, when executed by the at least one processor, cause the at least one processor to encode the information bits.

[0028] According to some other and any of the above embodiments, the information bits in the protection information portion of each of the m parallel polar codes are positioned in the non-ideal polarization bit channel of the corresponding parallel polar code among the m parallel polar codes.

[0029] According to some other and any of the above embodiments, for each of the m parallel polar codes, the positions in the non-ideal polarized bit channel are grouped into L blocks, wherein each of the L blocks includes a subset of the information bits within the protection information portion.

[0030] According to some other and any of the above embodiments, the information bits in the protection information portion of each of the m parallel polar codes are protected using a repetition code.

[0031] According to some other and any of the above embodiments, the information bits in one block of the L blocks of the first parallel polar code of the m parallel polar codes are repeated in one block of the L blocks of the second parallel polar code of the m parallel polar codes.

[0032] According to some other and any of the above embodiments, the information bits in one block of one of the L blocks of the first parallel polar code in the m parallel polar codes are repeated d times in the m parallel polar codes. i Next, among which, d i It is a factor of m and is greater than 1.

[0033] According to one aspect of this disclosure, there exists a decoder for decoding m polar-coded codewords received via a communication channel. The decoder includes circuitry configured to: for each node in each of the m polar-coded codewords: when the node is within a full-rate information portion, decode the node according to an LLR decoding algorithm to generate a first part of a decoded message; when the node is within a protection information portion, decode the node according to an average LLR decoding algorithm to generate a second part of the decoded message; and when a bit in the corresponding codeword is a frozen bit, generate decoded bits in the decoded message according to predetermined values. Attached Figure Description

[0034] The features and advantages of this disclosure will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, in which:

[0035] Figure 1 An encoder for polar codes (e.g., that can be used for polar coding) is shown in some exemplary embodiments.

[0036] Figure 2 This is a block diagram of a communication system that can implement the technology of this disclosure.

[0037] Figure 3 This is an exemplary diagram illustrating the bit channel capacity of the three polar codes.

[0038] Figure 4 This is an exemplary diagram illustrating the bit channel capacity of a polar code.

[0039] Figure 5 The structure of an exemplary parallel polar code provided by some exemplary embodiments is shown.

[0040] Figure 6 This is a flowchart of an encoding method provided by some exemplary embodiments.

[0041] Figure 7 This is a flowchart of a decoding method provided by some exemplary embodiments.

[0042] Figure 8 Simulation results of a parallel polar coding method provided by one implementation of the disclosed technique are shown.

[0043] It should be understood that in all the drawings and corresponding descriptions, the same features are identified by the same reference numerals. Furthermore, it should be understood that the drawings and the following description are for illustrative purposes only, and this disclosure is not intended to limit the scope of the claims. Detailed Implementation

[0044] Various representative embodiments of the disclosed technology will now be described more fully with reference to the accompanying drawings. However, the technology in this disclosure may be embodied in many different forms and should not be construed as limited to the representative embodiments set forth herein. In the drawings, the dimensions and relative dimensions of layers and regions may be exaggerated for clarity. Throughout the specification, similar numerals refer to similar elements.

[0045] It should be understood that although the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Therefore, without departing from the teachings of this disclosure, the first element discussed below may be referred to as the second element. The term “and / or” as used herein includes any and all combinations of one or more of the associated listed items.

[0046] It should be understood that when an element is referred to as "connected" or "coupled" to another element, the element may be directly connected or coupled to the other element, or there may be an intermediate element (e.g., indirect connection or coupling). Conversely, when an element is referred to as "directly connected" or "directly coupled" to another element, there is no intermediate element. Other terms used to describe the relationship between elements should be interpreted in a similar manner (e.g., "between" and "directly between," "adjacent" and "directly adjacent," etc.). Furthermore, it should be understood that elements may be "coupled" or "connected" in mechanical, electrical, communicative, wireless, optical, or other ways, depending on the type and nature of the element to which they are coupled or connected.

[0047] The terminology used herein is for describing specific, representative embodiments only and is not intended to limit the technology of this disclosure. Unless the context clearly indicates otherwise, the singular forms “a” and “described” as used herein also include the plural forms. It should also be understood that the term “comprising” as used herein is used to indicate the presence of the stated feature, integer, step, operation, element, and / or component, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or combinations thereof.

[0048] The functionality of the various elements shown in the figures, including any functional blocks labeled "processor," can be provided by using dedicated hardware and hardware capable of executing instructions, associated with appropriate software instructions. When provided by a processor, these functions can be provided by a single dedicated processor, a single shared processor, or multiple separate processors, some of which may share resources. In some embodiments of the technology in this disclosure, the processor can be a general-purpose processor, such as a central processing unit (CPU), or a purpose-specific processor, such as a digital signal processor (DSP). Furthermore, the explicit use of the term "processor" should not be construed as referring specifically to hardware capable of executing software, and may implicitly include, but is not limited to, application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), read-only memory (ROM), random access memory (RAM), and non-volatile memory for storing software. Other conventional and / or custom hardware may also be included.

[0049] A software module, or a simple module or unit implied as software, may herein be represented as a flowchart element or any combination of other elements indicating process steps and / or textual descriptions of performance. Such modules may be executed by hardware, whether explicitly or implicitly indicated. Furthermore, it should be understood that a module may include, but is not limited to, computer program logic, computer program instructions, software, stacks, firmware, hardware circuitry, or combinations thereof, providing the required capabilities. It should also be understood that a “module” typically defines a logical grouping or organization of associated software code or other elements as described above, related to a defined function. Therefore, those skilled in the art will understand that in some implementations, specific code or elements described as part of a “module” may be placed in other modules, depending on the logical organization of the software code or other elements, and such modifications are within the scope of the disclosure as defined in the claims.

[0050] It should be noted that the term "optimization" used in this article refers to improvement. "Optimization" does not mean that the technology has produced an objectively "best" solution, but rather that it has resulted in an improved solution. In the context of memory access, it usually means that the efficiency or speed of memory access can be improved.

[0051] As used in this document, the term "determine" generally means to perform a direct or indirect operation, calculation, decision, lookup, measurement, or detection. In some cases, such determination may be approximate. Therefore, determining a value means that the value or an approximation of the value can be performed directly or indirectly. If an item is "predetermined," then the item is determined at any time prior to the moment indicating that the item is a "predetermined" item.

[0052] The techniques disclosed herein can be implemented as a system, a method, and / or a computer program product. The computer program product may include one or more computer-readable storage media storing computer-readable program instructions. When executed by a processor, the computer-readable program instructions cause the processor to perform various aspects of the disclosed techniques. The computer-readable storage medium may be, for example, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of these devices. A non-exhaustive list of more specific examples of computer-readable storage media includes: portable computer disks, hard disks, RAM, ROM, flash memory, optical disks, memory sticks, floppy disks, mechanical or visual encoding media (e.g., punched cards or barcodes), and / or any combination of these devices. The computer-readable storage medium used herein should be construed as a non-transient computer-readable medium. It should not be construed as a transient signal, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides or other transmission media (e.g., light pulses through fiber optic cables), or electrical signals transmitted through wires.

[0053] It should be understood that computer-readable program instructions can be downloaded from a computer-readable storage medium to the corresponding computing or processing device, or downloaded via a network such as the Internet, local area network, wide area network, and / or wireless network to an external computer or external storage device. The network interface in each computing / processing device can receive and forward computer-readable program instructions over the network for storage in a computer-readable storage medium within the corresponding computing or processing device. Computer-readable program instructions used to perform the operations of this disclosure can be assembler instructions, machine instructions, firmware instructions, integrated circuit configuration data, or source code or object code written in any combination of one or more programming languages.

[0054] All descriptions and specific examples of the principles, aspects, and implementations of the technology described herein are intended to include their structural and functional equivalents, whether they are currently known or will be developed in the future. Therefore, for example, those skilled in the art will understand that any block diagram herein represents a conceptual view of an illustrative circuit embodying the principles of the technology of this disclosure. Similarly, it should be understood that any flowchart, flow diagram, state transition diagram, pseudocode, etc., represents various processes that can be substantially represented by computer-readable program instructions. These computer-readable program instructions can be provided to a processor or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of a computer or other programmable data processing apparatus, create components for implementing the functions / actions specified in the flowchart and / or one or more block steps. These computer-readable program instructions can also be stored in a computer-readable storage medium that can instruct a computer, programmable data processing apparatus, and / or other device to operate in a particular manner, such that the computer-readable storage medium storing the instructions comprises an article of manufacture containing the instructions for implementing various aspects of the functions / actions detailed in the flowchart, flow diagram, state transition diagram, pseudocode, etc.

[0055] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus or other equipment to cause a series of operational steps to be performed on the computer, other programmable apparatus or other equipment, thereby producing a computer-implemented process, such that the instructions executed on the computer, other programmable apparatus or other equipment are used to implement the functions / actions detailed in flowcharts, flow diagrams, state transition diagrams, pseudocode, etc.

[0056] In some alternative implementations, the functions marked in flowcharts, flow diagrams, state transition diagrams, pseudocode, etc., may not be executed in the order indicated in the diagram. For example, two steps shown consecutively in a flowchart may actually be executed substantially simultaneously, or, depending on the functions used, these steps may sometimes be executed in reverse order. It should also be noted that each function marked in the diagram, as well as combinations of these functions, can be implemented by a dedicated hardware system that performs the specified function or action, or by a combination of dedicated hardware and computer instructions.

[0057] Based on this foundational knowledge, the following non-limiting examples illustrate various implementations of different aspects of this disclosure.

[0058] Figure 1An encoder 100 for polar codes is shown. As described above, a polar code is a linear block code used to "polarize" the capacity of bit channels (also called sub-channels), so that the capacity of these channels is close to 1 (i.e., an ideal channel) or 0 (a completely noisy channel). The information bits 102 in the message are then transmitted through bit channels with a capacity close to 1, while the frozen bits 104 (i.e., predetermined constant bit values) are transmitted through bit channels with a capacity close to 0.

[0059] Assume N and k are positive integers, where k ≤ N. For an (N,k) block code, its input is a vector of k bits, and its output is a vector of N bits. An encoder is one implementation of the (N,k) block code, and can be a function in software or hardware. N is called the block size or block length. k / N can be called the code rate.

[0060] The polar encoder 100 typically encodes the input bits 106. The input bits 106 include information bits 102 and freeze bits 104, and the total block length is N = 2. n , where n is an integer. This can be called an (N,k) polar code, consisting of k information bits (i.e., information bits 10²) and N code bits 10⁸, with the remainder being (N–k) freeze bits 10⁴. In general, an (N,k) polar code can be constrained by an N×N generator matrix G, where

[0061]

[0062] In the above formula, This represents an n-fold power of Kronecker. Here, the input bits 106 represent u = [u1, u2, ..., u...]. N ] T The encoded bits 108 (collectively referred to as "codewords" x) are represented as x = [x1, x2, ..., x...]. N ] T The codeword is given by x = GBu, where B represents an N×N bit inverted permutation matrix. This operation takes place within the polar encoder 100.

[0063] It should be understood that the generator matrix G is only one generator matrix that produces polarization, and it is well known that other generator matrices will also produce this polarization. Furthermore, although for ease of illustration, the frozen bits 104 are shown to be located at the head of the input bits 106, they can actually be distributed among all the input bits 106.

[0064] It should also be understood that complete channel polarization is only achieved in the limit N→∞. For small to medium code lengths N, polar codes produce channels with a certain range of capacities. Although these capacities usually polarize to 1 (i.e., an ideal channel) or 0 (i.e., a completely noisy channel), they will not reach either of these limits. Therefore, for real-world polar coding, the k information bits 102 should be placed in the k most reliable (i.e., highest capacity) positions in u. The N–k frozen bits 104 can be placed in the least reliable positions in u, and are assigned to the encoder 100 and decoder (not shown in the original text). Figure 1 (As shown in the figure) are known fixed values.

[0065] Figure 2 This is a block diagram of a communication system 200 that can implement the technology of this disclosure. The communication system includes an encoder 202 and a transmitter 204, a communication channel 220, a receiver 250, and a decoder 252.

[0066] As described above, communication channel 220 can be a wireless communication channel, cable, or optical fiber, etc. It should be understood that noise or interference may exist on communication channel 220. Due to such noise or interference, some of the bits received at receiver 250 may be altered during transmission and therefore may differ from the bits transmitted by transmitter 204 through communication channel 220.

[0067] Encoder 202 receives a block of information (e.g., a message or part of a message) to be transmitted at its input 206, encodes the information according to one implementation of the disclosed technology described below to generate codewords for transmission via communication channel 220, and forwards the codewords to transmitter 204 for transmission via communication channel 220. In some implementations, encoder 202 includes one or more processors 210 and a memory 212, the memory 212 including programming instructions that cause processor 210 to encode information, as described below. It should be understood that in some implementations, for example in one or more chipsets, one or more microprocessors, one or more digital signal processors, one or more optical digital signal processors, one or more ASICs, one or more FPGAs, special-purpose logic circuits, or combinations thereof, encoder 202 may include alternative or additional hardware or circuitry for encoding information, as described below.

[0068] Transmitter 204 transmits codewords through communication channel 220. Therefore, the configuration of transmitter 204 depends on the nature of communication channel 220. Generally, transmitter 204 is a conventional transmitter for communication channel 220. Therefore, transmitter 204 may include modules for post-coding processing, as well as modules or components in the transmission chain for communication channel 220, such as modulators, amplifiers, multiplexers, light sources (e.g., for optical communication), antennas (e.g., for wireless communication), and / or other modules or components found in conventional transmitters.

[0069] Similarly, receiver 250 receives codewords via communication channel 220. Therefore, the details of the configuration of receiver 250 depend on the nature of communication channel 220. Receiver 250 is a conventional receiver for communication channel 220 and may include various modules and components from a conventional receiver chain (not shown), as well as components for any pre-decoding processing (not shown). For example, these modules and components may include antennas (e.g., for wireless communication), optical sensors or detectors (e.g., for optical communication), demodulators, amplifiers, demultiplexers, and / or other modules or components from a conventional receiver chain. The codewords received by receiver 250 are forwarded to decoder 252.

[0070] Decoder 252 receives codewords from receiver 250 and decodes the codewords according to one implementation of the disclosed technology described below to produce received information used by the decoder as output 256. In some implementations, decoder 252 includes one or more processors 260 and memory 262, the memory 262 including programming instructions that cause processor 260 to decode information, as described below. It should be understood that in some implementations, for example in one or more chipsets, one or more microprocessors, one or more digital signal processors, one or more optical digital signal processors, one or more ASICs, one or more FPGAs, special-purpose logic circuits, or combinations thereof, decoder 252 may include alternative or additional hardware or circuitry to decode information, as described below.

[0071] Figure 3This is an exemplary graph 300 illustrating the bit channel capacity of three polar codes. The signal-to-noise ratio (SNR) of the communication channel is 3 dB. The x-axis represents the ordered bit channel index divided by the block length N. Here, "divided by" refers to a mathematical operation. The y-axis represents the bit channel capacity value, where the capacity value "1" is called the Shannon capacity. It can be seen that among all three polar codes transmitted under the same conditions (e.g., SNR = 3 dB), for the polar code 310 with a block length N = 256, the ratio of the number of bit channels close to capacity 1 or 0 (i.e., ideal polarized bit channels) to the block length 256 is the smallest. For the polar code 320 with a block length N = 1024, the ratio of the number of bit channels close to capacity 1 or 0 (i.e., ideal polarized bit channels) to the block length 1024 is the second smallest. For polar code 330 with block length N = 4096, the ratio of the number of bit channels close to capacity 1 or 0 (i.e., ideally polarized bit channels) to the block length 4096 is the largest. This indicates that the channel polarization effect is better as N increases.

[0072] Figure 4 This is an exemplary graph 400 illustrating the bit channel capacity of a polar code. The x-axis represents the ordered bit channel index divided by the block length N. Here, "divided by" refers to a mathematical operation. The y-axis represents the bit channel capacity value. Assuming an SNR of 3dB, the gray area 450 represents the region of bit channels with bit channel capacities approximately between 0.05 and 0.95, which can be called non-ideal polarized bit channels. It should be understood that the definition of the bit channel capacity of a non-ideal polarized bit channel can vary depending on many factors such as communication channel noise, coding algorithm efficiency, communication standards (e.g., 4G vs. 5G) or communication channel types (e.g., wireless vs. optical communication); for example, in some cases, the bit channel capacity of a non-ideal polarized bit channel can be limited (according to Shannon capacity) to the range of 0.1 to 0.9.

[0073] like Figure 4 As shown, the ratio of the number of non-ideal polarized bit channels to the block length N typically decreases as the block length N increases. However, for medium to small code lengths N, polar codes can produce some channels with a certain range of capacity. Although these capacities usually polarize to 1 (i.e., ideal channel) or 0 (i.e., full noise channel), they will not reach either of these extremes. The ratio of ideal polarized bit channels to non-ideal polarized bit channels (or to block length N) typically decreases as the block length N decreases.

[0074] In traditional polar codes, non-ideal polarized bit channels are typically used as polarized bit channels: if the capacity of the bit channel is close to 1, full-rate information is transmitted through this channel; or, if the capacity of the bit channel is close to 0, the bits in this bit channel are used as frozen bits. However, the bit channels within region 450 are not actually ideal polarized bit channels, therefore the bit error rate (BER) of transmitting full-rate information through these bit channels may be higher than that through ideal polarized bit channels with a capacity close to 1 (e.g., Figure 4 Transmitting full-rate information through ideally polarized bit channels (above 450° in the middle region) results in a high bit error rate. On the other hand, using bits in these non-ideally polarized bit channels as frozen bits may waste the capacity of the bit channel. The technique in this disclosure utilizes non-ideally polarized bit channels to transmit information bits with some form of protection (security guarantee), for example, by using repetition codes on these bit channels when transmitting information bits, as detailed below. The disclosed technique provides a gain that can support higher throughput relative to conventional polar codes and can also be used in 5G wireless communication standards.

[0075] Figure 5 The structure 500 of the parallel polar code provided in this disclosure is shown. Groups are placed in different blocks b1, b2...b 28 The information bits are transmitted using m parallel polar codes, such that each of the m parallel polar codes includes a non-empty subset of the information bits (ignoring empty sets and empty subsets). Some blocks may repeat among the m parallel polar codes. As shown in the figure, in the illustrated example, there are m parallel polar codes 502, where m = 12, shown along the vertical axis as polar codes 1 to 12. Polar-coded codewords can be generated for each of the m parallel polar codes 502.

[0076] The polarization coding information is shown on the horizontal axis. The left side represents the least reliable bit channel, and the reliability of the positions increases from left to right. Frozen bits 503 are labeled f1, f2…f 12 The least reliable bit on the left (i.e., the bit channel with the closest capacity to 0) is occupied. The information bits in each polar code are divided into two parts, called the protection information part and the full-rate information part. The full-rate information part contains 506 information bits (grouped into blocks b1, b2…b…). 12 It occupies the most reliable bit channel (i.e., the bit channel with the capacity closest to 1) and transmits at full rate. In some embodiments, the information bit 506 in the full-rate information portion may be protected using conventional error-correcting codes such as BCH codes or Reed-Muller codes.

[0077] Information bit 505 in the protected information section (grouped into block b) 13 b 14...b 28 Occupying a non-ideal polarized bit channel position and transmitting at a rate less than 1 means, as detailed below, that information bit 505 is protected in one or more other rows of m parallel polar codes. It should be understood that b1, b2 to b... 28 They are all bit blocks and can each include one or more single bits (e.g., binary bits).

[0078] In some exemplary embodiments, in each of the m parallel polar codes 502, the information bits 505 at non-ideal polarized bit channel locations can be grouped into L bit blocks (hereinafter referred to as "one or more blocks"). Each of the L blocks includes a subset of the information bits 505 in the protection information portion. Figure 5 In the example shown, L = 5. The number of bits in each of the L blocks can be different.

[0079] For example, for polar code 1, information bits can be grouped into multiple blocks b. 13 b 14 b 16 b 19 and b 23 In one of the blocks. These blocks b 13 b 14 b 16 b 19 and b 23 Different code rates can be used for transmission. For example, still referring to polar code 1, block b 13 You can send at a rate of 1 / 12, block b 14 You can send at a rate of 1 / 6, block b 16 You can send at 1 / 4 rate, block b 19 You can send at 1 / 3 rate, block b 23 The transmission rate can be 1 / 2. Blocks in the protected information section can be protected using one method or another. In some embodiments, these blocks can be protected using repeating codes. In other embodiments, these blocks can be protected using BCH codes. Here, "protected" can refer to a bit pattern or encoding scheme that provides a degree of error correction.

[0080] The number of blocks including information bits 505 at the non-ideal polarization bit channel positions in each polarization code 502 can be determined by the total number of factors of m greater than 1. Figure 5 In the example shown, m = 12, and the six factors are 1, 2, 3, 4, 6, and 12, five of which are greater than 1. Therefore, block b... nThe total number (which can be represented by L) is 5. At this time, each polar code 502 includes a block of five (5) information bits 505 at the non-ideal polarization bit channel position.

[0081] In more general terms, given m parallel polar codes 502, suppose d i Let m represent the value of a factor of m that is greater than 1. Instead of sending m bit blocks or 0 bits through m bit channels, each bit block 505 is transmitted through each non-ideal polarized bit channel in each of the m parallel polar codes 502. Each bit in a block of bits can use a bit with length d i It uses a repeating code for protection. It has a length d. i The repeating code indicates that a bit (or bit block) can be repeated a total of d times in m parallel polar codes 502. i Second-rate.

[0082] In some embodiments, for one of the m parallel polar codes 502, the code rate 1 / d used to transmit the bit block at the non-ideal polarized bit channel position within the protection information portion is... i It can be done through d i Confirmed. Because in Figure 5 In the example shown, the protection information portion of each polar code 502 contains 5 bit blocks 505, each of which can be transmitted using a different code rate, where the code rate can be determined by a factor greater than 1 of m; here, m = 12. For example, looking at polar code 1, the least reliable bit position is grouped into the first block at the non-ideal polarized bit channel position (e.g., b). 13 In this block, the bit rate is 1 / 12, where d i =12 is the largest factor of m. As the reliability of the bit channel increases at non-ideal polarized bit channel locations, the second block (e.g., b) 14 It can be sent using a bitrate of 1 / 6, where d i =6 is the second largest factor of m; the third (e.g., b) 16 It can be sent at a bit rate of 1 / 4, where d i =4 is the third largest factor of m; the fourth (for example, b) 19 It can be sent using a bit rate of 1 / 3, where d i =3 is the fourth largest factor of m; the fifth (for example, b) 23 It can be sent using a bit rate of 1 / 2, where d i =2 is the smallest factor of m that is greater than 1.

[0083] As mentioned above, the bitrate is 1 / d iIt also indicates the use of a bitrate of 1 / d. i The block can be repeated d in m parallel polar codes 502 using repeating codes. i Next. Assume L represents the total number of blocks including information bits 505 at the non-ideal polarized bit channel positions in each polar code 502. When using repetition codes, one block (e.g., b) from the L blocks of the first parallel polar code (e.g., polar code 1) out of m parallel polar codes. 13 The information bit 505 in the code is repeated in one of the L blocks of the second parallel polar code (e.g., polar code 2) among m parallel polar codes. Block b n The number of repetitions can be determined by the number of blocks used to send block b. n bitrate 1 / d i express.

[0084] exist Figure 5 In the example shown, L=5, m=12 in column 505a at a rate of 1 / 12, block (e.g., b) 13 Repeat d among 12 parallel polar codes i = 12 times; in column 505b at rate 1 / 4, each block (e.g., b) 16 b 17 or b 18 Repeat d among 12 parallel polar codes i = 4 times; in column 505c at rate 1 / 2, each block (e.g., b) 23 To b 28 One block) is repeated in 12 parallel polar codes. i = 2 times. The information bit 505 in the protection information part of a parallel polar code can be repeated in more than one of the m parallel polar codes 502.

[0085] Therefore, the information bits 505 within the protected information section can be viewed as being encoded using polar codes (i.e., along the horizontal axis) and repetition codes (i.e., along the vertical axis). Furthermore, each of the m polar codes 502 includes a freeze bit 503 (labeled f1 to f...). 12 ).

[0086] It should be understood that Figure 5 Only one example is shown; other bit placement patterns and / or encoding schemes, including different numbers of parallel polar codes and different numbers of bit blocks, can be used according to the disclosed techniques. Generally, some advantages are provided in decoding when each bit within the protection information portion of a parallel polar code 502 appears within the protection information portion of at least one other parallel polar code 502. It should be understood that the illustrated example 500 only shows a simple repetition pattern of information bit 505, but other repetition patterns can also be used.

[0087] Assumption This indicates that each polar code 502 uses a number with length d. i The total number of non-ideal polarized bit channels protected by repeating codes. The optimization problem method described below can be used to calculate this.

[0088] Through density evolution (DE), the distribution and error probability of any bit channel (assuming continuous undecoding) can be calculated as follows. Assuming density pdf... k The k-th bit channel uses a length d k The repeated codes are used for protection. Then, the resulting density is... It can be calculated as follows:

[0089]

[0090] Here, "*" represents the mathematical operation of convolution.

[0091] The density obtained by using The error probability of the guard bit channel can be calculated. The effective rate r of m blocks in a polar code can be calculated using the following formula:

[0092]

[0093] Where K1 is the number of bits without additional protection.

[0094] The optimization problem can be expressed as:

[0095]

[0096] But the following conditions must be met:

[0097] in, Kc is the total number of bits in a non-ideal polarized bit channel, Pe(i k ) is the i-th k The error probability of a single bit channel can be determined in advance.

[0098] Assuming the bit channel is ordered according to its reliability, and more protection can be implemented for more unreliable bits, then FER can be written as:

[0099]

[0100] Among them, A i ={N-K1-…-K i +1:N-K1-…-K i},Pr(k,d i) is the k-th bit channel using a length d i The probability of error when using duplicate codes for protection.

[0101] This paper presents an efficient method for increasing the number and degree of protection of non-ideal polarized bit channels that require more protection by using density assessment.

[0102] Figure 6 This is a flowchart of an encoding method 600 provided in one implementation of the disclosed technology. The encoder receives p information bits and encodes the information using m parallel polar codes. In step 610, the encoder divides the p information bits to be encoded into m parts or subsets, where each part or subset is encoded into one of the m parallel polar codes. Some information bits within one part or subset of the m parts or subsets may be repeated within another part or subset of the m parts or subsets. Generally, p and m can be chosen such that this partitioning produces the same number of information bits to be encoded in each parallel polar code. Alternatively, p information bits can be padded to achieve this bit partitioning.

[0103] In step 620, the p / m information bits in each polar code are divided (separated or processed separately) into a protection information portion and a full-rate information portion. This division allows the information bits in the protection information portion to be transmitted using a non-ideal polarized bit channel, while the information bits in the full-rate information portion can be transmitted using an ideal polarized bit channel (e.g., a bit channel capacity in the range of 0.9 to 1).

[0104] In some embodiments, for each of the m parallel polar codes, the positions in the non-ideal polarized bit channel are grouped into L blocks, wherein each of the L blocks includes a subset of information bits within a guard information portion.

[0105] In some embodiments, the total number of blocks in the non-ideal polarized bit channel of each of the m parallel polarized codes is determined based on the total number of factors of m greater than 1.

[0106] In step 630, the information bits within the protection information portion of each of the m parallel polar codes are protected. To achieve this, in some implementations, the above combination can be used. Figure 5 The discussion may involve duplicate codes, but other protection schemes can also be used.

[0107] In some embodiments, the information bits in one block of the L blocks of the first parallel polar code of m parallel polar codes are repeated in one block of the L blocks of the second parallel polar code of m parallel polar codes.

[0108] In some embodiments, the information bits in one block of one of the L blocks in the first parallel polar code of m parallel polar codes are repeated d times in the m parallel polar codes. i Next, among which, d i It is a factor of m and is greater than 1.

[0109] In some embodiments, the information bits within the protection information portion of each of the m parallel polar codes are protected using BCH codes.

[0110] In some embodiments, the information bits in one block of the L blocks of the first parallel polar code among m parallel polar codes can be protected using two or more protection schemes such as repetition codes, BCH codes, and / or Reed-Muller codes.

[0111] In some embodiments, the parallel polar codes among the m parallel polar codes can be protected using a first protection scheme (e.g., a repetition code), while the other parallel polar code among the m parallel polar codes can be protected using a second protection scheme (e.g., a BCH code or a Reed-Muller code).

[0112] In step 640, the frozen bits are set in each of the m parallel polar codes. Here, "set" refers to the location or position of the bit within the parallel polar code. For example, one or more frozen bits can be added to each of the m parallel polar codes, where each frozen bit occupies an ideal polar bit channel with a bit capacity close to 0. Although for ease of illustration... Figure 5 The diagram shows that frozen bits 503 are located at the beginning of each of the m polar codes, i.e., before information bits 505 and 506. However, they can actually be distributed among information bits 505 and 506 in each polar code. Typically, these frozen bits can have the same constant value of "0" or "1", and both the encoder and decoder know this value. It should be understood that in some implementations, other patterns of frozen bits can be used, provided that both the encoder and decoder know the value of each frozen bit. With frozen bits, each parallel polar code should have a predetermined size, i.e., a power of 2 (i.e., the size of the polar code N = 2). n (where n is an integer).

[0113] In step 650, a conventional polar coding method is applied to each parallel polar code to generate coded codewords for each parallel polar code. These codewords can then be transmitted via channels such as wireless channels, cables, or optical fibers. The polar coding method can be a combination of the above. Figure 1The described coding method is the coding method described by E. Arikan in “Channel Polarization: A method for Constructing Capacity Achieving Codes for Symmetric Binary-Input Memoryless Channels”, Volume 55, Issue 7, July 2009, or any other known method or algorithm for polarization coding.

[0114] Use combination Figure 6 The encoder described above is for m×l protected +l unprotected Encode ) information bits, where l protected It is the number of bits in the protection information portion of each parallel polar code, l unprotected It is the number of bits in the full-rate information portion of each parallel polar code, where m is the number of parallel polar codes, and there are a total of m×l. protected +l unprotected +l frozen ) coded bits, where l frozen It is the number of frozen bits in each parallel polar code.

[0115] Figure 7 This is a flowchart of a decoding method 700 provided by various implementations of the disclosed technology. Typically, decoding is performed on codewords received through a noisy channel, with the aim of correctly decoding the originally encoded and transmitted information from the received codewords. Therefore, in step 770, the decoder receives m parallel polarized codewords 760 to be decoded. The codewords 760 are received through channels such as wireless channels, cables, or optical fibers. Noise or interference may exist on the channel, meaning that some bits in the received codewords 760 may be altered during transmission and therefore may be inconsistent with the bits in the codewords transmitted through the channel. Therefore, the decoder should be able to detect and (for FEC) correct these errors.

[0116] According to one implementation of the disclosed technology, the decoding method is designed with low complexity and achieves low-power decoding through an SC or SCL decoder. Method 700 can be implemented using parallel and independent decoding of several codewords before reaching the leaf node.

[0117] Method 700 is performed by an SC or SCL decoder on each of the m polar-coded codewords 760, each codeword comprising multiple coded bits. The coded bits may be frozen bits or a portion of a message encoded based on a part or subset of p information bits, as described above. Figure 6 The above describes the traditional SC decoding method. For a polar code of length N = 2n, the decoding method can be represented as a full binary tree Tn of depth n. In step 710, nodes in the binary tree Tn, which can be bits, are examined to determine whether the node is part of a set of leaf nodes, which are all frozen bits (“frozen nodes”). When a node belongs to this set of frozen nodes, it indicates that the encoded bits in the corresponding codeword are frozen bits. In step 720, decoded bits are generated in the decoding message 780 according to a predetermined value, where the predetermined value can be 1 or 0.

[0118] When a node does not belong to any set of frozen leaf nodes, in step 730, the decoder checks whether the node is within the protection information section. When the node is within the full-rate information section, in step 740, the decoder (which can be an SC or SCL decoder) can decode the node using the LLR decoding algorithm to generate the first part of the decoded message 780. For example, the SC decoder is described in the following literature: "Channel Polarization: A method for Constructing Capacity Achieving Codes for Symmetric Binary-Input Memoryless Channels" by E. Arikan, Vol. 55, No. 7, pp. 3051-3073, published in the IEEE Transactions on Information Theory (July 2009). For example, the SCL decoder is described in the following literature: “List Decoding of Polar Codes” by I. Tal and A. Vardy, published in the May 2015 issue of IEEE Transactions on Information Theory, Volume 61, Issue 5, pp. 2213-2226.

[0119] When the node is within the protected information section, in step 750, the decoder (which may be an SC or SCL decoder) can decode the node using an average LLR decoding algorithm to generate another part of the decoded message 780. In some embodiments, in step 750, the following average LLR is used to decode the node. Decode the nodes with repeating codes of length di in each information block:

[0120]

[0121] in, di is the total number of times a node is repeated in m polar-coded codewords. It is the LLR of the node in the corresponding codeword j among m polar-coded codewords, j = 1...m. Here, "*" represents the mathematical operation of multiplication.

[0122] In some embodiments, in step 750, different decoding algorithms, such as BCH codes or Reed-Muller codes, can be used for... The nodes in each information block that are protected by a repeating code of length di are decoded.

[0123] Decoding method 700 can perform parallel decoding on m parallel polar codewords.

[0124] Figure 8 This is a schematic diagram 800 showing the simulation results of a parallel polar coding method (“the method proposed in this disclosure”, curve 806) relative to the original polar code (“the original polar code”, curve 808), provided by one implementation of the aforementioned disclosed technology. The original polar code can be described in E. Arikan’s “Channel Polarization: A method for Constructing Capacity Achieving Codes for Symmetric Binary-Input Memoryless Channels”, Vol. 55, No. 7, pp. 3051-3073, published in the IEEE Transactions on Information Theory (July 2009). For the simulation, the polar code length N is 32768 bits, with an overhead of 67%. The horizontal axis shows the bit error rate (BER) without any coding. The vertical axis shows the BER with some coding.

[0125] As can be seen, the method curve 806 proposed in this disclosure is an improvement of approximately 0.25 dB compared to the original polar code curve 808. Those skilled in the art should understand that this indicates a significant improvement in the performance of the forward error correction code.

[0126] It should be understood that although the embodiments presented herein have been described with reference to specific features and structures, various modifications and combinations can be made without departing from these disclosures. Therefore, the specification and drawings are to be regarded merely as illustrative of the implementations or embodiments of the arguments and their principles as defined in the appended claims, and are intended to cover any and all modifications, variations, combinations, or equivalents falling within the scope of this disclosure.

Claims

1. A method for encoding information bits for transmission over a communication channel, characterized in that, The method comprises: allocating the information bits among m parallel polar codes such that each of the m parallel polar codes includes a subset of the information bits, where m is the number of parallel polar codes; partitioning the subset of information bits in each of the m parallel polar codes into a protected information portion and a full-rate information portion; protecting the information bits within the protected information portion in each of the m parallel polar codes; setting a plurality of frozen bits in each of the m parallel polar codes; generating a polar coded codeword for each of the m parallel polar codes; the information bits within the protected information portion in each of the m parallel polar codes are arranged at positions in a non-ideal polar bit channel in the respective one of the m parallel polar codes; for each of the m parallel polar codes, the information bits within the protected information portion are grouped into a plurality of L blocks, where each of the L blocks includes a subset of the information bits within the protected information portion, where L is the number of blocks.

2. The method of claim 1, wherein, the information bits within the protected information portion in each of the m parallel polar codes are protected using a repetition code.

3. The method of claim 2, wherein, the information bits in one of the L blocks in a first one of the m parallel polar codes are repeated in one of the L blocks in a second one of the m parallel polar codes.

4. The method of claim 3, wherein, information bits in one of the L blocks in a first one of the m parallel polar codes are repeated in the m parallel polar codes wherein is a factor of m and greater than 1.

5. The method according to any one of claims 1 to 4, characterized in that, a total number of blocks in the non-ideal polar bit channel in each of the m parallel polar codes is determined according to a total number of greater than one factors of m.

6. A method for decoding m polar coded codewords received over a communication channel, characterized in that, each of the m polar coded codewords is encoded from information bits in a plurality of nodes, the method comprising: receiving the polar coded codewords, where the polar coded codewords contain information bits and frozen bits encoded by m parallel polar codes, where m is the number of parallel polar codes; the information bits in each of the m parallel polar codes are partitioned into a protected information portion and a full-rate information portion, the information bits within the protected information portion are arranged at positions in a non-ideal polar bit channel in the respective one of the m parallel polar codes, the information bits within the protected information portion are grouped into a plurality of L blocks, where L is the number of blocks; for each node in each of the m polar coded codewords: when the node is within the full-rate information portion, decoding the node according to a log-likelihood ratio (LLR) decoding algorithm to generate a first portion of a decoded message; when the node is within the protected information portion, decoding the node according to an average-LLR decoding algorithm to generate a second portion of the decoded message.

7. The method of claim 6, wherein, The method further comprises, for each of the m polar coded codewords, when a bit in the respective codeword is a frozen bit, generating a decoded bit in the decoded message according to a predetermined value.

8. The method of claim 6, wherein, The decoding the nodes is performed by successive cancellation (SC) or successive cancellation list (SCL).

9. The method according to any one of claims 6 to 8, characterized in that, The average LLR decoding algorithm is based on: wherein, di is the total number of repetitions of the node in the m polar coded codewords, is the LLR of the node in the respective codeword j of the m polar coded codewords, j = 1...m, where ” denotes a multiplication mathematical operation.

10. An encoder that encodes information bits for transmission over a communication channel, characterized by, The encoder comprises circuitry for: allocating the information bits among m parallel polar codes such that each of the m parallel polar codes comprises a subset of the information bits, where m is the number of parallel polar codes; partitioning the subset of information bits in each of the m parallel polar codes into a protected information portion and a full-rate information portion; protecting the information bits within the protected information portion in each of the m parallel polar codes; setting a plurality of frozen bits in each of the m parallel polar codes; generating a polar coded codeword for each of the m parallel polar codes; the information bits within the protected information portion in each of the m parallel polar codes are arranged at positions in a non-ideal polar bit channel in the respective one of the m parallel polar codes; for each of the m parallel polar codes, the information bits within the protected information portion are grouped into a plurality of L blocks, where each of the L blocks comprises a subset of the information bits within the protected information portion, where L is the number of blocks.

11. The encoder of claim 10, wherein, The circuitry comprises at least one processor and a memory storing programming instructions, wherein the programming instructions, when executed by the at least one processor, cause the at least one processor to encode the information bits.

12. The encoder of claim 10, wherein, The information bits within the protected information portion in each of the m parallel polar codes are protected using a repetition code.

13. The encoder of claim 12, wherein, The information bits in one of the L blocks in a first one of the m parallel polar codes are repeated in one of the L blocks in a second one of the m parallel polar codes.

14. The encoder of claim 13, wherein, information bits in one of the L blocks in a first one of the m parallel polar codes are repeated in the m parallel polar codes wherein, is a factor of m and greater than 1.

15. A decoder for decoding m polar-coded codewords received through a communication channel, characterized in that, The decoder comprises circuitry for: receiving the polar coded codewords, wherein the polar coded codewords contain information bits and frozen bits encoded by m parallel polar codes, m being the number of parallel polar codes; the information bits in each of the m parallel polar codes are partitioned into a protected information portion and a full-rate information portion, the information bits within the protected information portion are arranged at positions in a non-ideal polar bit channel in the respective one of the m parallel polar codes, the information bits within the protected information portion are grouped into a plurality of L blocks, where L is the number of blocks; for each node in each of the m polar coded codewords: when the node is within the full-rate information portion, decoding the node according to a log-likelihood ratio (LLR) decoding algorithm to generate a first portion of a decoded message; when the node is within the protected information portion, decoding the node according to an average LLR decoding algorithm to generate a second portion of the decoded message; when a bit in the respective codeword is a frozen bit, generating a decoded bit in the decoded message according to a predetermined value.

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