Frame rate control method and apparatus, electronic device, and storage medium

Abstract

The application discloses a frame rate control method and device, electronic equipment and a storage medium, and belongs to the technical field of electronics. The method comprises the following steps: in the process of displaying by using a first frame rate, determining a target offset based on the window length of a data processing window corresponding to a second frame rate, the second frame rate being greater than the first frame rate; offsetting the data processing window corresponding to the first frame rate based on the target offset to obtain a first data processing window; and processing first data in the first data processing window, the first data being display data in the process of displaying by using the first frame rate.

Description

Technical Field

[0001] This application belongs to the field of electronic technology, specifically relating to a frame rate control method, device, electronic device, and storage medium. Background Technology

[0002] Currently, electronic devices can change the refresh rate of the screen to achieve frame rate switching, thereby altering the refresh speed of the content displayed on the screen. In related technologies, electronic devices can perform frame rate switching by sending commands to the screen driver, including the refresh rate to be updated, along with the corresponding configuration parameters and timing.

[0003] However, because the above commands contain a lot of information, the delay in sending commands from the electronic device to the screen driver is relatively large, which causes users to feel obvious stuttering during frame rate changes. As a result, the smoothness of the electronic device's frame rate change process is poor. Summary of the Invention

[0004] The purpose of this application is to provide a frame rate control method, apparatus, electronic device, and storage medium that can improve the smoothness of frame rate switching processes in electronic devices.

[0005] In a first aspect, embodiments of this application provide a frame rate control method, which includes: during the display process using a first frame rate, determining a target offset based on the window length of a data processing window corresponding to a second frame rate, wherein the second frame rate is greater than the first frame rate; offsetting the data processing window corresponding to the first frame rate based on the target offset to obtain a first data processing window; and processing first data within the first data processing window, wherein the first data is display data during the display process using the first frame rate.

[0006] Secondly, embodiments of this application provide a frame rate control device, which includes a determining module, an offset module, and a processing module. The determining module is used to determine a target offset based on the window length of a data processing window corresponding to a second frame rate during display at a first frame rate, wherein the second frame rate is greater than the first frame rate. The offset module is used to offset the data processing window corresponding to the first frame rate based on the target offset determined by the determining module, thereby obtaining a first data processing window. The processing module is used to process first data within the first data processing window obtained by the offset module, wherein the first data is the display data during the display process at the first frame rate.

[0007] Thirdly, embodiments of this application provide an electronic device including a processor and a memory, wherein the memory stores programs or instructions executable on the processor, and the programs or instructions, when executed by the processor, implement the steps of the method described in the first aspect.

[0008] Fourthly, embodiments of this application provide a readable storage medium on which a program or instructions are stored, which, when executed by a processor, implement the steps of the method described in the first aspect.

[0009] Fifthly, embodiments of this application provide a chip, the chip including a processor and a communication interface, the communication interface being coupled to the processor, the processor being used to run programs or instructions to implement the method as described in the first aspect.

[0010] In a sixth aspect, embodiments of this application provide a computer program product stored in a storage medium, which is executed by at least one processor to implement the method described in the first aspect.

[0011] In this embodiment, during display at a first frame rate, the electronic device can determine a target offset based on the window length of the data processing window corresponding to a second frame rate, where the second frame rate is greater than the first frame rate. Based on this target offset, the data processing window corresponding to the first frame rate is offset to obtain a first data processing window. Within this first data processing window, first data is processed; this first data is the display data generated during the display process at the first frame rate. In this solution, since the target offset is determined by the window length of the data processing window corresponding to the second frame rate, the window length of the first data processing window obtained by the electronic device based on this target offset can be approximately the same as the window length of the data processing window corresponding to the second frame rate. This allows the rendering and compositing timings corresponding to the first and second frame rates to be aligned. Thus, when the electronic device switches from the first to the second frame rate, the data processing window corresponding to the second frame rate can seamlessly connect to the first data processing window, thereby improving the smoothness of the electronic device during frame rate changes. Attached Figure Description

[0012] Figure 1 This is a model example diagram of a vertical synchronizing signal (vsync) in a related technology;

[0013] Figure 2 This is one of the timing diagrams of the vsync model in a related technology;

[0014] Figure 3 This is the second timing diagram of the vsync model in a related technology;

[0015] Figure 4 This is one of the flowcharts of a frame rate control method provided in the embodiments of this application;

[0016] Figure 5 This is a second flowchart of a frame rate control method provided in an embodiment of this application;

[0017] Figure 6 This is one of the timing diagrams of a vsync model provided in the embodiments of this application;

[0018] Figure 7 This is a second timing diagram of a vsync model provided in an embodiment of this application;

[0019] Figure 8 This is a schematic diagram of the structure of a frame rate control device provided in an embodiment of this application;

[0020] Figure 9 This is one of the hardware structure diagrams of an electronic device provided in the embodiments of this application;

[0021] Figure 10 This is a second schematic diagram of the hardware structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0022] The technical solutions of the embodiments of this application will be clearly described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application are within the scope of protection of this application.

[0023] The terms "first," "second," etc., used in the specification and claims of this application are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such terms can be used interchangeably where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class and the number of objects is not limited; for example, a first object can be one or more. Furthermore, in the specification and claims, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0024] The terms "at least one," "at least one of," etc., used in the specification and claims of this application refer to any one, any two, or a combination of two or more of the included items. For example, at least one of a, b, and c can mean: "a," "b," "c," "a and b," "a and c," "b and c," and "a, b, and c," where a, b, and c can be single or multiple. Similarly, "at least two" refers to two or more items, and its meaning is similar to that of "at least one."

[0025] The frame rate control method, apparatus, electronic device, and storage medium method provided in this application will be described in detail below with reference to the accompanying drawings and through specific embodiments and application scenarios.

[0026] The frame rate control method, apparatus, electronic device, and storage medium provided in this application can be applied in screen refresh scenarios.

[0027] With the development of electronic devices, most electronic devices now use Organic Light Emitting Display (OLED) screens. These OLED screens can support switching between different screen refresh rates. For example, an electronic device can switch the screen refresh rate from 60Hz to 120Hz, or vice versa. Understandably, the higher the refresh rate, the smoother the content displayed on the screen.

[0028] In related technologies, when an electronic device performs frame rate switching, the frame rate switching can be initiated by the system, which then calls the display driver on the screen. After processing the relevant procedures, the display driver sends a corresponding command code containing the frame rate to be switched to at the next moment, as well as the parameter configuration and timing related to the frame rate. Then, the electronic device can transmit the code to the display driver integrated circuit (DDIC) on the screen through a serial interface (Mobile Industry Processor Interface - Display Serial Interface, MIPI-DSI). After receiving the code, the DDIC can change the relevant parameter configuration and timing of the frame rate at the next moment to achieve the purpose of frame rate switching.

[0029] Generally, the DDIC in the screen of an electronic device can send a hardware vertical synchronization signal (HW-vsync) to the Data Processing Unit (DPU) and Graphics Processing Unit (GPU) within the device. This HW-vsync is used to synchronize the refresh rate and frame rate. The electronic device can then display data at different frame rates using the vsync model. For example, after receiving the HW-vsync, the DPU can sample and calculate it using the SurfaceFlinger service to obtain Vsync-app and Vsync-sf. Vsync-app indicates the timing of data composition for the screen, while Vsync-sf indicates the timing of rendering the composed data. The GPU can then render the composed data, and the DPU can compose the data—that is, the display data after changing the frame rate—and send it to the screen for display.

[0030] It's important to note that refresh rate and frame rate work together to display the content of applications on an electronic device on the screen. Specifically, the GPU acquires image data, renders it, and then presents the rendered image data on the screen. The refresh rate refers to the number of times the electron beam scans the image on the screen. In other words, the higher the refresh rate, the more stable the image displayed on the screen of an electronic device. The frame rate, on the other hand, is the frequency (rate) at which bitmap images, measured in frames, appear continuously on the display.

[0031] For example, Figure 1 A typical vsync model architecture diagram is shown, such as... Figure 1 As shown, this vsync model includes a Vsync-app layer, a Vsync-sf layer, and an HW-vsync layer. The Vsync-app layer is used to render data, the Vsync-sf layer is used to synthesize data, and the HW-vsync layer is used to transmit the processed data to the display panel for display.

[0032] For example, taking a frame of data displayed on the screen of an electronic device as an example, assuming that the frame of data contains image data of the status bar, image data of the navigation bar, and image data of the settings application, the electronic device can render the image data of the status bar, image data of the navigation bar, and image data of the settings application through the Vsync-app layer, and then send all the rendered image data to the Vsync-sf layer. Then, through the SurfaceFlinger service in the Vsync-sf layer, all the image data are sent to the DPU or GPU for data synthesis to obtain a frame of image data. Then, the frame of image data is sent to the HW-vsync layer. When the HW-vsync in the HW-vsync layer is triggered, the frame of image data is sent to the panel for display.

[0033] For example, in conjunction with the above Figure 1 , Figure 2 A vsync timing diagram for a vsync model is shown. For example... Figure 2 As shown, without considering phase offset, it is assumed that the Vsync-app layer of the vsync model contains a data processing window corresponding to Frame1 and a data processing window corresponding to Frame2, and the frame rate corresponding to Frame1 and the frame rate corresponding to Frame2 are the same.

[0034] Example 1: For Frame1, such as Figure 2 As shown, in the Vsync-app layer, the electronic device can render the image data within the data processing window corresponding to Frame1. After rendering, in the Vsync-sf layer, the electronic device can merge the image data corresponding to Frame1 after the data processing window of Frame1 in the Vsync-app layer. After compositing, in the HW-Vsync layer, the electronic device can display the image data corresponding to Frame1 after the data processing window of the Vsync-sf layer. Thus, it can be seen that under this offset state, one frame of layer data needs to be completed through three vsync timing sequences. One timing sequence corresponds to one level in the vsync model, and each timing sequence in different layers of the vsync model is shifted backward by the length occupied by one data processing window.

[0035] Example 2: For Frame 2 or subsequent Frame N, such as Figure 2 As shown, the processing timing can also be displayed sequentially according to the timing diagram. However, if a frame change occurs after Frame2, such as... Figure 3As shown, for example, if Frame1 and Frame2 are currently at 60Hz, and Frame3 needs to switch to 120Hz, then based on the above... Figure 1 In the vsync model shown, due to the longer window length of the data processing window corresponding to Frame2, a delay occurs between 60Hz and 120Hz. As a result, in the Vsync-sf layer, the data processing window corresponding to Frame3 cannot be connected after Frame3 in the Vsync-app layer. Similarly, the data processing window corresponding to Frame3 cannot be connected after Frame3 in the HW-Vsync layer. Moreover, since the code contains a lot of information, the above-mentioned delay will be further increased. Thus, the smoothness of the frame rate change process of the electronic device is poor.

[0036] In the frame rate control method, apparatus, electronic device, and storage medium provided in this application, since the target offset is determined by the window length of the data processing window corresponding to the second frame rate, the window length of the first data processing window obtained by the electronic device based on the target offset can be approximately the window length of the data processing window of the second frame rate. This allows the rendering timing and compositing timing corresponding to the first frame rate to be aligned with the rendering timing and compositing timing corresponding to the second frame rate. Thus, when the electronic device switches from the first frame rate to the second frame rate, the data processing window corresponding to the second frame rate can be seamlessly connected to the first data processing window, thereby improving the smoothness of the electronic device during frame rate changes.

[0037] The frame rate control method provided in this application can be executed by a frame rate control device, which can be an electronic device or a functional module within an electronic device. The following description uses an electronic device as an example to illustrate the technical solution provided in this application.

[0038] This application provides a frame rate control method. Figure 4 A flowchart of a frame rate control method provided in an embodiment of this application is shown. Figure 4 As shown, the frame rate control method provided in this application embodiment may include the following steps 201 to 203.

[0039] Step 201: During the display process using the first frame rate, the electronic device determines the target offset based on the window length of the data processing window corresponding to the second frame rate.

[0040] In this embodiment of the application, the second frame rate is greater than the first frame rate.

[0041] In this embodiment of the application, during the display process using the first frame rate, the electronic device can set a fixed target offset for the window length of the data processing window corresponding to the first frame rate according to the window length of the data processing window corresponding to the second frame rate. As a result, the rendering timing and compositing timing of the data processing corresponding to the first frame rate can be aligned with the rendering timing and compositing timing of the data processing corresponding to the second frame rate, and thus the data processing window corresponding to the first frame rate can be seamlessly connected with the data processing window corresponding to the second frame rate.

[0042] It should be noted that, in the process of displaying using the first frame rate, it can be understood that the use of the first frame rate in this scheme is before the use of the second frame rate.

[0043] For example, suppose the current content displayed on the screen of an electronic device is news information, and the frame rate of the displayed content can be 60Hz.

[0044] In the embodiments of the application, the aforementioned second frame rate may be determined by the electronic device; or, it may be selected by the user.

[0045] In the application embodiment, the data processing window corresponding to the second frame rate refers to the processing window through which the electronic device processes the image data corresponding to the second frame rate.

[0046] For example, assuming a frame rate of 60Hz, the window length of the data processing window corresponding to this frame rate is: the processing window required by the electronic device to process one frame of image data at 60Hz.

[0047] Optionally, in this embodiment of the application, the electronic device can obtain the second frame rate and the window length of the data processing window corresponding to the second frame rate based on the first correspondence relationship. That is, the electronic device can obtain the window length of the data processing window corresponding to the second frame rate by knowing the second frame rate.

[0048] For example, the aforementioned first correspondence can be preset by the electronic device.

[0049] For example, if the second frame rate is 120Hz, then the window length of the data processing window corresponding to 120Hz is 8.3ms. In other words, after obtaining the second frame rate, the electronic device can directly obtain the window length of the data processing window corresponding to the second frame rate.

[0050] Optionally, in this embodiment of the application, the electronic device may pre-store multiple correspondences, and then determine the window length of the data processing window corresponding to different frame rates based on these multiple correspondences.

[0051] For example, the above multiple correspondences include multiple correspondences for different frame rates, with one frame rate corresponding to one correspondence. The correspondence for any frame rate includes the mapping relationship between that frame rate and the window length of a data processing window.

[0052] For example, the above-mentioned multiple correspondences can be set according to actual needs or industry standards, and this application does not limit them.

[0053] Optionally, in this embodiment of the application, the target offset may be the same as the window length of the data processing window corresponding to the second frame rate, or the target offset may be different from the window length of the data processing window corresponding to the second frame rate.

[0054] Optionally, in the embodiments of this application, combined with Figure 4 ,like Figure 5 As shown, step 201 above can be specifically implemented through step 201a below.

[0055] Step 201a: The electronic device uses the window length of the data processing window corresponding to the second frame rate as the target offset.

[0056] In this embodiment of the application, after determining the second frame rate, the electronic device can obtain the window length of the data processing window corresponding to the second frame rate according to the first correspondence mentioned above, and then use the window length of the data processing window corresponding to the second frame rate as the target offset.

[0057] In this embodiment, the electronic device uses the window length of the data processing window corresponding to the second frame rate as the target offset, so that the window length of the data processing window corresponding to the first frame rate after offset can be consistent with the window length of the data processing window corresponding to the second frame rate. This makes the rendering timing and compositing timing corresponding to the first frame rate consistent with the rendering timing and compositing timing corresponding to the second frame rate. In this way, the electronic device can avoid large delays in frame rate switching due to inconsistent rendering timing or compositing timing when switching from the first frame rate to the second frame rate.

[0058] Step 202: Based on the above target offset, the electronic device offsets the data processing window corresponding to the first frame rate to obtain the first data processing window.

[0059] In this embodiment of the application, after obtaining the target offset, the electronic device can shift the data processing window corresponding to the first frame rate forward by the length corresponding to the target offset, and then obtain the first data processing window.

[0060] In one example, the electronic device can shift the data processing window corresponding to the first frame rate forward by the target offset length based on the target offset, thereby obtaining the first data processing window. That is, the electronic device can change the starting position of the data processing window corresponding to the first frame rate in the timing without changing the window length of the data processing window corresponding to the first frame rate.

[0061] For example, assuming the position of the data processing window corresponding to the first frame rate is 0 and the target offset is 8.3ms, the electronic device can offset the position of the data processing window corresponding to the first frame rate to -8.3ms.

[0062] In one example, the electronic device can compress the window length of the data processing window corresponding to the first frame rate to the length corresponding to the target offset based on the target offset, thereby obtaining the first data processing window. That is, the electronic device can update the window length of the data processing window corresponding to the first frame rate without changing the starting position of the data processing window in the timing.

[0063] For example, assuming the window length of the data processing window corresponding to the first frame rate is 16.67ms and the target offset is 8.3ms, the electronic device can compress the window length of the data processing window corresponding to the first frame rate, i.e., 16.67ms - 8.3ms, to obtain the compressed first data processing window, i.e., the window length of the compressed first data processing window is 8.37ms.

[0064] Optionally, in the embodiments of this application, step 202 above can be specifically implemented by step 202a below.

[0065] Step 202a: The electronic device compresses the data processing window corresponding to the first frame rate according to the above target offset and the parameters corresponding to the first frame rate to obtain the first data processing window.

[0066] In this embodiment of the application, the parameters corresponding to the first frame rate mentioned above include:

[0067] Vertical synchronization signal rendering parameters, vertical synchronization signal synthesis parameters, hardware vertical synchronization signal;

[0068] The vertical synchronization signal rendering parameter is used to indicate the timing of rendering the display data during the process of displaying at the first frame rate;

[0069] The vertical synchronization signal synthesis parameter is used to indicate the timing of data synthesis during the display process using the first frame rate;

[0070] The hardware vertical synchronization signal is used to indicate the timing of display data during the process of displaying at the first frame rate.

[0071] In this embodiment of the application, for the vertical synchronization signal rendering parameters, the electronic device can offset the rendering timing of the display data during the process of displaying the electronic device using the first frame rate based on the target offset, so that the rendering timing corresponding to the vertical synchronization signal rendering parameters can be consistent with the rendering timing corresponding to the second frame rate.

[0072] In this embodiment of the application, for the vertical synchronization signal synthesis parameters, the electronic device can, based on the target offset, determine the synthesis timing of the display data during the process of displaying the electronic device using the first frame rate, so that the synthesis timing corresponding to the vertical synchronization signal synthesis parameters can be consistent with the synthesis timing corresponding to the second frame rate.

[0073] In this embodiment of the application, for the hardware vertical synchronization signal, the electronic device can determine the display timing of the display data during the process of displaying the electronic device using the first frame rate based on the target offset, so that the display timing corresponding to the hardware vertical synchronization signal can be consistent with the display timing corresponding to the second frame rate.

[0074] In this embodiment of the application, the above-mentioned vertical synchronization signal rendering parameters can be the parameters corresponding to Vsync-app, the above-mentioned vertical synchronization signal synthesis parameters can be the parameters corresponding to Vsync-sf, and the above-mentioned hardware vertical synchronization signal can be the parameters corresponding to HW-vsync.

[0075] It can be understood that Vsync-app, Vsync-sf, and HW-vsync are different levels in the Vsync model, each representing a data processing timing. For the Vsync-app level, assuming it includes two data processing windows corresponding to the first frame rate, the electronic device can compress these two data processing windows to obtain the first data processing windows corresponding to the two first frame rates. Similarly, the Vsync-sf and HW-vsync levels can obtain the first data processing windows corresponding to the first frame rate at different levels using the same method.

[0076] For example, for the Vsync-app layer, after determining the target offset, the electronic device can subtract the target offset from the window length of the data processing window corresponding to the first frame rate to obtain the first data processing window, that is, the data processing window corresponding to the first frame rate is compressed as described above to obtain the first data processing window. In this way, the window length of the first data processing window obtained by the electronic device at different levels can be consistent with the window length of the data processing window corresponding to the second frame rate at different levels.

[0077] For example, such as Figure 6As shown, the electronic device can set a fixed target offset of 8.3ms for the Vsync-app layer, Vsync-sf layer, and HW-vsync layer in the Vsync model. Then, for each layer, the electronic device can subtract 8.3ms from the 16.67ms data processing time corresponding to 60Hz to obtain the updated data processing time, which is the first data processing window mentioned above. In this way, the electronic device can align the actual rendering of Vsync-app and the compositing timing of Vsync-sf at 60Hz to 120Hz, thereby ensuring a seamless transition between 60Hz and 120Hz.

[0078] In this way, electronic devices can adjust the rendering timing, compositing timing, and display timing by offsetting them, so that the data processing window corresponding to the first frame rate and the data processing window corresponding to the second frame rate can be seamlessly connected.

[0079] Optionally, in this embodiment of the application, after step 202 above, the frame rate control method provided in this embodiment of the application further includes step 301 as follows.

[0080] Step 301: The electronic device retains blank data processing windows other than the first data processing window in the data processing window corresponding to the first frame rate.

[0081] In other words, the first data processing window mentioned above is adjacent to the blank data processing window.

[0082] In this embodiment of the application, after the electronic device compresses the data processing window corresponding to the first frame rate, the electronic device can retain the data processing windows other than the first data processing window in the data processing window corresponding to the first frame rate. This ensures that the timing of the data processing windows corresponding to the same frame rate will not shift forward when the frame remains unchanged, and thus the timing of the first frame rate will not be disordered.

[0083] Step 203: Within the aforementioned first data processing window, the electronic device processes the first data.

[0084] In this embodiment of the application, the first data mentioned above is the display data during the display process using the first frame rate.

[0085] For example, assuming the window length of the data processing window corresponding to the first frame rate is 16.67ms, then the window length of the first data processing window is 8.37ms, i.e., 16.67ms - 8.3ms. In other words, the electronic device compresses the data processing window corresponding to the first frame rate, so that the window length of the data processing window for the first frame rate is approximately the same as the window length of the data processing window corresponding to the second frame rate. That is, the electronic device can perform data processing at the first frame rate using the window length of the data processing window corresponding to the second frame rate.

[0086] In the frame rate control method provided in this application embodiment, during the display process using a first frame rate, the electronic device can determine a target offset based on the window length of the data processing window corresponding to a second frame rate, where the second frame rate is greater than the first frame rate; and based on the target offset, offset the data processing window corresponding to the first frame rate to obtain a first data processing window; thereby, within the first data processing window, first data is processed, which is the display data during the display process using the first frame rate. In this solution, since the target offset is determined by the window length of the data processing window corresponding to the second frame rate, the window length of the first data processing window obtained by the electronic device based on the target offset can be approximately the window length of the data processing window of the second frame rate, so that the rendering timing and compositing timing corresponding to the first frame rate can be aligned with the rendering timing and compositing timing corresponding to the second frame rate. Thus, when the electronic device switches from the first frame rate to the second frame rate, the data processing window corresponding to the second frame rate can be seamlessly connected to the first data processing window, thereby improving the smoothness of the electronic device during frame rate changes.

[0087] Optionally, in this embodiment of the application, after step 202 above, the frame rate control method provided in this embodiment of the application further includes the following step 401.

[0088] Step 401: The electronic device offsets the data processing window corresponding to the second frame rate based on the above target offset.

[0089] In this embodiment of the application, the data processing window corresponding to the second frame rate after the offset is adjacent to the first data processing window.

[0090] It is understandable that, since the electronic device retains the blank data processing window other than the first data processing window in the data processing window corresponding to the first frame rate, the electronic device can shift the position of the data processing window corresponding to the second frame rate forward as a whole, so that the data processing window corresponding to the second frame rate can be adjacent to the first data processing window.

[0091] For example, combined Figure 6 ,like Figure 7 As shown, in the above vsync model, the electronic device can shift the position of the data processing window corresponding to 120Hz in the Vsync-app layer, Vsync-sf layer and HW-vsync layer forward by 8.3ms, so that the data processing window corresponding to 120Hz in each layer can be adjacent to the first data processing window corresponding to 60Hz.

[0092] In this embodiment, since the electronic device shifts the position of the data processing window corresponding to the second frame rate forward by the length corresponding to the target offset, the timing of the second frame rate being displayed on the screen can be advanced after the electronic device switches from the first frame rate to the second frame rate, so that the display data corresponding to the second frame rate can be displayed on the screen faster.

[0093] It can be understood that the above-mentioned screen display timing refers to the timing when the electronic device displays image data at the second frame rate.

[0094] It should be noted that the frame rate control method provided in this application can be executed by a frame rate control device, an electronic device, or a functional module or entity within an electronic device. This application uses the execution of the frame rate control method by a frame rate control device as an example to illustrate the frame rate control device provided in this application.

[0095] Figure 8 A schematic diagram of a possible structure of the frame rate control device involved in an embodiment of this application is shown. For example... Figure 8 As shown, the frame rate control device 70 may include: a determination module 71, an offset module 72, and a processing module 73.

[0096] The determining module 71 is used to determine a target offset based on the window length of the data processing window corresponding to the second frame rate, where the second frame rate is greater than the first frame rate, during the display process using the first frame rate. The offset module 72 is used to offset the data processing window corresponding to the first frame rate based on the target offset determined by the determining module 71, thereby obtaining a first data processing window. The processing module 73 is used to process first data within the first data processing window obtained by the offset module 72, where the first data is the display data generated during the display process using the first frame rate.

[0097] In one possible implementation, the aforementioned determining module 71 is specifically used to take the window length of the data processing window corresponding to the second frame rate as the target offset.

[0098] In one possible implementation, the offset module 73 is specifically used to compress the data processing window corresponding to the first frame rate according to the target offset and the parameters corresponding to the first frame rate to obtain the first data processing window; wherein, the parameters corresponding to the first frame rate include: vertical synchronization signal rendering parameters, vertical synchronization signal synthesis parameters, and hardware vertical synchronization signal; the vertical synchronization signal rendering parameters are used to indicate the rendering timing of display data during the display process using the first frame rate; the vertical synchronization signal synthesis parameters are used to indicate the synthesis timing of display data during the display process using the first frame rate; and the hardware vertical synchronization signal is used to indicate the display timing of display data during the display process using the first frame rate.

[0099] In one possible implementation, the frame rate control device provided in this application embodiment further includes: a retention module; the retention module is used to retain blank data processing windows other than the first data processing window in the data processing window corresponding to the first frame rate after the offset module 72 offsets the data processing window corresponding to the first frame rate based on the target offset amount to obtain the first data processing window.

[0100] In one possible implementation, the offset module 73 is further configured to offset the data processing window corresponding to the first frame rate based on the target offset to obtain the first data processing window, and then offset the data processing window corresponding to the second frame rate based on the target offset, wherein the offset data processing window corresponding to the second frame rate is adjacent to the first data processing window.

[0101] This application provides a frame rate control device. Since the target offset is determined by the window length of the data processing window corresponding to the second frame rate, the window length of the first data processing window obtained by the frame rate control device based on the target offset can be approximately the window length of the data processing window corresponding to the second frame rate. This allows the rendering timing and compositing timing corresponding to the first frame rate to be aligned with the rendering timing and compositing timing corresponding to the second frame rate. Thus, when the frame rate control device switches from the first frame rate to the second frame rate, the data processing window corresponding to the second frame rate can be seamlessly connected to the first data processing window, thereby improving the smoothness of the frame rate control device during frame rate changes.

[0102] The frame rate control device in this application embodiment can be an electronic device or a component within an electronic device, such as an integrated circuit or a chip. The electronic device can be a terminal or other devices besides a terminal. For example, a mobile electronic device can be a mobile phone, tablet computer, laptop computer, PDA, in-vehicle electronic device, mobile internet device (MID), augmented reality (AR) / virtual reality (VR) device, robot, wearable device, ultra-mobile personal computer (UMPC), netbook, or personal digital assistant (PDA), etc. It can also be a server, network attached storage (NAS), personal computer (PC), television set (TV), ATM, or self-service machine, etc. This application embodiment does not specifically limit the device.

[0103] The frame rate control device in this application embodiment can be a device with an operating system. This operating system can be Android, iOS, or other possible operating systems; this application embodiment does not specifically limit the specific operating system used.

[0104] The frame rate control device provided in this application embodiment can implement the various processes implemented in the above method embodiments, and will not be described again here to avoid repetition.

[0105] Optionally, such as Figure 9 As shown, this application embodiment also provides an electronic device 90, including a processor 91 and a memory 92. The memory 92 stores a program or instructions that can run on the processor 91. When the program or instructions are executed by the processor 91, they implement the various steps of the above-described frame rate control method embodiment and can achieve the same technical effect. To avoid repetition, they will not be described again here.

[0106] It should be noted that the electronic devices in the embodiments of this application include the mobile electronic devices and non-mobile electronic devices described above.

[0107] Figure 10 A schematic diagram of the hardware structure of an electronic device to implement an embodiment of this application.

[0108] The electronic device 100 includes, but is not limited to, components such as: radio frequency unit 101, network module 102, audio output unit 103, input unit 104, sensor 105, display unit 106, user input unit 107, interface unit 108, memory 109, and processor 110.

[0109] Those skilled in the art will understand that the electronic device 100 may also include a power supply (such as a battery) for supplying power to various components. The power supply may be logically connected to the processor 110 through a power management system, thereby enabling functions such as managing charging, discharging, and power consumption through the power management system. Figure 10 The electronic device structure shown does not constitute a limitation on the electronic device. The electronic device may include more or fewer components than shown, or combine certain components, or have different component arrangements, which will not be elaborated here.

[0110] The processor 110 is configured to, during the display process using a first frame rate, determine a target offset based on the window length of the data processing window corresponding to a second frame rate, wherein the second frame rate is greater than the first frame rate; and offset the data processing window corresponding to the first frame rate based on the target offset to obtain a first data processing window; and process first data within the first data processing window, wherein the first data is the display data during the display process using the first frame rate.

[0111] This application provides an electronic device in which the target offset is determined by the window length of the data processing window corresponding to the second frame rate. Therefore, the window length of the first data processing window obtained by the electronic device based on the target offset can be approximately the window length of the data processing window corresponding to the second frame rate. This allows the rendering timing and compositing timing corresponding to the first frame rate to be aligned with the rendering timing and compositing timing corresponding to the second frame rate. As a result, when the electronic device switches from the first frame rate to the second frame rate, the data processing window corresponding to the second frame rate can be seamlessly connected to the first data processing window, thereby improving the smoothness of the electronic device during frame rate changes.

[0112] Optionally, in this embodiment of the application, the processor 110 is specifically used to take the window length of the data processing window corresponding to the second frame rate as the target offset.

[0113] Optionally, in this embodiment of the application, the processor 110 is specifically used to compress the data processing window corresponding to the first frame rate according to the target offset and the parameters corresponding to the first frame rate to obtain the first data processing window; wherein, the parameters corresponding to the first frame rate include: vertical synchronization signal rendering parameters, vertical synchronization signal synthesis parameters, and hardware vertical synchronization signal; the vertical synchronization signal rendering parameters are used to indicate the rendering timing of display data during the display process using the first frame rate; the vertical synchronization signal synthesis parameters are used to indicate the synthesis timing of display data during the display process using the first frame rate; and the hardware vertical synchronization signal is used to indicate the display timing of display data during the display process using the first frame rate.

[0114] Optionally, in this embodiment of the application, the processor 110 is further configured to offset the data processing window corresponding to the first frame rate based on the target offset, and after obtaining the first data processing window, retain the blank data processing window other than the first data processing window in the data processing window corresponding to the first frame rate.

[0115] Optionally, in this embodiment of the application, the processor 110 is further configured to offset the data processing window corresponding to the first frame rate based on the target offset to obtain the first data processing window, and then offset the data processing window corresponding to the second frame rate based on the target offset, wherein the offset data processing window corresponding to the second frame rate is adjacent to the first data processing window.

[0116] The electronic device provided in this application embodiment can implement the various processes implemented in the above method embodiments and achieve the same technical effect. To avoid repetition, it will not be described again here.

[0117] The beneficial effects of the various implementation methods in this embodiment can be found in the beneficial effects of the corresponding implementation methods in the above method embodiments. To avoid repetition, they will not be repeated here.

[0118] It should be understood that, in this embodiment, the input unit 104 may include a graphics processing unit (GPU) 1041 and a microphone 1042. The GPU 1041 processes image data of still images or videos obtained by an image capture device (such as a camera) in video capture mode or image capture mode. The display unit 106 may include a display panel 1061, which may be configured in the form of a liquid crystal display, an organic light-emitting diode, or the like. The user input unit 107 includes at least one of a touch panel 1071 and other input devices 1072. The touch panel 1071 is also called a touch screen. The touch panel 1071 may include a touch detection device and a touch controller. Other input devices 1072 may include, but are not limited to, a physical keyboard, function keys (such as volume control buttons, power buttons, etc.), a trackball, a mouse, and a joystick, which will not be described in detail here.

[0119] The memory 109 can be used to store software programs and various data. The memory 109 may primarily include a first storage area for storing programs or instructions and a second storage area for storing data. The first storage area may store the operating system, application programs or instructions required for at least one function (such as sound playback, image playback, etc.). Furthermore, the memory 109 may include volatile memory or non-volatile memory, or both. The non-volatile memory may be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. Volatile memory can be random access memory (RAM), static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDRSDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link dynamic random access memory (SLDRAM), and direct memory bus RAM (DRRAM). The memory 109 in the embodiments of this application includes, but is not limited to, these and any other suitable types of memory.

[0120] Processor 110 may include one or more processing units; optionally, processor 110 integrates an application processor and a modem processor, wherein the application processor mainly handles operations involving the operating system, user interface, and applications, and the modem processor mainly handles wireless communication signals, such as a baseband processor. It is understood that the aforementioned modem processor may also not be integrated into processor 110.

[0121] This application also provides a readable storage medium storing a program or instructions. When the program or instructions are executed by a processor, they implement the various processes of the above method embodiments and achieve the same technical effect. To avoid repetition, they will not be described again here.

[0122] The processor is the processor in the electronic device described in the above embodiments. The readable storage medium includes computer-readable storage media, such as computer read-only memory (ROM), random access memory (RAM), magnetic disk, or optical disk.

[0123] This application embodiment also provides a chip, which includes a processor and a communication interface. The communication interface is coupled to the processor. The processor is used to run programs or instructions to implement the various processes of the above method embodiments and achieve the same technical effect. To avoid repetition, it will not be described again here.

[0124] It should be understood that the chip mentioned in the embodiments of this application may also be referred to as a system-on-a-chip, system chip, chip system, or system-on-a-chip, etc.

[0125] This application provides a computer program product, which is stored in a storage medium and executed by at least one processor to implement the various processes of the frame rate control method embodiments described above, and can achieve the same technical effect. To avoid repetition, it will not be described again here.

[0126] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. Furthermore, it should be noted that the scope of the methods and apparatuses in the embodiments of this application is not limited to performing functions in the order shown or discussed, but may also include performing functions substantially simultaneously or in the reverse order, depending on the functions involved. For example, the described methods may be performed in a different order than described, and various steps may be added, omitted, or combined. Additionally, features described with reference to certain examples may be combined in other examples.

[0127] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a computer software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a terminal (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods described in the various embodiments of this application.

[0128] The embodiments of this application have been described above with reference to the accompanying drawings. However, this application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of this application without departing from the spirit and scope of the claims, and all of these forms are within the protection scope of this application.

Claims

1. A frame rate control method, characterized in that, The method includes: During the display process using the first frame rate, the target offset is determined based on the window length of the data processing window corresponding to the second frame rate, where the second frame rate is greater than the first frame rate. According to the target offset and the parameters corresponding to the first frame rate, the data processing window corresponding to the first frame rate is compressed to obtain the first data processing window. Within the first data processing window, the first data is processed, and the first data is the display data during the process of displaying using the first frame rate; The parameters corresponding to the first frame rate include: Vertical synchronization signal rendering parameters, vertical synchronization signal synthesis parameters, hardware vertical synchronization signal; The vertical synchronization signal rendering parameters are used to indicate the timing of rendering the display data during the process of displaying at the first frame rate; The vertical synchronization signal synthesis parameters are used to indicate the timing of data synthesis during the display process using the first frame rate; The hardware vertical synchronization signal is used to indicate the timing of displaying data during the process of displaying at the first frame rate.

2. The method according to claim 1, characterized in that, Determining the target offset based on the window length of the data processing window corresponding to the second frame rate includes: The window length of the data processing window corresponding to the second frame rate is used as the target offset.

3. The method according to any one of claims 1 to 2, characterized in that, After compressing the data processing window corresponding to the first frame rate according to the target offset and the parameters corresponding to the first frame rate to obtain the first data processing window, the method further includes: Retain blank data processing windows other than the first data processing window in the data processing window corresponding to the first frame rate.

4. The method according to claim 1, characterized in that, After compressing the data processing window corresponding to the first frame rate according to the target offset and the parameters corresponding to the first frame rate to obtain the first data processing window, the method further includes: Based on the target offset, the data processing window corresponding to the second frame rate is offset, and the offset data processing window corresponding to the second frame rate is adjacent to the first data processing window.

5. A frame rate control device, characterized in that, The device includes: a determination module, an offset module, and a processing module; The determining module is used to determine the target offset based on the window length of the data processing window corresponding to the second frame rate during the display process using the first frame rate, wherein the second frame rate is greater than the first frame rate; The offset module is used to compress the data processing window corresponding to the first frame rate according to the target offset determined by the determining module and the parameters corresponding to the first frame rate, so as to obtain the first data processing window. The processing module is used to process the first data within the first data processing window obtained based on the offset module, wherein the first data is the display data during the process of displaying using the first frame rate; The parameters corresponding to the first frame rate include: Vertical synchronization signal rendering parameters, vertical synchronization signal synthesis parameters, hardware vertical synchronization signal; The vertical synchronization signal rendering parameters are used to indicate the timing of rendering the display data during the process of displaying at the first frame rate; The vertical synchronization signal synthesis parameters are used to indicate the timing of data synthesis during the display process using the first frame rate; The hardware vertical synchronization signal is used to indicate the timing of displaying data during the process of displaying at the first frame rate.

6. The apparatus according to claim 5, characterized in that, The determining module is specifically used to take the window length of the data processing window corresponding to the second frame rate as the target offset.

7. The apparatus according to any one of claims 5 to 6, characterized in that, The frame rate control device further includes: a reservation module; The retention module is used to retain blank data processing windows other than the first data processing window in the data processing window corresponding to the first frame rate after the offset module offsets the data processing window corresponding to the first frame rate based on the target offset amount to obtain the first data processing window.

8. The apparatus according to claim 5, characterized in that, The offset module is further configured to offset the data processing window corresponding to the first frame rate based on the target offset amount to obtain the first data processing window, and then offset the data processing window corresponding to the second frame rate based on the target offset amount, wherein the offset data processing window corresponding to the second frame rate is adjacent to the first data processing window.

9. An electronic device, characterized in that, It includes a processor, a memory, and a program or instructions stored in the memory and executable on the processor, wherein the program or instructions, when executed by the processor, implement the steps of the frame rate control method as described in any one of claims 1 to 4.

10. A readable storage medium, characterized in that, The readable storage medium stores a program or instructions that, when executed by a processor, implement the steps of the frame rate control method as described in any one of claims 1 to 4.

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