A delay circuit and a memory

Abstract

The embodiments of the present disclosure disclose a delay circuit and a memory, comprising a self-shielding module and a delay module. The self-shielding module is configured to receive an initial command signal and N initial clock signals, register the initial command signal according to a first initial clock signal of the N initial clock signals that triggers the initial command signal first, shield N-1 second initial clock signals of the N initial clock signals, and output N intermediate command signals, wherein N is an integer greater than or equal to 2; the N initial clock signals have the same frequency and different phases; the delay module is electrically connected with the self-shielding module and is configured to receive the N intermediate command signals and the N initial clock signals, delay output the N intermediate command signals to obtain delay command signals. The present disclosure can improve the accuracy of signal processing.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuits, and more particularly to a delay circuit and a memory. Background Technology

[0002] In semiconductor chips, the frequency of the clock signal is a crucial indicator of chip performance. With the continuous development of integrated circuit technology, the frequency of clock signals in chips is constantly increasing; for example, the clock signal frequency in DDR5 is twice that of DDR4. However, the higher the signal frequency, the weaker its anti-interference capability. Therefore, the increase in clock signal frequency also increases the probability of errors in signal processing performed using the clock signal.

[0003] Therefore, in some signal processing steps, such as registering and delaying command signals, a frequency-divided clock signal can be used. Since the frequency of the frequency-divided clock signal is lower than that of the main clock signal, the probability of error can be reduced. Summary of the Invention

[0004] In view of this, embodiments of the present disclosure provide a delay circuit and a memory that can improve the accuracy of signal processing.

[0005] The technical solution of this disclosure embodiment is implemented as follows:

[0006] This disclosure provides a delay circuit, including:

[0007] The self-masking module is configured to receive an initial command signal and N initial clock signals, register the initial command signal based on the first initial clock signal that triggers the initial command signal first among the N initial clock signals, mask the other N-1 second initial clock signals among the N initial clock signals, and output N intermediate command signals, where N is an integer greater than or equal to 2; the N initial clock signals have the same frequency but different phases.

[0008] The delay module, electrically connected to the self-shielding module, is configured to receive N intermediate command signals and N initial clock signals, and delay the output of the N intermediate command signals to obtain a delayed command signal.

[0009] In the above scheme, the self-shielding module includes: a shielding unit configured to receive N initial clock signals and output N intermediate clock signals; wherein the N intermediate clock signals include one valid first intermediate clock signal and N-1 invalid second intermediate clock signals; and a register unit electrically connected to the shielding unit, configured to receive the initial command signal and the N intermediate clock signals, register the initial command signal according to the first intermediate clock signal, and obtain and output the N intermediate command signals.

[0010] In the above scheme, the register unit includes: N self-masking flip-flops; all N self-masking flip-flops are D flip-flops; the N intermediate command signals include one valid first intermediate command signal and N-1 invalid second intermediate command signals; the first input terminals of all N self-masking flip-flops receive the initial command signal, and the second input terminals of all N self-masking flip-flops are connected to the output terminal of the masking unit; the first self-masking flip-flop among the N self-masking flip-flops that receives the first intermediate clock signal registers the initial command signal according to the first intermediate clock signal and outputs the first intermediate command signal at its first output terminal; the other N-1 second self-masking flip-flops among the N self-masking flip-flops receive N-1 second intermediate clock signals one by one and output N-1 second intermediate command signals one by one at their first output terminals.

[0011] In the above scheme, the shielding unit includes: N AND gates, each of which includes a first input terminal and N-1 second input terminals; the first input terminals of the N AND gates receive N initial clock signals one by one, and the output terminals of the N AND gates are connected to the second input terminals of the N self-masking flip-flops one by one; the N-1 second input terminals of each AND gate are connected to the second output terminals of N-1 other self-masking flip-flops other than its corresponding self-masking flip-flop one by one.

[0012] In the above scheme, the shielding unit includes: N inverters and N NOR gates; each NOR gate includes a first input terminal and N-1 second input terminals; the input terminals of the N inverters receive N initial clock signals one by one, the output terminals of the N inverters are connected to the first input terminals of the N NOR gates one by one, the output terminals of the N NOR gates are connected to the second input terminals of the N self-masking flip-flops one by one; the N-1 second input terminals of each NOR gate are connected to the first output terminals of N-1 other self-masking flip-flops other than its corresponding self-masking flip-flop.

[0013] In the above scheme, the delay module includes: M-level second register units, where M is an integer greater than or equal to 2; each level of the second register unit includes: N delay triggers; all N delay triggers are D triggers; the second input terminals of the N delay triggers in each level of the second register unit receive N initial clock signals one by one; the first input terminals of the N delay triggers in the first level of the second register unit are connected to the first output terminals of the N self-masking triggers one by one; the first input terminals of the N delay triggers in the i-th level of the second register unit are connected to the output terminals of the N delay triggers in the previous level of the second register unit, where i is greater than 1 and less than or equal to M.

[0014] In the above scheme, M = (CL-A) / N, where CL is the maximum number of delay cycles and A is the number of cycles corresponding to the command pre-operation.

[0015] In the above scheme, the delay module further includes: an OR gate, which has N input terminals; N delay triggers in the Mth stage second register unit, whose first output terminals are connected one-to-one with the N input terminals of the OR gate; and the output terminal of the OR gate outputs the delay command signal.

[0016] In the above scheme, N=2, and the N initial clock signals are odd-even frequency division clock signals. The odd-even frequency division clock signals include: odd clock signals and even clock signals; the odd clock signals and the even clock signals have the same frequency and opposite phase.

[0017] In the above scheme, the self-shielding module includes: a shielding unit and a register unit; the register unit includes: a first self-shielding trigger and a second self-shielding trigger; both the first self-shielding trigger and the second self-shielding trigger are D triggers; the first input terminal of the first self-shielding trigger and the first input terminal of the second self-shielding trigger both receive the command signal.

[0018] In the above scheme, the shielding unit includes: a first AND gate and a second AND gate; both the first AND gate and the second AND gate are two-input AND gates; the first input of the first AND gate receives the even clock signal, the output of the first AND gate is connected to the second input of the first self-masking flip-flop, and the second input of the first AND gate is connected to the second output of the second self-masking flip-flop; the first input of the second AND gate receives the odd clock signal, the output of the second AND gate is connected to the second input of the second self-masking flip-flop, and the second input of the second AND gate is connected to the second output of the first self-masking flip-flop.

[0019] In the above scheme, the shielding unit includes: a first inverter, a second inverter, a first NOR gate, and a second NOR gate; both the first NOR gate and the second NOR gate are two-input NOR gates; the input of the first inverter receives the even clock signal, and the output of the first inverter is connected to the first input of the first NOR gate; the output of the first NOR gate is connected to the second input of the first self-masking flip-flop, and the second input of the first NOR gate is connected to the first output of the second self-masking flip-flop; the input of the second inverter receives the odd clock signal, and the output of the second inverter is connected to the first input of the second NOR gate; the output of the second NOR gate is connected to the second input of the second self-masking flip-flop, and the second input of the second NOR gate is connected to the first output of the first self-masking flip-flop.

[0020] This disclosure also provides a memory, characterized in that the memory includes the delay circuit described above.

[0021] In the above scheme, the memory is electrically connected to the control module, wherein the memory meets the DDR4 specification and the control module meets the DDR5 specification; the memory also includes a frequency divider circuit; the memory receives a standard clock signal from the control module, divides the standard clock signal into an initial clock signal through the frequency divider circuit, and transmits the initial clock signal to the delay circuit.

[0022] Therefore, this disclosure provides a delay circuit and a memory, including a self-masking module and a delay module. The self-masking module is configured to receive an initial command signal and N initial clock signals. Based on the first initial clock signal that triggers the initial command signal first among the N initial clock signals, it registers the initial command signal, masks the other N-1 second initial clock signals among the N initial clock signals, and outputs N intermediate command signals, where N is an integer greater than or equal to 2; the N initial clock signals have the same frequency but different phases. The delay module, electrically connected to the self-masking module, is configured to receive the N intermediate command signals and the N initial clock signals, delay the N intermediate command signals, and output the delayed command signals. In this way, the delay circuit controls the registration and delay of the command signals only through the first initial clock signal, masking the second initial clock signals, avoiding errors caused by the simultaneous action of N initial clock signals, and improving the accuracy of signal processing. Attached Figure Description

[0023] Figure 1 This is a schematic diagram of the delay circuit provided in the embodiments of this disclosure. Figure 1 ;

[0024] Figure 2 This is a signal schematic of the delay circuit provided in the embodiments of this disclosure. Figure 1 ;

[0025] Figure 3 This is a schematic diagram of the delay circuit provided in the embodiments of this disclosure. Figure 2 ;

[0026] Figure 4 This is a schematic diagram of the delay circuit provided in the embodiments of this disclosure. Figure 3 ;

[0027] Figure 5 This is a schematic diagram of the delay circuit provided in the embodiments of this disclosure. Figure 4 ;

[0028] Figure 6 This is a signal schematic of the delay circuit provided in the embodiments of this disclosure. Figure 2 ;

[0029] Figure 7 This is a schematic diagram of the delay circuit provided in the embodiments of this disclosure. Figure 5 ;

[0030] Figure 8 This is a schematic diagram of the delay circuit provided in the embodiments of this disclosure. Figure 6 ;

[0031] Figure 9 This is a signal schematic of the delay circuit provided in the embodiments of this disclosure. Figure 3 ;

[0032] Figure 10 This is a signal schematic of the delay circuit provided in the embodiments of this disclosure. Figure 4 ;

[0033] Figure 11 This is a schematic diagram of the delay circuit provided in the embodiments of this disclosure. Figure 7 ;

[0034] Figure 12 This is a schematic diagram of the delay circuit provided in the embodiments of this disclosure. Figure 8 ;

[0035] Figure 13 This is a signal schematic of the delay circuit provided in the embodiments of this disclosure. Figure 5 ;

[0036] Figure 14 This is a schematic diagram of the delay circuit provided in the embodiments of this disclosure. Figure 9 ;

[0037] Figure 15 This is a signal schematic of the delay circuit provided in the embodiments of this disclosure. Figure 6 ;

[0038] Figure 16 This is a schematic diagram of the delay circuit provided in the embodiments of this disclosure. Figure 10 ;

[0039] Figure 17 This is a schematic diagram of the delay circuit provided in the embodiments of this disclosure. Figure 10 one;

[0040] Figure 18 This is a schematic diagram of the structure of the memory provided in the embodiments of this disclosure. Figure 1 ;

[0041] Figure 19 This is a schematic diagram of the structure of the memory provided in the embodiments of this disclosure. Figure 2 . Detailed Implementation

[0042] To make the objectives, technical solutions, and advantages of this disclosure clearer, the technical solutions of this disclosure are further described in detail below with reference to the accompanying drawings and embodiments. The described embodiments should not be regarded as limitations on this disclosure. All other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0043] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0044] If the application documents contain similar descriptions such as "first / second", the following explanation shall be added: In the following description, the terms "first / second / third" are used only to distinguish similar objects and do not represent a specific order of objects. It is understood that "first / second / third" may be interchanged in a specific order or sequence where permitted, so that the embodiments of this disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0045] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing embodiments of this disclosure only and is not intended to be limiting of this disclosure.

[0046] Figure 1 This is a schematic diagram of a delay circuit provided in an embodiment of the present disclosure, as shown below. Figure 1 As shown, this embodiment of the disclosure provides a delay circuit 10, including a self-shielding module 101 and a delay module 102. The self-shielding module 101 is configured to receive an initial command signal CMD and N initial clock signals CLK<1:N> (i.e., initial clock signals CLK). <1> ~CLK <n>Based on the first initial clock signal that triggers the initial command signal CMD first among the N initial clock signals CLK<1:N>, the initial command signal CMD is registered, the effects of the other N-1 second initial clock signals in the N initial clock signals CLK<1:N> are masked, and N intermediate command signals CMD_i (i is greater than or equal to 1 and less than or equal to N) are output, where N is an integer greater than or equal to 2; the N initial clock signals have the same frequency and different phases.

[0047] The delay module 102 is electrically connected to the self-shielding module 101 and is configured to receive N intermediate command signals CMD_i and N initial clock signals CLK<1:N>, and delay the N intermediate command signals according to the N initial clock signals CLK<1:N> to obtain the delayed command signal CMD_SHIFT.

[0048] In this embodiment, the initial clock signal can be a frequency-divided clock signal. A frequency-divided clock signal is obtained by dividing the clock signal in the chip, and its period is a multiple of the clock signal's period. For example, the period of a 4-divided clock signal is four times the clock signal's period, meaning its frequency is one-quarter of the clock signal's frequency. Similarly, the period of an odd-even divided clock signal (i.e., a 2-divided clock signal) is twice the clock signal's period, meaning its frequency is half the clock signal's frequency. In use, multiple frequency-divided clock signals with different phases can be used simultaneously to meet various needs.

[0049] It should be noted that the initial command signal can be active high or active low. For example, in memory, the "read command" is usually active high, while the "write command" is active low. This disclosure does not impose any restrictions on this. Figure 2 The command signal CMD shown is active high, such as... Figure 2 As shown, the initial command signal CMD is low under normal conditions, and a control effect is generated when the initial command signal CMD contains a high-level pulse.

[0050] In this embodiment of the disclosure, in the self-shielding module 101, the initial command signal CMD is registered upon triggering. Since the phases of the N initial clock signals CLK<1:N> are different, the times at which the N initial clock signals CLK<1:N> reach the trigger edge corresponding to the initial command signal CMD are not the same. Figure 2 For example, the initial clock signal CLK <1> CLK <2> CLK <3> and CLK <4> The clock signal CLK is a four-divided frequency signal, with each division having a 90° phase difference. The initial command signal CMD is triggered on the rising edge. Therefore, within the effective pulse width of the initial command signal CMD, the initial clock signal CLK... <1> First to reach the rising edge (e.g.) Figure 2 (As shown by the dashed arrow in the middle), that is, the initial clock signal CLK. <1> The first trigger edge that reaches the initial command signal CMD becomes the first initial clock signal.

[0051] It should be noted that the initial command signal CMD can also be set to fall-edge triggered. In this case, the initial clock signal that reaches the fall edge first within the effective pulse width of the initial command signal CMD becomes the first initial clock signal, without any restrictions.

[0052] In this embodiment of the disclosure, the self-shielding module 101 can shield the second initial clock signal other than the first initial clock signal among the N initial clock signals CLK<1:N>. Here, shielding the second initial clock signal means that the second initial clock signal will not trigger the initial command signal CMD register.

[0053] In this embodiment of the disclosure, the effective pulse width of the command signal is greater than or equal to the period length of each initial clock signal. In this way, each initial clock signal can reach the trigger edge at least once within the effective pulse width of the command signal, ensuring that the command signal can always be registered and delayed by the delay circuit provided in this embodiment of the disclosure.

[0054] It is understood that the delay circuit provided in this disclosure controls the registration and delay of the command signal only through the first initial clock signal, shielding the second initial clock signal, thus avoiding errors caused by the simultaneous action of N initial clock signals and improving the accuracy of signal processing. Furthermore, since the delay circuit provided in this disclosure registers the command signal based on the first initial clock signal that triggers the command signal first among the N initial clock signals, it ensures that the delay caused by the registration of the command signal is the shortest, i.e., shortening the relative delay between delayed command signals.

[0055] In some embodiments of the application, such as Figure 3 As shown, the self-shielding module 101 includes a shielding unit 201 and a register unit 202. The shielding unit 201 is configured to receive N initial clock signals CLK<1:N>, shield the effects of the other N-1 second initial clock signals in the N initial clock signals CLK<1:N>, and output N intermediate clock signals / CLK<1:N> (i.e., intermediate clock signals / CLK). <1> ~ / CLK <n>Among them, the N intermediate clock signals / CLK<1:N> include one valid first intermediate clock signal and N-1 invalid second intermediate clock signals.

[0056] The register unit 202 is electrically connected to the shield unit 201 and is configured to receive the initial command signal CMD and N intermediate clock signals / CLK<1:N>, register the initial command signal CMD according to the first intermediate clock signal, and obtain and output the N intermediate command signals CMD_i.

[0057] In this embodiment, the first intermediate clock signal is a valid signal, meaning it can trigger the registration of the initial command signal CMD; the waveform of the first intermediate clock signal is the same as that of the first initial clock signal, meaning the first initial clock signal triggers the registration of the initial command signal CMD. The N-1 second intermediate clock signals are invalid signals, meaning none of them can trigger the registration of the initial command signal CMD; the N-1 second intermediate clock signals correspond to the N-1 second initial clock signals, meaning the function of the N-1 second initial clock signals is masked.

[0058] It is understandable that the shielding unit shields the effects of N-1 second initial clock signals, and the register unit controls the registering of command signals only through the first initial clock signal. In this way, the error caused by the simultaneous action of N initial clock signals is avoided, and the accuracy of signal processing is improved.

[0059] In some embodiments of the application, such as Figure 4 As shown, register unit 202 includes: N self-masking flip-flops 30, all of which are D flip-flops. The N intermediate command signals CMD_1 to CMD_N include one valid first intermediate command signal and N-1 invalid second intermediate command signals.

[0060] The first input terminals D of all N self-masking flip-flops 30 receive the initial command signal CMD, and the second input terminals C of all N self-masking flip-flops 30 are connected to the output terminal of the shielding unit 201. The first self-masking flip-flop among the N self-masking flip-flops 30 that receives the first intermediate clock signal registers the initial command signal according to the first intermediate clock signal and outputs the first intermediate command signal at its first output terminal Q. The other N-1 second self-masking flip-flops among the N self-masking flip-flops 30 receive N-1 second intermediate clock signals one-to-one and output N-1 second intermediate command signals one-to-one at their first output terminals Q.

[0061] In this embodiment, the first intermediate command signal is triggered and output by the first intermediate clock signal. The first intermediate command signal contains pulses and is a valid signal. Since the effects of the N-1 second initial clock signals are masked, the N-1 second intermediate command signals are not pulse signals that are triggered and output. Therefore, the N-1 second intermediate command signals do not contain pulses and are invalid signals.

[0062] In some embodiments of the application, the shielding unit includes: N AND gates; each of the N AND gates is an N-input AND gate, and each AND gate includes a first input and N-1 second inputs. The first inputs of the N AND gates receive N initial clock signals one-to-one, and the outputs of the N AND gates are connected to the second inputs of N self-masking flip-flops one-to-one. The N-1 second inputs of each AND gate are connected to the second outputs of N-1 other self-masking flip-flops besides its corresponding self-masking flip-flop.

[0063] by Figure 5 For example, the shielding unit 201 may include four AND gates, namely AND gate 401, AND gate 402, AND gate 403, and AND gate 404. These four AND gates are all four-input AND gates, each including a first input and three second inputs. The first inputs of the four AND gates receive four initial clock signals in a one-to-one correspondence. That is, the first input of AND gate 401 receives the initial clock signal CLK. <1> The first input of AND gate 402 receives the initial clock signal CLK. <2> The first input of AND gate 403 receives the initial clock signal CLK. <3> The first input of AND gate 404 receives the initial clock signal CLK. <4> .

[0064] The outputs of the four AND gates are connected one-to-one to the second inputs C of the four self-masking flip-flops. Specifically, the output of AND gate 401 is connected to the second input C of self-masking flip-flop 301, the output of AND gate 402 is connected to the second input C of self-masking flip-flop 302, the output of AND gate 403 is connected to the second input C of self-masking flip-flop 303, and the output of AND gate 404 is connected to the second input C of self-masking flip-flop 304. The output of AND gate 401 transmits the intermediate clock signal / CLK. <1> The intermediate clock signal / CLK is transmitted to the second input terminal C of the self-masking flip-flop 301 and the output terminal of the AND gate 402. <2> The intermediate clock signal / CLK is transmitted to the second input terminal C of the self-masking flip-flop 302 and the output terminal of the AND gate 403. <3> The intermediate clock signal / CLK is transmitted to the second input terminal C of the self-masking flip-flop 303 and the output terminal of the AND gate 404. <4> To the second input terminal C of the self-masking trigger 304.

[0065] Each AND gate's three second inputs are connected one-to-one with the second outputs of three other self-maskable flip-flops, excluding its corresponding self-maskable flip-flop. In other words, the three second input terminals of AND gate 401 are connected one-to-one to the second output terminals of self-masking flip-flop 302. The second output terminal of the self-masking trigger 303 and the second output terminal of the self-masking trigger 304 The three second inputs of AND gate 402 are connected one-to-one to the second output of self-masking flip-flop 301. The second output terminal of the self-masking trigger 303 and the second output terminal of the self-masking trigger 304 The three second inputs of AND gate 403 are connected one-to-one to the second output of self-masking flip-flop 301. The second output terminal of the self-masking trigger 302 and the second output terminal of the self-masking trigger 304 The three second inputs of AND gate 404 are connected one-to-one to the second output of self-masking flip-flop 301. The second output terminal of the self-masking trigger 302 and the second output terminal of the self-masking trigger 303

[0066] In this embodiment of the disclosure, combined with Figure 5 and Figure 6 ,Will Figure 6 The initial command signal CMD and the initial clock signal CLK are shown. <1> CLK <2> CLK <3> and CLK <4> Corresponding input Figure 5 The circuit shown.

[0067] When the initial command signal CMD is not triggered and is registered, the first outputs Q of the self-masking flip-flops 301, 302, 303, and 304 all output CMD_1, CMD_2, CMD_3, and CMD_4 are low (CMD_2, CMD_3, and CMD_4 are low in the register). Figure 6 (Not shown in the diagram), then for each of AND gates 401, 402, 403, and 404, all three of their second inputs receive a high level. In this case, AND gates 401, 402, 403, and 404 do not produce a shielding effect, and the intermediate clock signal / CLK... <1> and the initial clock signal CLK <1> The waveforms are the same, except for the intermediate clock signal / CLK. <2> and the initial clock signal CLK <2> The waveforms are the same, the intermediate clock signal is / CLK <3> and the initial clock signal CLK <3> The waveforms are the same, the intermediate clock signal is / CLK <4> and the initial clock signal CLK <4> The waveforms are the same.

[0068] Within the effective pulse width 'a' of the initial command signal CMD, the initial clock signal CLK <1> The first rising edge to arrive, i.e., the initial clock signal CLK <1> This becomes the first initial clock signal. At this time, the self-masking flip-flop 301 receives the intermediate clock signal / CLK. <1> The initial command signal CMD is registered upon triggering, and the first intermediate command signal CMD_1 is output at its first output terminal Q. Simultaneously, the inverted signal of the first intermediate command signal CMD_1 is transmitted to AND gates 402, 403, and 404, i.e., the intermediate clock signal / CLK. <1> This becomes a valid first intermediate clock signal. Since the inverted signal of the first intermediate command signal CMD_1 includes a low-level pulse, during the duration b of this low-level pulse, the intermediate clock signal / CLK output by AND gates 402, 403, and 404... <2> / CLK <3> and / CLK <4> All remain at a low level, meaning that the intermediate clock signal / CLK remains low for duration b. <2> / CLK <3> and / CLK <4> All are shielded, i.e., the intermediate clock signal / CLK <2> / CLK <3> and / CLK <4> All of these are invalid second intermediate clock signals. Furthermore, within the effective pulse width 'a' of the initial command signal CMD, the intermediate clock signal / CLK... <2> / CLK <3> and / CLK <4> No rising edge will be generated to trigger the self-masking flip-flops 302, 303, and 304 to register the initial command signal CMD. The CMD_2, CMD_3, and CMD_4 output by the first output terminal Q of the self-masking flip-flops 302, 303, and 304 will remain low without any pulse. Figure 6 (Not shown in the image).

[0069] Understandably, the first initial clock signal triggers the initial command signal register to obtain the shift command signal. Then, the N-1 AND gates that did not receive the first initial clock signal will shield the second initial clock signal according to the shift command signal, thereby avoiding the error caused by the simultaneous action of N initial clock signals and improving the accuracy of signal processing.

[0070] In some embodiments of the application, the shielding unit includes: N inverters and N NOR gates; the N NOR gates are all N-input NOR gates, each including a first input and N-1 second inputs. The inputs of the N inverters receive N initial clock signals one-to-one, the outputs of the N inverters are connected to the first inputs of the N NOR gates one-to-one, and the outputs of the N NOR gates are connected to the second inputs of the N self-masking flip-flops one-to-one. The N-1 second inputs of each NOR gate are connected to the first outputs of N-1 other self-masking flip-flops besides its corresponding self-masking flip-flop.

[0071] by Figure 7 For example, the shielding unit 201 may include: four inverters 411, 412, 413, and 414; and four NOR gates, namely inverters 411, 412, 413, and 414; NOR gates 421, 422, 423, and 424. These four NOR gates are all four-input NOR gates, each including a first input and three second inputs. The inputs of the four inverters receive four initial clock signals in a one-to-one correspondence; that is, the input of inverter 411 receives the initial clock signal CLK. <1> The input of inverter 412 receives the initial clock signal CLK. <2> The input of inverter 413 receives the initial clock signal CLK. <3> The input of inverter 414 receives the initial clock signal CLK. <4> .

[0072] The outputs of the four inverters are connected one-to-one with the first inputs of the four NOR gates. That is, the output of inverter 411 is connected to the first input of NOR gate 421, the output of inverter 412 is connected to the first input of NOR gate 422, the output of inverter 413 is connected to the first input of NOR gate 423, and the output of inverter 414 is connected to the first input of NOR gate 424.

[0073] The outputs of the four NOR gates are connected one-to-one to the second input C of the four self-masking flip-flops. Specifically, the output of NOR gate 421 is connected to the second input C of self-masking flip-flop 301, the output of NOR gate 422 is connected to the second input C of self-masking flip-flop 302, the output of NOR gate 423 is connected to the second input C of self-masking flip-flop 303, and the output of NOR gate 424 is connected to the second input C of self-masking flip-flop 304. The output of NOR gate 421 transmits the intermediate clock signal / CLK. <1> The intermediate clock signal / CLK is transmitted to the second input C of the self-masking flip-flop 301 and the output of the NOR gate 422. <2> The intermediate clock signal / CLK is transmitted to the second input terminal C of the self-masking flip-flop 302 and the output terminal of the NOR gate 423. <3> The intermediate clock signal / CLK is transmitted to the second input terminal C of the self-masking flip-flop 303 and the output terminal of the NOR gate 424. <4> To the second input terminal C of the self-masking trigger 304.

[0074] Each of the three second input terminals of the NOR gate is connected one-to-one with the first output terminal Q of the three other self-masking flip-flops besides its corresponding self-masking flip-flop. That is, the three second input terminals of NOR gate 421 are connected one-to-one with the first output terminal Q of self-masking flip-flop 302, the first output terminal Q of self-masking flip-flop 303, and the first output terminal Q of self-masking flip-flop 304; the three second input terminals of NOR gate 422 are connected one-to-one with the first output terminal Q of self-masking flip-flop 301, the first output terminal Q of self-masking flip-flop 303, and the first output terminal Q of self-masking flip-flop 304; the three second input terminals of NOR gate 423 are connected one-to-one with the first output terminal Q of self-masking flip-flop 301, the first output terminal Q of self-masking flip-flop 302, and the first output terminal Q of self-masking flip-flop 304; and the three second input terminals of NOR gate 424 are connected one-to-one with the first output terminal Q of self-masking flip-flop 301, the first output terminal Q of self-masking flip-flop 302, and the first output terminal Q of self-masking flip-flop 303.

[0075] In this embodiment of the disclosure, combined with Figure 6 and Figure 7 ,Will Figure 6 The initial command signal CMD and the initial clock signal CLK are shown. <1> CLK <2> CLK <3> and CLK <4> Corresponding input Figure 7 The circuit shown.

[0076] When the initial command signal CMD is not triggered and is registered, the first outputs Q of the self-masking flip-flops 301, 302, 303, and 304 all output CMD_1, CMD_2, CMD_3, and CMD_4 are low (CMD_2, CMD_3, and CMD_4 are low in the register). Figure 6 If (not shown in the diagram), then each of the NOR gates 421, 422, 423, and 424 receives a low level at all three of its second inputs. In this case, the NOR gates 421, 422, 423, and 424 do not produce a shielding effect, and the intermediate clock signal / CLK... <1> and the initial clock signal CLK <1> The waveforms are the same, the intermediate clock signal is / CLK <2> and the initial clock signal CLK <2> The waveforms are the same, the intermediate clock signal is / CLK <3> and the initial clock signal CLK <3> The waveforms are the same, the intermediate clock signal is / CLK <4> and the initial clock signal CLK <4> The waveforms are the same.

[0077] Within the effective pulse width 'a' of the initial command signal CMD, the initial clock signal CLK <1> The first rising edge to arrive, i.e., the initial clock signal CLK <1> This becomes the first initial clock signal. At this time, the self-masking flip-flop 301 receives the intermediate clock signal / CLK. <1> The initial command signal CMD is registered upon triggering, and the first intermediate command signal CMD_1 is output at its first output terminal Q. Simultaneously, the first intermediate command signal CMD_1 is transmitted to NOR gates 422, 423, and 424, i.e., the intermediate clock signal / CLK. <1> This becomes a valid first intermediate clock signal. Since the first intermediate command signal CMD_1 includes a high-level pulse, during the duration b of this high-level pulse, the intermediate clock signal / CLK output by NOR gates 422, 423, and 424... <2> / CLK <3> and / CLK <4> All remain at a low level, meaning that the intermediate clock signal / CLK remains low for duration b. <2> / CLK <3> and / CLK <4> All are shielded, i.e., the intermediate clock signal / CLK <2> / CLK <3> and / CLK <4> All of these are invalid second intermediate clock signals. Furthermore, within the effective pulse width 'a' of the initial command signal CMD, the intermediate clock signal / CLK... <2> / CLK <3> and / CLK <4> No rising edge will be generated to trigger the self-masking flip-flops 302, 303, and 304 to register the initial command signal CMD. The CMD_2, CMD_3, and CMD_4 output by the first output terminal Q of the self-masking flip-flops 302, 303, and 304 will remain low without any pulse. Figure 6 (Not shown in the image).

[0078] Understandably, the first initial clock signal triggers the initial command signal register to obtain the shift command signal. Then, the N-1 NOR gates that do not receive the first initial clock signal through the inverter will shield the second initial clock signal according to the shift command signal, thereby avoiding the error caused by the simultaneous action of N initial clock signals and improving the accuracy of signal processing.

[0079] In some embodiments of this disclosure, such as Figure 8 As shown, the delay module 102 includes M-stage second register units 203, where M is an integer greater than or equal to 2. Each stage of the second register unit 203 includes N delay flip-flops 31, all of which are D flip-flops. The first input terminal D of the N delay flip-flops 31 in the first stage of the second register unit 203 is connected one-to-one with the first output terminal Q of the N self-masking flip-flops 30. The second input terminal C of the N delay flip-flops 31 in each stage of the second register unit 203 receives one-to-one with the N initial clock signals CLK. <1> CLK <2> …CLK <n>(i.e., CLK<1:N>).

[0080] In this embodiment of the disclosure, when M is greater than or equal to 2, the first input terminals D of the N delay triggers 31 in the i-th stage second register unit 203 are connected one-to-one with the first output terminals Q of the N delay triggers 31 in the previous stage second register unit 203, where i is greater than 1 and less than or equal to M. For example... Figure 8 As shown in the example, the first input terminal D of the N delay triggers 31 in the second register unit 203 of the second stage is connected one-to-one with the first output terminal Q of the N delay triggers 31 in the first register unit 203 of the first stage; the first input terminal D of the N delay triggers 31 in the second register unit 203 of the M stage is connected one-to-one with the first output terminal Q of the N delay triggers 31 in the (M-1)th stage of the second register unit 203 of the M stage.

[0081] In this embodiment of the disclosure, the number of stages of the second register unit 203 is M = (CL - A) / N, where CL is the maximum number of delay cycles and A is the number of cycles corresponding to the command pre-operation. Both CL and A meet the requirements of integrated circuit design standards.

[0082] Here, the clock cycles corresponding to CL and A can be the period of the external clock, that is, one-Nth of the period of the initial clock signal. Command pre-operation includes pre-write and pre-read, so A = a1 + a2. When the initial command signal is "read command", a1 corresponds to the clock cycle of preamble, and a2 corresponds to the clock cycle of offset (clock signal deviation margin).

[0083] In this embodiment of the disclosure, such as Figure 8 As shown, the delay module 102 also includes an OR gate 32, which has N inputs. The first outputs Q of the N delay triggers 31 in the Mth stage second register unit 203 are connected one-to-one with the N inputs of the OR gate 32. The output of the OR gate 32 serves as the output of the delay module 102, outputting the delay command signal CMD_SHIFT.

[0084] In this embodiment of the disclosure, combined with Figure 8 and Figure 9 If the initial clock signal CLK <1> If the initial clock signal CMD becomes the first initial clock signal, then the initial command signal CMD is registered as the first intermediate command signal CMD_1. Therefore, the first intermediate command signal CMD_1, after passing through the M-level second register unit 203, is delayed to become the signal CMD_1m, and is input to the OR gate 32. The waveforms of the initial command signal CMD, the first intermediate command signal CMD_1, and the signal CMD_1m are as follows: Figure 9 As shown. Simultaneously, the second intermediate command signals CMD_2 to CMD_N remain low, excluding any pulses. Therefore, after passing through the M-level second register unit 203, the first output Q of the delay trigger 31 in the M-level second register unit 203 corresponding to the second intermediate command signals CMD_2 to CMD_N remains low, excluding any pulses. Thus, one input of the OR gate 32 receives the signal CMD_1m, and the second input receives a continuous low level. Therefore, the delayed command signal CMD_SHIFT output by the OR gate 32 has the same waveform as the signal CMD_1m, and the effective pulse width of the delayed command signal CMD_SHIFT is equal to the effective pulse width of the initial command signal CMD.

[0085] Understandably, the self-shielding module shields the effect of the second initial clock signal, outputting only a single shift command signal. Consequently, the delay module can delay the single shift command signal, thus ensuring that the effective pulse width of the final delayed command signal is equal to the effective pulse width of the initial command signal, thereby improving the accuracy of signal processing.

[0086] In some embodiments of this disclosure, N=2, and the N initial clock signals are odd-even frequency division clock signals, such as... Figure 10 As shown, the odd-even frequency divider clock signals include: an odd clock signal CLK_O and an even clock signal CLK_E. The odd clock signal CLK_O and the even clock signal CLK_E have the same frequency but opposite phases. The odd clock signal CLK_O and the even clock signal CLK_E are divided-by-two of the clock signal CLK; their periods are twice the period of the clock signal CLK, and their frequencies are half the frequency of the clock signal CLK.

[0087] In some embodiments of this disclosure, such as Figure 11 As shown, the self-shielding module 101 includes a shielding unit 201 and a register unit 202, wherein the register unit 202 includes a first self-shielding trigger 501 and a second self-shielding trigger 502. Combined with... Figure 10 and Figure 11 Both the first self-masking trigger 501 and the second self-masking trigger 502 are D flip-flops. The first input terminal D of the first self-masking trigger 501 and the first input terminal D of the second self-masking trigger 502 both receive the initial command signal CMD. The shielding unit 201 receives the odd clock signal CLK_O and the even clock signal CLK_E respectively, and is connected to the second input terminal C of the first self-masking trigger 501 and the second self-masking trigger 502 respectively.

[0088] In some embodiments of this disclosure, such as Figure 12 As shown, the shielding unit 101 includes a first AND gate A1 and a second AND gate A2, both of which are two-input AND gates. The first input of the first AND gate A1 receives the even clock signal CLK_E, the output of the first AND gate A1 is connected to the second input C of the first self-shielding flip-flop 501, and the second input of the first AND gate A1 is connected to the second output of the second self-shielding flip-flop 502. The first AND gate A1 outputs the intermediate clock signal CLK_E1. The first input of the second AND gate A2 receives the odd clock signal CLK_O. The output of the second AND gate A2 is connected to the second input C of the second self-masking flip-flop 502. The second input of the second AND gate A2 is connected to the second output of the first self-masking flip-flop 501. The second AND gate A2 outputs the intermediate clock signal CLK_O1.

[0089] Combination Figure 12 and Figure 13 If the initial command signal CMD is not triggered and is registered, and both the first output Q of the first self-masking flip-flop 501 and the first output Q of the second self-masking flip-flop 502 (CMD_E and CMD_O) are low, then the second input of the second AND gate A2 and the second input of the first AND gate A1 will both receive a high level. In this case, the first AND gate A1 and the second AND gate A2 will not produce a shielding effect, the intermediate clock signal CLK_E1 and the even clock signal CLK_E have the same waveform, and the intermediate clock signal CLK_O1 and the odd clock signal CLK_O have the same waveform.

[0090] In the effective pulse width c of the initial command signal CMD, the even clock signal CLK_E arrives at the rising edge before the odd clock signal CLK_O (e.g., ...). Figure 13 (As shown by the dashed arrow), the even clock signal CLK_E becomes the first initial clock signal. At this time, the first self-masking flip-flop 501 is triggered by the intermediate clock signal CLK_E1, registers the initial command signal CMD, and outputs the shift command signal CMD_E at its first output terminal Q. Simultaneously, it outputs the inverted signal of the shift command signal CMD_E to the second input terminal of the second AND gate A2. Since the inverted signal of the shift command signal CMD_E includes a low-level pulse, the intermediate clock signal CLK_O1 output by the second AND gate A2 remains low during the duration d of this low-level pulse. That is, the second AND gate A2 masks the odd clock signal CLK_O during the duration d. Consequently, the intermediate clock signal CLK_O1 will not generate a rising edge to trigger the second self-masking flip-flop 502 to register the initial command signal CMD, and the CMD_O output by the first output terminal Q of the second self-masking flip-flop 502 remains low without including any pulse.

[0091] Correspondingly, if the initial clock signal CLK_O becomes the first initial clock signal, then the second self-masking flip-flop 502 is triggered by the intermediate clock signal CLK_O1 to register the initial command signal CMD, while the CMD_E output by the first output terminal Q of the first self-masking flip-flop 501 remains low without including any pulses.

[0092] In this embodiment of the disclosure, such as Figure 14 As shown, the delay module 102 may include M-stage second register units 203, where M is an integer greater than or equal to 2. Each stage of the second register unit 203 includes delay triggers 511 and 512, both of which are D flip-flops. In the first stage of the second register unit 203, the first input terminal D of the delay trigger 511 is connected to the first output terminal Q of the self-masking trigger 501, and the first input terminal D of the delay trigger 512 is connected to the first output terminal Q of the self-masking trigger 502. In each stage of the second register unit 203, the second input terminal C of the delay trigger 511 receives the even clock signal CLK_E, and the second input terminal C of the delay trigger 512 receives the odd clock signal CLK_O. Where M is greater than or equal to 2, the first input terminal D of the delay trigger 511 in the i-th stage second register unit 203 is connected to the first output terminal Q of the delay trigger 511 in the previous stage second register unit 203, and the first input terminal D of the delay trigger 512 in the i-th stage second register unit 203 is connected to the first output terminal Q of the delay trigger 512 in the previous stage second register unit 203, i is greater than 1 and less than or equal to M.

[0093] like Figure 14 As shown, the delay module 102 also includes an OR gate 52, which is a two-input OR gate. The delay triggers 511 and 512 in the M-th stage second register unit 203 have their first outputs Q connected one-to-one to the two inputs of the OR gate 52. The output of the OR gate 52 serves as the output of the delay module 102, outputting the delay command signal CMD_SHIFT.

[0094] In this embodiment of the disclosure, combined with Figure 14 and Figure 15 If the even clock signal CLK_E becomes the first initial clock signal, then the initial command signal CMD is registered as the shift command signal CMD_E. Therefore, after passing through the M-level second register unit 203, the shift command signal CMD_E is delayed to the signal CMD_Em and input to the OR gate 52. The waveforms of the initial command signal CMD, the shift command signal CMD_E, and the signal CMD_Em are as follows: Figure 15 As shown. Simultaneously, the signal CMD_O output by the self-masking trigger 502 remains low, excluding any pulses. Therefore, after passing through the M-stage second register unit 203, the signal CMD_Om output by the delay trigger 512 in the M-stage second register unit 203 remains low, excluding any pulses. Thus, one input of the OR gate 52 receives the signal CMD_Em, and the other input receives a continuous low level. Therefore, the delayed command signal CMD_SHIFT output by the OR gate 52 has the same waveform as the signal CMD_Em, and the effective pulse width of the delayed command signal CMD_SHIFT is equal to the effective pulse width of the initial command signal CMD.

[0095] Understandably, the first initial clock signal triggers the initial command signal register to obtain the shift command signal. The AND gate that does not receive the first initial clock signal then masks the other frequency-divided clock signal according to the shift command signal, so that the self-masking module only outputs a single shift command signal. In turn, the delay module can delay the single shift command signal, thereby avoiding the error caused by the simultaneous action of odd and even clock signals, ensuring that the effective pulse width of the final delayed command signal is equal to the effective pulse width of the initial command signal, and improving the accuracy of signal processing.

[0096] In some embodiments of this disclosure, such as Figure 16 As shown, the shielding unit 101 includes: a first inverter N1, a second inverter N2, a first NOR gate NOR1, and a second NOR gate NOR2; both the first NOR gate NOR1 and the second NOR gate NOR2 are two-input NOR gates. The input of the first inverter N1 receives an even clock signal CLK_E, and the output of the first inverter N1 is connected to the first input of the first NOR gate NOR1. The output of the first NOR gate NOR1 is connected to the second input C of the first self-masking flip-flop 501, and the second input of the first NOR gate NOR1 is connected to the first output Q of the second self-masking flip-flop 502. The input of the second inverter N2 receives an odd clock signal CLK_O, and the output of the second inverter N2 is connected to the first input of the second NOR gate NOR2. The output of the second NOR gate NOR2 is connected to the second input C of the second self-masking flip-flop 502, and the second input of the second NOR gate NOR2 is connected to the first output Q of the first self-masking flip-flop 501.

[0097] Combination Figure 16 and Figure 13 When the initial command signal CMD is not triggered and is registered, the CMD_E output from the first output Q of the first self-masking flip-flop 501 and the CMD_O output from the first output Q of the second self-masking flip-flop 502 are both low, meaning that the second input of the second NOR gate NOR2 and the second input of the first NOR gate NOR1 both receive a low level. In this case, the first NOR gate NOR1 and the second NOR gate NOR2 will not produce a shielding effect, the waveforms of the first intermediate clock signal CLK_E1 and the even clock signal CLK_E are the same, and the waveforms of the second intermediate clock signal CLK_O1 and the odd clock signal CLK_O are the same.

[0098] In the effective pulse width c of the initial command signal CMD, the even clock signal CLK_E arrives at the rising edge before the odd clock signal CLK_O (e.g., ...). Figure 13 (As shown by the dashed arrow), the even clock signal CLK_E becomes the first initial clock signal. At this time, the first self-masking flip-flop 501 is triggered by the first intermediate clock signal CLK_E1, registers the initial command signal CMD, and outputs the shift command signal CMD_E to the second input of the second NOR gate NOR2 at its first output terminal Q. Since the shift command signal CMD_E includes a high-level pulse, the second intermediate clock signal CLK_O1 output by the second NOR gate NOR2 remains low during the duration d of the high-level pulse. That is, the odd clock signal CLK_O is masked during the duration d. Consequently, the second intermediate clock signal CLK_O1 will not generate a rising edge to trigger the second self-masking flip-flop 502 to register the initial command signal CMD, and the CMD_O output by the first output terminal Q of the second self-masking flip-flop 502 remains low without including any pulse.

[0099] Correspondingly, if the initial clock signal CLK_O becomes the first initial clock signal, then the second self-masking flip-flop 502 is triggered by the second intermediate clock signal CLK_O1, registers the initial command signal CMD, and the CMD_E output by the first output terminal Q of the first self-masking flip-flop 501 remains at a low level without including any pulses.

[0100] In this embodiment of the disclosure, such as Figure 17 As shown, the delay module 102 may include M-stage second register units 203, where M is an integer greater than or equal to 2. Each stage of the second register unit 203 includes delay triggers 511 and 512, both of which are D flip-flops. In the first stage of the second register unit 203, the first input terminal D of the delay trigger 511 is connected to the first output terminal Q of the self-masking trigger 501, and the first input terminal D of the delay trigger 512 is connected to the first output terminal Q of the self-masking trigger 502. In each stage of the second register unit 203, the second input terminal C of the delay trigger 511 receives the even clock signal CLK_E, and the second input terminal C of the delay trigger 512 receives the odd clock signal CLK_O. Where M is greater than or equal to 2, the first input terminal D of the delay trigger 511 in the i-th stage second register unit 203 is connected to the first output terminal Q of the delay trigger 511 in the previous stage second register unit 203, and the first input terminal D of the delay trigger 512 in the i-th stage second register unit 203 is connected to the first output terminal Q of the delay trigger 512 in the previous stage second register unit 203, i is greater than 1 and less than or equal to M.

[0101] like Figure 17 As shown, the delay module 102 also includes an OR gate 52, which is a two-input OR gate. The delay triggers 511 and 512 in the M-th stage second register unit 203 have their first outputs Q connected one-to-one to the two inputs of the OR gate 52. The output of the OR gate 52 serves as the output of the delay module 102, outputting the delay command signal CMD_SHIFT.

[0102] In this embodiment of the disclosure, combined with Figure 17 and Figure 15 If the even clock signal CLK_E becomes the first initial clock signal, then the initial command signal CMD is registered as the shift command signal CMD_E. Therefore, after passing through the M-level second register unit 203, the shift command signal CMD_E is delayed to the signal CMD_Em and input to the OR gate 52. The waveforms of the initial command signal CMD, the shift command signal CMD_E, and the signal CMD_Em are as follows: Figure 15 As shown.

[0103] Meanwhile, the signal CMD_O output by the self-masking trigger 502 will remain low and will not include any pulses. Therefore, after passing through the M-level second register unit 203, the signal CMD_Om output by the delay trigger 512 in the M-level second register unit 203 will still be low and will not include any pulses.

[0104] Thus, one input of OR gate 52 receives the signal CMD_Em, and the other input receives a continuous low level. Therefore, the delayed command signal CMD_SHIFT output by OR gate 52 has the same waveform as the signal CMD_Em, and the effective pulse width of the delayed command signal CMD_SHIFT is equal to the effective pulse width of the initial command signal CMD.

[0105] Understandably, the first initial clock signal triggers the initial command signal register to obtain the shift command signal. The NOR gate that does not receive the first initial clock signal through the inverter then shields the other frequency-divided clock signal according to the shift command signal, so that the self-shielding module outputs only a single shift command signal. Consequently, the delay module can delay the single shift command signal, thereby avoiding the error caused by the simultaneous action of odd and even clock signals, ensuring that the effective pulse width of the final delayed command signal is equal to the effective pulse width of the initial command signal, and improving the accuracy of signal processing.

[0106] In some embodiments of this disclosure, the initial command signal is active high, and the effective pulse width of the initial command signal is greater than or equal to the period length of each initial clock signal. The initial command signal is a read command from the memory.

[0107] In this embodiment of the disclosure, the initial command signal is normally low, and when the initial command signal contains a high-level pulse, it generates a control effect.

[0108] The effective pulse width of the initial command signal is greater than or equal to the period length of each initial clock signal. This ensures that each initial clock signal reaches the trigger edge at least once within the effective pulse width of the initial command signal, guaranteeing that the initial command signal can always be registered and delayed by the delay circuit provided in this embodiment. The initial command signal can be a read command from the memory, meaning it can be used to control the reading of data from the memory.

[0109] This disclosure also provides a memory 80, such as... Figure 18 As shown, the memory 80 includes the delay circuit 10 provided in the aforementioned embodiments. Figure 18 The memory 80 shown can be a dynamic random access memory (DRAM).

[0110] In some embodiments of this disclosure, such as Figure 19 As shown, the memory 80 is electrically connected to the control module 90, wherein the memory 80 meets the DDR4 specification and the control module 90 meets the DDR5 specification. The memory 80 also includes a frequency divider circuit 81. The memory 80 receives a standard clock signal from the control module 90, divides the standard clock signal into an initial clock signal through the frequency divider circuit 81, and transmits the initial clock signal to the delay circuit 10.

[0111] In this embodiment, the memory 80 conforms to the DDR4 specification, and the control module 90 conforms to the DDR5 specification. The clock signal frequency under the DDR5 specification is twice that under the DDR4 specification. Therefore, the standard clock signal received by the memory 80 from the control module 90 meets the requirements of the DDR5 specification. After the frequency divider circuit 81 divides the standard clock signal into an initial clock signal, the delay circuit 10 can complete the delay of the initial command signal under the DDR4 specification. In other words, the memory 80 is compatible with the DDR5 specification external control module 90 under the DDR4 specification, thus improving the usability of the memory 80.

[0112] Meanwhile, since the clock signal frequency is too high under the DDR5 specification, a frequency-divided clock signal is used to register and delay the read command. In this way, the delay circuit 10 provided in the aforementioned embodiment can ensure that the effective pulse width of the read command before and after the delay is equal, thereby improving the accuracy of signal processing.

[0113] It should be noted that, in this disclosure, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0114] The sequence numbers of the embodiments disclosed above are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments. The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined to obtain new method embodiments without conflict. The features disclosed in the several product embodiments provided in this disclosure can be arbitrarily combined to obtain new product embodiments without conflict. The features disclosed in the several method or device embodiments provided in this disclosure can be arbitrarily combined to obtain new method embodiments or device embodiments without conflict.

[0115] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.< / n> < / n> < / n>

Claims

1. A delay circuit, characterized in that, include: The self-masking module is configured to receive an initial command signal and N initial clock signals, register the initial command signal based on the first initial clock signal that triggers the initial command signal first among the N initial clock signals, mask the other N-1 second initial clock signals among the N initial clock signals, and output N intermediate command signals, where N is an integer greater than or equal to 2; the N initial clock signals have the same frequency but different phases, and the N intermediate command signals include one valid first intermediate command signal and N-1 invalid second intermediate command signals; The delay module, electrically connected to the self-shielding module, is configured to receive N intermediate command signals and N initial clock signals, and delay the output of the N intermediate command signals to obtain a delayed command signal.

2. The delay circuit according to claim 1, characterized in that, The self-shielding module includes: The shielding unit is configured to receive N initial clock signals and output N intermediate clock signals; wherein the N intermediate clock signals include one valid first intermediate clock signal and N-1 invalid second intermediate clock signals; The register unit, electrically connected to the shielding unit, is configured to receive the initial command signal and N intermediate clock signals, register the initial command signal according to the first intermediate clock signal, and obtain and output the N intermediate command signals.

3. The delay circuit according to claim 2, characterized in that, The register unit includes: N self-masking flip-flops; all N self-masking flip-flops are D flip-flops; The first input terminals of all N self-masking triggers receive the initial command signal, and the second input terminals of all N self-masking triggers are connected to the output terminal of the shielding unit. The first self-masking flip-flop among the N self-masking flip-flops receives the first intermediate clock signal, registers the initial command signal according to the first intermediate clock signal, and outputs the first intermediate command signal at its first output terminal. The other N-1 second self-masking flip-flops among the N self-masking flip-flops each receive N-1 second intermediate clock signals and output N-1 second intermediate command signals at their first output terminals.

4. The delay circuit according to claim 3, characterized in that, The shielding unit includes N AND gates, each of which includes a first input terminal and N-1 second input terminals; The first input terminals of the N AND gates are connected to the N initial clock signals in a one-to-one correspondence, and the output terminals of the N AND gates are connected to the second input terminals of the N self-masking flip-flops in a one-to-one correspondence. Each AND gate's N-1 second input terminals are connected one-to-one with the second output terminals of N-1 other self-maskable flip-flops, excluding its corresponding self-maskable flip-flop.

5. The delay circuit according to claim 3, characterized in that, The shielding unit includes: N inverters and N NOR gates; each NOR gate includes a first input terminal and N-1 second input terminals; The input terminals of the N inverters each receive one of the N initial clock signals, the output terminals of the N inverters each connect one of the first input terminals of the N NOR gates, and the output terminals of the N NOR gates each connect one of the second input terminals of the N self-masking flip-flops. Each of the N-1 second input terminals of the NOR gate is connected one-to-one with the first output terminals of N-1 other self-maskable flip-flops other than its corresponding self-maskable flip-flop.

6. The delay circuit according to claim 3, characterized in that, The delay module includes: M-level second register units, where M is an integer greater than or equal to 2; each level of the second register unit includes: N delay triggers; all N delay triggers are D triggers; Each of the N delay triggers in the second register unit of each stage receives the N initial clock signals at its second input terminal. The first input terminals of the N delay triggers in the first stage second register unit are connected one-to-one with the first output terminals of the N self-masking triggers. The N delay flip-flops in the second register unit of the i-th stage have their first input terminals connected one-to-one with the output terminals of the N delay flip-flops in the second register unit of the previous stage, where i is greater than 1 and less than or equal to M.

7. The delay circuit according to claim 6, characterized in that, M = (CL - A) / N, where CL is the maximum number of delay cycles and A is the number of cycles corresponding to the command pre-operation.

8. The delay circuit according to claim 6, characterized in that, The delay module further includes an OR gate, which has N input terminals; The N delay triggers in the second register unit of the Mth stage have their first output terminals connected one-to-one with the N input terminals of the OR gate; the output terminal of the OR gate outputs the delay command signal.

9. The delay circuit according to claim 1, characterized in that, N=2, and the N initial clock signals are odd-even frequency division clock signals, which include odd clock signals and even clock signals; the odd clock signals and the even clock signals have the same frequency and opposite phase.

10. The delay circuit according to claim 9, characterized in that, The self-shielding module includes: a shielding unit and a register unit; The register unit includes: a first self-masking trigger and a second self-masking trigger; both the first self-masking trigger and the second self-masking trigger are D flip-flops; Both the first input terminal of the first self-masking trigger and the first input terminal of the second self-masking trigger receive the command signal.

11. The delay circuit according to claim 10, characterized in that, The shielding unit includes: a first AND gate and a second AND gate; both the first AND gate and the second AND gate are two-input AND gates. The first input terminal of the first AND gate receives the even clock signal, the output terminal of the first AND gate is connected to the second input terminal of the first self-masking flip-flop, and the second input terminal of the first AND gate is connected to the second output terminal of the second self-masking flip-flop. The first input of the second AND gate receives the odd clock signal, the output of the second AND gate is connected to the second input of the second self-masking flip-flop, and the second input of the second AND gate is connected to the second output of the first self-masking flip-flop.

12. The delay circuit according to claim 10, characterized in that, The shielding unit includes: a first inverter, a second inverter, a first NOR gate, and a second NOR gate; both the first NOR gate and the second NOR gate are two-input NOR gates. The input terminal of the first inverter receives the even clock signal, and the output terminal of the first inverter is connected to the first input terminal of the first NOR gate. The output of the first NOR gate is connected to the second input of the first self-masking flip-flop, and the second input of the first NOR gate is connected to the first output of the second self-masking flip-flop. The input terminal of the second inverter receives the odd clock signal, and the output terminal of the second inverter is connected to the first input terminal of the second NOR gate; The output of the second NOR gate is connected to the second input of the second self-masking flip-flop, and the second input of the second NOR gate is connected to the first output of the first self-masking flip-flop.

13. A memory, characterized in that, The memory includes a delay circuit as described in any one of claims 1 to 12.

14. The memory according to claim 13, characterized in that, The memory is electrically connected to the control module, wherein the memory meets the DDR4 specification and the control module meets the DDR5 specification; The memory also includes a frequency divider circuit; the memory receives a standard clock signal from the control module, divides the standard clock signal into an initial clock signal through the frequency divider circuit, and transmits the initial clock signal to the delay circuit.

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