A refresh address generation circuit

Abstract

The embodiment of the present application discloses a refresh address generation circuit, comprising: a refresh control circuit and an address generator. Wherein, the refresh control circuit sequentially receives a plurality of first refresh instructions and correspondingly performs a plurality of first refresh operations, outputs a first clock signal when the number of first refresh operations is less than m, and outputs a second clock signal when the number of first refresh operations is equal to m, m is an integer greater than or equal to 1. The address generator is coupled to the refresh control circuit, used for pre-storing a first address, receiving the first clock signal or the second clock signal, outputting a to-be-refreshed address during each first refresh operation in response to the first clock signal, and changing the first address in response to the second clock signal. The to-be-refreshed address comprises the first address or a second address, and the least significant bit of the second address is opposite to the least significant bit of the first address. The present application can ensure that the refresh operation is carried out without omission, and the integrity of the address is maintained.

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