A manufacturing method and structure of a high temperature resistant short circuit IGBT

Abstract

The invention discloses a method for manufacturing a high-temperature short-circuit IGBT, comprising the following steps: after an active area is photolithographically formed on an N-type silicon substrate, ion implantation is performed to form a carrier storage layer, wherein the implanted ions are phosphorus ions, the implantation dose is 1E+11-1E+13, and the implantation energy is 500KeV-2000KeV; SiO2 with a thickness of 1-4um is deposited as a hard mask by a plasma enhanced chemical vapor deposition method, and then SiO2 is etched after photolithography to remove the photoresist; a groove structure with a depth of 2-8um is obtained by etching the silicon substrate by a dry etching process, the SiO2 hard mask is removed, and a gate oxide layer SiO2 with a thickness of 20-150nm is formed by a thermal oxidation process; the method for manufacturing a high-temperature short-circuit IGBT and the structure thereof provided by the invention have the advantages of reducing the dependence of Vth on increasing temperature.

Description

Technical Field

[0001] The present invention relates to the field of semiconductors, and in particular to a manufacturing method and structure of a high temperature resistant short circuit IGBT with a novel gate dielectric. Background Art

[0002] At present, my country's new power electronic devices mainly include VDMOS and IGBT devices, and the main representatives of new material power electronic devices are SiC and GaN devices. SiC is a typical wide bandgap semiconductor material with the characteristics of large bandgap width, high critical electric field, high carrier saturation velocity, stable physical and chemical properties, high hardness, good thermal stability and high thermal conductivity. It is very suitable for making high-temperature, radiation-resistant, high-frequency, high-power and high-density integrated power electronic devices. IGBT (Insulated Gate Bipolar Transistor), insulated gate bipolar transistor, is a new type of composite power device developed on the basis of MOSFET and BJT. It combines the advantages of both, with MOS input and bipolar output functions, and integrates the advantages of BJT devices such as small on-state voltage drop, high current density, high withstand voltage and power MOSFET with small driving power, fast switching speed, high input impedance and good thermal stability. Since its advent, it has quickly developed into a mainstream power switching device in the field of medium and high power power electronics. It has been widely used in industrial control, automotive electronics, home appliances, network communications and other fields.

[0003] See also Figure 1 , Figure 1 It is a conventional trench gate field dielectric IGBT structure. The gate dielectric of a conventional IGBT is a layer of silicon dioxide generated by thermal oxidation. The threshold voltage Vth of the device will decrease with increasing temperature. Therefore, when the temperature is too high during IGBT operation, the device will not be able to shut down and fail. Especially under short-circuit and high current conditions, the IGBT temperature rises rapidly and Vth further decreases, the gate loses its ability to shut down the device, and finally causes the device to fail. Summary of the invention

[0004] The present invention provides a manufacturing method of a high temperature short circuit resistant IGBT with a novel gate dielectric and a structure thereof, which has the advantage of reducing the dependency of Vth decreasing with increasing temperature and solves the problems existing in the prior art.

[0005] According to an embodiment of the present application, a method for manufacturing a high temperature short-circuit IGBT with a novel gate dielectric is provided, comprising the following steps:

[0006] After the active area is photolithographically formed on the N-type silicon substrate, ion implantation is performed to form a carrier storage layer. The implanted ions are phosphorus ions, the implantation dose is 1E+11~1E+13, and the implantation energy is 500KeV-2000KeV. SiO2 with a thickness of 1-4um is deposited as a hard mask by plasma enhanced chemical vapor deposition, and then SiO2 is etched after photolithography to remove the photoresist.

[0007] The silicon substrate is etched by dry etching process to obtain a trench structure with a depth of 2-8um, the SiO2 hard mask is removed, and then a gate oxide layer SiO2 with a thickness of 20-150nm is formed by thermal oxidation process;

[0008] The ferroelectric material P (VDF–TrFE) is deposited by magnetron sputtering with a thickness of 50-500 nm, and then polysilicon is deposited to fill the trenches and then the surface polysilicon is removed by etching;

[0009] A P base region is formed on the upper layer of the substrate by photolithography and P-type ion implantation, and a high-temperature push-in junction is performed after debonding. The P-type ions implanted are boron ions, with an implantation dose of 5E+12~5E+14 and an implantation energy of 20-2000KeV. An N+ emitter is formed by photolithography and N-type ion implantation. The N-type ions implanted are phosphorus or arsenic ions, with an implantation dose of 1E+14~1E+16 and an implantation energy of 60-1000KeV. Annealing is performed after debonding.

[0010] USG and BPSG are deposited as isolation dielectric layers with a total thickness of 1-4um. Contact holes are etched by photolithography, and P+ contacts are formed by ion implantation. The first BF2 is injected with an injection dose of 5E+13~1E+16 and an injection energy of 20-120KeV. The second boron ion is injected with an injection dose of 5E+13~1E+16 and an injection energy of 20-120KeV. Annealing is performed to activate impurities and deposit the top metal.

[0011] Preferably, the method further comprises the following steps:

[0012] Phosphorus ions are implanted on the back of the N-type silicon substrate to form a field dielectric layer, wherein the implantation dose is 5E+11~1E+14 and the implantation energy is 200-1000KeV;

[0013] Or a field dielectric layer is formed by hydrogen ion implantation, and then boron ions are implanted to form a P+ collector. The implantation dose is 1E+12~1E+15, and the implantation energy is 20-120KeV.

[0014] The present invention also provides a structure of a high temperature short-circuit resistant IGBT with a new gate dielectric, which is manufactured according to the above-mentioned manufacturing method of a high temperature short-circuit resistant IGBT with a new gate dielectric. The structure of the high temperature short-circuit resistant IGBT with a gate dielectric is composed of a stacked structure of silicon dioxide and ferroelectric material P (VDF–TrFE) as the gate dielectric layer.

[0015] The technical solution provided by the embodiments of the present application may have the following beneficial effects:

[0016] The present invention uses a stacked structure of silicon dioxide plus a ferroelectric material P (VDF-TrFE) as the gate dielectric of the IGBT. The dielectric constant of P (VDF-TrFE) decreases with increasing temperature after exceeding a certain temperature, and the capacitance of the corresponding gate dielectric layer decreases, and Vth increases. Therefore, the introduction of the stacked structure of silicon dioxide plus a ferroelectric material P (VDF-TrFE) greatly reduces the dependence of Vth decreasing with increasing temperature, and increases the short-circuit safe operating area (SCSOA) of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying any creative work.

[0018] Figure 1 It is a schematic diagram of the structure of a conventional trench gate field dielectric IGBT in the prior art of the present invention;

[0019] Figure 2-Figure 8 The present invention is a schematic structural diagram of each step of a method for manufacturing a high temperature short circuit resistant IGBT with a novel gate dielectric. DETAILED DESCRIPTION

[0020] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0021] It should also be understood that the terms used in this specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. As used in the specification of the present invention and the appended claims, unless the context clearly indicates otherwise, the singular forms "a", "an" and "the" are intended to include plural forms.

[0022] It should be further understood that the term "and / or" used in the present description and the appended claims refers to and includes any and all possible combinations of one or more of the associated listed items.

[0023] The stacked structure of silicon dioxide plus ferroelectric material P (VDF–TrFE) is used as the gate dielectric layer, such as Figure 2 As shown in the figure, the dependence of the IGBT's Vth decreasing with increasing temperature is reduced, thereby improving the short-circuit capability of the device.

[0024] The present invention provides a method for manufacturing a high temperature resistant short circuit IGBT with a novel gate dielectric, comprising the following steps:

[0025] After the active area is photolithographically formed on the N-type silicon substrate (N-sub), ion implantation is performed to form a carrier storage layer (CS layer), wherein the implanted ions are phosphorus ions, the implantation dose is 1E+11~1E+13, and the implantation energy is 500KeV-2000KeV. SiO2 with a thickness of 1-4um is deposited as a hard mask by plasma enhanced chemical vapor deposition (PECVD), and then SiO2 is etched after photolithography. After removing the photoresist, the following is obtained Figure 3 structure;

[0026] The silicon substrate is etched by dry etching to obtain a trench structure with a depth of 2-8um, the SiO2 hard mask is removed, and then a gate oxide layer SiO2 with a thickness of 20-150nm is formed by thermal oxidation process. Figure 4 As shown;

[0027] Ferroelectric material P (VDF–TrFE) is deposited by magnetron sputtering process with a thickness of 50-500nm, and then polysilicon is deposited to fill the trench and then the surface polysilicon is etched away, such as Figure 5 As shown;

[0028] A P base region is formed on the upper layer of the substrate by photolithography and P-type ion implantation, and a high-temperature push junction is performed after debonding. The P-type ions implanted are boron ions, the implantation dose is 5E+12~5E+14, the implantation energy is 20-2000KeV, the temperature of the high-temperature push junction is 1000-1200℃, and the time is 30-600min. An N+ emitter is formed by photolithography and N-type ion implantation, and the N-type ions implanted are phosphorus or arsenic ions, the implantation dose is 1E+14~1E+16, and the implantation energy is 60-1000KeV. After debonding, annealing is performed at a temperature of 800-1000℃ for 30s-60min to obtain a structure such as Figure 6 As shown;

[0029] Deposit USG and BPSG as isolation dielectric layers with a total thickness of 1-4um, etch contact holes by photolithography, and form P+ contacts by ion implantation. The first BF2 implantation has an implantation dose of 5E+13~1E+16 and an implantation energy of 20-120KeV. The second boron ion implantation has an implantation dose of 5E+13~1E+16 and an implantation energy of 20-120KeV. Annealing is performed to activate impurities at a temperature of 800-1000℃ for 30s-60min. Deposit the top metal layer, such as Figure 7 As shown;

[0030] Phosphorus ions are injected into the back of N-sub to form a field stop layer (FS layer), where the injection dose is 5E+11~1E+14 and the injection energy is 200-1000KeV. The FS layer can also be formed by hydrogen ion injection. Boron ions are then injected to form the P+ collector, with an injection dose of 1E+12~1E+15 and an injection energy of 20-120KeV. Figure 8 shown.

[0031] The present invention also provides a structure of a high temperature short-circuit resistant IGBT with a new gate dielectric, which is made according to the above-mentioned manufacturing method of a high temperature short-circuit resistant IGBT with a new gate dielectric. The structure of the high temperature short-circuit resistant IGBT with a gate dielectric is composed of a stacked structure of silicon dioxide and ferroelectric material P as the gate dielectric layer.

[0032] The technical solution provided by the embodiments of the present application may have the following beneficial effects:

[0033] The present invention uses a stacked structure of silicon dioxide plus a ferroelectric material P (VDF-TrFE) as the gate dielectric of the IGBT. The dielectric constant of P (VDF-TrFE) decreases with increasing temperature after exceeding a certain temperature, and the capacitance of the corresponding gate dielectric layer decreases, and Vth increases. Therefore, the introduction of the stacked structure of silicon dioxide plus a ferroelectric material P (VDF-TrFE) greatly reduces the dependence of Vth decreasing with increasing temperature, and increases the short-circuit safe operating area (SCSOA) of the device.

[0034] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any technician familiar with the technical field can easily think of various equivalent modifications or replacements within the technical scope disclosed by the present invention, and these modifications or replacements should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention shall be based on the protection scope of the claims.

Claims

1. A method for manufacturing a high temperature resistant short circuit IGBT, comprising the following steps: After the active area is photolithographically formed on the N-type silicon substrate, ion implantation is performed to form a carrier storage layer. The implanted ions are phosphorus ions, the implantation dose is 1E+11~1E+13, and the implantation energy is 500KeV-2000KeV. SiO2 with a thickness of 1-4um is deposited as a hard mask by plasma enhanced chemical vapor deposition, and then SiO2 is etched after photolithography to remove the photoresist. The silicon substrate is etched by dry etching process to obtain a trench structure with a depth of 2-8um, the SiO2 hard mask is removed, and then a gate oxide layer SiO2 with a thickness of 20-150nm is formed by thermal oxidation process; The ferroelectric material P (VDF–TrFE) is deposited by magnetron sputtering with a thickness of 50-500 nm, and then polysilicon is deposited to fill the trenches and then the surface polysilicon is removed by etching; A P base region is formed on the upper layer of the substrate by photolithography and P-type ion implantation, and a high-temperature push-in junction is performed after debonding. The P-type ions implanted are boron ions, with an implantation dose of 5E+12~5E+14 and an implantation energy of 20-2000KeV. An N+ emitter is formed by photolithography and N-type ion implantation. The N-type ions implanted are phosphorus or arsenic ions, with an implantation dose of 1E+14~1E+16 and an implantation energy of 60-1000KeV. Annealing is performed after debonding. Deposit an isolation dielectric layer with a total thickness of 1-4um, etch contact holes by photolithography, and form P+ contacts by ion implantation. The first BF2 injection has an injection dose of 5E+13~1E+16 and an injection energy of 20-120KeV. The second boron ion injection has an injection dose of 5E+13~1E+16 and an injection energy of 20-120KeV. Annealing is performed to activate impurities and deposit the top metal.

2. The method for manufacturing a high temperature resistant short circuit IGBT according to claim 1, characterized in that: The following steps are also included: Phosphorus ions are implanted on the back of the N-type silicon substrate to form a field dielectric layer, wherein the implantation dose is 5E+11~1E+14 and the implantation energy is 200-1000KeV; Alternatively, a field dielectric layer is formed by hydrogen ion implantation, and then boron ions are implanted to form a P+ collector. The implantation dose is 1E+12~1E+15, and the implantation energy is 20-120KeV.

3. A structure of a high temperature resistant short circuit IGBT, manufactured according to the method for manufacturing a high temperature resistant short circuit IGBT according to claim 2, characterized in that: The structure of the high temperature resistant short circuit IGBT comprises a stacked structure of silicon dioxide and ferroelectric material P (VDF-TrFE) as a gate dielectric layer.

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