High-speed, high-density ferroelectric memory, its fabrication methods and applications

Abstract

This invention discloses a high-speed, high-density ferroelectric memory, its fabrication method, and its applications, belonging to the field of semiconductor memories. The memory consists of an array of multiple memory cells, with substantially orthogonal word lines and bit lines connecting the two sides of the array. The memory cells of this invention employ a stacked structure of a top electrode, a varactor dielectric layer, an intermediate metal layer, a ferroelectric dielectric layer, and a bottom electrode. Electrically, this is equivalent to a ferroelectric capacitor connected in series with a varactor selector. By adjusting the voltage division relationship of the memory cells, the voltage division of the ferroelectric capacitor in the unselected cells is reduced, thus reducing its disturbance. Furthermore, the series capacitors reduce the RC delay of the memory cells, improving memory access speed. Therefore, this invention reduces the disturbance of unselected cells, increases the memory's storage window, reduces the memory's bit error rate, and improves memory access speed without increasing additional area overhead.

Description

Technical Field

[0001] This invention relates to the field of semiconductor memory, and in particular to a high-speed, high-density ferroelectric memory. Background Technology

[0002] With the continuous advancement of electronic information technology, the demand for low-power, high-capacity memory is constantly increasing. Traditional flash memory utilizes the principle of charge storage and employs hot electron injection and FN tunneling for erasing and writing, resulting in high power consumption and long erase / write times. Traditional dynamic random access memory (DRAM), on the other hand, suffers from short memory retention times due to transistor leakage, requiring high-frequency refresh rates and leading to significant dynamic power consumption. Today, with the continuous development of the Internet of Things, artificial intelligence, and big data, these problems will become increasingly severe.

[0003] Ferroelectric materials, due to their asymmetric lattice structure, exhibit spontaneous polarization charges that can be controlled by an electric field, and the polarization reversal rate depends on the lattice relaxation time. Therefore, memories designed based on ferroelectric materials have the advantages of low power consumption and high speed. However, traditional ferroelectric materials based on perovskite structures (such as PZT and BTO) have complex compositions, low CMOS process compatibility, and significant size effects, making them unsuitable for integration in advanced process nodes. As a result, memories based on traditional ferroelectric materials are only used in certain special edge applications.

[0004] In recent years, researchers have discovered that CMOS-compatible hafnium oxide (HfO2) thin films can induce ferroelectricity under specific doping, stress, and annealing conditions, breaking the constraints of poor integration and miniaturization of ferroelectric material devices. Among different types of hafnium oxide-based ferroelectric memories, cross-matrix memories based on ferroelectric capacitors have high storage density, enabling high-speed data read and write, and exhibiting good data retention and low power consumption, making them a promising alternative to traditional DRAM. However, further research has revealed that HfO2-based ferroelectric materials possess polycrystalline and multi-domain characteristics, and their ferroelectric domains have a wide coercive field distribution. This results in significant perturbations to unselected cells during write and read operations on selected cells in the array, easily causing severe bit-flipping problems. In existing technologies, a resistive switching device (RSD) is connected in series with the gate of a ferroelectric transistor. The varying resistance of the RSD at different voltages increases the RC delay at the gate of the unselected cell, thereby reducing the equivalent gate disturbance voltage. However, this disturbance suppression scheme for ferroelectric transistors does not fully consider the characteristic that semiconductor capacitance changes under different voltages. Furthermore, connecting the RSD in series also increases the RC delay of the selected cell, reducing memory access speed. Therefore, realizing a high-speed, low-disturbance ferroelectric cross-matrix memory has become an urgent problem to be solved. Summary of the Invention

[0005] The purpose of this invention is to propose a high-speed, high-density ferroelectric memory with a lower bit error rate and a larger storage window.

[0006] The specific technical solution of this invention is as follows:

[0007] A ferroelectric capacitor memory based on a cross-matrix structure is characterized in that the memory consists of an array of multiple memory cells, and the two sides of the memory cell array are connected by substantially orthogonal word lines and bit lines; the memory cell is composed of multiple layers of stacked materials, which are arranged from top to bottom as a top electrode, a varactor dielectric layer, an intermediate metal layer, a ferroelectric dielectric layer and a bottom electrode. By simultaneously applying positive and negative half-select voltages to the word / bit line, the memory cell connected to the word / bit line can complete the read and write operations.

[0008] The storage cell structure of this invention employs a top electrode, a varactor dielectric layer, an intermediate metal layer, a ferroelectric dielectric layer, and a bottom electrode, which is electrically equivalent to a ferroelectric capacitor connected in series with a varactor selector. When the voltage applied to the storage cell does not exceed a certain limit, the varactor selector is in a low capacitance state. When the voltage is high enough, metal atoms migrate and form metal filaments in the varactor dielectric layer, reducing the equivalent spacing between the plates and significantly increasing the capacitance value of the varactor selector. The ferroelectric dielectric layer has a spontaneous polarization intensity that can be reversed by an applied voltage, enabling non-volatile data storage.

[0009] When a positive and negative half-select voltage is applied simultaneously to a pair of word / bit lines, the memory cell connected to that word / bit line receives twice the half-select voltage, i.e., the full-swing voltage. This memory cell becomes the selected memory cell, and its varactor selector becomes high-capacitance. Most of the voltage drop is across the ferroelectric capacitor, causing the ferroelectric capacitor to spontaneously polarize and flip, thus selecting the memory cell to complete the read / write operation. Other memory cells connected to the corresponding word / bit lines are disturbed memory cells, affected by one half-select voltage. The voltage applied to the disturbed memory cells cannot cause their varactor selectors to become high-capacitance. Therefore, most of the voltage drop of the disturbed memory cells is across the low-capacitance varactor selector, thereby reducing the voltage drop across the ferroelectric capacitor in the disturbed memory cells and reducing the disturbance caused by the half-select voltage to the disturbed memory cells.

[0010] The top electrode in the aforementioned memory cell is made of a material that readily undergoes electromigration in the dielectric layer, preferably Ag. To provide sufficient stress during annealing to allow ferroelectric crystal formation in the ferroelectric dielectric layer, the intermediate metal layer and bottom electrode can be selected from the following: TiN, TaN, Pt, Mo, Ru, W, etc. The variable capacitance dielectric layer is based on HfO2 or TaO. xThe dielectric material can produce a varactor effect and has metal barrier intercalation layers such as SiO2 to prevent conduction; the ferroelectric dielectric layer: adopts traditional ferroelectric materials such as perovskite ferroelectric (PZT, BFO, SBT) and ferroelectric polymer (P(VDF-TrFE)) or novel ferroelectric materials based on HfO2 to produce ferroelectricity under specific treatments (doping, stress, annealing, etc.). In the above-mentioned ferroelectric capacitor memory based on cross-matrix, the electrode thickness is preferably 10-100 nm; the thickness of the varactor dielectric layer and the ferroelectric dielectric layer is preferably 8-15 nm.

[0011] The present invention further provides an electronic device including the above-described cross-matrix ferroelectric capacitor memory.

[0012] The beneficial effects of the cross-matrix ferroelectric capacitor memory of the present invention are as follows:

[0013] When accessing a memory cell in a cross-matrix ferroelectric capacitor memory, positive and negative half-select voltages are applied to the corresponding word / bit line of that memory cell. The selected memory cell receives a full-swing voltage (twice the half-select voltage), causing its varactor selector to become high-capacitance. This causes most of the voltage to drop across the ferroelectric capacitor of the memory cell, resulting in a ferroelectric polarization reversal and completing the read / write operation. Meanwhile, the disturbed memory cell connected to the same word / bit line is subjected to a single half-select voltage, keeping its varactor selector in a low-capacitance state. This also causes most of the voltage to drop across the varactor selector, reducing the voltage drop across the ferroelectric capacitor. This reduces the disturbance of the half-select voltage to the information stored in the ferroelectric capacitor, lowers the memory error rate, and increases the memory window. Furthermore, since the memory cell is composed of two capacitors connected in series, the overall capacitance is low, resulting in lower RC delay during memory access and improved access speed. Compared to traditional cross-matrix ferroelectric capacitor memories, the memory of this invention has smaller read / write disturbances, a lower error rate, and a larger memory window. Attached Figure Description

[0014] Figure 1 This is a schematic diagram of a cross-matrix ferroelectric capacitor memory based on a variable capacitance selector according to an embodiment of the present invention.

[0015] In the picture:

[0016] 1—Substrate; 2—Bit Line (BL)

[0017] 3 – Word Line (WL) 4 – Storage Cell (SC)

[0018] Figure 2 This is a cross-sectional schematic diagram of a single storage cell according to an embodiment of the present invention.

[0019] In the picture:

[0020] 5 – Top Electrode (TE) 6 – Upper Dielectric (UD)

[0021] 7 – Middle Electrode (ME) – 8 – Lower Dielectric (LD) –

[0022] 9—Bottom Electrode, BE Detailed Implementation

[0023] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0024] like Figure 1 As shown, this embodiment provides a cross-matrix ferroelectric capacitor memory, which consists of multiple memory cells arranged in an array, with the two sides of the memory cell array connected by substantially orthogonal word lines and bit lines. Wherein, as Figure 2 As shown, each memory cell consists of a top electrode TE, a varactor dielectric layer UD, an intermediate metal layer ME, a ferroelectric dielectric layer LD, and a bottom electrode BE, from top to bottom. The top electrode layer is preferably Ag; the intermediate metal layer and the bottom electrode are made of TiN, TaN, Pt, Mo, Ru, W, etc. The varactor dielectric layer is based on HfO2 or TaO. x The method combines a dielectric material capable of producing a varactor effect with a SiO2 metal barrier intercalation layer. The ferroelectric dielectric layer utilizes traditional ferroelectric materials such as perovskite ferroelectrics (PZT, BFO, SBT) and ferroelectric polymers (P(VDF-TrFE)), or novel ferroelectric materials based on HfO2 that exhibit ferroelectricity under specific treatments (doping, stress, annealing, etc.). The thickness of the top or bottom electrode layer is preferably 10–100 nm; the thickness of the varactor and ferroelectric dielectric layers is preferably 8–15 nm. This embodiment also provides a method for fabricating the aforementioned cross-matrix ferroelectric capacitor memory, the fabrication process of which is as follows:

[0025] (1) The bottom electrode material was prepared on a SiO2 substrate by physical vapor deposition (PVD);

[0026] (2) Define the bottom electrode pattern by photolithography and form the bottom electrode by wet etching or dry etching;

[0027] (3) A ferroelectric material is grown on the surface of the bottom electrode prepared in step (2) by atomic layer deposition (ALD);

[0028] (4) Define the intermediate layer metal pattern using photolithography;

[0029] (5) An intermediate metal material is grown on a patterned photoresist by PVD;

[0030] (6) The intermediate metal layer is peeled off and shaped by removing adhesive;

[0031] (7) Continue to grow the deformable medium material by ALD;

[0032] (8) Define the top electrode pattern using photolithography;

[0033] (9) The top electrode metal material is grown on a patterned photoresist by PVD;

[0034] (10) The top electrode is peeled and shaped by removing adhesive;

[0035] (11) Crystallization by rapid thermal annealing (RTA) under certain conditions causes the variable capacitance dielectric material to crystallize and the ferroelectric dielectric material to produce ferroelectricity.

[0036] (12) Photolithography defines the position of the bottom electrode contact hole;

[0037] (13) Etch to expose the bottom electrode for contact.

[0038] For example, when accessing a memory cell, a positive half-select voltage V is applied to the word line containing that memory cell. dd / 2, apply a negative half-select voltage -V to the corresponding bit line dd / 2, other word / bit lines are grounded. At this time, the selected memory cell is subjected to a full-swing voltage V. dd In this memory cell, the varactor selector becomes high-capacitance, causing most of the voltage drop across the ferroelectric capacitor, enabling information writing or reading from the ferroelectric capacitor; simultaneously, the disturbed memory cell on the same word / bit line is subjected to a half-select voltage V. dd Due to the influence of / 2, its varactor selector maintains a low capacitance state, resulting in most of the voltage drop across the varactor selector. The voltage drop across the ferroelectric capacitor is very small, reducing the disturbance of the half-select voltage to the stored information.

[0039] The beneficial effects of the present invention are illustrated in this embodiment:

[0040] Conventional ferroelectric cross-matrix capacitor memories suffer from severe half-selection voltage disturbances, resulting in high bit error rates and small memory windows. This invention addresses this issue by employing a stacked structure of a top electrode, a varactor dielectric layer, an intermediate metal layer, a ferroelectric dielectric layer, and a bottom electrode. This reduces the voltage drop across unselected cells, thus minimizing disturbances. Furthermore, it reduces cell RC delay, improving memory access speed. In summary, this invention, without increasing area overhead, improves the memory's memory window, reduces the bit error rate, and enhances access speed.

[0041] Finally, it should be noted that the purpose of disclosing the embodiments is to help further understand the present invention. However, those skilled in the art will understand that various substitutions and modifications are possible without departing from the spirit and scope of the present invention and the appended claims. Therefore, the present invention should not be limited to the content disclosed in the embodiments, and the scope of protection of the present invention is defined by the claims.

Claims

1. A cross-matrix ferroelectric capacitor memory, characterized in that, The memory consists of an array of multiple memory cells connected on both sides by substantially orthogonal word lines and bit lines. Each memory cell is constructed from multiple layers of stacked materials, consisting of a top electrode, a varactor dielectric layer, an intermediate metal layer, a ferroelectric dielectric layer, and a bottom electrode, from top to bottom. The varactor dielectric layer is based on HfO2 or TaO. x The combination of a variable capacitance dielectric material and a SiO2 metal barrier intercalation layer, wherein the ferroelectric dielectric layer is made of perovskite ferroelectric material, ferroelectric polymer material, or ferroelectric material based on HfO2 that generates ferroelectricity after treatment, the thickness of the variable capacitance dielectric layer or ferroelectric dielectric layer is 8~15nm, the top electrode is made of Ag, and the middle metal layer and bottom electrode are made of TiN, TaN, Pt, Mo, Ru or W, the thickness of the top electrode, bottom electrode or middle metal layer is 10~100nm. When a positive / negative half-select voltage is applied to a pair of word / bit lines at the same time, the memory cell connected to the word / bit line at the same time receives twice the half-select voltage, and this memory cell is the selected memory cell. The selected memory cell completes the read and write operation. Other memory cells corresponding to the word / bit lines are disturbed memory cells.

2. A method for fabricating a cross-matrix ferroelectric capacitor memory as described in claim 1, comprising the following steps: 1) The bottom electrode material is prepared on the substrate by physical vapor deposition; 2) Define the bottom electrode pattern using photolithography, and form the bottom electrode using wet etching or dry etching methods; 3) Ferroelectric materials are grown on the surface of the bottom electrode via atomic layer deposition; 4) Define the intermediate metal pattern using photolithography; 5) An intermediate metal layer is grown on a patterned photoresist using physical vapor deposition; 6) The intermediate metal layer is peeled off and shaped by removing the adhesive; 7) Continue to grow deformable dielectric materials using atomic layer deposition (ALD). 8) Define the top electrode pattern using photolithography; 9) A top electrode metal layer is grown on a patterned photoresist using physical vapor deposition. 10) The top electrode is peeled and shaped by removing the adhesive; 11) Rapid thermal annealing crystallizes the variable capacitance dielectric material, and the ferroelectric dielectric material develops ferroelectricity. 12) Photolithography defines the location of the bottom electrode contact hole; 13) Etch to expose the bottom electrode for contact.

3. An electronic device, characterized in that, Including the cross-matrix ferroelectric capacitor memory as described in claim 1.

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