Semiconductor structure and method of forming the same

Abstract

The semiconductor structure and the forming method thereof, the forming method comprises the following steps: forming a barrier layer above the substrate, above the dummy gate structure, and on the sidewall of the dummy gate structure and one side of the stack structure; forming a source layer on the other sidewall of the stack structure and the dummy gate structure on both sides of the dummy gate structure; removing the barrier layer to form an interlayer dielectric layer covering the source layer; forming a non-planar drain layer on the sidewall of the barrier layer in the stack structure; sequentially forming a non-planar bottom electrode layer and a variable resistance layer above the interlayer dielectric layer, above the dummy gate structure and above the drain layer; forming a top electrode layer above the variable resistance layer and exposing the top of the dummy gate structure, the interlayer dielectric layer and the variable resistance layer; removing the dummy gate structure to form a gate opening and expose the stack structure and the isolation layer; removing the sacrificial layer in the channel stack to form a through slot; filling the gate structure in the gate opening and the through slot. By using the above scheme, the electrical performance of the semiconductor structure can be improved.

Description

Technical Field

[0001] This specification relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a method for forming the same. Background Technology

[0002] Resistive random access memory (RRAM) is a novel type of non-volatile memory that uses controllable resistance changes to store data. It consists of a top electrode, a resistive switching layer, and a bottom electrode. Data can be written to and erased by applying voltages of different magnitudes or polarities across the resistive switching layer.

[0003] Currently, Resistive Random Access Memory (RRAM) is typically coupled to active devices in semiconductor devices via a metal-insulator-metal structure to form a resistive random access memory device that communicates with external circuits. However, the RRAM formed using this method has a planar structure, and when it is in operation, the conductive path can be turned on at any position of the resistive switching layer, making the entire conduction process uncontrollable and resulting in poor electrical performance of the formed semiconductor device. Summary of the Invention

[0004] The problem addressed by the embodiments in this specification is to provide a semiconductor structure and a method for forming the same, thereby improving the electrical performance of the semiconductor structure.

[0005] To address the aforementioned problems, this specification provides a semiconductor structure comprising: a substrate; a channel structure layer located above the substrate, comprising one or more channel layers spaced apart from bottom to top; an isolation layer located on the substrate and exposing the channel structure layer; a gate structure located above the isolation layer, spanning and surrounding the channel structure layer, the gate structure filling the spaces between adjacent channel layers and between the channel layers and the substrate; inner sidewalls located between the channel layers, with the outer surfaces of the inner sidewalls vertically flush with the end faces of the channel layers; and a drain layer, L-shaped, located above the substrate and... The channel structure layer is located on one sidewall of the gate structure and is in contact with the end of the channel layer along the extension direction; the bottom electrode layer is located above the L-shaped drain layer and is in contact with the sidewall of the gate structure; the resistive switching layer is located above the bottom electrode layer, and the L-shaped drain layer, the bottom electrode layer, and the resistive switching layer are all non-planar structures; the top electrode layer is located above the resistive switching layer; the source layer is located above the substrate and on the sidewall of the channel structure layer and the gate structure on the other side, and is in contact with the end of the channel layer along the extension direction; the interlayer dielectric layer is located above the source layer and is in contact with the gate structure.

[0006] Accordingly, embodiments of this specification also provide a method for forming a semiconductor structure, comprising: providing a substrate, including a substrate and a stacked structure located above the substrate, the stacked structure including one or more channel stacks stacked sequentially from bottom to top, the channel stack including a sacrificial layer and a channel layer located above the sacrificial layer, an isolation layer being formed on the substrate, and the isolation layer exposing the stacked structure; forming a dummy gate structure across the stacked structure on the isolation layer; forming trenches within the stacked structures on both sides of the dummy gate structure, the trenches being located within the sacrificial layer; forming inner sidewalls within the trenches, the outer surfaces of the formed inner sidewalls being vertically flush with the end faces of the channel layers; forming a barrier layer on the sidewalls above the substrate, above the dummy gate structure, and on one side of the dummy gate structure and the stacked structure; and forming the stacked structures and the dummy gate junction on both sides of the dummy gate structure. A source layer is formed on the other sidewall of the structure; the barrier layer is removed to form an interlayer dielectric layer covering the source layer; a non-planar drain layer is formed on the sidewall of the barrier layer in the stacked structure; a non-planar bottom electrode layer and a resistive switching layer are sequentially formed above the interlayer dielectric layer, above the dummy gate structure, and above the drain layer; a top electrode layer is formed above the resistive switching layer, exposing the top of the dummy gate structure, the interlayer dielectric layer, and the resistive switching layer; the dummy gate structure is removed to form a gate opening, exposing the stacked structure and the isolation layer; the sacrificial layer in the channel stack is removed to form a through-slot, which is surrounded by adjacent channel layers or by the channel layers and the isolation layer; a gate structure is filled in the gate opening and the through-slot, the gate structure surrounding the channel layer, and the gate structure is located on top of the isolation layer and spans the channel layer.

[0007] Compared with the prior art, the technical solutions of the embodiments in this specification have the following advantages:

[0008] In the semiconductor structure provided in the embodiments of this specification, the drain layer is located above the substrate and on the sidewall of the channel structure layer and the gate structure on one side. The source layer is located above the substrate and on the sidewall of the channel structure layer and the gate structure on the other side. Both are in contact with the end of the channel layer along the extension direction. By placing the source layer and drain layer on the sidewalls of the gate structure on both sides, the formed drain layer can be controlled to be an L-shaped non-planar structure. This makes the bottom electrode layer above the drain layer and the resistive switching layer above the bottom electrode layer non-planar structures. Through the gate structure, the resistive switching layer can be electrically connected to the substrate. Therefore, when the semiconductor device is working, the conduction path can be controlled by controlling the voltage magnitude or polarity on the resistive switching layer with the non-planar structure, thereby improving the electrical performance of the semiconductor device.

[0009] In the semiconductor structure formation method provided in the embodiments of this specification, after forming trenches in the stacked structures on both sides of the dummy gate structure, a barrier layer is formed above the substrate, above the dummy gate structure, and on one side wall of the dummy gate structure and the stacked structure. This allows space to be occupied for the subsequent formation of the drain layer. Furthermore, by first forming a source layer on the other side wall of the stacked structures on both sides of the dummy gate structure and forming an interlayer dielectric layer covering the source layer, damage to the source layer can be avoided. Subsequently, by forming a non-planar L-shaped drain layer on the side wall of the barrier layer in the stacked structure, both the bottom electrode layer and the resistive switching layer are non-planar structures. By filling the gate opening and the through trench with a gate structure, electrical connection between the resistive switching layer and the substrate can be achieved. Thus, when the semiconductor device is operating, the conduction path can be controlled by controlling the voltage magnitude or polarity on the resistive switching layer with the non-planar structure, thereby improving the electrical performance of the semiconductor device. Attached Figure Description

[0010] Figure 1 This is a schematic diagram of a semiconductor structure.

[0011] Figure 2 This is a schematic diagram of a semiconductor structure according to an embodiment of the present invention;

[0012] Figures 3 to 28 This is a schematic diagram of another embodiment of the semiconductor structure of the present invention. Detailed Implementation

[0013] As the background technology shows, the performance of resistive random access memory (IRRAM) devices still needs improvement. This paper analyzes the reasons why the performance of IRRAM devices needs further improvement, using a specific semiconductor structure as an example. Figure 1 This is a schematic diagram of a semiconductor structure.

[0014] The semiconductor structure includes: a substrate, comprising a substrate 10 and an active region 11 located on the substrate 10, and a source / drain doped layer 12 surrounding the active region 11; a gate layer 13 located above the substrate 10; a channel structure layer 14 located on the gate layer 13; a gate structure 15 located above the substrate 10 and in contact with the channel structure layer 14; a conductive plug 16 located inside the gate structure 15; a metal-insulator-metal structure 17 located above the gate structure 15 and electrically connected to the conductive plug 16; a bottom electrode layer 18 electrically connected to the metal-insulator-metal structure 17; a resistive switching layer 19 located above the bottom electrode layer 18; and a top electrode layer 20 located above the resistive switching layer 19 and electrically connected to the metal-insulator-metal structure 17.

[0015] With the above semiconductor structure, since the bottom electrode layer 18, resistive switching layer 19 and top electrode layer 20, which are electrically connected to the substrate 10 through the metal-insulator-metal structure 17, are all planar structures, when the semiconductor device is working, the conductive path can be turned on at any position of the resistive switching layer 19, making the entire conduction process uncontrollable, resulting in poor electrical performance of the formed semiconductor device.

[0016] To solve the above-mentioned technical problems, in the semiconductor structure provided in the embodiments of this specification, the drain layer is located above the substrate and on the sidewall of the channel structure layer and the gate structure on one side, and the source layer is located above the substrate and on the sidewall of the channel structure layer and the gate structure on the other side. Both are in contact with the end of the channel layer along the extension direction. By placing the source layer and drain layer on the sidewalls of the gate structure on both sides, the formed drain layer can be controlled to be an L-shaped non-planar structure. This makes the bottom electrode layer above the drain layer and the resistive switching layer above the bottom electrode layer non-planar structures. Through the gate structure, the resistive switching layer can be electrically connected to the substrate. Therefore, when the semiconductor device is working, the conduction path can be controlled by controlling the voltage magnitude or polarity on the resistive switching layer with the non-planar structure, thereby improving the electrical performance of the semiconductor device.

[0017] To solve the above-mentioned technical problems, in the semiconductor structure formation method provided in the embodiments of this specification, after forming trenches in the stacked structures on both sides of the dummy gate structure, a barrier layer is formed above the substrate, above the dummy gate structure, and on one side wall of the dummy gate structure and the stacked structure. This allows space to be occupied for the subsequent formation of the drain layer. Furthermore, by first forming a source layer on the other side wall of the stacked structures on both sides of the dummy gate structure and forming an interlayer dielectric layer covering the source layer, damage to the source layer can be avoided. Subsequently, by forming a non-planar L-shaped drain layer on the side wall of the barrier layer in the stacked structure, both the bottom electrode layer and the resistive switching layer formed are non-planar structures. By filling the gate opening and the through trench with a gate structure, electrical connection between the resistive switching layer and the substrate can be achieved. Thus, when the semiconductor device is working, the conduction path can be controlled by controlling the voltage magnitude or polarity on the resistive switching layer with the non-planar structure, thereby improving the electrical performance of the semiconductor device.

[0018] To make the above-mentioned objects, features and advantages of the embodiments of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0019] refer to Figure 2 A schematic diagram of an embodiment of the semiconductor structure of the present invention is shown, wherein, Figure 2Subgraph (a) is a cross-sectional view along the direction of the channel extension, and subgraph (b) is a cross-sectional view perpendicular to the direction of the channel extension.

[0020] like Figure 2 As shown in the embodiment of the specification, the semiconductor structure includes: a substrate 100; a channel structure layer 300 located above the substrate 100, including one or more channel layers 30 spaced apart from bottom to top; an isolation layer 110 located on the substrate 100 and exposing the channel structure layer 300; a gate structure 190 located above the isolation layer 110, spanning and surrounding the channel structure layer 300, the gate structure 190 filling the spaces between adjacent channel layers 30 and between the channel layers 30 and the substrate 100; inner sidewalls 240 located between the channel layers 30, with the outer surfaces of the inner sidewalls 240 vertically flush with the end faces of the channel layers 30; and a drain layer 160, L-shaped, located above the substrate 100 and above the channel structure layer 300. The following layers are present: a bottom electrode layer 171, located on the sidewall of the L-shaped drain layer 160 and in contact with the sidewall of the gate structure 190; a resistive switching layer 172, located on the bottom electrode layer 171, wherein the L-shaped drain layer 160, the bottom electrode layer 171, and the resistive switching layer 172 are all non-planar structures; a top electrode layer 173, located on the resistive switching layer 172; a source layer 140, located above the substrate 100 and on the sidewall of the channel structure layer 300 and the gate structure 190, and in contact with the end of the channel layer 30 in the extending direction; and an interlayer dielectric layer 150, located above the source layer 140 and in contact with the gate structure 190.

[0021] The substrate serves as a process platform for the formation of semiconductor structures. In this specification, the formation of a gate-all-around (GAA) transistor is used as an example. In other embodiments, the formation method can also be used to form a forksheet transistor or a complementary field-effect transistor (CFET).

[0022] In the embodiments described in the specification, the substrate 100 may be a silicon substrate, that is, the material of the substrate 100 is single-crystal silicon. In other embodiments, the substrate material may also be one or more of germanium, silicon germanide, silicon carbide, gallium nitride, gallium arsenide, and indium gallium nitride, and the substrate may also be other types of substrates such as silicon-on-insulator substrates or germanium-on-insulator substrates.

[0023] The channel structure layer 300 is used to provide a conductive channel for the field-effect transistor. As an example, the channel structure layer 300 is a fin structure extending laterally.

[0024] In the embodiments described in this specification, such as Figure 2 As shown, in the channel structure layer 300, there are three channel layers 30, and the stacking direction of the channel layers 30 is perpendicular to the surface of the substrate 100. In other embodiments, the number of channel layers may also be different.

[0025] The isolation layer 110 is used to isolate adjacent channel structure layers 300. In the embodiment described, the material of the isolation layer 110 is silicon oxide. The isolation layer 110 can also be other insulating materials.

[0026] Continue to refer to Figure 2 When the device is in operation, the gate structure 190 is used to control the opening and closing of the conductive channel.

[0027] In the embodiment of the specification, the gate structure 190 is a metal gate structure, and the gate structure 190 includes a gate dielectric layer (not shown) and a work function layer located on the gate dielectric layer. Figure 2 (not shown) and located on the work function layer and filling the through slot ( Figure 2 (not shown) and gate opening ( Figure 2 Gate electrode layer (not shown) Figure 2 (Not shown).

[0028] The gate dielectric layer is used to achieve electrical isolation between the work function layer and the gate electrode layer and the channel. The material of the gate dielectric layer includes one or more of silicon oxide, nitrogen-doped silicon oxide, HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, La2O3, and Al2O3. As an example, the gate dielectric layer includes a high-k gate dielectric layer, which is made of a high-k dielectric material. The material of the high-k gate dielectric layer may also be selected from ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or Al2O3. In other embodiments, the gate dielectric layer may include a gate oxide layer and a high-k gate dielectric layer located on the gate oxide layer.

[0029] The work function layer is used to adjust the work function of the gate structure 190, thereby adjusting the threshold voltage of the field-effect transistor. When forming an NMOS transistor, the work function layer is an N-type work function layer, and the material of the work function layer includes one or more of titanium aluminide, tantalum carbide, aluminum, or titanium carbide; when forming a PMOS transistor, the work function layer is a P-type work function layer, and the material of the work function layer includes one or more of titanium nitride, tantalum nitride, titanium carbide, silicon tantalum nitride, silicon titanium nitride, and tantalum carbide.

[0030] The gate electrode layer serves as the external electrode for electrical connection between the gate structure 190 and external circuitry. The gate electrode layer is made of a conductive material, such as W, Al, Cu, Ag, Au, Pt, Ni, or Ti.

[0031] In the embodiments described herein, a metal gate structure 190 is used as an example. In other embodiments, based on actual process requirements, the gate structure may be other types of gate structures, such as polycrystalline silicon gate structures or amorphous silicon gate structures.

[0032] In the embodiment described in the specification, the gate structure 190 includes a first portion spanning the channel structure layer 300. Figure 2 (Not shown). And the sidewall of the first portion is recessed relative to the sidewall of the channel layer 30.

[0033] In the embodiments described in the specification, continue to refer to Figure 2 The semiconductor structure further includes a protective sidewall 121 located on the sidewall of the first portion. The protective sidewall 121 is used to protect the sidewall of the gate structure 190.

[0034] In the embodiments described, the material of the protective sidewall 121 may include silicon nitride, silicon oxide, silicon oxynitride, low-k dielectric material, or ultra-low-k dielectric material, and the protective sidewall 121 may be a single-layer or multi-layer structure. As an example, the protective sidewall 121 is a single-layer structure, and the material of the protective sidewall 121 is silicon nitride.

[0035] In the embodiment described in the specification, the inner wall 240 is used to achieve isolation between the source layer 140, the drain layer 160 and the gate structure 190, and also increases the distance between the gate structure 190 and the source layer 140 and the drain layer 160, which is beneficial to reduce the parasitic capacitance between the gate structure 190 and the source layer 140 and the drain layer 160.

[0036] In the embodiments described in the specification, the inner wall 240 is made of an insulating material to achieve isolation between the source layer 140, the drain layer 160, and the gate structure 190. In the embodiments described in the specification, the material of the inner wall 240 includes silicon nitride, silicon oxide, silicon oxynitride, a low-k dielectric material, or an ultra-low-k dielectric material. As an example, the material of the inner wall 240 is silicon nitride.

[0037] The source layer 140 and the drain layer 160 are used as the source and drain of the field-effect transistor, respectively. When the field-effect transistor is working, the source layer 140 and the drain layer 160 are used to provide the source of the carriers.

[0038] In the embodiments described, the source layer 140 and drain layer 160 include ion-doped stress layers. These stress layers provide stress to the channel region, thereby improving carrier mobility. Specifically, when forming an NMOS transistor, the source layer 140 and drain layer 160 include N-type ion-doped stress layers, and the stress layer material is Si or SiC; when forming a PMOS transistor, the source layer 140 and drain layer 160 include P-type ion-doped stress layers, and the stress layer material is Si or SiGe.

[0039] Continue to refer to Figure 2 In the embodiments described in this specification, the drain layer 160 is an L-shaped non-planar structure. As a specific example, the non-planar structure of the L-shaped drain layer 160 includes a serrated shape.

[0040] Correspondingly, the bottom electrode layer 171 located above the drain layer 160 and the resistive switching layer 172 located above the bottom electrode layer 171 are both non-planar structures. By forming a non-planar drain layer on the sidewall of the barrier layer in the stacked structure, both the bottom electrode layer and the resistive switching layer can be non-planar structures. Furthermore, by filling the gate opening and the through-hole with a gate structure, electrical connection between the resistive switching layer and the substrate can be achieved. Thus, when the semiconductor device is operating, the conduction path can be controlled by controlling the voltage magnitude or polarity on the resistive switching layer with the non-planar structure, thereby improving the electrical performance of the semiconductor device.

[0041] In some embodiments of this specification, the non-planar structure of the bottom electrode layer includes a serrated structure matching the shape of the drain layer; the non-planar structure of the resistive switching layer includes a serrated structure matching the shape of the bottom electrode layer. It is understood that the bottom electrode layer and the resistive switching layer can also be non-planar structures of other shapes, such as wavy. The embodiments of this specification do not limit the specific form of the non-planar structure, as long as the formed drain layer, bottom electrode layer, and resistive switching layer are all matching non-planar structures.

[0042] In some embodiments of this specification, the bottom electrode layer 171 serves as the bottom electrode in an RRAM cell device. The material of the bottom electrode layer 171 includes one or more of TiN, TaN, Pt, AlCu, and Au. As an example, the material of the bottom electrode layer 171 is TiN. In other embodiments, the material of the bottom electrode layer is TaN.

[0043] The top electrode layer 173 serves as the top electrode in the RRAM cell device. As an example, the material of the top electrode layer 173 is TiN. For a detailed description of the material of the top electrode layer 173, please refer to the corresponding description of the bottom electrode layer 173 above, which will not be repeated here.

[0044] Depending on the voltage applied to the variable resistance layer 172, the layer changes accordingly between a high-resistivity state and a low-resistivity state, thereby opening or blocking the current flow path and utilizing this property to store various information. In the embodiment described, the variable resistance material layer 172 is a metal oxide layer. Specifically, the material of the variable resistance layer 172 includes one or more of hafnium oxide, tantalum oxide, and titanium oxide.

[0045] Continue to refer to Figure 2 The semiconductor structure may further include conductive plugs 195, located within the top electrode layer 173, the interlayer dielectric layer 195, and the gate structure 190, respectively. The conductive plugs 195 are used to establish electrical connections between the source layer 140 and the drain layer 160 and external circuits or other interconnect structures.

[0046] In some embodiments of this specification, the material of the conductive plug 195 may include W. In other embodiments, the material of the conductive plug 195 may also include Al, Cu, Ag, Au, Pt, Ni, or Ti, etc.

[0047] It should be noted that, continue to refer to Figure 2 Since the interlayer dielectric layer 150 is an insulating material, the formed conductive plug 195 is in direct contact with the top of the source layer 140.

[0048] Accordingly, the present invention also provides a method for forming a semiconductor structure. Figures 3 to 28 This is a schematic diagram of the structure corresponding to each step in an embodiment of the semiconductor structure formation method of the present invention, wherein, Figures 4 to 28 Subgraph (a) is a cross-sectional view along the direction of the channel extension, and subgraph (b) is a cross-sectional view perpendicular to the direction of the channel extension.

[0049] The method for forming a semiconductor structure according to an embodiment of this specification will be described in detail below with reference to the accompanying drawings.

[0050] refer to Figure 3 A substrate is provided, including a substrate 100 and a stacked structure 200 above the substrate. The stacked structure 200 includes one or more channel stacks 210 stacked sequentially from bottom to top. The channel stacks 210 may include a sacrificial layer 20 and a channel layer 30 above the sacrificial layer 20. An isolation layer 110 is formed on the substrate (e.g., Figure 7 As shown), the isolation layer 110 exposes the stacked structure 200.

[0051] The substrate serves as a process platform for subsequent fabrication processes. In this specification, the formation of a gate-all-around (GAA) transistor is used as an example. In other embodiments, the formation method can also be used to form a forksheet transistor or a complementary field-effect transistor (CFET).

[0052] In the embodiments described in this specification, the substrate 100 is a silicon substrate, that is, the material of the substrate 100 is single-crystal silicon. In other embodiments, the substrate material may also be one or more of germanium, silicon germanide, silicon carbide, gallium nitride, gallium arsenide, and indium gallium nitride, and the substrate may also be other types of substrates such as silicon-on-insulator substrates or germanium-on-insulator substrates.

[0053] In the stacked structure 200, the stacking direction of the channel stack 210 is perpendicular to the surface of the substrate 100, and the channel stack 210 provides the process basis for the subsequent formation of the channel layer 30 with a suspended arrangement. Specifically, the channel layer 30 is used to provide the conductive channel of the field-effect transistor, and the sacrificial layer 20 is used to support the channel layer 30, thereby providing the process basis for the subsequent realization of the spaced and suspended arrangement of the channel layer 30. The sacrificial layer 20 is also used to occupy space for the subsequent formation of the gate structure.

[0054] In the embodiments of this specification, when forming an NMOS transistor, the material of the channel layer 30 can be Si, and the material of the sacrificial layer 20 can be SiGe. During the subsequent removal of the sacrificial layer 20, the etching selectivity of SiGe and Si is relatively high. Therefore, by setting the material of the sacrificial layer 20 to SiGe and the material of the channel layer 30 to Si, the impact of the removal process of the sacrificial layer 20 on the channel layer 30 can be effectively reduced, thereby improving the quality of the channel layer 30 and thus contributing to improved device performance.

[0055] In other embodiments, when forming a PMOS transistor, SiGe channel technology can be used to improve the performance of the PMOS transistor. The channel layer 30 can be made of SiGe, and the sacrificial layer 20 can be made of Si. In other embodiments, the channel layer 30 can also be made of one or more of germanium, silicon carbide, gallium nitride, gallium arsenide, and indium gallium nitride.

[0056] As an example, the number of channel stacks 210 is three. In other embodiments, the number of channel stacks may also be other.

[0057] Some of the points mentioned in this manual can be used. Figures 4 to 7 The process shown involves forming an isolation layer 110 on the substrate 100.

[0058] Reference Figure 4 A portion of the channel stack 210 and the substrate 100 are removed to form an opening 300.

[0059] In some embodiments of this specification, a dry etching process can be used to obtain the opening 300.

[0060] It should be noted that, since it is necessary to remove part of the channel stack 200 and the substrate 100, therefore, Figure 4 The width of the channel stack 210 and the substrate 100 in neutron diagram (a) is smaller than that of the substrate 100. Figure 3 The channel stack 210 and the substrate 100 are in the middle.

[0061] Reference Figure 5 An isolation material layer 111 is formed above the channel stack 210 and the substrate 100.

[0062] In some embodiments of this specification, the insulating material layer 111 may be formed using a chemical vapor deposition (PVD) process. In other embodiments, the insulating material layer may also be formed using a physical vapor deposition (PVD) process.

[0063] Reference Figure 6 Remove part of the isolation material layer 111 to expose the top of the channel stack 210.

[0064] In some embodiments of this specification, a chemical mechanical polishing process may be used, with the top surface of the channel stack 210 serving as the etching stop position.

[0065] Reference Figure 7 Remove the isolation material layers 111 on both sides of the channel stack 210 until the formed isolation layer 110 exposes the stack structure 200.

[0066] In some embodiments of this specification, the isolation layer 110 serves to isolate adjacent stacked structures 200 and also to isolate the substrate 100 from the subsequent gate structure. In these embodiments, the isolation layer 110 may be made of silicon oxide. The isolation layer 110 may also be other insulating materials, such as one or more of silicon oxynitride, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, boron nitride, and boron carbonitride.

[0067] refer to Figure 8 A pseudo-gate structure 120 is formed on the isolation layer 110, spanning the stacked structure 200. The pseudo-gate structure 120 is used to pre-reserve space for the subsequent formation of the gate structure.

[0068] Specifically, the dummy gate structure 120 is located on the isolation layer 110 and covers a portion of the top and sidewalls of the stacked structure 200. The dummy gate structure 120 extends longitudinally.

[0069] The dummy gate structure 120 can be a stacked structure or a single-layer structure. In the embodiment described in the specification, the dummy gate structure 120 is a stacked structure, including a dummy gate oxide layer (not shown) and a dummy gate layer (not shown) located on the dummy gate oxide layer. Specifically, the dummy gate structure 120 is a polysilicon gate structure, the material of the dummy gate oxide layer can be silicon oxide or silicon oxynitride, and the material of the dummy gate layer can be polysilicon.

[0070] Continue to refer to Figure 8 The upper part of the pseudo-gate structure 120 also includes a gate mask layer 121, which is used as a mask in the process of forming the pseudo-gate structure 110.

[0071] refer to Figure 9 The method for forming the semiconductor structure further includes: after forming the dummy gate structure 110, forming the trench 220 (e.g., Figure 11 Before (as shown), a protective sidewall 122 is formed on the sidewall of the dummy gate structure 120. The protective sidewall 122 is used together with the dummy gate structure 120 as an etching mask for the subsequent etching process to form the groove, and the protective sidewall 122 is also used to protect the sidewalls of the dummy gate structure 120 and the subsequent gate structure.

[0072] In the embodiments described, the material of the protective sidewall 122 may include silicon nitride, silicon oxide, silicon oxynitride, low-k dielectric material, or ultra-low-k dielectric material, and the protective sidewall 122 may be a single-layer or multi-layer structure. As an example, the protective sidewall 122 may be a single-layer structure, and the material of the protective sidewall 122 may be silicon nitride.

[0073] refer to Figure 10 and Figure 11 Grooves 220 are formed in the stacked structures 200 on both sides of the pseudo-gate structure 120, and the grooves 220 are located in the sacrificial layer 20.

[0074] Reference Figure 10 Grooves 230 are formed in the stacked structures 200 on both sides of the pseudo-gate structure 120.

[0075] The groove 230 provides space for the formation of the source and drain layers. The sidewalls of the groove 140 expose the stacked structure 200, which facilitates the formation of the source and drain layers on the sidewalls of the channel layer 30 and the substrate 100 exposed by the epitaxial process; and also facilitates the subsequent etching of a portion of the sacrificial layer 20 in the lateral direction.

[0076] In the embodiments described in this specification, the bottom of the groove 230 exposes the substrate.

[0077] In some embodiments of this specification, an anisotropic etching process (e.g., anisotropic dry etching process) is used to etch the stacked structure 200 on both sides of the dummy gate structure 120 and the gate sidewall 122, which is beneficial to improve the cross-sectional morphology quality of the groove 230, thereby facilitating precise control of the sidewall morphology of the groove 230.

[0078] Specifically, the stacked structures 200 on both sides of the pseudo-gate structure 120 and the gate sidewall 122 are removed to form the groove 230.

[0079] Reference Figure 11 After forming the groove 230, the sacrificial layer 20, a portion of the sidewall thickness of the groove 230, is etched along the transverse direction to form a trench 220. The trench 220 is formed by adjacent channel layers 30 and the sacrificial layer 20, wherein the trench 220 provides space for the subsequent formation of the inner sidewall.

[0080] In the embodiment described in the specification, a vapor etching process is used to etch the sacrificial layer 20, representing a portion of the sidewall thickness of the groove 230, along the lateral direction. Vapor etching is an isotropic etching process, capable of etching the sacrificial layer 20 along the lateral direction. Furthermore, vapor etching easily achieves a large etching selectivity, which helps reduce the difficulty of etching the sacrificial layer 20 and decreases the probability of damage to other film structures (such as the channel layer 30).

[0081] In the embodiment described in the specification, the sacrificial layer 20 is made of SiGe, and the channel layer 30 is made of Si. The sacrificial layer 20 on the sidewall of the groove 230 is etched using HCl vapor. The etching rate of HCl vapor on SiGe material is much greater than that on Si material, which can effectively reduce the probability of damage to the channel layer 30.

[0082] In other embodiments, when the channel layer is made of SiGe and the sacrificial layer is made of Si, a dry etching process can be used to etch the sacrificial layer on the sidewall of the trench along the transverse direction. The etchant used in the dry etching process can include a mixture of plasmas of CF4, O2, and N2. The difference between the etching rate of Si and the etching rate of SiGe in the plasma mixture is relatively large, which can effectively reduce the probability of the channel layer being damaged.

[0083] Reference Figure 12 An inner wall 240 is formed within the trench 220, and the outer side of the inner wall 240 is vertically flush with the end face of the trench layer 30.

[0084] In some embodiments of this specification, the inner sidewall 240 is used to protect the sidewall of the channel layer 30, reducing the probability of damage to the channel layer 30. The inner sidewall 240 can isolate the subsequently formed source layer, drain layer and gate structure, and appropriately increase the distance between the gate structure and the source layer and drain layer, which is beneficial to reduce the parasitic capacitance between the gate structure and the source layer and drain layer.

[0085] In some embodiments of this specification, the inner sidewall 240 is made of a material that has etching selectivity with the material of the channel layer 30, so that the inner sidewall 240 can protect the channel layer 30 in subsequent process manufacturing, and the inner sidewall 240 has a high etching selectivity ratio with other film layers during the subsequent removal process, so as to reduce the difficulty of removing the inner sidewall 240 and reduce damage to other film layers.

[0086] In the embodiments described in the specification, the material of the inner wall 240 includes one or more of silicon oxide, silicon oxynitride, silicon nitride, silicon carbide, silicon carbide, silicon carbonitride, and boron carbide.

[0087] In the embodiment of the specification, the step of forming the inner sidewall 240 includes: forming a conformal covering sidewall material layer (not shown) on the bottom and sidewall of the groove 230; and removing the sidewall material layer on the top of the exposed channel stack 210 and the top of the isolation layer 110 in the groove 230.

[0088] In the embodiments described, atomic layer deposition (ALD) is used to form the sidewall material layer. ALD has high step coverage, which is beneficial for the deposition of the sidewall material layer on the bottom and sidewalls of the groove 230, and also helps to improve the thickness uniformity of the sidewall material layer.

[0089] In the embodiment described in the specification, an anisotropic etching process is used to remove the sidewall material layer on the top of the trench stack 210 exposed in the groove 230 and on the top of the isolation layer 110, and the remaining sidewall material layer serves as the inner sidewall 240.

[0090] Reference Figures 13 to 15 A barrier layer 130 is formed above the substrate 100, above the dummy gate structure 120, and on the sidewall of one side of the dummy gate structure 120 and the stacked structure 200.

[0091] Reference Figure 13 A barrier material layer 131 is formed by a deposition process to cover the substrate 100, the stacked structure 200 and the pseudo-gate structure 120.

[0092] In some embodiments of this specification, in order to precisely control the thickness of the barrier material layer 131 and form a high-quality barrier layer 130 (see reference 130), Figure 15 A protective material layer 131 can be formed by depositing atomic layer deposition (ALD) technology.

[0093] In some embodiments of this specification, the barrier material layer includes one or more of silicon oxide, silicon nitride, or silicon oxynitride.

[0094] Reference Figure 14 A first anti-reflective coating 132 and a first photoresist layer 133 are sequentially formed above the barrier material layer 131. The first photoresist layer 133 forms a first patterned opening that exposes a portion of the first anti-reflective coating 132. Figure 14 (Not shown).

[0095] In some embodiments of this specification, and in the embodiments of the present invention, the material of the first anti-reflective coating 132 includes: dielectric anti-reflective coating (DARC) material or bottom anti-reflective coating (BARC) material, organic dielectric layer (ODL) material, etc.

[0096] Reference Figure 15 Using the first photoresist layer 132 as a mask, the first anti-reflective coating 132 and the barrier material layer 133 are sequentially etched along the first pattern opening, and a portion of the barrier material layer 133 is removed to form the barrier layer 130.

[0097] It should be noted that after forming the barrier layer 130, the first anti-reflective coating 132 and the first photoresist layer 133 also need to be removed.

[0098] Reference Figures 16 to 22 A source layer 140 and a drain layer 160 are formed above the stacked structure 200 on both sides of the dummy gate structure 120 and the substrate 100. The source layer 140 and the drain layer 160 are used as the source and drain of the field-effect transistor, and when the field-effect transistor is working, the source layer 140 and the drain layer 160 are used to provide a source of charge carriers.

[0099] In the embodiments described, the source layer 140 and drain layer 160 include ion-doped stress layers. These stress layers provide stress to the channel region, thereby improving carrier mobility. Specifically, when forming an NMOS transistor, the source layer 140 and drain layer 160 include N-type ion-doped stress layers, and the stress layer material is Si or SiC; when forming a PMOS transistor, the source layer 140 and drain layer 160 include P-type ion-doped stress layers, and the stress layer material is Si or SiGe.

[0100] The following detailed description, in conjunction with the accompanying drawings, outlines the specific steps involved in forming the source and drain layers in the embodiments of this specification.

[0101] Reference Figure 16 A source layer 140 is formed on the stacked structure 200 on both sides of the pseudo-gate structure 120 and on the other sidewall of the pseudo-gate structure 120.

[0102] It is understood that the terms "one side" and "the other side" used in the embodiments of this specification only refer to two relative positions of the corresponding film layers in the semiconductor structure.

[0103] In the embodiments described in the specification, an epitaxial process can be used to form a stress layer, and during the formation of the stress layer, ions are self-doped in situ. The stress layer doped with ions is used as the source layer 140.

[0104] Specifically, epitaxial growth is performed based on the exposed sidewalls of the stacked structure 200 and the pseudo-gate structure 120.

[0105] In practice, the morphology and size of the source layer 140 can be adjusted according to actual process requirements.

[0106] Reference Figure 17 The barrier layer 130 is removed by an etching process.

[0107] In actual operation, dry etching or wet etching can be used to remove the barrier layer 130.

[0108] In some embodiments of this specification, the substrate 100 includes multiple stacked structures 200. However, in actual operation, only a portion of the stacked structures is needed to form the drain layer and the subsequent bottom electrode layer and resistive switching layer formed on top of the drain layer. Furthermore, if adjacent devices are in direct contact, a short circuit may occur. Therefore, in the embodiments of this specification, the stacked structures used to form the drain layer can be exposed to form the drain layer and isolate adjacent devices.

[0109] Reference Figure 18An interlayer dielectric material layer 151 is formed above the source layer 140, above the pseudo-gate structure 120, and above the substrate 100.

[0110] In some embodiments of this specification, the interlayer dielectric material layer 151 may be formed using a PVD process. In these embodiments, the material of the interlayer dielectric material layer 151 may include silicon oxide. In other embodiments, the interlayer dielectric material layer 151 may also be other insulating materials; for example, the insulating layer 151 may also be one or more of silicon oxynitride, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, boron nitride, and boron carbonitride.

[0111] Reference Figure 19 This exposes the top of the pseudo-gate structure 120. Specifically, the top surface of the capping layer 121 can be used as the etching stop position, and a chemical mechanical polishing process can be used to remove part of the interlayer dielectric material layer 151, thereby exposing the top of the pseudo-gate structure 120. Using the top surface of the capping layer 121 as the stop position can avoid accidental etching of the pseudo-gate structure.

[0112] Reference Figure 20 A second photoresist layer 152 is sequentially formed above a portion of the interlayer dielectric material layer 151 and a portion of the pseudo-gate structure 120. The pseudo-gate structure 120 is patterned using the second photoresist layer 152 as a mask.

[0113] Reference Figure 21 The portion of the interlayer dielectric material layer 151 not covered by the second photoresist layer 152 is removed, and the remaining portion of the interlayer dielectric material layer 151 serves as the interlayer dielectric layer 150 covering the source layer. The interlayer dielectric layer 160 isolates adjacent devices and also supports the channel layer 30 during subsequent removal of the dummy gate structure 120 and the sacrificial layer 20, thus achieving a suspended space separation between adjacent channel layers 30. In the embodiment described, the material of the interlayer dielectric layer 160 is silicon oxide. The material of the interlayer dielectric layer 160 can also be other insulating materials.

[0114] In the embodiment described in the specification, the interlayer dielectric layer 160 also exposes the top of the dummy gate structure 120 to facilitate subsequent removal of the dummy gate structure 120. Then, refer to... Figure 22 An L-shaped drain layer 160 with a non-planar structure is formed on the sidewall of the barrier layer in the stacked structure 200.

[0115] In the embodiments described, an L-shaped drain layer with a non-planar structure can be formed on the sidewall of the barrier layer in the stacked structure using an epitaxial crystal orientation process. Specifically, an epitaxial crystal orientation process is used to form a stress layer, and ions are self-doped in situ during the formation of the stress layer. The stress layer doped with ions is used as the drain layer 160.

[0116] Specifically, epitaxial growth is performed based on the exposed inner wall 240. In practice, the shape of the generated drain layer can be controlled by adjusting parameters such as the temperature range and gas flow rate during the epitaxial growth process at different locations, thereby forming a non-planar L-shaped drain layer 160.

[0117] In some embodiments of this specification, reference continues to be made to... Figure 22 The non-planar L-shaped drain layer may include a sawtooth-shaped drain layer, wherein the number of sawtooth protrusions is the same as the number of channel layers 30. In other embodiments, the non-planar L-shaped drain layer may also be a wavy or other non-planar structure. In specific implementations, the morphology and size of the drain layer 160 can be adjusted according to actual process requirements.

[0118] Reference Figure 23 and Figure 24 A bottom electrode layer 171, a resistive switching layer 172, and a top electrode layer 173 are sequentially formed on the drain layer 160.

[0119] Reference Figure 23 A non-planar bottom electrode layer 171 and a resistive switching layer 172 are sequentially formed above the interlayer dielectric layer 150, above the pseudo-gate structure 120, and above the drain layer 160.

[0120] In specific implementations, in order to ensure that the bottom electrode layer 171, the resistive switching layer 172 and the drain layer have the same morphology, in some embodiments of this specification, a conformal coating process can be used to sequentially form a non-planar bottom electrode layer 171 and a resistive switching layer 172 above the interlayer dielectric layer 150, above the pseudo-gate structure 120 and above the drain layer 160.

[0121] As a specific example, an atomic layer deposition (ALD) process can be used to sequentially form a non-planar bottom electrode layer 171 and a resistive switching layer 172 above the interlayer dielectric layer 150, above the pseudo-gate structure 120, and above the drain layer 160.

[0122] In some embodiments of this specification, the non-planar bottom electrode layer includes a sawtooth-shaped bottom electrode layer that matches the shape of the L-shaped drain layer; the non-planar resistive switching layer includes a sawtooth-shaped resistive switching layer that matches the shape of the bottom electrode layer.

[0123] Reference Figure 24 A top electrode layer 172 is formed above the resistive switching layer, exposing the top of the dummy gate structure 120, the interlayer dielectric layer 160, and the resistive switching layer 171.

[0124] The specific steps include: using a deposition process to form a top electrode material layer (not shown in the figure) covering the resistive switching layer 172 above the resistive switching layer 172; using a chemical mechanical polishing process to remove part of the top electrode material layer until the top of the pseudo gate structure 120, the interlayer dielectric layer 160 and the resistive switching layer 171 are exposed; and using the remaining top electrode material layer as the top electrode layer 173.

[0125] In practice, the top electrode layer can be formed using either PVD or ALD deposition processes.

[0126] In some embodiments of this specification, the bottom electrode layer 171 serves as the bottom electrode in an RRAM cell device. The material of the bottom electrode layer 171 includes one or more of TiN, TaN, Pt, AlCu, and Au. As an example, the material of the bottom electrode layer 171 is TiN. In other embodiments, the material of the bottom electrode layer is TaN.

[0127] The top electrode layer 173 serves as the top electrode in the RRAM cell device. As an example, the material of the top electrode layer 173 is TiN. For a detailed description of the material of the top electrode layer 173, please refer to the corresponding description of the bottom electrode layer 173 above, which will not be repeated here.

[0128] Depending on the voltage applied to the variable resistance layer 172, the layer changes accordingly between a high-resistivity state and a low-resistivity state, thereby opening or blocking the current flow path and utilizing this property to store various information. In the embodiment described, the variable resistance material layer 172 is a metal oxide layer. Specifically, the material of the variable resistance layer 172 includes one or more of hafnium oxide, tantalum oxide, and titanium oxide.

[0129] refer to Figure 25 The pseudo-gate structure 120 is removed to form a gate opening 123, exposing the stacked structure 200 and the isolation layer 110.

[0130] The gate opening 123 provides space for forming the gate structure. The gate opening 123 exposes the stacked structure 200 to facilitate subsequent removal of the sacrificial layer 20 in the channel stack 210 through the gate opening 123.

[0131] In the embodiment described in the specification, the gate opening 123 spans the stacked structure 200 and is located above the isolation layer 110.

[0132] refer to Figure 26 The sacrificial layer 20 in the channel stack 220 is removed to form a through groove 180, which is surrounded by adjacent channel layers 30 or by the channel layer 30 and the isolation layer 110.

[0133] The through-slot 180 and the gate opening 123 together provide space for forming the gate structure. The through-slot 180 is connected to the gate opening 123.

[0134] In the embodiment of the specification, after removing the sacrificial layer 20, when there are multiple trench layers 30, the multiple trench layers 30 are spaced apart to form a trench structure layer 300.

[0135] In the embodiments described in the specification, a vapor etching process is used to remove the sacrificial layer 20. Specifically, the channel layer 30 is made of Si, and the sacrificial layer 20 is made of SiGe. Therefore, the sacrificial layer 20 exposed by the gate opening 123 is removed by HCl vapor. HCl vapor has a high etching selectivity between SiGe and Si, which is beneficial to improving the removal efficiency of the sacrificial layer 20 and reducing the probability of damage to the channel layer 30.

[0136] refer to Figure 27 A gate structure 190 is filled within the gate opening 123 and the through-slot 180. The gate structure 190 surrounds the channel layer 30 and is located on top of the isolation layer 110, spanning the channel layer 30. During device operation, the gate structure 190 is used to control the opening and closing of the conductive channel.

[0137] In the embodiments described in the specification, the gate structure 190 is a metal gate structure, and the gate structure 190 may include a gate dielectric layer (…). Figure 27 (Not shown), work function layer located on the gate dielectric layer ( Figure 27 (not shown) and the gate electrode layer located on the work function layer and filling the through-slot 180 and the gate opening 123 ( Figure 27 (Not shown).

[0138] The gate dielectric layer is used to achieve electrical isolation between the work function layer and the gate electrode layer and the conductive channel. The material of the gate dielectric layer may include one or more of silicon oxide, nitrogen-doped silicon oxide, HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, La2O3, and Al2O3.

[0139] In one embodiment of the specification, the gate dielectric layer may include a high-k gate dielectric layer, the material of which is a high-k dielectric material. In other embodiments, the gate dielectric layer may further include a gate oxide layer and a high-k gate dielectric layer located on the gate oxide layer.

[0140] The work function layer is used to adjust the work function of the gate structure 190, thereby adjusting the threshold voltage of the field-effect transistor. When forming an NMOS transistor, the work function layer is an N-type work function layer, and the material of the work function layer includes one or more of titanium aluminide, tantalum carbide, aluminum, or titanium carbide; when forming a PMOS transistor, the work function layer is a P-type work function layer, and the material of the work function layer includes one or more of titanium nitride, tantalum nitride, titanium carbide, silicon tantalum nitride, silicon titanium nitride, and tantalum carbide.

[0141] The gate electrode layer serves as the external electrode for electrical connection between the gate structure 190 and external circuitry. The gate electrode layer is made of a conductive material, such as W, Al, Cu, Ag, Au, Pt, Ni, or Ti.

[0142] In the embodiments described herein, a metal gate structure 190 is used as an example. In other embodiments, based on actual process requirements, the gate structure may be other types of gate structures, such as polycrystalline silicon gate structures or amorphous silicon gate structures.

[0143] Reference Figure 28 Subsequent steps typically include forming conductive plugs 195 within the top electrode layer 173, the interlayer dielectric layer 195, and the gate structure 190. The conductive plugs 195 are used to establish electrical connections between the source layer 140 and the drain layer 160 and external circuitry or other interconnect structures.

[0144] In a specific implementation, the step of forming the conductive plug 195 may specifically include: forming contact holes in the top electrode layer 173, the interlayer dielectric layer 195, and the gate structure 190, respectively. Figure 28 (Not shown), a conductive plug material layer is deposited in the contact hole to form a conductive plug material layer, and the conductive plug material layer located on top of the top electrode layer 173, the interlayer dielectric layer 195 and the gate structure 190 is removed to obtain the conductive plug 195.

[0145] In some embodiments of this specification, the material of the conductive plug 195 may include W. In other embodiments, the material of the conductive plug 195 may also include Al, Cu, Ag, Au, Pt, Ni, or Ti, etc.

[0146] Continue to refer to Figure 28 Since the interlayer dielectric layer 150 located above the source layer 140 is an insulating material, the conductive plug 195 formed in the interlayer dielectric layer 150 is in direct contact with the top of the source layer 140.

[0147] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, comprising: Substrate, including substrate; A channel structure layer, located above the substrate, includes one or more channel layers spaced apart from bottom to top; An isolation layer is located on the substrate and exposes the channel structure layer; A gate structure is located above the isolation layer, spans and surrounds the channel structure layer, and the gate structure fills the space between adjacent channel layers and between the channel layer and the substrate; The inner wall is located between the trench layers, and the outer surface of the inner wall is vertically flush with the end face of the trench layer. The drain layer, which is L-shaped, is located above the substrate and on the sidewall of the channel structure layer and the gate structure, and is in contact with the end of the channel layer along the extension direction. The bottom electrode layer is located above the drain layer of the L-shape and is in contact with the sidewall of the gate structure; A resistive switching layer is located above the bottom electrode layer, and the L-shaped drain layer, the bottom electrode layer, and the resistive switching layer are all non-planar structures; The top electrode layer is located above the resistive switching layer; The source layer is located above the substrate and on the sidewall of the channel structure layer and the gate structure on the other side, and is in contact with the end of the channel layer along the extension direction; An interlayer dielectric layer is located above the source layer and is in contact with the gate structure.

2. The semiconductor structure according to claim 1, characterized in that, Also includes: Conductive plugs are located within the top electrode layer, the interlayer dielectric layer, and the gate structure, respectively.

3. The semiconductor structure according to claim 1, characterized in that, The gate structure includes a first portion that spans the channel structure layer; The semiconductor structure further includes a protective sidewall located on the sidewall of the first portion.

4. The semiconductor structure according to claim 1, wherein the gate structure comprises a gate dielectric layer and a gate electrode layer located on the gate dielectric layer.

5. The semiconductor structure according to claim 1, characterized in that, The non-planar structure of the L-shaped drain layer includes a sawtooth structure; The non-planar structure of the bottom electrode layer includes a serrated structure that matches the shape of the L-shaped drain layer; The non-planar structure of the resistive switching layer includes a serrated structure that matches the shape of the bottom electrode layer.

6. The semiconductor structure according to claim 1, characterized in that, The material of the bottom electrode layer includes one or more of TiN, TaN, Pt, AlCu, Au, and Ti; The resistive switching layer is made of one or more of HfO2, Ta2O5, and TiO2. The material of the top electrode layer includes one or more of TiN, TaN, Pt, AlCu, Au, and Ti.

7. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, including a substrate and a stacked structure above the substrate, the stacked structure including one or more channel stacks stacked sequentially from bottom to top, the channel stack including a sacrificial layer and a channel layer above the sacrificial layer, an isolation layer is formed on the substrate, and the isolation layer exposes the stacked structure; A pseudo-gate structure is formed on the isolation layer, spanning the stacked structure; Grooves are formed in the stacked structures on both sides of the pseudo-gate structure, and the grooves are located in the sacrificial layer; An inner wall is formed in the trench, and the outer surface of the inner wall is vertically flush with the end face of the trench layer. A barrier layer is formed above the substrate, above the dummy gate structure, and on one sidewall of the dummy gate structure and the stacked structure; A source layer is formed on the stacked structure on both sides of the pseudo-gate structure and on the other sidewall of the pseudo-gate structure; Remove the barrier layer to form an interlayer dielectric layer covering the source layer; In the stacked structure, an L-shaped drain layer with a non-planar structure is formed on the sidewall of the barrier layer; A non-planar bottom electrode layer and a resistive switching layer are sequentially formed above the interlayer dielectric layer, above the pseudo-gate structure, and above the drain layer; A top electrode layer is formed above the resistive switching layer, exposing the dummy gate structure, the interlayer dielectric layer, and the top of the resistive switching layer; Remove the pseudo-gate structure to form a gate opening, exposing the stacked structure and isolation layer; The sacrificial layer in the trench stack is removed to form a through groove, which is surrounded by adjacent trench layers or by the trench layer and the isolation layer; A gate structure is filled within the gate opening and the through-slot, the gate structure surrounding the channel layer, and the gate structure being located on top of the isolation layer and spanning the channel layer.

8. The method for forming a semiconductor structure according to claim 7, characterized in that, Also includes: Conductive plugs are formed within the top electrode layer, the interlayer dielectric layer, and the gate structure.

9. The method for forming a semiconductor structure according to claim 7, characterized in that, The formation of a barrier layer above the substrate, above the dummy gate structure, and on a sidewall of one side of the dummy gate structure and the stacked structure includes: A barrier material layer covering the substrate, the stacked structure, and the pseudo-gate structure is formed using a deposition process; A first anti-reflective coating and a first photoresist layer are sequentially formed on the barrier material layer, wherein the first photoresist layer forms a first patterned opening that exposes a portion of the first anti-reflective coating. Using the first photoresist layer as a mask, the first anti-reflective coating and the barrier material layer are sequentially etched along the first pattern opening to remove part of the barrier material layer and form the barrier layer.

10. The method for forming a semiconductor structure according to claim 9, characterized in that, The deposition process includes atomic layer deposition.

11. The method for forming a semiconductor structure according to claim 9 or 10, characterized in that, The barrier material layer includes one or more of silicon oxide, silicon nitride, or silicon oxynitride.

12. The method for forming a semiconductor structure according to claim 7, characterized in that, The process of removing the blocking layer to form an interlayer dielectric layer covering the source layer includes: The barrier layer is removed using an etching process; An interlayer dielectric material layer is formed above the source layer, above the dummy gate structure, and above the substrate; Exposing the top of the pseudo-gate structure; A second photoresist layer is sequentially formed above a portion of the interlayer dielectric material layer and a portion of the pseudo-gate structure. The pseudo-gate structure is then patterned using the second photoresist layer as a mask. Remove the interlayer dielectric material layer that is not covered by the second photoresist layer, and use the remaining portion of the interlayer dielectric material layer as the interlayer dielectric layer covering the source layer.

13. The method for forming a semiconductor structure according to claim 7, characterized in that, A non-planar drain layer is formed on the sidewall of the barrier layer in the stacked structure using an epitaxial crystal orientation process.

14. The method for forming a semiconductor structure according to claim 7 or 13, characterized in that, The non-planar L-shaped drain layer includes a sawtooth-shaped drain layer.

15. The method for forming a semiconductor structure according to claim 14, characterized in that, A non-planar bottom electrode layer and a resistive switching layer are sequentially formed above the interlayer dielectric layer, above the pseudo-gate structure, and above the drain layer using a conformal coating process.

16. The method for forming a semiconductor structure according to claim 14, characterized in that, Its features are, The non-planar bottom electrode layer includes a sawtooth-shaped bottom electrode layer that matches the shape of the L-shaped drain layer; the non-planar resistive switching layer includes a sawtooth-shaped resistive switching layer that matches the shape of the bottom electrode layer.

17. The method for forming a semiconductor structure according to claim 7, characterized in that, The process of removing the sacrificial layer in the trench stack to form the through-groove includes: an isotropic dry etching process.

18. The method for forming a semiconductor structure according to claim 7, characterized in that, Also includes: After the pseudo-gate structure is formed and before the trench is formed, a protective sidewall is formed on the sidewall of the pseudo-gate structure.

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