Charge source circuit, analog-to-digital converter and OLED touch device

Abstract

This invention provides a charge source circuit, an analog-to-digital converter, and an OLED touch device. The charge source circuit includes a reference current generation module, a current mirror module, and a charge output module. The charge output module no longer provides charge using the traditional voltage multiplied by capacitance method, but instead provides charge using current multiplied by time. This avoids the use of voltage divider technology, driver operational amplifiers, and a large number of capacitors, thus simplifying the circuit, reducing costs, and saving circuit layout area. Furthermore, by changing the current gradient and time gradient, the charge quantity can be continuously and precisely adjusted within a desired range with a very small area and a very small voltage, allowing the adjustment range of the equivalent capacitance corresponding to the charge quantity to range from tens of fF to hundreds of pF. Further, when applied to an OLED touch device, this charge source circuit extracts or injects the induced charge on the input electrodes of the OLED touch device to achieve a subtraction reference for the induced charge of the OLED touch device.

Description

Technical Field

[0001] This invention relates to the field of OLED touch technology, and in particular to a charge source circuit, an analog-to-digital converter, and an OLED touch device. Background Technology

[0002] The charge source can output a corresponding amount of charge to provide to subsequent circuits, such as providing a charge as a subtraction reference to calibrate the output of the analog-to-digital converter in the subsequent stage.

[0003] Existing charge sources typically provide charge using the formula Qdc = Vcom * Cin. Therefore, they require voltage divider technology and driving operational amplifiers to achieve a precise voltage Vcom across many bits. In some existing technologies, the voltage Vcom is fixed, thus requiring many bits of capacitors to regulate the charge. As a result, existing charge sources have low precision, a small adjustment range, and increase circuit layout area due to the use of too many capacitors. Furthermore, the use of voltage divider technology and driving operational amplifiers increases circuit cost and implementation difficulty. Summary of the Invention

[0004] The purpose of this invention is to provide a charge source circuit, an analog-to-digital converter, and an OLED touch device that can output a high range and high precision charge quantity with a very small layout area and a very small voltage. Furthermore, the charge source circuit extracts and injects the induced charge on the input electrode of the OLED touch device to achieve a reference reduction (DC reduction) of the induced charge of the OLED touch device, thereby improving the reference reduction effect of the OLED touch device.

[0005] To achieve the above objectives, the present invention provides a charge source circuit, comprising:

[0006] A reference current generation module is used to provide a reference current;

[0007] A current mirroring module, coupled to the reference current generating module, is used to perform current mirroring on the reference current;

[0008] A charge output module, coupled to the current mirror module, is used to convert the mirrored current output by the current mirror module into a corresponding charge output, and the output charge is calculated using the following formula:

[0009] Qdc = Idc * t,

[0010] Wherein, Qdc is the amount of charge output by the charge output module, Idc is the magnitude of the current provided by the charge output module, and t is the time for the charge output module to provide the current. The time t is divided into at least two consecutive time periods, wherein the lengths of the two consecutive time periods are in a binary multiple relationship, so that the amount of charge Qdc is continuously adjustable.

[0011] Optionally, in any two consecutive time periods, the difference between the minimum value of charge Qdc in the earlier time period and the maximum value of charge Qdc in the later time period is the minimum precision of charge Qdc in the later time period.

[0012] Optionally, the charge output module provides the corresponding current Idc in a binary weighted manner for each time period.

[0013] Optionally, the maximum adjustment range of the current Idc provided by the charge output module in each time period is k bits;

[0014] When the required charge Qdc adjustment range is M bits, M≥k+1, and M is divisible by k, the number of time periods n divided by the time t is n=M / k, and the charge Qdc provided in each of the n time periods is k bits.

[0015] When the required charge Qdc adjustment range is M bits, M≥k+1, and M is not divisible by k, the number of time periods n divided by time t is n=int(M / k)+1, and the charge Qdc adjustment range provided in each of the first n-1 time periods is k bits, and the charge Qdc adjustment range provided in the last time period is M-(n-1)*k bits.

[0016] Optionally, the lengths of the n time periods arranged in chronological order are gradually shortened in a binary multiple relationship.

[0017] Optionally, the charge output module has k current source branches, k≥2, wherein each current source branch includes a current source and a control switch for selecting the output of the current source. The control terminal of each current source is coupled to the current mirror module. The charge output module controls the output of the k current source branches by turning on or off the corresponding control switch, thereby realizing a binary weighted sum of the current Idc output by the charge output module in different time periods.

[0018] Optionally, the charge output module has k current source branches, where k ≥ 2. Each current source branch includes an upper current source, an upper control switch, a lower control switch, and a lower current source that are coupled in sequence. Each upper current source and upper control switch controls the current drawn by the k current source branches, and each lower current source and lower control switch controls the current injected by the k current source branches.

[0019] Optionally, each of the upper current sources includes a cascaded PMOS transistor, and each of the lower current sources includes a cascaded NMOS transistor.

[0020] Optionally, the reference current generating module is a constant current source;

[0021] Alternatively, the reference current generation module includes an operational amplifier, a first switching transistor, a second switching transistor, and a resistor, wherein the drain of the first switching transistor is coupled to the source of the second switching transistor, the drain of the second switching transistor is coupled to one end of the resistor and the non-inverting input of the operational amplifier, and the gate of the first switching transistor is coupled to the output of the operational amplifier.

[0022] Optionally, the current mirror module includes an upper main mirror transistor, an upper cascade transistor, a lower cascade transistor, and a lower main mirror transistor coupled in sequence. The gate of the upper main mirror transistor is coupled to the corresponding terminals of the reference current generation module and the charge output module, respectively, and the gate of the lower main mirror transistor is coupled to the corresponding terminal of the charge output module.

[0023] Based on the same inventive concept, the present invention also provides an analog-to-digital converter, which includes an integrator and a charge source circuit as described in the present invention; wherein, the output terminal of the charge source circuit is coupled to the inverting input terminal of the integrator and is used to provide a corresponding charge to the integrator; the integrator is used to perform a subtraction reference based on the charge and output a corresponding digital signal.

[0024] Based on the same inventive concept, the present invention also provides an OLED touch device, which includes an input electrode and an analog-to-digital converter as described in the present invention, wherein a charge source circuit in the analog-to-digital converter is coupled to the input electrode, the charge source circuit is used to extract or inject the induced charge on the input electrode, and the analog-to-digital converter outputs a corresponding digital signal based on the induced charge after the charge source circuit extracts or injects the charge.

[0025] Compared with the prior art, the technical solution of the present invention has at least one of the following beneficial effects:

[0026] 1. Provide charge according to Qdc=Idc*t, avoiding the difficulty and circuit cost of providing precise voltage for different bits when using the traditional Qdc=Vcom*Cin method, which requires voltage divider technology and driving operational amplifiers, as well as the problem of greatly increasing the layout area due to the use of precise capacitors for different bits.

[0027] 2. By changing the current gradient of current Idc and the time gradient of the time period, the charge Qdc can be continuously adjusted with precision within the required range under a very small area and a very small voltage.

[0028] 3. The current Idc adopts a binary weighted method, and the time period adopts a binary multiple method, thereby realizing that the charge Qdc can be continuously adjusted with higher bit precision in a higher bit range (e.g., 13 bits or more). The adjustment range of the equivalent capacitance C corresponding to the charge Qdc can be from tens of fF to hundreds of pF.

[0029] 4. When applied to ADCs, it can reduce the range requirements of the ADC.

[0030] 5. When applied to OLED touch devices, the charge source circuit extracts or injects the induced charge on the input electrode of the OLED touch device to achieve a reference reduction (DC reduction) of the induced charge of the OLED touch device, thereby improving the reference reduction effect of the OLED touch device and improving the OLED touch detection accuracy. Attached Figure Description

[0031] Figure 1 This is a schematic diagram of an existing charge source circuit and an ADC with the charge source circuit.

[0032] Figure 2 This is a schematic diagram of the charge source circuit according to an embodiment of the present invention.

[0033] Figure 3 for Figure 2 The diagram shows an example curve illustrating how the current gradient of a charge source circuit changes over time.

[0034] Figure 4 for Figure 2 This is another example of a schematic diagram showing the current gradient of a charge source circuit changing over a time period.

[0035] Figure 5 for Figure 2 The diagram shows a specific example of the structure of a charge source circuit.

[0036] Figure 6 for Figure 5 The diagram shows an example curve illustrating how the current gradient of a charge source circuit changes over time.

[0037] Figure 7 for Figure 5 This is another example of a schematic diagram showing the current gradient of a charge source circuit changing over a time period. Detailed Implementation

[0038] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the invention. However, it will be apparent to those skilled in the art that the invention may be practiced without one or more of these details. In other instances, certain technical features well-known in the art have not been described in order to avoid confusion with the invention. It should be understood that the invention can be embodied in various forms and should not be construed as limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the invention to those skilled in the art. The same reference numerals denote the same elements throughout. It should be understood that when an element is referred to as "connected to" or "coupled to" other elements, it may be directly connected to other elements, or there may be intervening elements. Conversely, when an element is referred to as "directly connected to" other elements, there are no intervening elements. As used herein, the singular forms "a," "an," and "the" are also intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the term "comprising" is used to identify the presence of features, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups. When used herein, the term "and / or" includes any and all combinations of the associated listed items.

[0039] As described in the background section, existing charge sources typically provide charge in the form of Qdc = Vcom * Cin.

[0040] For example, in organic light-emitting diode (OLED) touch panel applications, the capacitance C of a finger or other object approaching or touching the OLED touch panel is measured. finger The change (of which is a variable, ranging from tens of fF to several pF) is used to detect the corresponding touch information, where the capacitance C finger Typically, conversion is performed using an analog-to-digital converter (ADC), and the finger capacitance C is measured during the acquisition process. finger It will be superimposed on the screen capacitance C pannel Above (a constant value, ranging from a few pF to several hundred pF). Currently, to avoid finger capacitance C... finger and screen capacitor C pannelThe problem that the total capacitance collected might exceed the ADC's range is generally addressed by subtracting the reference capacitance, allowing the ADC's integrator 11 to subtract the screen capacitance C. pannel The resulting charge quantity Qdc is obtained by the corresponding charge source circuit 10 (which is used as a charge collector in this case) collecting (including extraction or injection) the charge on the input electrode of the OLED touch panel.

[0041] For details, please refer to Figure 1 Traditional analog-to-digital converters for OLED touch devices include a charge source circuit 10 and an integrator 11. The charge source circuit 10 typically employs an array of n+1 capacitors. The charge source circuit 10 extracts or injects a charge amount Qdc (output of the charge source circuit 10) from the induced charge on the input electrodes (not shown) of the OLED touch device to achieve a reference (DC reduction) of the induced charge of the OLED touch device.

[0042] Taking n=6 as an example, the charge source circuit 10 includes: capacitors C0 to C6 (forming a capacitor array), switches SB0 to SB6, SA0 to SA6, and S0 to S1. One end of capacitors C0 to C6 and one end of switch S0 are interconnected and connected to the inverting input of integrator A0 to provide the integrator A0 with a charge Qdc that is subtracted from the reference. The other end of capacitor C0 is coupled to one end of switches SA0 and SB0. The other end of capacitor C1 is coupled to one end of switches SA1 and SB1. The other end of capacitor C2 is coupled to one end of switches SA2 and SB2. The other end of capacitor C3 is coupled to one end of switches SA3 and SB3. At one end, the other end of capacitor C4 is coupled to one end of switches SA4 and SB4; the other end of capacitor C5 is coupled to one end of switches SA5 and SB5; the other end of capacitor C6 is coupled to one end of switches SA6 and SB6; the other ends of switches SA0 to SA6 and switch S0 are all coupled to the first voltage line Vcom; the other ends of switches SB0 to SB6 are all coupled to the second voltage line, and one end of the second voltage line is coupled to the fixed end of switch S1. The movable end of switch S1 can be selectively connected to the second voltage 2*Vcom or grounded AVSS. The control ends of switches SB0 to SB6 are connected to the switch signal V_S one by one. <0> ~V_S <6> The control terminals of switches SA0 to SA6 are connected to the switch signal V_L one by one. <0> ~V_L <6> The control terminal of switch S0 is connected to the clock signal CLK.

[0043] The capacitance values ​​of capacitors C0 through C6 are binary weighted. For example, the capacitance value of capacitor C0 is 1*150fF, the capacitance value of capacitor C1 is 2*150fF, the capacitance value of capacitor C2 is 4*150fF, the capacitance value of capacitor C3 is 8*150fF, the capacitance value of capacitor C4 is 16*150fF, the capacitance value of capacitor C5 is 32*150fF, and the capacitance value of capacitor C6 is 64*150fF. That is to say, the capacitance value of C1 is twice that of C0, the capacitance value of C2 is twice that of C1, the capacitance value of C3 is twice that of C2, the capacitance value of C4 is twice that of C3, the capacitance value of C5 is twice that of C4, and the capacitance value of C6 is twice that of C5.

[0044] In the circuit described above, the digital signal value Data<6:0> output by the analog-to-digital converter (ADC) corresponds to the 7-bit switching signals V_S<6:0> and V_L<6:0> of the capacitor array, controlling the value of the input Cin. Since the capacitance values ​​of capacitors C0 to C6 are binary weighted, respectively [64,32,16,8,4,2,1]*150fF, when the switching signals V_S<6:0> and V_L<6:0> take values ​​from 1111111 to 0000000, the total capacitance value Cin can be N*150fF, where N is any natural number from 0 to 127.

[0045] In the above scheme, if the charge Qdc of different bits is to be subtracted from the reference (e.g., to achieve a subtraction reference value of several hundred pF and an accuracy of tens of fF), then Vcom and Cin need to provide the required accuracy of the charge Qdc (e.g., accuracy of more than 13 bits). At this time, Vcom needs to use voltage divider technology and drive operational amplifiers to provide accurate voltages for different bits, which will make the circuit more complex and costly. If Cin needs to provide a lot of bit accuracy, large capacitors need to be added, and the increase in layout area is proportional to the capacitance, which will obviously greatly increase the layout area of ​​the capacitor.

[0046] Based on this, the present invention provides a novel technical solution that can provide charge quantities with an accuracy of over 13 bits within a very small area and at a very small voltage, with an adjustment range from tens of fF to hundreds of pF. It also avoids the problem of increasing circuit layout area due to the use of excessive capacitors, enabling the analog-to-digital converter to achieve low power consumption while simultaneously achieving small circuit layout area, large range, high speed, and high accuracy. Furthermore, by using this charge source circuit to extract and inject the induced charge on the input electrodes of the OLED touch device, a reference reduction (DC reduction) is achieved for the induced charge of the OLED touch device, thereby improving the reference reduction effect of the OLED touch device.

[0047] The technical solution proposed by the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.

[0048] Please refer to Figure 2 An embodiment of the present invention provides a charge source circuit 10, which includes a reference current generating module 101, a current mirroring module 102 and a charge output module 103 coupled in sequence.

[0049] The reference current generation module 101 provides a reference current, the current mirroring module 102 mirrors the reference current output by the reference current generation module 101, and the charge output module 103 converts the mirrored current output by the current mirroring module 102 into a corresponding charge quantity Qdc. The output charge quantity is calculated using the following formula: Qdc = Idc * t, where Qdc is the charge quantity output by the charge output module, Idc is the current magnitude provided by the charge output module, and t is the corresponding time provided by the charge output module. The time t is divided into at least two consecutive time periods, and the lengths of the two consecutive time periods are in a binary multiple relationship, so that the charge quantity Qdc is continuously adjustable.

[0050] In this embodiment, the charge output module 103 provides the corresponding current Idc in a binary weighted manner in each time period. Furthermore, the total time t is divided into n time periods according to the number of bits of the adjustment range of the actual required charge Qdc and the maximum number of bits of the current that can be provided in a time period (i.e., the maximum adjustment range of the current in a time period).

[0051] Specifically, let the maximum adjustment range of the current Idc that the charge output module can provide in each time period be k bits (that is, the maximum number of bits of current in a time period is k), and the adjustment range of the required charge Qdc be M bits, where M≥k+1.

[0052] When M is divisible by k, the number of time intervals divided by time t is n = M / k. Thus, n fixed time intervals are set for the required charge Qdc of M bits, and the adjustment range of the current Idc provided in each time interval is k bits. Consequently, the adjustment range of the charge Qdc in each time interval is k bits.

[0053] When M is not divisible by k, the number of time periods n divided by time t is n = int(M / k) + 1. Therefore, n fixed time periods are set for the required charge Qdc of M bits. The adjustment range of the charge Qdc provided in each of the first n-1 time periods is k bits, and the adjustment range of the charge Qdc provided in the last time period is M - (n-1) * k bits. Here, int() is the integer function, which means taking the integer without rounding.

[0054] It should be noted that, in order to achieve continuous adjustment of the charge quantity Qdc, the difference between the minimum value of the charge quantity Qdc in the earlier time period and the maximum value of the charge quantity Qdc in the later time period in any two consecutive time periods of n time periods is the minimum precision of the charge quantity Qdc.

[0055] Furthermore, to shorten the total time t, the n time intervals are arranged in chronological order, and the lengths of the time intervals gradually decrease in a binary multiple relationship. That is, in any two consecutive time intervals of the n time intervals, the length of the earlier time interval is p times the length of the later time interval (p = 2). q (i.e., a power of 2), and at the same time, the minimum current provided in the earlier time period is greater than the maximum current Idc provided in the later time period, thereby enabling a relatively high bit adjustment of the charge Qdc in the earlier time period and a relatively low bit adjustment of the charge Qdc in the later time period.

[0056] In this embodiment, to save circuit layout area, please further combine... Figure 5 Both the current mirror module 102 and the charge output module 103 are capacitor-free circuit modules, mainly constructed using transistors such as MOSFETs. The charge output module 103 has k current source branches, where k ≥ 2. When the charge output module 103 outputs charge Qdc bidirectionally, each current source branch includes an upper current source, an upper control switch SBW, a lower control switch SAW, and a lower current source, sequentially coupled. Each upper current source and upper control switch controls the current extraction of the k current source branches, and each lower current source and lower control switch controls the current injection of the k current source branches. The control terminals of the upper and lower current sources are coupled to the current mirror module 102. The upper end of the upper current source is connected to the corresponding operating voltage AVDD, and the lower segment of the lower current source is grounded to AVSS. The charge output module 103 controls the output of the k current source branches by controlling the on and off states of the corresponding upper control switch SBW and lower control switch SAW, achieving a binary weighted sum of the output current Idc at different time periods. Furthermore, the current source Idc flows into the input node of the integrator A2 in the subsequent stage, through the k-bit switching signal SBW. <k:1>The control generates a current of Idc = Nb * I0, where Nb is a k-bit binary value, ranging from [0 to (2^k). k -1)], I0 is the mirror current (i.e., unit mirror current) output by the current mirror module 101; the lower current source is the input node of the integrator A2 after the current Idc flows out, controlled by the k-bit switching signal SAW<6:1>, and the magnitude of the generated current is Idc=Na*I0, where Na is also a k-bit binary value, and its value range is [0~(2 k -1)].

[0057] As an example, please refer to Figure 3 The maximum number of bits for the current Idc provided in each time period is k, and the required number of bits for the charge Qdc is M = 3k. At this time, the number of time periods divided by time t is n = 3, meaning the charge output module 103 divides the time into three consecutive time periods: time 1, time 2, and time 3. The charge output by the charge output module 103 in each time period is Qdc = Idc * t, and the adjustment range of Idc in each time period from time 1 to time 3 is k bits. Specifically, the upper control switch SBW uses a k-bit switching signal SBW. <k:1>Control, the lower control switch SAW is controlled by a k-bit switching signal SAW. <k:1>Control. Specifically, when the duration t3 of time 3 is taken as the minimum system time, i.e., the reciprocal of the system frequency 1 / f, low-k-bit control of the charge quantity Qdc can be achieved. Time 2 is taken as 2 times the value of time 3. k Assuming k = 6, or 64 / f, it can achieve k-bit control of the charge Qdc, with time 1 taking the value of time 2. k Assuming k = 6, i.e., 64 * 64 / f, it can achieve high k-bit control of the charge Qdc, thus achieving a maximum of M = 3k-bit control of the charge Qdc. Furthermore, the minimum value of the charge Qdc provided in time 1 (the minimum value of Idc is I0, so the minimum value of the charge Qdc provided in time 1 = I0 * t1) and the maximum value of the charge Qdc provided in time 2 (for example, if k = 6, then the maximum value of Idc is (2...) 5 +2 4 +2 3 +2 2 +2 1 +2 0 If t1 = 63 * I0, then the maximum value of the charge Qdc provided within time 2 is 63 * I0 * t2. The difference between t1 and t2 is the minimum precision of the charge Qdc within time 2, which allows the charge Qdc to be continuously adjustable from the beginning of time 1 to the end of time 2. Therefore, time 1 needs to be set to 64 times time 2, i.e., t1 = 64 * t2. The minimum value of the charge Qdc provided at time 2 (the minimum value of Idc is I0, so the minimum value of the charge Qdc provided in time 2 = I0*t2) and the maximum value of the charge Qdc provided at time 3 (for example, if k = 6, then as mentioned before, the maximum value of Idc is 63*I0, so the maximum value of the charge Qdc provided in time 3 = 63*I0*t3) also differ from the minimum precision of the charge Qdc in time 3 by I0*t3. This allows the charge Qdc to be continuously adjustable from the beginning of time 2 to the end of time 3. Therefore, assuming k = 6, time 2 needs to be set to 64 times time 3, i.e., t2 = 64*t3, where t3 is set as the minimum system time.

[0058] As another example, please refer to Figure 4 , the maximum number of bits of the current Idc provided in each time period is k, the number of bits M of the required charge amount Qdc, and 2k < M < 3k. At this time, the number of time periods n into which the time t is divided is 3, that is, the charge output module 103 divides into three consecutive time periods: time 1, time 2, and time 3. The charge amount Qdc output by the charge output module 103 in each time period is Qdc = Idc * t. And the number of bits of the adjustment range of the current Idc in time 1 and time 2 is both k, and the number of bits of the adjustment range of the current provided in time 3 is M - 2k. Among them, when the duration t3 of time 3 takes the minimum time of the system, that is, the reciprocal 1 / f of the system frequency, it can achieve low (M - 2k)-bit control of the charge amount Qdc, and the value of time 2 is 2 (M-2K) times that of time 3. Assuming k = 6, that is, 4 / f, it can achieve medium k-bit control of the charge amount Qdc, and the value of time 1 is 2 k times that of time 2. Assuming k = 6, that is, 64 * 64 / f, it can achieve high k-bit control of the charge amount Qdc. Thus, a total of M-bit control of the charge amount Qdc can be achieved at most. And between the minimum value of the charge amount Qdc provided by time 1 and the maximum value of the charge amount Qdc provided by time 2, there is a difference of the minimum accuracy I0 * t2 of the charge amount Qdc in time 2. Between the minimum value of the charge amount Qdc provided by time 2 and the maximum value of the charge amount Qdc provided by time 3, there is also a difference of the minimum accuracy I0 * t3 of the charge amount Qdc in time 3. Thus, the charge amount Qdc can be continuously adjusted within the time from time 1 to the end of time 3.

[0059] When it is necessary for the charge output module 103 to unidirectionally output the charge amount (for example, the charge output module 103 realizes the extraction or injection of the induced charge on the input electrode of the OLED touch device to achieve the reduction of the reference), if only the induced charge is extracted, only the lower current source and the lower control switch are required, and the upper current source and the upper control switch can be omitted. If only the induced charge is injected, only the upper current source and the upper control switch are required, and the lower current source and the lower control switch can be omitted.

[0060] It should be noted that in this embodiment, each time period (such as the above time 1, time 2, and time 3) is fixed and does not participate in the adjustment of the charge amount Qdc. It is preset according to the adjustment range and accuracy required by the charge amount Qdc. Thus, in this embodiment, by adjusting the Na and Nb values in different time periods, different-bit adjustment of the charge amount Qdc can be achieved.

[0061] Furthermore, by setting the number and length of time periods, a higher bit range of charge Qdc output can be obtained first using a relatively longer time, followed by a shorter time to obtain a lower bit range of charge Qdc output. This shortens the overall output time of the total charge Qdc and improves speed. In particular, when the charge source circuit of this embodiment is applied to an analog-to-digital converter, it can improve the processing speed of the analog-to-digital converter; and when applied to an OLED touch device, it can improve the touch detection speed of the OLED touch device.

[0062] Furthermore, it should be understood that the implementation of the time interval gradient as a binary multiple and the current gradient as a binary weighted average are merely specific examples of the present invention and do not limit the technical scope of the present invention. In other embodiments of the present invention, the time interval gradient can also be any other suitable non-binary multiple method, and the current Idc gradient can also be any suitable non-binary weighted average method. In addition, the reference current generation module 101, the current mirror module 102, and the charge output module 103 can adopt any suitable circuit structure design, as long as they implement the function of the charge source circuit of the present invention.

[0063] As an example, the reference current generation module 101 can be a constant current source capable of outputting a constant current.

[0064] As another example, please refer to Figure 5 The reference current generation module 101 includes an operational amplifier A1, a first switching transistor PMb, a second switching transistor PMa, and a resistor R. Both the first switching transistor PMb and the second switching transistor PMa can be PMOS transistors. The source of the first switching transistor PMb is connected to the operating voltage AVDD, and the drain of the first switching transistor PMb is coupled to its source. The drain of the second switching transistor PMa is coupled to one end of the resistor R and the non-inverting input (+) of the operational amplifier A1. The other end of the resistor R is grounded. The inverting input (-) of the operational amplifier A1 is connected to the reference voltage Vref. The gate of the first switching transistor PMb is coupled to the output of the operational amplifier A1, and the gate of the second switching transistor PMa is connected to the first bias voltage signal Vbias1. When both the first switching transistor PMb and the second switching transistor PMa are turned on, the reference current generation module 101 generates a constant current I0 = Vref / R through the resistor R.

[0065] The current mirror module 102 includes an upper main mirror transistor PMb1, an upper cascade transistor PMa1, a lower cascade transistor NMa1, and a lower main mirror transistor NMb1. The source of the upper main mirror transistor PMb1 is connected to the operating voltage AVDD, the drain of the upper main mirror transistor PMb1 is coupled to the source of the upper cascade transistor PMa1, the drain of the upper cascade transistor PMa1 is coupled to the drain of the lower cascade transistor NMa1, the source of the lower cascade transistor NMa1 is coupled to the drain of the lower main mirror transistor NMb1, and the source of the lower main mirror transistor NMb1 is grounded A. VSS, the gate of the upper main mirror transistor PMb1 is coupled to the gate of the first switching transistor PMb and the output terminal of the operational amplifier A1, the gate of the upper cascade transistor PMa1 is connected to the first bias voltage signal Vbias1, the gate of the lower cascade transistor NMa1 is connected to the second bias voltage signal Vbias2, and the gate of the lower main mirror transistor NMb1 is coupled to the connection node between the upper cascade transistor PMa1 and the lower cascade transistor NMa1 and the corresponding terminal of each current source branch in the charge output module 103 (e.g., the gate of each second lower transistor).

[0066] Among them, the size of the upper main mirror transistor PMb1 is defined as M=1, which can mirror the current I0 flowing through the first switching transistor PMb in a 1:1 ratio.

[0067] The charge output module 103 is capable of bidirectionally outputting charge Qdc. It includes 6 current source branches, i.e., k=6. Each current source branch includes an upper current source, an upper control switch SBW, a lower control switch SAW, and a lower current source that are coupled in sequence. The upper current source includes a first upper transistor and a second upper transistor, and the lower current source includes a first lower transistor and a second lower transistor.

[0068] Specifically, the first current source branch includes a first upper transistor PM1b, a second upper transistor PM1a, and a circuit controlled by the switching signal SBW. <1> The upper control switch SBW is controlled by the switch signal SAW. <1> The lower control switch SAW, the first lower transistor NM1a, and the second lower transistor NM1b; the second current source branch includes the first upper transistor PM2b, the second upper transistor PM2a, and the switch signal SBW. <2> The upper control switch SBW is controlled by the switch signal SAW. <2> The lower control switch SAW, the first lower transistor NM2a, and the second lower transistor NM2b; the third current source branch includes the first upper transistor PM3b, the second upper transistor PM3a, and the switch signal SBW. <3> The upper control switch SBW is controlled by the switch signal SAW. <3> The lower control switch SAW, the first lower transistor NM3a, and the second lower transistor NM3b; the fourth current source branch includes the first upper transistor PM4b, the second upper transistor PM4a, and the switch signal SBW. <4> The upper control switch SBW is controlled by the switch signal SAW. <4> The lower control switch SAW, the first lower transistor NM4a, and the second lower transistor NM4b; the fifth current source branch includes the first upper transistor PM5b, the second upper transistor PM5a, and the switch signal SBW. <5> The upper control switch SBW is controlled by the switch signal SAW. <5> The lower control switch SAW, the first lower transistor NM5a, and the second lower transistor NM5b; the sixth current source branch includes the first upper transistor PM6b, the second upper transistor PM6a, and the switch signal SBW. <6> The upper control switch SBW is controlled by the switch signal SAW. <6> The lower control switch SAW, the first lower transistor NM6a, and the second lower transistor NM6b.

[0069] In the first current source branch, the drain of the first upper transistor PM1b is coupled to the source of the second upper transistor PM1a, the drain of the second upper transistor PM1a is coupled to one end of the upper control switch in the branch, the drain of the first lower transistor NM1a is coupled to one end of the lower control switch in the branch, the drain and source of the first lower transistor NM1a are coupled to the drain of the second lower transistor NM1b, and the source of the second lower transistor NM1b is grounded to AVSS.

[0070] The connections of the transistors and control switches in the current source branches 2 through 6 are the same as those in the current source branch 1, and will not be described in detail here.

[0071] Furthermore, the gates of the first upper transistors PM1b to PM6b can be coupled to each other and to the gate of the upper main mirror transistor PMb1 and the output terminal of the operational amplifier A1. The gates of the second upper transistors PM1a to PM6a can be coupled to each other and connected to the first bias voltage signal Vbias1. The gates of the first lower transistors NM1a to NM6a can be coupled to each other and connected to the second bias voltage signal Vbias2. The gates of the second lower transistors NM1b to NM6b can be coupled to each other and connected to the gate of the lower main mirror transistor NMb1.

[0072] It should be noted that the transistor sizes of the first upper transistors PM1b to PM6b are weighted in binary order. That is, the transistor size of the first upper transistor PM1b is M=1 and is the same as the transistor size of the upper main mirror transistor PMb1; the transistor size of the first upper transistor PM2b is M=2, which is twice the size of the first upper transistor PM1b; the transistor size of the first upper transistor PM3b is M=4, which is twice the size of the first upper transistor PM2b; the transistor size of the first upper transistor PM4b is M=8, which is twice the size of the first upper transistor PM3b; the transistor size of the first upper transistor PM5b is M=16, which is twice the size of the first upper transistor PM4b; and the transistor size of the first upper transistor PM6b is M=32, which is twice the size of the first upper transistor PM5b.

[0073] The dimensions of the second-lower transistors NM1b to NM6b are also weighted in binary. That is, the dimension M of the second-lower transistor NM1b is 1 and is the same as the dimension of the lower main mirror transistor NMb1; the dimension M of the second-lower transistor NM2b is 2, which is twice the dimension of the second-lower transistor NM1b; the dimension M of the second-lower transistor NM3b is 4, which is twice the dimension of the second-lower transistor NM2b; the dimension M of the second-lower transistor NM4b is 8, which is twice the dimension of the second-lower transistor NM3b; the dimension M of the second-lower transistor NM5b is 16, which is twice the dimension of the second-lower transistor NM4b; and the dimension M of the second-lower transistor NM6b is 32, which is twice the dimension of the second-lower transistor NM5b.

[0074] It should be noted that, in addition to using the size of the first upper transistor PM1b~PM6b and the second lower transistor NM1b~NM6b to achieve binary weighting of the mirror current magnitude of the 6 current source branches, parallel transistors can also be used (for example, the M=2 branch can be implemented by connecting two identical transistors in parallel as the M=1 branch) to achieve binary weighting of the mirror current magnitude of the 6 current source branches.

[0075] Furthermore, the second switching transistor PMa, the first switching transistor PMb, each of the first upper transistors, each of the second upper transistors, the upper main mirror transistor PMb1, and the upper cascade transistor PMa1 can all be PMOS transistors, and the lower cascade transistor NMa1, the lower main mirror transistor NMb1, each of the first lower transistors, and each of the second lower transistors can all be NMOS transistors. Of course, in other embodiments of the present invention, these MOS transistors can be replaced by suitable switching elements such as bipolar transistors or triodes.

[0076] Furthermore, each second upper transistor is a cascaded transistor of its cascaded first upper transistor, each first lower transistor is a cascaded transistor of its cascaded second lower transistor, the second switch PMa is a cascaded transistor of the first switch PMb, the upper cascaded transistor PMa1 is a cascaded transistor of the upper main mirror transistor PMb1, and the lower cascaded transistor NMa1 is a cascaded transistor of the lower main mirror transistor NMb1. The purpose of these cascaded transistors is to improve the load-carrying capacity and output current capability of their respective branches, reduce output impedance, without affecting current or voltage gain, and avoid output distortion in their respective branches.

[0077] In the current source branches of the charge output module 103 in this example, the cascaded first and second upper transistors constitute an upper current mirror (in other embodiments, more PMOS transistors can be cascaded to form an upper current mirror). This upper current mirror provides the current flowing into the inverting input of integrator A2, which can charge integrator A2. Therefore, when the switching signal SAW<6:1> controls all the first and second lower transistors to turn off, and further controls the on and off of the corresponding upper control switches through the switching signal SBW<6:1>, the number Nb of upper current mirrors providing current to integrator A2 can be adjusted. At this time, the current Idc flowing into the inverting input of integrator A2 is Ib*I0, and the corresponding charge Qdc = Idc*t = Nb*I0*t is injected into integrator A2. The value of Nb is 6-bit binary. When the switching signal SBW<6:1> is 111111, the maximum value of Nb is 32 + 16 + 8 + 4 + 2 + 1 = 2. 6 -1 = 63. When the switch signal SBW<6:1> is 00000, the value of Nb is at its minimum = 0. Therefore, the value range of Nb is 0 to 63.

[0078] It is worth noting that if the charge source circuit 10 is used for the OLED touchscreen's subtraction reference, then the screen capacitance C of the touchscreen is generally present after the touchscreen leaves the factory. pannel That's it, based on the screen capacitance C. pannel The amount of charge to be extracted or injected to reduce the reference is Qdc = Idc * t, where time t is controlled by the value of a control register of the processing unit (not shown, e.g., MCU); the magnitude of current Idc is determined by the processing unit (not shown, e.g., MCU) controlling the upper control switch SBW and the lower control switch SAW to adjust the values ​​of Na and Nb.

[0079] In this example, the required Qdc adjustment range is 18 bits (i.e., M = 18). Please further combine... Figure 6 The switching signal SAW<6:1> controls the lower current mirror to be completely turned off (i.e., no current output), and the switching signal SBW<6:1> controls the corresponding upper current mirror to charge the integrator A2. The charging time t is divided into n = M / k = 18 / 6 = 3 time periods, namely time 1 (duration or length t1), time 2 (duration t2), and time 3 (duration t3). The current Idc provided by the charge output module 103 in each time period can be controlled by 6 bits.

[0080] Let the lowest current be I. min Time 3 is selected as the minimum system time, i.e., t3 = the reciprocal of the system frequency f, 1 / f. Time 2 is 64 times time 3 (i.e., t2 = 64 / f), and time 1 is 64 times time 2 (i.e., t1 = 64 * 64 / f). Time 3 determines the minimum accuracy of the charge subtraction from the reference charge in integrator A2: Qdc = I0 * t3 = I min *1 / f, its equivalent minimum capacitance C 等效最小 For (I) min *1 / f) / Vin, where Vin is the input voltage.

[0081] Therefore, the total charge during the entire process of the switching signal SBW<6:1> controlling the upper current mirror to charge the integrator A2 is as follows:

[0082] Qdc = Qdc1 (时间1) +Qdc2 (时间2) +Qdc3 (时间3)

[0083] =Nb1 (时间1) *I0*t1+Nb2 (时间2) *I0*t2+Nb3 (时间3) *I0*t3

[0084] ={64*64*Nb1 (时间1) +64*Nb2 (时间2) +Nb3 (时间3) }*I0*t3.

[0085] Among them, Nb1 ( time 1) This indicates the value of Nb controlled by SBW<6:1> within time 1, where Nb1 is the value of Nb. (时间1) The value is 6 bits binary, ranging from 0 to 63, and can be obtained through Nb1 within time 1. (时间1) Achieve high 6-bit control of charge quantity Qdc; Nb2 (时间2) This indicates the value of Nb controlled by SBW<6:1> within time 2, Nb2 (时间2) The value is also 6 bits binary, ranging from 0 to 63, and can be obtained within 2 seconds using Nb2. (时间2 Achieve 6-bit control of charge quantity Qdc; Nb3 (时间3) This indicates the value of Nb controlled by SBW<6:1> within time 3, where Nb3 is the value of Nb. (时间3) The value is also 6 bits binary, ranging from 0 to 63, and can be obtained through Nb3 within 3 seconds. (时间3) Implement the lower 6 bits of charge quantity Qdc control.

[0086] Ultimately, the Qdc across the three time periods achieved 18-bit control, at which point the provided equivalent capacitance C... 等效 The adjustable range is 0 to C. 等效最小 *2 18 When C 等效最小 When the capacitance is over 50 fF, the equivalent capacitance C corresponding to the 18-bit Qdc is... 等效 The value range can meet the requirements from a few pF to several hundred pF. Moreover, because the time period and current gradient are continuous, Qdc can achieve continuous bit control within the three time periods. Specifically, within time period 3, a low-level adjustable Qdc3 is provided. Since Nb3 is 6-bit adjustable, its value range is 0 to 63. Therefore, the minimum value of Qdc3 in this level is 0 (when Nb3 takes the minimum value of 0), and the maximum value of Qdc3 in this level is 63 * I0 * t3 (when Nb3 takes the maximum value of 63). Within time 2, Qdc2 is adjustable at the medium setting. Since Nb2 is 6-bit adjustable, its value range is 0 to 63. When Nb2 is 1, the minimum value of Qdc2 for that setting is obtained = 64 * I0 * t3. The difference between the minimum value of Qdc2 provided within time 2 and the maximum value of Qdc3 provided within time 3 is exactly the minimum precision value of Qdc within time 3, I0 * t3. Therefore, time 2 and time 3 together perfectly achieve continuous bit control of Qdc. When Nb2 is 63, the maximum value of Qdc2 provided at the medium setting within time 2 is obtained = 64 * 63 * I0 * t3. Within time 1, Qdc1 is adjustable at a higher level. Since Nb1 is 6-bit adjustable, its value range is 0 to 63. When Nb1 is 1, the minimum value of Qdc1 at this level is 64 * 64 * I0 * t3. The difference between the minimum value of Qdc1 provided within time 1 and the maximum value of Qdc2 provided within time 2 is exactly the minimum precision value of Qdc within time 2, which is 64 * I0 * t3. Therefore, time 1 and time 2 together also achieve continuous bit control of Qdc.

[0087] In practical applications, only 14-bit precision (i.e., M=14) may be required, and the total time spent providing charge needs to be reduced (i.e., the time for the ADC to subtract the reference needs to be decreased). In this case, the following method is still used. Figure 5 The charge source circuit design shown is given, and k = 6. Further, combined with... Figure 7 In this practical application, the switching signal SAW<6:1> controls the lower current mirror to be completely turned off (i.e., no current flows in or out), and the switching signal SBW<6:1> controls the corresponding upper current mirror to charge the integrator A2 for a period of time t, which is divided into n = int(M / k) + 1 = int(14 / 6) + 1 = 2 + 1 = 3 time periods, namely time 1 (duration t1), time 2 (duration t2), and time 1 (duration t3). Time 3 is the minimum system time (i.e., t1 = the reciprocal of the system frequency 1 / f), time 2 is 4 times the value of time 3 (i.e., t2 = 4 / f), and time 1 is 64 times the value of time 2 (i.e., t1 = 64 * 4 / f). Furthermore, during time 3, the upper current mirror is controlled to charge integrator A2 via the switching signal SBW<2:1>, and during times 1 and 2, the upper current mirror is controlled to charge integrator A2 via the switching signal SBW<6:1>. The total charge amount for the entire process is as follows:

[0088] Qdc = Qdc1 (时间1) +Qdc2 (时间2) +Qdc3 (时间3)

[0089] =Nb1 (时间1) *I0*t1+Nb2 (时间2) *I0*t2+Nb3 (时间3) *I0*t3

[0090] ={64*4*Nb1 (时间1) +4*Nb2 (时间2) +Nb3 (时间3) }*I0*t3.

[0091] Among them, Nb1 (时间1) This indicates the value of Nb controlled by SBW<6:1> within time 1, where Nb1 is the value of Nb. (时间1) The value is 6 bits binary, ranging from 0 to 63, and can be obtained through Nb1 within time 1. (时间1) Achieve high 6-bit control of charge quantity Qdc; Nb2 (时间2) This indicates the value of Nb controlled by SBW<6:1> within time 2, Nb2 (时间2) The value is also 6 bits binary, ranging from 0 to 63, and can be obtained within 2 seconds using Nb2. (时间2 Achieve 6-bit control of charge quantity Qdc; Nb3 (时间3) This indicates the value of Nb controlled by SBW<2:1> within time 3, where Nb3 is the value of Nb. (时间3) The value is 2 bits binary, ranging from 0 to 3, and can be obtained within 3 seconds using Nb3. (时间3) To achieve low-2-bit control of the charge quantity Qdc, the adjustment range of Qdc provided in time periods 1 and 2 is k = 6 bits, and the adjustment range of Qdc provided in time period 3 is M - (n-1)*k = 14 - 2*6 = 2 bits. Ultimately, the overall Qdc across the three time periods achieves 14-bit control. Furthermore, when Nb3 reaches its maximum value of 3, the maximum value of Qdc3 in time period 3 is 3 * I0 * t3. When Nb2 reaches 1, the minimum value of Qdc2 in time period 2 is 4 * I0 * t3. The difference between the minimum value of Qdc2 in time period 2 and the maximum value of Qdc3 in time period 3 is exactly the minimum precision value of Qdc in time period 3, I0 * t3. Therefore, time periods 2 and 3 together achieve continuous bit control of Qdc. When Nb2 is 63, the maximum value of Qdc2 for the medium setting is 4*63*I0*t3 within time 2. When Nb1 is 1, the minimum value of Qdc1 for this setting is 64*4*I0*t3. The difference between the minimum value of Qdc1 provided within time 1 and the maximum value of Qdc2 provided within time 2 is exactly the minimum precision value of Qdc within time 2, which is 4*I0*t3. Therefore, time 1 and time 2 together also achieve continuous bit control of Qdc.

[0092] Similarly, in each current source branch of the charge output module 103 in this example, the cascaded first and second lower transistors form a lower current mirror. This lower current mirror provides the current flowing out of the inverting input terminal of integrator A2, and can discharge integrator A2. Therefore, when the switching signal SBW<6:1> controls all the first and second upper transistors to turn off, and further controls the conduction and turn-off of the corresponding upper control switches through the switching signal SAW<6:1>, the number Na of lower current mirrors providing current to integrator A2 can be adjusted. At this time, the current Idc flowing out of the inverting input terminal of integrator A2 is Na*I0, and the corresponding charge Qdc = Idc*t = Na*I0*t is extracted from integrator A2. The value of Na is 6-bit binary. When the switching signal SAW<6:1> is 111111, the maximum value of Na is 32+16+8+4+2+1=2. 6 -1 = 63. When the switch signal SAW<6:1> is 00000, the Na value is at its minimum of 0. Therefore, the range of Na is 0 to 63.

[0093] In this example, the required Qdc adjustment range is 18 bits (i.e., M = 18). Please further combine... Figure 6 The switching signal SBW<6:1> controls the upper current mirror to be completely turned off (i.e., no current flows in or out), and the switching signal SAW<6:1> controls the corresponding lower current mirror to discharge the integrator A2. The discharge time t is also divided into three consecutive time periods: time 1 (duration t1), time 2 (duration t2), and time 3 (duration t3) (i.e., n = M / k = 18 / 6 = 3). The current Idc provided by the charge output module 103 in each time period can be controlled by 6 bits.

[0094] Let the lowest current be I. min Time 3 is selected as the minimum system time, i.e., t1 = the reciprocal of the system frequency f, 1 / f. Time 2 is 64 times time 3 (i.e., t2 = 64 / f), and time 1 is 64 times time 2 (i.e., t1 = 64 * 64 / f). Time 1 determines the accuracy of the charge amount subtracted from the reference by the integrator A2: Qdc = I0 * t1 = I min *1 / f, its equivalent capacitance is (I min *1 / f) / Vin, where Vin is the input voltage.

[0095] Therefore, the total charge amount during the entire process of the switching signal SAW<6:1> controlling the discharge of the corresponding lower current mirror to integrator A2 is as follows:

[0096] Qdc = Qdc1 (时间1) +Qdc2 (时间2) +Qdc3 (时间3)

[0097] =Na1 (时间1) *I0*t1+Na2 (时间2) *I0*t2+Na3 (时间3) *I0*t3

[0098] ={64*64*Na1 (时间1) +64*Na2 (时间2) +Na3 (时间3) }*I0*t3.

[0099] Among them, Na1 (时间1) This indicates the value of Na controlled by SAW<6:1> within time 1, where Na1 is the value of Na. (时间1) The value is 6 bits binary, ranging from 0 to 63, and can be obtained through Nb1 within time 1. (时间1) Achieve high 6-bit control of current Idc; Na2 (时间2) This indicates the value of Na controlled by SAW<6:1> within time 2, Na2 (时间2) The value is also 6 bits binary, ranging from 0 to 63, and can be obtained through Na2 within time 2. (时间2 Achieve 6-bit control of current Idc; Na3 (时间3) This indicates the value of Na controlled by SAW<6:1> within time 3, Na3. (时间3) The value is also 6 bits binary, ranging from 0 to 63, and can be obtained through Na3 within 3 seconds. (时间3) The lower 6 bits of the current Idc are controlled. Ultimately, the overall Qdc across the three time periods achieves continuous 18-bit adjustment.

[0100] It should be understood that in the above examples, the charge output module 103 is bidirectional, capable of injecting or extracting charge into or out of the inverting input of the integrator 11 (i.e., providing current or charge flowing into and out of the integrator 11). However, the technical solution of the present invention is not limited to this. In other examples of the present invention, the charge output module 103 can be unidirectional, for example, by omitting... Figure 5 The upper circuits of each current source branch (including the first upper transistor, the second upper transistor, and the upper control switch) are configured so that the charge output module 103 can only provide the current flowing out of the integrator 11. Alternatively, the upper circuits of each current source branch (including the first upper transistor, the second upper transistor, and the upper control switch) are omitted. Figure 5 The lower circuits of each current source branch (including the first lower transistor, the second lower transistor, and the lower control switch) are configured so that the charge output module 103 can only provide current flowing into the integrator 11. Furthermore, in implementing the unidirectional output of the charge output module 103, the circuitry of modules such as the current mirror module 102 and the reference current generation module 101 can be adaptively adjusted to eliminate redundant circuitry that provides unwanted signals to the charge output module 103.

[0101] It should be further understood that, in the above examples, cascaded transistors and other components are provided, but the technical solution of the present invention is not limited to this, and cascaded transistors may be omitted in other embodiments of the present invention.

[0102] Based on the same inventive concept, please refer to Figure 5 This embodiment also provides an analog-to-digital converter (ADC), which includes an integrator 11 and a charge source circuit 10 as described in this invention. The output terminal of the charge source circuit 10 is coupled to the inverting input terminal of the integrator 11 and is used to provide a corresponding charge quantity Qdc to the integrator 11; the integrator 11 is used to perform a subtraction reference based on the charge quantity Qdc and output a corresponding digital signal.

[0103] Based on the same inventive concept, please refer to Figure 5 This embodiment also provides an OLED touch device, which includes an input electrode (not shown) and an analog-to-digital converter (ADC) as described above. The charge source circuit 10 in the ADC is coupled to the input electrode. The charge source circuit 10 is used to extract or inject a charge amount Qdc into the induced charge on the input electrode. The ADC outputs a corresponding digital signal based on the induced charge amount Qdc extracted or injected by the charge source circuit 10.

[0104] In summary, the charge source circuit, analog-to-digital converter, and OLED touch device of this invention no longer provide charge using the traditional Qdc = Vcom * Cin method, but instead provide charge according to Qdc = Idc * t. This avoids the use of voltage divider technology, driving operational amplifiers, and a large number of capacitors, thus simplifying the circuit, reducing costs, and saving circuit layout area. More importantly, by changing the current gradient of the current Idc and the time gradient of the time period, the charge Qdc can be continuously adjusted with precision within the required range in a very small area and at a very small voltage. This allows the adjustment range of the equivalent capacitance C corresponding to the charge Qdc to range from tens of fF to hundreds of pF, reducing the range requirements of the ADC. When applied to an OLED touch device, this charge source circuit extracts or injects the induced charge on the input electrode of the OLED touch device to achieve a reference reduction (DC reduction) of the induced charge of the OLED touch device, thereby improving the reference reduction effect of the OLED touch device and improving the OLED touch detection accuracy.

[0105] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the scope of the present invention.

Claims

1. A charge source circuit, characterized in that, include: A reference current generation module is used to provide a reference current; A current mirroring module, coupled to the reference current generating module, is used to perform current mirroring on the reference current; A charge output module, coupled to the current mirror module, is used to convert the mirrored current output by the current mirror module into a corresponding charge output, and the output charge is calculated using the following formula: Qdc = Idc * t, Wherein, Qdc is the amount of charge output by the charge output module, Idc is the magnitude of the current provided by the charge output module, and t is the time for the charge output module to provide the current. The time t is divided into at least two consecutive time periods, wherein the lengths of the two consecutive time periods are in a binary multiple relationship, so that the amount of charge Qdc is continuously adjustable.

2. The charge source circuit as described in claim 1, characterized in that, In any two consecutive time periods, the difference between the minimum value of charge Qdc in the earlier time period and the maximum value of charge Qdc in the later time period is the minimum precision of charge Qdc in the later time period.

3. The charge source circuit as described in claim 2, characterized in that, The charge output module provides the corresponding current Idc in a binary weighted manner at each time period.

4. The charge source circuit as described in claim 2, characterized in that, The maximum adjustment range of the current Idc provided by the charge output module in each time period is k bits; When the required charge Qdc adjustment range is M bits, M≥k+1, and M is divisible by k, the number of time periods n divided by the time t is n=M / k, and the charge Qdc provided in each of the n time periods is k bits. When the required charge Qdc adjustment range is M bits, M≥k+1, and M is not divisible by k, the number of time periods n divided by time t is n=int(M / k)+1, and the charge Qdc adjustment range provided in each of the first n-1 time periods is k bits, and the charge Qdc adjustment range provided in the last time period is M-(n-1)*k bits.

5. The charge source circuit as described in claim 4, characterized in that, The lengths of the n time periods arranged in chronological order are gradually shortened in a binary multiple relationship.

6. The charge source circuit as described in claim 3, characterized in that, The charge output module has k current source branches, k≥2, wherein each current source branch includes a current source and a control switch for selecting the output of the current source. The control terminal of each current source is coupled to the current mirror module. The charge output module controls the output of the k current source branches by turning on or off the corresponding control switch, thereby realizing a binary weighted sum of the current Idc output by the charge output module in different time periods.

7. The charge source circuit as described in claim 3, characterized in that, The charge output module has k current source branches, where k ≥ 2. Each current source branch includes an upper current source, an upper control switch, a lower control switch, and a lower current source that are coupled in sequence. Each upper current source and upper control switch controls the current drawn by the k current source branches, and each lower current source and lower control switch controls the current injected by the k current source branches.

8. The charge source circuit as described in claim 7, characterized in that, Each of the aforementioned upper current sources includes a cascaded PMOS transistor, and each of the aforementioned lower current sources includes a cascaded NMOS transistor.

9. The charge source circuit according to any one of claims 1 to 8, characterized in that, The reference current generation module is a constant current source; Alternatively, the reference current generation module includes an operational amplifier, a first switching transistor, a second switching transistor, and a resistor, wherein the drain of the first switching transistor is coupled to the source of the second switching transistor, the drain of the second switching transistor is coupled to one end of the resistor and the non-inverting input of the operational amplifier, and the gate of the first switching transistor is coupled to the output of the operational amplifier.

10. The charge source circuit according to any one of claims 1 to 8, characterized in that, The current mirror module includes an upper main mirror transistor, an upper cascade transistor, a lower cascade transistor, and a lower main mirror transistor coupled in sequence. The gate of the upper main mirror transistor is coupled to the corresponding terminals of the reference current generation module and the charge output module, respectively. The gate of the lower main mirror transistor is coupled to the corresponding terminal of the charge output module.

11. An analog-to-digital converter, characterized in that, The system includes an integrator and a charge source circuit as described in any one of claims 1 to 10; wherein the output terminal of the charge source circuit is coupled to the inverting input terminal of the integrator and is used to provide a corresponding charge quantity to the integrator; the integrator is used to perform a subtraction reference based on the charge quantity.

12. An OLED touch device, characterized in that, The system includes an input electrode and an analog-to-digital converter as described in claim 11, wherein a charge source circuit in the analog-to-digital converter is coupled to the input electrode, the charge source circuit is used to extract or inject the induced charge on the input electrode, and the analog-to-digital converter outputs a corresponding digital signal based on the induced charge after the charge source circuit extracts or injects the charge.

Images