A data processing method, device and storage medium

Abstract

The application discloses a data processing method, device and storage medium, wherein the method is applied to a DPU device, and the method comprises the following steps: through a hardware parser, it is confirmed that a received message is a bidirectional forwarding detection (BFD) message, and the BFD message is identified by bit; according to the bit identification, the BFD message is identified and sent to an open virtual switch (OVS); BFD session information sent by the OVS according to the BFD message is received, and a BFD control message sent by a network processor (NP) at a preset interval is received. Through the method, the processing delay can be reduced, and the timeliness and accuracy of fault detection can be improved.

Description

Technical Field

[0001] The present invention relates to the field of data processing, and in particular to a data processing method, device and storage medium. Background Art

[0002] In the DPU design, OVS's echo BFD is used to quickly detect communication failures between neighboring nodes. However, because echo BFD messages require a fast response, they may not be processed promptly, causing BFD to fail. Without timely processing, the sender may not be able to accurately determine the connection status, making it impossible to properly fix the problem. Summary of the Invention

[0003] The embodiments of the present application provide a data processing method to reduce processing delays and improve the timeliness and accuracy of fault detection.

[0004] In a first aspect, a data processing method is provided, characterized in that it is applied to a DPU device, and the method comprises the following steps:

[0005] The hardware analyzer confirms that the received message is a bidirectional forwarding detection (BFD) message and performs bit identification on the BFD message.

[0006] Identify the BFD message according to the bit identifier and send it to the open virtual switch OVS;

[0007] Receive BFD session information sent by the OVS according to the BFD message, and receive BFD control messages sent by the network processor NP according to a preset interval.

[0008] The above steps address the current DPU-based implementation's issues of delayed BFD message parsing and identification, as well as the significant processing latency caused by software processing of echo BFD messages. By implementing hardware marking, the DPU can rapidly process BFD messages and control messages used to establish BFD sessions, reducing processing latency and improving the timeliness and accuracy of fault detection. Furthermore, through optimized collaboration with OVS, the flexibility and reliability of network connections can be further enhanced.

[0009] In combination with the first aspect, in some implementations of the first aspect, the method further includes: the hardware parser performs bit identification on the BFD message through layered protocol parsing.

[0010] In conjunction with the first aspect, in some implementations of the first aspect, the method further includes:

[0011] Each processing module of the hardware parser adds two 32-bit flags registers, which parse the layered protocol based on the message content and set the corresponding bits to 1.

[0012] In conjunction with the first aspect, in certain implementations of the first aspect, the method includes:

[0013] Whether the message is a BFD message is determined by the flag in the flags register.

[0014] In combination with the first aspect, in some implementations of the first aspect, the method further includes: storing the initialization session from the OVS in a hash table in the data offload engine DOE, and setting the initialization state to down.

[0015] In conjunction with the first aspect, in certain implementations of the first aspect, the method includes:

[0016] When the NP receives a BFD echo message from the peer, it sets the state to up. If no message is received within a configured time interval, it sets the state to down.

[0017] In a second aspect, the present application provides a data processing device comprising a memory and a processor; the memory and the processor are coupled; the memory is used to store computer program code, and the computer program code comprises computer instructions; wherein, when the processor executes the computer instructions, the data processing device executes the data processing method as in the first aspect.

[0018] The device in the second aspect can be a chip, and the processor can be implemented by hardware or software. When implemented by hardware, the processor can be a logic circuit, an integrated circuit, etc.; when implemented by software, the processor can be a general-purpose processor, which is implemented by reading the software code stored in the memory. The memory can be integrated into the processor or can be located outside the processor and exist independently.

[0019] In a third aspect, the present application provides a processor comprising: an input circuit, an output circuit, and a processing circuit. The processing circuit is configured to receive a signal through the input circuit and transmit a signal through the output circuit, so that the processor executes the method in the first aspect.

[0020] In a fourth aspect, the present application provides a computer program product, comprising: a computer program (also referred to as code, or instruction), which enables a computer to execute the method in the first aspect when the computer program is executed.

[0021] In a fifth aspect, the present application provides a computer-readable storage medium, which stores a computer program (also referred to as code, or instructions) which, when run on a data processing device, enables the data processing device to execute the method in the first aspect above. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 A schematic flow chart of a data processing method provided in an embodiment of the present application;

[0023] Figure 2 A network structure diagram provided for an embodiment of the present application;

[0024] Figure 3 Flowchart of a method for sending a BFD control message to detect link status and update a BFD session provided in an embodiment of the present application;

[0025] Figure 4 A schematic diagram of session information provided in an embodiment of the present application;

[0026] Figure 5 A schematic structural diagram of a data processing device provided in the present application. DETAILED DESCRIPTION

[0027] In order to make the objects, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the examples and drawings. The illustrative embodiments of the present invention and their description are only used to explain the present invention and are not intended to limit the present invention. Any embodiment or design described as an "example" in this application should not be interpreted as being more preferred or more advantageous than other embodiments or design. The terms "include", "comprise", "have" and their variations all mean "including but not limited to", unless otherwise specifically emphasized. "At least one" means one or more, and "plurality" means two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural. The character " / " generally indicates that the associated objects before and after are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b and c can represent: a, or b, or c, or a and b, or a and c, or b and c, or a, b and c. Among them, a, b and c can be single or multiple. The descriptions related to network element A sending messages, information or data to network element B, and network element B receiving messages, information or data from network element A, are intended to explain to which network element the message, information or data is to be sent, but do not limit whether they are sent directly or indirectly via other network elements. Descriptions such as "when...", "in the case of...", "if" and "if" all mean that the device will make corresponding processing under certain objective circumstances, but do not limit the time, nor do they require the device to have a judgment action when implementing, nor do they mean that there are other limitations.

[0028] In addition, the architecture and business scenarios described in the embodiments of the present application are intended to more clearly illustrate the technical solutions of the embodiments of the present application, and do not constitute a limitation on the technical solutions provided in the embodiments of the present application. Ordinary technicians in this field can know that with the evolution of the architecture and the emergence of new business scenarios, the technical solutions provided in the embodiments of the present application are also applicable to similar technical problems.

[0029] The following are the abbreviations and full English and Chinese names of some terms in this application: DPU (Data Processing Unit), OVS (Open vSwitch), BFD (Bidirectional Forwarding Detection), DOE (Data Offload Engine), ETH (Ethernet), VLAN (Virtual Local Area Network), IPV4 (Internet Protocol Version 4), IPV6 (Internet Protocol Version 6), UDP (User Datagram Protocol), session, and parser.

[0030] In DPU design, different nodes need to maintain communication in some way to ensure that data can be transmitted correctly throughout the system. To achieve this, a software called OVS (Open vSwitch) is needed. It is an open source virtual switch that can provide network connection management and monitoring.

[0031] BFD is a network protocol dedicated to providing a fast connection status detection and notification mechanism. Through bidirectional detection, BFD can independently and in real time detect changes in network connections, such as link failures or node downtime. Its basic principle involves the periodic transmission of control messages containing key information about the connection status, such as sequence numbers and the peer IP address. A key feature of BFD is its extremely short message transmission interval, typically in the millisecond level, which ensures rapid detection of faults and the implementation of timely measures. Through a defined state machine, BFD describes changes in connection status, including initialization, start, and stop states. This flexible protocol can be widely used in multiple fields such as data center networks, wide area networks, and mobile networks to improve network stability and reliability, and is particularly suitable for scenarios requiring low latency and fast fault detection. BFD is a lightweight, fast-response protocol that provides the network with an efficient fault detection and notification mechanism, ensuring the stability of network connections.

[0032] In the DPU design, different node neighbors use OVS's BFD echo to quickly detect communication failures. BFD echo is a special message used to confirm whether the connection between the sender and receiver is still valid. If the sender does not receive a response to this message within a certain period of time, it assumes that the connection is broken and takes appropriate action to repair the problem.

[0033] However, due to the fast response requirements of ECHO BFD packets, these packets may not be processed in a timely manner, resulting in BFD failure. If these packets are not processed in a timely manner, the sender may not be able to accurately determine the connection status and thus cannot properly repair the fault.

[0034] Figure 1 1 is a schematic flow chart of a data processing method 100 provided in this application. The method 100 includes at least part of the following contents:

[0035] S201: Confirming, through a hardware parser, that a received message is a Bidirectional Forwarding Detection (BFD) message and performing bit marking on the BFD message;

[0036] In one implementation, the hardware parser in the DPU can identify BFD packets because these packets are encapsulated with a specific identifier when they are sent. In the BFD protocol, packets have a special field that identifies the packet type. Upon receiving a packet, the hardware parser first checks the value of this field. If the value indicates that the packet is a BFD packet, the hardware parser performs special processing on the packet, such as setting a specific bit to mark it as a BFD packet.

[0037] In other possible implementations, hardware parsers use deep packet inspection technology to deeply analyze network traffic and identify packets of various protocols, including BFD packets. This technology can analyze network traffic packet by packet, identify the signature codes and field information of various protocols, and thus determine the type of packet.

[0038] After a packet enters the DPU, it uses the hardware parser's bit identification to quickly identify BFD packets. A hardware parser is a hardware component specifically designed to parse network packets. It uses specific bit identification to quickly identify BFD packets. This identification can be a preset flag or field that indicates that the packet is a BFD packet. This allows the DPU to quickly identify and process BFD packets without relying on software parsing and identification.

[0039] The following is a way for the hardware parser to identify BFD packets:

[0040] Each processing module of the programmable Parser pipeline has added two 32-bit flags (registers) to perform logic to set any bit to 1; this allows the processing module to mark the layered protocol while parsing the layered protocol. Moreover, because the processing modules are combinable and linked, the bit marking of each layered protocol is not limited to 2 bits, and more markings can be provided through combination.

[0041] Each processing module can set any bit to 1, which means that multiple layered protocols can also implement the OR operation on the same bit.

[0042] By adding marking logic to the DPU's Parser pipeline, packets can be marked. This allows for faster identification and parsing of BFD packets and other layered protocols, improving data processing speed and efficiency.

[0043] Figure 2 A network structure diagram is shown. Figure 2 In the network structure shown, the BFD message starts from the ETH node and is parsed layer by layer according to the message content. The parsing path will be as follows: Figure 2 The arrow in the middle moves in the feasible direction, and the corresponding parsing action will be executed every time a node is passed. The bit marking capability of the programmable parser provides Figure 2 The tagging capability of each node on the network, for example, parsing BFD packets with VLAN encapsulation: ETH->VLAN1->IPV4->UDP->BFD.

[0044] S102: Identify the BFD message according to the bit identifier and send it to the open virtual switch OVS;

[0045] The DPU sends the identified BFD packets to the OVS for processing. The OVS is a virtual switch responsible for managing and processing network packets and also for configuring and managing BFD sessions. Based on the rules and configuration information of the BFD state machine, the OVS sends the BFD session to the DPU. The BFD state machine manages the state transitions of BFD sessions, including establishment, maintenance, and termination. The BFD session contains session parameters and configuration to enable subsequent link status detection.

[0046] In an optional embodiment, the method further includes:

[0047] S103: Receive BFD session information sent by the OVS according to the BFD message, and receive BFD control messages sent by the NP according to a preset interval.

[0048] The BFD session is sent by the OVS to the DPU. Subsequently, the NP will periodically send BFD control packets according to the configured time interval to detect the link status and update the BFD session.

[0049] In one embodiment, the OVS sends an initialization echo bfd session DOE based on the BFD configuration information. The information content includes the following fields:

[0050] Bfd configure:

[0051] bfd:enable

[0052] Bfd:fowrding_if_rx

[0053] Bfd:min_rx

[0054] Bfd:min_tx

[0055] Bfd:status

[0056] Bfd:bfd_src_ip

[0057] Bfd:bfd_dst_ip

[0058] bfd_src_ip is a random IP address generated by configuration, bfd_dst_ip is the peer IP address, and the initialized bfd:status is down. The local end sends a BFD echo packet. When the NP receives a BFD echo packet from the peer end, it sets the status to UP. If no packet is received within the configured time interval, the status is set to DOWN, indicating a link problem.

[0059] Figure 3 This is a flowchart of a method for optionally sending BFD control messages to detect link status and update BFD sessions. The specific implementation method is as follows:

[0060] 1. Echo bfd initializes the session uniformly from OVS configuration to DOE (Data offload engine) and stores it in hash table format. The session information content is as follows: Figure 4 As shown, the initial status is down.

[0061] 2. The NP determines based on the BFD enable bit. If BFD is enabled, it polls the BFD session in the DOE (Data Offload Engine) and returns the session content in the local buffer, waiting to trigger the sending of a BFD echo message.

[0062] 3. The NP allocates timer resources based on min_tx, then constructs an echo BFD packet and sends it to the designated egress.

[0063] 4. Upon receiving an echo BFD packet from the peer, the session status is updated to UP. BFD echo packets are then sent periodically at intervals. If no echo BFD packet is received within the specified detection time, the link is considered to have a problem and the session status is updated to DOWN.

[0064] 5. When NP updates the status of the session in DOE (Data Offload Engine), if the status changes, it needs to notify the software such as OVS through interruption to link the corresponding software protocol processing to achieve the purpose of rapid response.

[0065] The above steps address the current DPU-based implementation's issues of delayed BFD message parsing and identification, as well as the significant processing latency caused by software processing of echo BFD messages. By implementing hardware marking, the DPU can rapidly process BFD messages and control messages used to establish BFD sessions, reducing processing latency and improving the timeliness and accuracy of fault detection. Furthermore, through optimized collaboration with OVS, the flexibility and reliability of network connections can be further enhanced.

[0066] Figure 5 This is a structural diagram of a data processing device provided by an exemplary embodiment of the present application. Figure 5 As shown, the data processing device 500 includes at least one processor 501 and a memory 502 coupled to the processor 501. The processor 501 can execute corresponding steps in the above method disclosed in the embodiment of the present disclosure.

[0067] The processor 501 can also be referred to as a central processing unit (CPU), which can be an integrated circuit chip with signal processing capabilities. Each step in the method disclosed in the embodiment of the present disclosure can be completed by hardware integrated logic circuits in the processor 501 or by software instructions. The processor 501 can be a general-purpose processor, a digital signal processor (DSP), an ASIC, a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the method disclosed in the embodiment of the present disclosure can be directly implemented as being executed by a hardware decoding processor, or can be executed by a combination of hardware and software modules in the decoding processor. The software module can be located in the memory 502, such as a random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other storage media mature in the art. The processor 501 reads the information in the memory 502 and, in conjunction with its hardware, completes the steps of the method. In addition, the data processing device may further include a transceiver 503 coupled to the processor 501 for receiving and sending information or data.

[0068] An embodiment of the present disclosure further provides a computer-readable storage medium, wherein, when instructions in the computer-readable storage medium are executed by a processor of an electronic device, the electronic device is enabled to execute the above method disclosed in the embodiment of the present disclosure.

[0069] The computer-readable storage medium in the embodiments of the present disclosure can be a tangible medium that can contain or store a program for use by an instruction execution system, device or equipment or used in combination with an instruction execution system, device or equipment. The above-mentioned computer-readable storage medium can include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices or equipment, or any suitable combination of the above. More specifically, the above-mentioned computer-readable storage medium can include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above.

[0070] The computer-readable medium may be included in the data processing device, or may exist independently without being incorporated into the data processing device.

[0071] The embodiments of the present disclosure further provide a computer program product, including a computer program, wherein when the computer program is executed by a processor, the method disclosed in the embodiments of the present disclosure is implemented.

[0072] In embodiments of the present disclosure, computer program code for performing operations of the present disclosure may be written in one or more programming languages, or a combination thereof, including, but not limited to, object-oriented programming languages ​​such as Java, Smalltalk, and C++, as well as conventional procedural programming languages ​​such as "C" or similar programming languages. The program code may execute entirely on the user's computer, partially on the user's computer, as a stand-alone software package, partially on the user's computer and partially on a remote computer, or entirely on the remote computer or server.

[0073] In this specification, adjectives such as first and second may be used only to distinguish one element or action from another element or action, without necessarily requiring or implying any actual such relationship or order. Where circumstances permit, reference to an element or component or step (etc.) should not be construed as being limited to only one of the elements, components, or steps, but may be one or more of the elements, components, or steps, etc.

[0074] The various embodiments in this specification are described in a progressive manner. Similar portions between the various embodiments can be referenced to each other. Each embodiment focuses on the differences between the other embodiments. In particular, the hardware + program embodiments are generally similar to the method embodiments, so their description is relatively simple. For relevant portions, refer to the description of the method embodiments.

[0075] The foregoing description of this specification describes specific embodiments. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recited in the claims can be performed in an order different from that described in the embodiments and still achieve the desired results. Furthermore, the processes depicted in the accompanying drawings do not necessarily require the specific order shown or the sequential order to achieve the desired results. In certain embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0076] Although the present application provides method operation steps as described in the embodiments or flowcharts, more or fewer operation steps may be included based on conventional or non-creative work. The order of steps listed in the embodiments is only one way of executing the steps among many steps and does not represent the only execution order. When the actual device or client product is executed, it can be executed in sequence or in parallel according to the method shown in the embodiments or the drawings (for example, in a parallel processor or multi-threaded processing environment).

[0077] The systems, devices, modules or units described in the above embodiments may be implemented by computer chips or entities, or by products with certain functions.

[0078] Although the present specification embodiment provides the method operation steps as described in the embodiment or flow chart, more or less operation steps may be included based on conventional or non-creative means. The order of steps listed in the embodiment is only one way in the order of execution of many steps and does not represent a unique execution order. When the device or terminal product in practice is executed, it can be performed in sequence or in parallel according to the method shown in the embodiment or the accompanying drawings (such as a parallel processor or a multi-threaded processing environment, or even a distributed data processing environment). The term "comprise", "comprising" or any other variant thereof is intended to cover non-exclusive inclusion, so that the process, method, product or equipment including a series of elements not only include those elements, but also include other elements not clearly listed, or also include elements inherent to such process, method, product or equipment. In the absence of more restrictions, it is not excluded that there are other identical or equivalent elements in the process, method, product or equipment including the elements.

[0079] For the convenience of description, the above devices are described in terms of functions divided into various modules. Of course, when implementing the embodiments of this specification, the functions of each module can be implemented in the same or multiple software and / or hardware, or the modules that implement the same function can be implemented by a combination of multiple sub-modules or sub-units, etc. The device embodiments described above are merely schematic. For example, the division of the units is only a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or units, which can be electrical, mechanical or other forms.

[0080] Those skilled in the art will also appreciate that, in addition to implementing the controller in pure computer-readable program code, it is entirely possible to implement the same functionality by logically programming the method steps in the form of logic gates, switches, application-specific integrated circuits, programmable logic controllers, embedded microcontrollers, and the like. Therefore, such a controller can be considered a hardware component, and the devices included therein for implementing various functions can also be considered structures within the hardware component. Alternatively, the devices for implementing various functions can be considered both software modules implementing the method and structures within the hardware component.

[0081] The present invention is described with reference to flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowcharts and / or block diagrams, as well as combinations of processes and / or blocks in the flowcharts and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowcharts and / or block diagrams. Figure 1 a process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0082] These computer program instructions may also be stored in a computer readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 a process or multiple processes and / or boxes Figure 1 The function specified in one or more boxes.

[0083] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operational steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing the instructions executed on the computer or other programmable device for implementing the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0084] In a typical configuration, a computing device includes one or more processors (CPUs), input / output interfaces, network interfaces, and memory.

[0085] Memory may include non-permanent storage in a computer-readable medium, random access memory (RAM) and / or non-volatile memory in the form of read-only memory (ROM) or flash RAM. Memory is an example of a computer-readable medium.

[0086] Computer-readable media includes permanent and non-permanent, removable and non-removable media that can be implemented by any method or technology to store information. The information can be computer-readable instructions, data structures, program modules or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disc read-only memory (CD-ROM), digital versatile disc (DVD) or other optical storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices or any other non-transmission media that can be used to store information that can be accessed by a computing device. As defined herein, computer-readable media does not include transitory computer-readable media (transitory media), such as modulated data signals and carrier waves.

[0087] Those skilled in the art will appreciate that the embodiments of this specification may be provided as methods, systems, or computer program products. Therefore, the embodiments of this specification may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Furthermore, the embodiments of this specification may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to magnetic disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0088] Embodiments of this specification may be described in the general context of computer-executable instructions executed by a computer, such as program modules. Generally, program modules include routines, programs, objects, components, data structures, and the like that perform specific tasks or implement specific abstract data types. Embodiments of this specification may also be practiced in distributed computing environments where tasks are performed by remote processing devices connected via a communications network. In distributed computing environments, program modules may be located in local and remote computer storage media, including storage devices.

[0089] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between the various embodiments can be referenced across them. Each embodiment focuses on the differences from the other embodiments. In particular, since the system embodiments are generally similar to the method embodiments, their description is relatively simple. For relevant parts, reference can be made to the description of the method embodiments. Throughout this specification, reference to the terms "one embodiment," "some embodiments," "example," "specific example," or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with that embodiment or example are included in at least one embodiment or example of the embodiments in this specification. In this specification, the schematic representations of these terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, those skilled in the art may combine and integrate the different embodiments or examples, and features of different embodiments or examples, described in this specification, without conflict.

[0090] The above description is merely an example of the embodiments of this specification and is not intended to limit the embodiments of this specification. For those skilled in the art, various modifications and variations of the embodiments of this specification are possible. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the embodiments of this specification shall be included within the scope of the claims of the embodiments of this specification.

Claims

1. A data processing method, characterized in that: Applied to a data processing unit (DPU), the method includes: The hardware analyzer confirms that the received message is a bidirectional forwarding detection (BFD) message and performs bit identification on the BFD message. Identify the BFD message according to the bit identifier and send it to the open virtual switch OVS; receiving BFD session information sent by the OVS according to the BFD message, and receiving BFD control messages sent by the network processor NP according to a preset interval; Each level of processing module of the hardware parser is added with two 32-bit flags registers. The hardware parser performs bit identification on each layered protocol of the BFD message through layered protocol parsing.

2. The method according to claim 1, characterized in that The method comprises: The hardware parser parses the layered protocol based on the message content and sets the corresponding bits to 1.

3. The method according to claim 1, characterized in that Whether the message is a BFD message is determined by the flag in the flags register.

4. The method according to claim 1, wherein The receiving the BFD session information sent by the OVS according to the BFD message includes: The initialization session from the OVS is stored in a data offloading engine DOE in a hash table format, and the initialization state is set to down.

5. The method according to claim 4, characterized in that The method comprises: When the NP receives a BFD echo message from the peer, it sets the state to up. If no message is received within a configured time interval, it sets the state to down.

6. A data processing device, characterized in that: The invention comprises a memory and a processor; the memory and the processor are coupled; the memory is used to store computer program code, and the computer program code includes computer instructions; wherein, when the processor executes the computer instructions, the data processing device executes the data processing method according to any one of claims 1 to 5.

7. A computer-readable storage medium, characterized in that The computer-readable storage medium stores computer instructions; wherein, when the computer instructions are executed on a data processing device, the data processing device is caused to execute the data processing method according to any one of claims 1 to 5.

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