A method for realizing 4G signal air interface synchronization on 4G optical fiber repeater and small base station FPGA

Abstract

The present invention belongs to the field of wireless communication technology, and specifically relates to a method for realizing air interface synchronization of 4G signals on an optical fiber repeater and a small base station FPGA. The method comprises the following steps: performing power-on detection on a 4G optical fiber repeater or an integrated small base station to complete device initialization; performing synchronization channel capture configuration on the initialized 4G optical fiber repeater or the integrated small base station, shutting downlink processing of the 4G optical fiber repeater or the integrated small base station, and configuring the device to work in an uplink full-receiving mode; executing a signal processing algorithm in the FPGA of the optical fiber repeater or the integrated small base station, capturing a synchronization channel of a macro base station, and processing the capture correlation of a main synchronization channel; generating a new 10ms pulse according to the captured synchronization channel to complete time synchronization; optimizing the BOM list of a product, reducing a wireless communication module, and reducing material costs; optimizing the structural design of the product, and reducing the space occupied by the product.

Description

Technical Field

[0001] The present invention belongs to the technical field of wireless communications, and in particular relates to a method for realizing air interface synchronization of 4G signals on an optical fiber repeater and a small base station FPGA. Background Art

[0002] Fiber optic repeaters are repeaters that use optical fiber for signal transmission. They use the characteristics of low transmission loss, convenient wiring, and suitability for long-distance transmission to solve the problem of villages, towns, tourist areas, highways, etc. that cannot receive base station signals, as well as the problem of signal coverage in large and super-large buildings. They are used in large high-rise regional buildings (groups), communities, and other occasions with high requirements. Small base stations are devices used for wireless communications that can provide wireless signal coverage and realize mobile communication functions. The working principle of small base stations is to achieve communication by receiving and sending wireless signals. The first prerequisite for the operation of fiber optic repeaters and integrated small base stations is time synchronization, and the wireless scheduling frame must be aligned with the surrounding macro base stations at 10ms, so that the RF signals can be sent and received correctly.

[0003] At present, the technical solution of time synchronization by capturing satellite signals through star cards requires that the site where the communication equipment is deployed must have an aerial surface. Otherwise, due to insufficient satellite search, the star card will not be able to output the correct 10ms pulse, resulting in time synchronization failure.

[0004] In addition, time synchronization can be achieved by adding a 4G wireless communication module to the hardware to provide a 10ms timing pulse, but there will be an extra item on the hardware BOM table, and space must also be left in the structural design and selection of the hardware, which increases costs and is not conducive to the miniaturization of the equipment. Summary of the invention

[0005] The purpose of the present invention is to provide a method for realizing 4G signal air interface synchronization on a fiber optic repeater and a small base station FPGA, without adding a 4G wireless communication module. By capturing the synchronization channel of the surrounding macro base stations inside the fiber optic repeater and the integrated small base station, 10ms time synchronization is generated to solve the problems raised in the above background technology.

[0006] To achieve the above-mentioned purpose, the present invention adopts the following technical scheme: a method for realizing air interface synchronization of 4G signals on a fiber optic repeater and a small base station FPGA, comprising: performing power-on detection on the 4G fiber optic repeater or the integrated small base station to complete equipment initialization; performing synchronization channel capture configuration on the initialized 4G fiber optic repeater or the integrated small base station, shutting down the downlink processing of the 4G fiber optic repeater or the integrated small base station, and configuring the equipment to work in an uplink full reception mode; executing a signal processing algorithm in the FPGA of the fiber optic repeater or the integrated small base station, capturing the synchronization channel of the macro base station, and processing the capture correlation of the main synchronization channel; generating a new 10ms pulse according to the captured synchronization channel to complete time synchronization.

[0007] The power-on detection of the 4G fiber optic repeater or the integrated small base station includes: after the 4G fiber optic repeater or the integrated small base station is powered on, completing the hardware self-test operation to confirm that the initial working state of the equipment is normal; the crystal oscillator inside the 4G fiber optic repeater or the integrated small base station drives the clock phase-locked loop to enter the locked state of the local clock and generate a local 10ms pulse; and generating the PSS sequence and SSS sequence of the local synchronization channel in the RAM of the 4G fiber optic repeater or the integrated small base station.

[0008] The synchronous channel capture configuration of the initialized 4G fiber optic repeater or integrated small base station includes: the 4G fiber optic repeater or integrated small base station turns off the downlink processing of the repeater or the integrated small base station through the OM configuration interface, configures the device to work in the uplink full reception mode, configures the downlink transmission working frequency of the adjacent surrounding 4G wireless network through the OM configuration interface, and the device enters the silent reception state.

[0009] The capture correlation of the synchronization channel is processed, including: time domain data block processing, data block processing of the time domain data according to the bandwidth and sampling rate configuration of the 4G signal, and labeling of the block data; FFT transformation processing of the block data by the FFTCore operation inside the FPGA; extraction of intermediate frequency band data, the data of the main synchronization channel is located in the middle of the frequency band, the frequency domain data is extracted for processing, and correlation operation processing is performed with the local main synchronization channel sequence to calculate the correlation peak; search for the largest correlation peak, according to the setting of the algorithm, the correlation peak operation result only retains the largest correlation peak operation result, which is described in pseudo code; according to the setting of the algorithm threshold, it is determined whether the largest correlation peak exists, and according to the simulation calculation results, it is determined that the synchronization channel sequence is captured successfully; if the largest correlation peak does not exist, it is recalculated and the next data block is processed; if the largest correlation peak exists, the number of the largest correlation peak data block is recorded for the next step of processing.

[0010] The calculation of the correlation peak value includes: the main synchronization sequence is a complex sequence, the same sequence correlation operation will produce a correlation calculation value, and the correlation calculation results produced by different sequence correlation operations are obviously smaller; the main synchronization sequence correlation operation is a sequence multiplication and accumulation operation:

[0011] ;

[0012] According to the 4G protocol, the correlation calculation must be performed with the three local main synchronization sequences respectively, and the calculation results are recorded in the following format: {[starting offset], X_0 correlation calculation value, X_1 correlation calculation value, X_2 correlation calculation value}.

[0013] The pseudocode description of searching for the maximum correlation peak of the main synchronization sequence includes: at each [starting offset], if the X_0 correlation calculation value is greater than the current maximum correlation peak calculation value, then the current maximum correlation peak calculation value is equal to the X_0 correlation calculation value; if the X_1 correlation calculation value is greater than the current maximum correlation peak calculation value, then the current maximum correlation peak calculation value is equal to the X_1 correlation calculation value; if the X_2 correlation calculation value is greater than the current maximum correlation peak calculation value, then the current maximum correlation peak calculation value is equal to the X_2 correlation calculation value.

[0014] The method of generating a new 10ms pulse based on the captured synchronization channel to complete time synchronization includes: generating a local 5ms scheduling pulse based on the data block number output by the maximum correlation peak search algorithm; judging whether the 4G signal of the macro base station is FDD or TDD based on the position of the auxiliary synchronization signals of FDD and TDD in the wireless frame structure diagram; calculating the 10ms clock adjustment amount based on the 5ms pulse alignment according to the position relationship of the auxiliary synchronization signal, generating a new 10ms scheduling pulse, and completing air interface time synchronization.

[0015] The method of generating a local 5 ms scheduling pulse according to the data block number output by the maximum correlation peak search algorithm includes:

[0016] According to the correlation peak search operation in the previous step, the relevant local 5ms pulse where the correlation peak appears has been obtained. According to the number of symbol samples appearing in the main synchronization channel, the target is adjusted, and the local 5ms is adjusted to align the local 5ms with the target 5ms, including: if the maximum correlation peak capture point [starting offset] is greater than the number of sampling points 28528, the local 5ms clock is delayed, and the number of delayed samples is equal to the difference between the number of [starting offset] points and the number of 28528 samples; if the maximum correlation peak capture point [starting offset] is less than the number of sampling points 28528, the local 5ms clock is advanced, and the number of advanced samples is equal to the difference between the number of 28528 samples and the number of [starting offset] points.

[0017] The method of judging whether the 4G signal of the macro base station is FDD or TDD includes: the auxiliary synchronization signal of FDD is advanced by 1 symbol of the main synchronization signal, and the auxiliary synchronization signal of TDD is advanced by 2 symbols of the main synchronization signal, and data is intercepted according to the symbol offset based on the alignment of the previous 5ms clock; the auxiliary synchronization signal is also mapped on the 6RB in the middle of the frequency band, and the basic sequence length is also 62. What is different from the main synchronization is that 5 zeros are added to the head and tail of the sequence; the modulation mode of the auxiliary synchronization sequence is BPSK, plus 10 zeros at the head and tail; based on the comparison result of the auxiliary synchronization sequence, it is determined whether it is TDD or FDD, and the exact symbol position of the first half frame or the second half frame.

[0018] The calculation of the 10ms clock adjustment amount includes:

[0019] If the current 4G signal is in FDD mode, then determine whether the local 5ms is in the first half frame or the second half frame of FDD. If it is in the first half frame, the local 10ms advance adjustment amount is equal to 28528 sampling points; if it is in the second half frame, the local 10ms advance adjustment amount is equal to 182128 sampling points.

[0020] If the current 4G signal is in TDD mode, then determine whether the local 5ms is in the first half frame or the second half frame of TDD. If it is in the first half frame, the local 10ms advance adjustment amount is equal to 39504 sampling points; if it is in the second half frame, the local 10ms advance adjustment amount is equal to 193104 sampling points.

[0021] Technical effects and advantages of the present invention: The method for realizing 4G signal air interface synchronization on a fiber repeater and a small base station FPGA proposed by the present invention has the following advantages over the prior art:

[0022] The present invention performs power-on detection on a 4G optical fiber repeater or an integrated small base station to complete device initialization; performs synchronization channel capture configuration on the initialized 4G optical fiber repeater or integrated small base station, turns off downlink processing of the 4G optical fiber repeater or the integrated small base station, and configures the device to work in an uplink full-receiving mode; executes a signal processing algorithm in the FPGA of the optical fiber repeater or the integrated small base station, captures the synchronization channel of the macro base station, and processes the capture correlation of the main synchronization channel; generates a new 10ms pulse according to the captured synchronization channel to complete time synchronization; the BOM list of the product can be optimized, a wireless communication module can be reduced, and the material cost can be reduced. The structural design of the product can be optimized, and the space occupied by the product can be reduced. Compared with the time synchronization completed by an external wireless communication module, the synchronization time can be shortened. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1It is a flow chart of a method for realizing 4G signal air interface synchronization on a fiber optic repeater and a small base station FPGA of the present invention;

[0024] Figure 2 This is a flow chart of power-on detection of the present invention;

[0025] Figure 3 A flowchart configured for capturing the present invention;

[0026] Figure 4 A flowchart for processing the acquisition correlation of the primary synchronization channel of the present invention;

[0027] Figure 5 This is a flow chart of TDD or FDD determination of the present invention;

[0028] Figure 6 It is a flow chart of judging the first half frame or the second half frame of the present invention;

[0029] Figure 7 This is a flow chart of the time synchronization of the present invention. DETAILED DESCRIPTION

[0030] The following will be combined with the accompanying drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments. The specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0031] The present invention provides a method for realizing 4G signal air interface synchronization on a fiber optic repeater and a small base station FPGA, such as Figure 1-Figure 7 As shown, the following steps are included:

[0032] Step 1: Power on the 4G fiber repeater or integrated small base station for testing and complete device initialization;

[0033] Specifically, after the 4G fiber optic repeater or integrated small base station is powered on, the hardware self-test operation is completed to confirm that the initial working status of the equipment is normal; the crystal oscillator inside the 4G fiber optic repeater or integrated small base station drives the clock phase-locked loop to enter the locked state of the local clock and generate a local 10ms pulse; the PSS sequence and SSS sequence of the local synchronization channel are generated in the RAM of the 4G fiber optic repeater or integrated small base station (according to the provisions of 36211 6.11.1.1, the PSS main synchronization sequence has 3 root sequences, which can be generated in advance for direct reading and use) and SSS sequence (according to the provisions of 362116.11.2.1, there are 168 SSS sequences).

[0034] Step 2: Perform synchronous channel capture configuration on the initialized 4G fiber repeater or integrated small base station, turn off the downlink processing of the 4G fiber repeater or integrated small base station, and configure the device to work in the uplink full reception mode;

[0035] Specifically, the 4G fiber-optic repeater or integrated small base station uses the OM configuration interface to turn off the downlink processing of the repeater or integrated small base station, configures the device to work in the uplink full-receive mode, and configures the downlink transmission working frequency of the adjacent surrounding 4G wireless network through the OM configuration interface, and the device enters the silent receiving state.

[0036] Furthermore, there is a default working premise for configuring the downlink transmission working frequency of the adjacent surrounding 4G wireless networks, that is, the general working deployment mode of the repeater and the integrated small base station is to fill the blind spots of the existing 4G network, so the repeater or the integrated small base station and the surrounding 4G public network have the same frequency.

[0037] Step 3: In the FPGA of the optical fiber repeater or integrated small base station, execute the signal processing algorithm to capture the synchronization channel of the macro base station and process the capture correlation of the main synchronization channel;

[0038] Specifically, processing the acquisition correlation of the synchronization channel includes:

[0039] a. Block processing of time domain data. Block the time domain data according to the bandwidth and sampling rate configuration of the 4G signal, and label the block data. Block and sliding window processing of time domain signals are the key to synchronous channel search. The following takes the 4G bandwidth 20M and the sampling rate 30.72M as an example to explain the signal block method;

[0040] a.1 The synchronization channel will appear twice in 10ms, that is, a synchronization channel will appear every 5ms, so the first step of the algorithm is to traverse each sampling point in 5ms and search for the synchronization channel.

[0041] a.2 The time domain signal is divided by [starting offset];

[0042] Because it is driven by the local clock, the target signal is searched traversally. At the same time, it has been explained that as long as the search is traversed for 5ms, the synchronization channel can be searched. [Start offset] means: how many sampling points are offset from the 5ms pulse of the local clock; according to the 4G protocol, each 1ms is a subframe, and the search interval is 5ms, so the search subframe number is 0-4; according to the 4G protocol, each subframe consists of 14 symbols, so the symbol number is 0-13. The following table explains the number of sampling points of 1 subframe symbol with 20M bandwidth:

[0043]

[0044] a.3 Based on the structure of the synchronization channel, it is known that the primary synchronization channel will only appear at symbol 13 or symbol 4, so in the processing of time domain data blocks, the number of samples taken from the [start offset] position each time is 2192 sampling points.

[0045] b. FFT transformation processing of time domain data. In the data block processing in the previous step, the algorithm intercepted 2192 sampling point data. The current setting is 20M bandwidth, FFT_SIZE is 2048, and after removing 144 CP prefix samples, FFT operation is performed. This step is executed by the FFTCore operation inside the FPGA.

[0046] c. Extraction of intermediate frequency band data: The data of the primary synchronization channel is located in the middle of the frequency band, and the frequency domain data is extracted for processing (according to 4G protocol specification 362116.11.1, the PSS sequence length is 62 samples).

[0047] d. Perform correlation processing with the local primary synchronization channel sequence and calculate the correlation peak value:

[0048] d.1 The main synchronization sequence is a complex sequence with strong autocorrelation characteristics. The same sequence correlation operation will produce a large correlation calculation value, and the correlation calculation results produced by different sequence correlation operations will be significantly smaller.

[0049] d.2 The main synchronization sequence correlation operation is a sequence multiplication and accumulation operation

[0050]

[0051] According to the 4G protocol, there are three alternative main synchronization sequences, so the correlation calculation here needs to be performed with the three local main synchronization sequences respectively, and the calculation results are recorded in the following format:

[0052] {[starting offset], X_0 related calculated value, X_1 related calculated value, X_2 related calculated value};

[0053] e. Search for the largest correlation peak. According to the algorithm settings, the correlation peak calculation results only retain the largest correlation peak operation results, including: at each [starting offset], if the X_0 correlation calculation value is greater than the current maximum correlation peak calculation value, then the current maximum correlation peak calculation value is equal to the X_0 correlation calculation value; if the X_1 correlation calculation value is greater than the current maximum correlation peak calculation value, then the current maximum correlation peak calculation value is equal to the X_1 correlation calculation value; if the X_2 correlation calculation value is greater than the current maximum correlation peak calculation value, then the current maximum correlation peak calculation value is equal to the X_2 correlation calculation value. Pseudo code is described as follows:

[0054] begin

[0055] if(X_0 correlation calculation value>maximum correlation value)

[0056] then{maximum correlation value = X_0 correlation calculation value, maximum offset = current offset}

[0057] if(X_1 correlation value > maximum correlation value)

[0058] then{maximum correlation value = X_1 correlation calculation value, maximum offset = current offset}

[0059] if(X_2 correlation calculation value>maximum correlation value)

[0060] then{maximum correlation value = X_2 correlation calculation value, maximum offset = current offset}

[0061] end.

[0062] f. According to the algorithm threshold setting, determine whether the maximum correlation peak exists

[0063] According to the simulation calculation results, when the X_correlation operation value>(32768*62), it can be determined that the synchronization channel sequence is captured successfully. In actual engineering applications, the signal-to-noise ratio must be actually tested to adjust the size of the judgment value.

[0064] g. If the maximum correlation peak does not exist, the algorithm flow returns to a and processes the next data block (the sliding window processing here is to perform a new operation from the offset+1 position); if the maximum correlation peak exists, the number of the maximum correlation peak data block is recorded for the next step of processing.

[0065] Step 4: Generate a new 10ms pulse based on the captured synchronization channel to complete time synchronization;

[0066] The specific steps are as follows:

[0067] a. Generate a local 5ms scheduling pulse based on the data block number output by the maximum correlation peak search algorithm;

[0068] a.1 According to the correlation peak search operation in the previous step, the [starting offset] of the local 5ms pulse where the correlation peak appears has been obtained. According to the number of symbol samples appearing in the primary synchronization channel (FDD is at symbol 13, the sample offset number is 28528; TDD is at symbol 4, the sample offset number is 30720+8784);

[0069] a.2 Take 28528 as the adjustment target of the local 5ms, adjust the local 5ms to align the local 5ms with the target 5ms, including: if the maximum correlation peak capture point [starting offset] is greater than the sampling point number 28528, then the local 5ms clock needs to be delayed, and the number of delayed samples is equal to the difference between the number of [starting offset] points and the number of 28528 samples; if the maximum correlation peak capture point [starting offset] is less than the sampling point number 28528, then the local 5ms clock needs to be advanced, and the number of advanced samples is equal to the difference between the number of 28528 samples and the number of [starting offset] points. The pseudo code is described as follows (the meaning of this step of 5ms time adjustment is: the 2192 sampling point data taken from the current 5ms starting point is the symbol where the primary synchronization channel is located):

[0070] begin

[0071] if[starting offset]>28528

[0072] Then the local delay is 5ms, and the number of delayed samples = [starting offset] – 28528

[0073] else

[0074] Then the local time is advanced by 5 ms, and the number of advanced samples = 28528 – [starting offset]

[0075] end.

[0076] b. According to the position of the auxiliary synchronization signals of FDD and TDD in the wireless frame structure diagram, determine whether the 4G signal of the macro base station is FDD or TDD;

[0077] b.1 The auxiliary synchronization signal of FDD is one symbol ahead of the main synchronization signal, and the auxiliary synchronization signal of TDD is two symbols ahead of the main synchronization signal. Based on the alignment of the previous 5ms clock, data is intercepted according to the symbol offset;

[0078] b.2 The auxiliary synchronization signal is also mapped on the 6RB in the middle of the frequency band. The basic sequence length is also 62. What is different from the primary synchronization is that 5 zeros are added at the beginning and end of the sequence.

[0079] b.3 The auxiliary synchronization has different data combinations in the first half frame and the second half frame, so there are 168*2 combinations of auxiliary synchronization;

[0080] b.4 The modulation mode of the auxiliary synchronization sequence is BPSK, with 10 zeros at the beginning and the end, so the correlation operation determination method of the auxiliary synchronization sequence is the sequence direct comparison method;

[0081] b.5 Based on the comparison result of the auxiliary synchronization sequence, it can be determined whether it is TDD or FDD, and whether it is the precise symbol position of the first half frame or the second half frame.

[0082] c. According to the position relationship of the auxiliary synchronization signal, on the basis of 5ms pulse alignment, calculate the 10ms clock adjustment amount, generate a new 10ms scheduling pulse, and complete the air interface time synchronization; including: if the current 4G signal is in FDD mode, then determine whether the local 5ms is in the first half frame or the second half frame of FDD. If it is in the first half frame, the local 10ms advance adjustment amount is equal to 28528 sampling points; if it is in the second half frame, the local 10ms advance adjustment amount is equal to 182128 sampling points. If the current 4G signal is in TDD mode, then determine whether the local 5ms is in the first half frame or the second half frame of TDD. If it is in the first half frame, the local 10ms advance adjustment amount is equal to 39504 sampling points; if it is in the second half frame, the local 10ms advance adjustment amount is equal to 193104 sampling points. The pseudo code for calculating the 10ms clock adjustment amount is as follows:

[0083] begin

[0084] if(is FDD mode)

[0085] if (is the first half frame)

[0086] Then 10ms advance adjustment amount = 28528

[0087] else

[0088] Then 10ms advance adjustment amount = 28528 + 30720*5;

[0089] end

[0090] if (is TDD mode)

[0091] if (is the first half frame)

[0092] Then 10ms advance adjustment amount = 8784+30720

[0093] else

[0094] Then 10ms advance adjustment amount = 8784+30720 + 30720*5;

[0095] end.

[0096] In this embodiment, the 4G fiber optic repeater or integrated small base station is powered on for detection to complete device initialization; the initialized 4G fiber optic repeater or integrated small base station is configured for synchronization channel capture, the downlink processing of the 4G fiber optic repeater or integrated small base station is turned off, and the device is configured to work in an uplink full reception mode; in the FPGA of the fiber optic repeater or integrated small base station, a signal processing algorithm is executed to capture the synchronization channel of the macro base station, and the capture correlation of the main synchronization channel is processed; a new 10ms pulse is generated according to the captured synchronization channel to complete time synchronization; the BOM list of the product can be optimized, one wireless communication module can be reduced, and the material cost can be reduced. The structural design of the product can be optimized, and the product occupancy space can be reduced. Compared with the time synchronization completed by the external wireless communication module, the synchronization time can be shortened.

[0097] In addition, the abbreviations and key terms involved in this embodiment are defined as follows:

[0098] 10ms: 10 milliseconds. In the field of wireless communications, the length of each frame of data transmitted by a wireless signal is 10 milliseconds;

[0099] 5ms: 5 milliseconds. In 4G 5G communications, half the length of each frame is 5 milliseconds;

[0100] TDD: Timing Division Duplex, uplink and downlink work on the same frequency in time division;

[0101] FDD: Frequency Division Duplex, uplink and downlink work at different frequencies respectively;

[0102] PSS: Primary synchronization signal The primary synchronization signal of the 4G communication system;

[0103] SSS: Secondary synchronization signal 4G communication system auxiliary synchronization signal;

[0104] Related: cross-corelation correlation operation;

[0105] Air interface: air interface for wireless communication;

[0106] Time synchronization: The base station ensures that the wireless frame of the air interface is aligned with the 10ms of the timing system.

[0107] Finally, it should be noted that the above is only a preferred embodiment of the present invention and is not intended to limit the present invention. Although the present invention has been described in detail with reference to the aforementioned embodiments, it is still possible for those skilled in the art to modify the technical solutions described in the aforementioned embodiments or to make equivalent substitutions for some of the technical features therein. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A method for realizing 4G signal air interface synchronization on a 4G optical fiber repeater and a small base station FPGA, characterized in that: include: Power on the 4G optical fiber repeater or integrated small base station for testing and complete device initialization; Perform synchronous channel capture configuration on the initialized 4G fiber repeater or integrated small base station, turn off the downlink processing of the 4G fiber repeater or integrated small base station, and configure the device to work in the uplink full reception mode; In the FPGA of the 4G fiber repeater or integrated small base station, the signal processing algorithm is executed to capture the synchronization channel of the macro base station and process the capture correlation of the main synchronization channel sequence; Generate a new 10ms pulse based on the captured synchronization channel to complete time synchronization; The power-on detection of the 4G optical fiber repeater or the integrated small base station includes: After the 4G fiber repeater or integrated small base station is powered on, complete the hardware self-test operation to confirm that the initial working status of the device is normal; The crystal oscillator inside the 4G fiber repeater or integrated small base station drives the clock phase-locked loop, enters the locked state of the local clock, and generates a local 10ms pulse; Generate a primary synchronization channel sequence and a secondary synchronization channel sequence of a local synchronization channel in the RAM of a 4G optical fiber repeater or an integrated small base station; The synchronous channel capture configuration of the initialized 4G optical fiber repeater or integrated small base station includes: The 4G fiber repeater or integrated small base station uses the OM configuration interface to turn off the downlink processing of the 4G fiber repeater or integrated small base station, configure the device to work in the uplink full reception mode, and configure the downlink transmission working frequency of the adjacent surrounding 4G wireless network through the OM configuration interface, and the device enters the silent reception state; Processing the acquisition correlation of the primary synchronization channel sequence includes: Time domain data block processing: divide the time domain data into blocks according to the bandwidth and sampling rate configuration of the 4G signal, and number the time domain block data; The FFTCore inside the FPGA performs FFT transformation on the time domain block data; Extraction of intermediate frequency band data: The data of the primary synchronization channel sequence is located in the middle of the frequency band. The frequency domain data is extracted for processing and correlated with the local primary synchronization channel sequence to calculate the correlation peak value. Search for the largest correlation peak. According to the algorithm settings, the correlation peak calculation results only retain the largest correlation peak search result, which is described by pseudo code; According to the setting of the algorithm threshold, determine whether the maximum correlation peak exists, and according to the calculation result, determine whether the main synchronization channel sequence is successfully captured; If the maximum correlation peak does not exist, the next time domain block data is recalculated and the next time domain block data is processed; if the maximum correlation peak exists, the number of the time domain block data with the maximum correlation peak is recorded for the next step of processing; The calculating of the correlation peak value comprises: The primary synchronization channel sequence is a complex sequence. The correlation operation of the same sequence will produce a correlation calculation value, and the correlation calculation result produced by the correlation operation of different sequences will be significantly smaller. The primary synchronization channel sequence correlation operation is a sequence multiplication and accumulation operation: ； According to the 4G protocol, the correlation operation must be performed with the three local primary synchronization channel sequences respectively, and the operation results are recorded; The step of generating a new 10ms pulse according to the captured synchronization channel to complete time synchronization includes: The starting offset of the local 5ms pulse is generated according to the number of the time domain block data with the maximum correlation peak output from the maximum correlation peak search, and the local 5ms pulse is adjusted according to the number of symbol samples appearing in the primary synchronization channel sequence, so that the local 5ms pulse is aligned with the target 5ms pulse, and a local 5ms scheduling pulse is generated; On the basis that the 5ms pulse has been aligned, the position of the auxiliary synchronization channel of FDD and TDD in the wireless frame structure diagram is used to determine whether the 4G signal of the macro base station is FDD or TDD, and whether the local 5ms scheduling pulse is in the first half frame or the second half frame; According to the position relationship of the auxiliary synchronization channel, the clock adjustment amount of the 10ms pulse is calculated, and a new 10ms scheduling pulse is generated to complete the air interface time synchronization.

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