FPGA update method, apparatus, equipment, and program products based on GLink control system

Abstract

This invention relates to the field of data processing technology, and discloses an FPGA update method, apparatus, device, and program product based on a GLink control system. The method includes: acquiring the operating mode of the node to be updated and a first target update file corresponding to the operating mode; determining the transmission mode of the first target update file based on the operating mode; and sending the first target update file to a non-volatile memory based on the transmission mode, so that the non-volatile memory updates the initial file to a second target update file; wherein the non-volatile memory stores the initial file, and the second target update file is used for FPGA updates. This invention controls the FPGA via the GLink bus, allowing firmware update files to be transmitted via a network or other general-purpose interfaces, eliminating the need for a specific manufacturer's dedicated JTAG downloader. Furthermore, remote upgrades via the network eliminate the need for on-site engineer operation, reducing manpower and time costs while avoiding the risk of operational errors.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of data processing, and particularly relates to an FPGA updating method, device, equipment and program product based on a GLink control system. BACKGROUND

[0002] If a GLink bus used in a control system in the field of aerospace wants to realize a GLink node function, a Field Programmable Gate Array (FPGA) chip must be used. However, the FPGA chip has the characteristics of strong programmability and high flexibility, and therefore, in the process of design and development, the FPGA chip often needs to be updated in function.

[0003] At present, a special JTAG downloader corresponding to a manufacturer often needs to be used, and must be connected to a corresponding download port of the equipment. One end is connected to a node card special download interface, one end is connected to a computer using a USB interface, and the computer also needs to be installed with specific drivers and host computer software to complete the download function, and then a professional engineer on site is needed to operate the update.

[0004] However, the way of on-site operation by a professional engineer increases the labor and time cost, and at the same time, there is a risk of operation error, which leads to node failure or data loss. SUMMARY

[0005] Therefore, the present application provides an FPGA updating method, device, equipment and program product based on a GLink control system to solve the problem that the way of on-site operation by a professional engineer increases the labor and time cost, and at the same time, there is a risk of operation error, which leads to node failure or data loss.

[0006] In a first aspect, the present application provides an FPGA updating method based on a GLink control system, which comprises: acquiring a working mode of a node to be updated and a first target updating file corresponding to the working mode; determining a transmission mode of the first target updating file based on the working mode; and sending the first target updating file to a non-volatile memory based on the transmission mode, so that the non-volatile memory updates an initial file to a second target updating file; wherein the non-volatile memory stores the initial file, and the second target updating file is used for FPGA updating.

[0007] The FPGA updating method based on the GLink control system provided in this embodiment can transmit the firmware updating file of the FPGA through a network or other general interfaces through the GLink bus control system, without using a special JTAG downloader of a specific manufacturer, and can be remotely upgraded through the network without on-site operation by an engineer, thereby reducing the labor and time cost and avoiding the risk of operation error.

[0008] In an optional embodiment, the GLink bus control system comprises: an FPGA module, a GLink bus chip and a non-volatile memory, the FPGA module is in communication connection with the GLink bus chip and the non-volatile memory respectively, and the working mode comprises: a client service mode, and the working mode of the node to be updated is configured in the GLink bus chip; wherein the first target update file is sent to the non-volatile memory based on the transmission mode, so that the non-volatile memory updates the initial file to the second target update file, which comprises: the first target update file and an update signal are sent to the FPGA module based on the client service mode, so that the FPGA module downloads the first target update file to the non-volatile memory; the non-volatile memory is controlled to load the first target update file, so that the initial file is updated to the second target update file; and the FPGA is updated based on the second target update file.

[0009] The FPGA update method based on the GLink control system provided in the embodiment is simple and fast for the update operation of the FPGA firmware through the GLink bus control system. The FPGA module can automatically receive and process the signals by only sending the first target update file and the update signal by the industrial computer, and the update of the FPGA module is completed, thereby greatly reducing the possibility of human operation and errors.

[0010] In addition, the firmware is stored through the non-volatile memory, which guarantees the persistence and security of the data, and the data will not be lost even in the case of power failure.

[0011] In an optional embodiment, the GLink bus control system comprises: an FPGA module, a GLink bus chip and a non-volatile memory, the FPGA module is in communication connection with the GLink bus chip and the non-volatile memory respectively, and the working mode comprises: a client service mode, and the working mode of the node to be updated is configured in the GLink bus chip; wherein the first target update file is sent to the non-volatile memory based on the transmission mode, so that the non-volatile memory updates the initial file to the second target update file, which comprises: the first target update file and an update signal are sent to the FPGA module based on the client service mode, so that the FPGA module downloads the first target update file to the non-volatile memory; the non-volatile memory is controlled to load the first target update file, so that the initial file is updated to the second target update file; and the FPGA is updated based on the second target update file.

[0012] The FPGA updating method based on the GLink control system provided in the embodiment has clear initiator and responder of communication, that is, the server sends a data fetching instruction, and the FPGA module responds as a client. The clear communication process makes the whole updating process more orderly and controllable. After sending the data fetching instruction, the server detects whether the to-be-updated node (the FPGA module) returns an acknowledgement signal, ensuring the reliability of communication. Only when the FPGA module responds normally, the server continues to send the updating file, avoiding updating failure caused by communication failure.

[0013] In addition, once the FPGA module returns the acknowledgement signal, the server immediately sends the first target updating file. Since the GLink bus supports high-speed data transmission, the updating file is transmitted at a high speed, and the firmware updating of the FPGA can be quickly completed. The updating file is downloaded into the non-volatile memory, which has persistence and security, and data will not be lost even in the case of power failure. Therefore, even if the device restarts or is powered off accidentally, the updated FPGA firmware will not be affected.

[0014] In an optional embodiment, the updating of the FPGA based on the second target updating file comprises: detecting whether a preset condition is met between the first target updating file and the second target updating file; and if the preset condition is met between the first target updating file and the second target updating file, performing the step of updating the FPGA based on the second target updating file.

[0015] The FPGA updating method based on the GLink control system provided in the embodiment ensures that no data corruption or tampering occurs in the downloading and transmission process by detecting whether a preset condition is met between the first target updating file and the second target updating file, thereby guaranteeing the consistency and integrity of the updating file.

[0016] In an optional embodiment, the GLink bus control system further comprises: a computer memory, which is in communication connection with the FPGA module; and when the number of the first target updating files is multiple, the method further comprises: controlling the FPGA module to send the multiple first target updating files to the computer memory; and controlling the non-volatile memory to load one of the first target updating files, so that the initial file is updated to the second target updating file.

[0017] The FPGA updating method based on the GLink control system provided in the embodiment can orderly send multiple first target updating files to the computer memory when the multiple first target updating files exist, and then load one of the first target updating files from the computer memory, so that the file storage and access are more efficient, and the confusion and errors caused by file dispersion are reduced.

[0018] In an optional implementation, the method for controlling the non-volatile memory to load one of the first target update files to update the initial file to the second target update file comprises: determining, based on the update signal, the first target update file corresponding to the update signal from the plurality of first target update files; and performing the step of controlling the non-volatile memory to load one of the first target update files to update the initial file to the second target update file based on the first target update file corresponding to the update signal.

[0019] The FPGA updating method based on the GLink control system provided in the embodiment determines the corresponding file from the plurality of first target update files based on the update signal, ensures the accuracy and precision of the loading process, avoids possible incorrect loading, and thus guarantees the correctness and stability of FPGA updating.

[0020] In addition, the update signal is used as the basis for selecting the update file, which simplifies the operation process. The user or the system does not need to manually select the update file, the possibility of error is reduced, and the operation efficiency is improved.

[0021] In a second aspect, the present application provides an FPGA updating device based on a GLink control system, which comprises: an acquisition module configured to acquire a working mode of a node to be updated and a first target update file corresponding to the working mode; a first determination module configured to determine a transmission mode of the first target update file based on the working mode; and a sending update module configured to send the first target update file to a non-volatile memory based on the transmission mode, so that the non-volatile memory updates an initial file to a second target update file. The non-volatile memory stores the initial file, and the second target update file is used for FPGA updating.

[0022] In a third aspect, the present application provides a computer device, which comprises a memory and a processor, the memory and the processor are communicatively connected, the memory stores computer instructions, and the processor executes the computer instructions to perform the FPGA updating method based on the GLink control system of the first aspect or any of the corresponding embodiments thereof.

[0023] In a fourth aspect, the present application provides a computer readable storage medium, which stores computer instructions, and the computer instructions are used to make a computer execute the FPGA updating method based on the GLink control system of the first aspect or any of the corresponding embodiments thereof.

[0024] In a fifth aspect, the present application provides a computer program product, which comprises computer instructions, and the computer instructions are used to make a computer execute the FPGA updating method based on the GLink control system of the first aspect or any of the corresponding embodiments thereof. BRIEF DESCRIPTION OF DRAWINGS

[0025] In order to more clearly illustrate the technical solutions in the specific embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the specific embodiments or prior art description. Obviously, the drawings described below are some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained without creative labor on the basis of these drawings.

[0026] Figure 1 FIG. 1 is a flow diagram of a GLink control system-based FPGA updating method according to an embodiment of the present application;

[0027] Figure 2 FIG. 2 is a structural diagram of a GLink control system according to an embodiment of the present application;

[0028] Figure 3 FIG. 3 is a flow diagram of another GLink control system-based FPGA updating method according to an embodiment of the present application;

[0029] Figure 4 FIG. 4 is a flow diagram of still another GLink control system-based FPGA updating method according to an embodiment of the present application;

[0030] Figure 5 FIG. 5 is a diagram of a ring topology of a GLink control system according to an embodiment of the present application;

[0031] Figure 6 FIG. 6 is a diagram of a switching topology of a GLink control system according to an embodiment of the present application;

[0032] Figure 7 FIG. 7 is a structural block diagram of a GLink control system-based FPGA updating device according to an embodiment of the present application;

[0033] Figure 8 FIG. 8 is a hardware structure diagram of a computer device according to an embodiment of the present application. DETAILED DESCRIPTION

[0034] In order to more clearly illustrate the technical solutions in the specific embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the specific embodiments or prior art description. Obviously, the drawings described below are some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained without creative labor on the basis of these drawings.

[0035] Based on the related art, if the GLink bus used by the control system in the field of aerospace wants to realize the function of the GLink node, the FPGA chip must be used. However, the FPGA chip has the characteristics of programmable and high flexibility, so in the design and development, the function of the FPGA chip often needs to be updated.

[0036] At present, it is often necessary to use the special JTAG downloader of the corresponding manufacturer, which must be connected to the corresponding download port of the device. One end is connected to the node card special download interface, one end is connected to the computer using the USB interface, and the computer also needs to install the specific driver and host computer software to complete the download function, and then the professional engineers on-site operation is updated.

[0037] However, the way of on-site operation by professional engineers increases the cost of manpower and time, and there is a risk of operation error, which leads to node failure or data loss.

[0038] The present application provides a kind of based on GLink control system's FPGA updating method, the firmware update file of FPGA can be transmitted through network or other general interface by GLink bus control system, without using the special JTAG downloader of specific manufacturer, and by network remote upgrade, without engineer on-site operation, reduce the cost of manpower and time, while avoiding the risk of operation error.

[0039] According to the embodiment of the present application, a GLink control system-based FPGA updating method embodiment is provided, it should be noted that the steps shown in the flowchart of the drawing can be executed in a computer system, such as a set of computer executable instructions, and although the logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in a different order from here.

[0040] In this embodiment, a GLink control system-based FPGA updating method is provided, which can be used in the above-mentioned computer equipment, such as computer, server, etc., Figure 1 The flowchart of the GLink control system-based FPGA updating method according to the embodiment of the present application is shown in FIG. Figure 1 As shown in the figure, the flowchart includes the following steps:

[0041] Step S101, the working mode of the node to be updated and the first target update file corresponding to the working mode are obtained.

[0042] The working mode can be used to represent the state or configuration of the node to be updated in normal operation. The working mode can include a terminal service mode, a client service mode, a network monitoring mode, etc., which are not limited herein. The first target update file can be used to represent the firmware version, configuration information, etc. of the FPGA, which are not limited herein.

[0043] Specifically, the node to be updated and the working mode of the node to be updated can be identified by a management system or a monitoring tool (such as an industrial computer). Then, the corresponding first target update file is determined according to the working mode of the node to be updated. The first target update file contains software or firmware version, configuration information, etc. compatible with the working mode.

[0044] Step S102, determining the transmission mode of the first target update file based on the working mode.

[0045] The transmission mode of the GLink control system internal node is different. Specifically, the transmission mode can be used to represent the transmission of data from the external node to the internal node or the transmission of data from the internal node to the external node. For example, when the working mode of the GLink control system internal node is the client service working mode, the corresponding transmission mode can be the transmission of data from the internal node to the external node, etc., which are not limited herein and can be implemented by those skilled in the art.

[0046] Step S103, sending the first target update file to the non-volatile memory based on the transmission mode, so that the non-volatile memory updates the initial file to the second target update file; wherein the non-volatile memory stores the initial file, and the second target update file is used for FPGA update.

[0047] In the non-volatile memory, there is an initial file, which is the current configuration or data of the FPGA. The received first target update file is written into the non-volatile memory to replace or update the initial file. Specifically, it can be implemented by a specific writing protocol or API call, which depends on the type of non-volatile memory and the configuration mode of FPGA, which are not limited herein and can be implemented by those skilled in the art.

[0048] The second target update file can be a file obtained after updating the initial file. The second target update file can be used for FPGA update.

[0049] The FPGA updating method based on the GLink control system provided in the embodiment can transmit the firmware updating file of the FPGA through a network or other general interfaces through the GLink bus control system, without using a special JTAG downloader of a specific manufacturer, and remotely upgrades through the network, without the on-site operation of engineers, thereby reducing the labor and time cost and avoiding the risk of operation errors.

[0050] In combination Figure 2 As shown in the figure, in an optional embodiment, the GLink bus control system comprises an FPGA module, a GLink bus chip and a non-volatile memory, and the FPGA module is in communication connection with the GLink bus chip and the non-volatile memory respectively.

[0051] Preferably, the industrial control computer can communicate with the FPGA module through PCI / PCIe, a network port or a serial port, so that the GLink bus chip can be controlled through the design of corresponding host computer software to save the FPGA file to be updated; the FPGA module completes the data exchange with the industrial control computer and buffers the data through a computer memory (Double Data Rate 3, DDR3) or a non-volatile memory FLASH; the DDR3 buffers large data, and the FLASH can save the firmware loaded by the FPGA; at the same time, the FPGA module realizes the control of the GLink bus JLK1263 chip interface timing, including an EMIF interface and a FIFO interface; a Joint Test Action Group (JTAG) is used for factory downloading of the FPGA firmware.

[0052] The GLink bus chip JLK1263 realizes the GLink bus protocol, configures the chip register through the EMIF interface and small data interaction, and realizes large-capacity data interaction with the FPGA through the FIFO interface; finally, the EMIF / FIFO data is converted into the GLink protocol to communicate with other node cards through the high-speed SerDes interface.

[0053] The internal logic circuit of the FPGA can be defined and modified through programming, so as to realize different hardware functions. The FPGA has high flexibility and reconfigurability.

[0054] The non-volatile memory can be FLASH and the like, which is not specifically limited here. The non-volatile memory is a form of static random access memory, which can keep data from being lost in the case of turning off the computer or sudden power failure.

[0055] The FPGA updating method based on the GLink control system can be applied to the GLink bus control system. The working mode includes a client service mode, and the working mode of the node to be updated in the GLink bus chip is configured. The first target updating file is sent to the non-volatile memory based on the transmission mode, so that the non-volatile memory updates the initial file to the second target updating file, including:

[0056] Step a1, the first target updating file and the updating signal are sent to the FPGA module based on the client service mode, so that the FPGA module downloads the first target updating file to the non-volatile memory.

[0057] According to the running condition and business demand of the GLink bus control system, the FPGA module to be updated is determined. The first target updating file is determined, which contains the latest software or firmware version required by the FPGA module. In the client service mode, the first target updating file and the updating signal are sent to the FPGA module through the GLink bus chip. The updating signal is used to trigger the FPGA module to start the updating process.

[0058] Step a2, the non-volatile memory is controlled to load the first target updating file, so that the initial file is updated to the second target updating file.

[0059] After the FPGA module receives the first target updating file and the updating signal, it is stored in the internal cache or temporary storage area. The FPGA module writes the first target updating file into the non-volatile memory through the communication connection with the non-volatile memory. After the non-volatile memory loads the first target updating file, the configuration information or firmware code in the first target updating file is replaced with the original initial file, and the updating from the initial file to the second target updating file is completed.

[0060] Step a3, updating the FPGA based on the second target updating file.

[0061] The FPGA module reads the second target updating file from the non-volatile memory. The FPGA module reconfigures or loads a new firmware version for the FPGA according to the configuration information or firmware code in the second target updating file. This process may involve restarting, resetting, and other operations of the FPGA. After the FPGA is updated, the running test program or the running state of the FPGA is checked to verify whether the updating is successful and to ensure that the FPGA normally runs according to the new configuration or firmware version.

[0062] The FPGA updating method based on the GLink control system provided by the embodiment makes the updating operation of the FPGA firmware simple and fast through the GLink bus control system. Only the first target updating file and the updating signal need to be sent by the industrial computer, and the FPGA module can automatically receive and process the signals to complete the updating of the FPGA module, thereby greatly reducing the possibility of human operation and errors.

[0063] In addition, the firmware storage through the non-volatile memory guarantees the persistence and security of data, and the data will not be lost even in the case of power failure.

[0064] In an optional embodiment, the working mode includes a server service mode or a network monitoring mode, and the working mode of the node to be updated is configured in the GLink bus chip; and the first target updating file is sent to the non-volatile memory based on the transmission mode, so that the non-volatile memory updates the initial file to the second target updating file, including:

[0065] Step b1, sending a data taking instruction to the FPGA module through the GLink bus chip based on the server service mode.

[0066] In the server service mode, a data taking instruction is first sent to the FPGA module through the GLink bus chip. The instruction is usually a special communication protocol or command for requesting the FPGA module to prepare to receive updating data.

[0067] Step b2, detecting whether the node to be updated returns a response signal based on the data taking instruction.

[0068] After sending the data taking instruction, the server waits for the response of the FPGA module. After receiving the data taking instruction, the FPGA module should return a response signal to confirm that it has prepared to receive updating data. The server needs to detect the response signal to ensure that the FPGA module has responded correctly.

[0069] Step b3, if the node to be updated returns a response signal, the first target updating file is sent to the FPGA module based on the server service mode, so that the FPGA module downloads the first target updating file to the non-volatile memory.

[0070] If the response signal of the FPGA module is received, the first target updating file is started to be sent. The file contains the latest software or firmware version required by the FPGA module. The file can be sent to the FPGA module through the GLink bus chip in the data transmission mode according to the communication protocol or standard.

[0071] Preferably, a time range can be defined, that is, the node to be updated returns an acknowledgement signal within the preset time range, and the server sends the first target update file to the FPGA module based on the service mode of the server, so that the FPGA module downloads the first target update file to the non-volatile memory.

[0072] In step b4, the non-volatile memory is controlled to load the first target update file, so that the initial file is updated to the second target update file.

[0073] After the FPGA module receives the first target update file, it will download the first target update file to the non-volatile memory connected thereto according to the built-in update logic or program. After the non-volatile memory loads the first target update file, the configuration information or firmware code therein is replaced with the original initial file, and the update of the initial file to the second target update file is completed. During this process, the FPGA module may need to verify the integrity and format of the file to ensure the validity of the file.

[0074] In step b5, the FPGA is updated based on the second target update file.

[0075] After the file update in the non-volatile memory is completed, the FPGA module will start updating itself according to the data in the second target update file. Specifically, it can update the logical configuration of the FPGA, set the functional parameters, etc. After the update is completed, the FPGA module will run according to the new configuration or firmware version.

[0076] The FPGA update method based on the GLink control system provided in the embodiment clearly defines the initiator and responder of the communication, that is, the server sends the data retrieval instruction, and the FPGA module responds as the client. This clear communication process makes the entire update process more orderly and controllable. After sending the data retrieval instruction, the server detects whether the node to be updated (FPGA module) returns an acknowledgement signal to ensure the reliability of the communication. Only when the FPGA module responds normally, the update file will be sent, avoiding update failure caused by communication failure.

[0077] In addition, once the FPGA module returns an acknowledgement signal, the server will immediately send the first target update file. Since the GLink bus supports high-speed data transmission, the transmission speed of the update file is fast, and the firmware update of the FPGA can be quickly completed. The update file is downloaded to the non-volatile memory, which has persistence and security, and even in the case of power failure, the data will not be lost. Therefore, even if the device is restarted or power failure occurs, the updated FPGA firmware will not be affected.

[0078] In an optional embodiment, updating the FPGA based on the second target update file comprises:

[0079] Step c1, detecting whether the preset condition is met between the first target update file and the second target update file.

[0080] The system compares and verifies the first target update file (i.e., the update file before sending to the FPGA module) and the second target update file (i.e., the update file that has been written to the non-volatile memory and is ready to be loaded to the FPGA) to ensure consistency and integrity between the two.

[0081] The preset condition can include file integrity check, version check, dependency and compatibility check, etc., which are not specifically limited here. The following describes each preset condition.

[0082] File integrity check: using hash algorithms such as MD5, SHA-1 or SHA-256 to check the two files to ensure that the files have not been tampered with during transmission and storage.

[0083] File size check: compare the sizes of the two files to ensure that they have not lost or increased data during transmission and storage.

[0084] Version check: verify whether the version number of the second target update file is consistent with the first target update file to ensure that the old version or incorrect update file is not loaded by mistake.

[0085] Dependency and compatibility check: check whether the second target update file contains all necessary dependencies and is compatible with the current configuration and hardware of the FPGA module.

[0086] Step c2, if the preset condition is met between the first target update file and the second target update file, execute the step of updating the FPGA based on the second target update file.

[0087] Before loading the new configuration, the FPGA needs to be reset to the initial state. The second target update file is read from the non-volatile memory and loaded into the configuration memory of the FPGA. Once the new configuration is loaded into the FPGA, the FPGA can be restarted to run under the new configuration. After the FPGA is started, a series of tests are performed to ensure the correctness and stability of the new configuration. Specifically, it can be functional testing, performance testing and stability testing, etc., which are not specifically limited here.

[0088] The FPGA update method based on the GLink control system provided in this embodiment ensures that no data corruption or tampering occurs during download and transmission by detecting whether the preset condition is met between the first target update file and the second target update file, thereby ensuring the consistency and integrity of the update file.

[0089] In an alternative embodiment, the method further comprises: Figure 2 As shown in FIG. 1, the GLink bus control system further comprises a computer memory communicatively connected to the FPGA module. When there are multiple first target update files, the method further comprises:

[0090] Step d1, controlling the FPGA module to send the multiple first target update files to the computer memory.

[0091] When the multiple first target update files are sent to the FPGA module through the GLink bus chip, the FPGA module can need to temporarily store these files, i.e., directly forward the files to the computer memory. The computer memory usually has larger storage capacity and more flexible data processing capability, and is suitable for storing, backing up and selectively loading files.

[0092] Step d2, controlling the non-volatile memory to load one of the first target update files, so as to update the initial file to the second target update file.

[0093] After all the first target update files are stored in the computer memory, the system needs to decide which file to load into the non-volatile memory of the FPGA module. This decision can be based on multiple factors, such as the version number of the update file, user specification, system requirements, etc., which are not limited here. Once it is decided which file to load, the system will control the non-volatile memory to load the file and write its content to the configuration area of the FPGA module, thereby updating the initial configuration or software of the FPGA.

[0094] Preferably, during the loading process, the system can also need to perform some verification steps, such as file integrity check, version compatibility check, etc., to ensure that the loaded update file is correct and safe.

[0095] The FPGA update method based on the GLink control system provided in this embodiment can orderly send multiple first target update files to the computer memory when there are multiple first target update files, and then load one of the first target update files from the computer memory, so that file storage and access are more efficient, and confusion and errors caused by file dispersion are reduced.

[0096] In an alternative embodiment, the method further comprises:

[0097] Step e1, determining the first target update file corresponding to the update signal from the multiple first target update files based on the update signal.

[0098] When the update signal is received, the system needs to identify the specific update file to which the signal points. This usually involves parsing the information in the update signal, such as the file name, version number or identifier, to determine the specific update file to be loaded. If the update signal contains enough information to directly locate the specific update file, the system can directly use the information. Otherwise, the system may need to search multiple first target update files in the computer memory to find the first target update file corresponding to the matching update signal.

[0099] Step e2, based on the first target update file corresponding to the update signal, performing the step of controlling the non-volatile memory to load one of the first target update files to update the initial file to the second target update file.

[0100] Once the specific first target update file to be loaded is determined, the system can start performing the loading and updating process. This may include reading the file from the computer memory, verifying its integrity (such as using a hash function), and transferring it to the non-volatile memory. Then the system needs to control the non-volatile memory to write the new update file to the configuration area of the FPGA or the corresponding storage location to replace the old initial file. During the updating process, the system may need to restart the FPGA or perform other necessary steps to make the new configuration or software effective.

[0101] The FPGA updating method based on the GLink control system provided by the embodiment ensures the accuracy and accuracy of the loading process, avoids possible erroneous loading, and thus guarantees the correctness and stability of the FPGA updating.

[0102] Moreover, by using the update signal as the basis for selecting the update file, the operation process is simplified. The user or system does not need to manually select the update file, reducing the possibility of errors and improving the operation efficiency.

[0103] In an optional embodiment, in combination with Figure 3 As shown in the figure, the FPGA updating method based on the GLink control system can include:

[0104] 1. When the NC node (i.e. the client mode described above) needs to be updated, the file for updating the FPGA is first copied to the corresponding industrial control computer, and then the file data is sent to the FPGA through PCI / PCIe, network interface or serial port, and a program update signal is sent to the FPGA at the same time;

[0105] 2. After receiving the update signal and the update file, the FPGA first buffers to the DDR3, then downloads it to the non-volatile memory, and after the download is completed, reloads the non-volatile memory, and sends the data containing the FPGA1 version to the industrial control computer through the PCI / PCIe, network interface or serial port;

[0106] 3. Wait for the loading to be completed, and the industrial control computer receives the FPGA data, indicating that the local NC update is completed.

[0107] In an optional embodiment, in combination with Figure 4 As shown in the figure, the FPGA update method based on the GLink control system can include:

[0108] (1) The NT (i.e. the above-mentioned service mode) and NM (i.e. the above-mentioned network monitoring mode) nodes need to be updated, and the remote NC needs to periodically broadcast the agreed update FPGA program instruction through the EMIF interface of JLK1263, and always sends the data acquisition instruction until the return response signal of the corresponding NT / NM of the opposite end is received. At the same time, the industrial computer sends the update data to the local NC node;

[0109] (2) The NC receives the return response signal and sends it to the corresponding NT / NM through the FIFO interface of JLK1263;

[0110] (3) After the NT / NM node card receives the data, it is buffered to the DDR3, and then downloaded to the non-volatile memory, and after the download is completed, the FLASH program is reloaded, and the update completion instruction is returned.

[0111] In a preferred embodiment, a Glink bus network system can be composed of several terminal modules. In combination with Figure 5 、 Figure 6 As shown in the figure, each node card in the GLink bus network can quickly and conveniently update the corresponding FPGA firmware program using the application, thereby meeting different functional requirements in the later period.

[0112] Figure 5 In the figure, Node (Node) 1 to Node6 form a ring topology structure. Figure 6 In the figure, Node1 to Node4 form a switching topology structure.

[0113] Specifically, the GLink bus control system has multiple nodes when applied to a networking scene, and when multiple nodes need to be updated at the same time, multiple JTAG downloaders need to be updated at the same time, or multiple downloaders need to be plugged in and out for updating. This is a large workload for FPGA engineers and requires a long waiting time. The method of the present application can flexibly and quickly change the functions of multiple different node cards. Moreover, the node cards of the GLink are assembled in aerospace systems, and through the present solution, there is no need to consider the structural problems caused by the design of the JTAG port, and there is no need to disassemble the node cards to update the FPGA module through the JTAG port, greatly reducing the trouble of disassembling the FPGA module.

[0114] Each node in the GLink bus control system has a different working mode, and there are three modes in total, NC, NT and NM. In the entire system, NC and NT interact with each other, usually in units of exchanges. Each exchange contains a command frame, a data frame and a status frame; wherein, NC acts as the master node, and according to the needs, first sends the corresponding command frame, then sends data to NT or receives data from NT, and after the exchange is completed, the status frame is received; an NC can send and receive data through the EMIF interface and the FIFO interface at the same time. NT acts as a slave node, and after receiving the corresponding command frame from NC, it receives or sends data, and finally sends the status frame. NM acts as a monitoring node, and can monitor the entire link status in real time, and can also listen to the command frame, the data frame and the status frame on the link.

[0115] In the present embodiment, a GLink control system-based FPGA updating device is also provided, which is used to implement the above-mentioned embodiments and preferred embodiments, and will not be described again. As used below, the term "module" can be a combination of software and / or hardware that implements a predetermined function. Although the device described in the following embodiments is preferably implemented in software, hardware, or a combination of software and hardware is also possible and is contemplated.

[0116] The present embodiment provides a GLink control system-based FPGA updating device, as shown in Figure 7 The device includes an acquisition module 701 configured to acquire a working mode of a node to be updated and a first target updating file corresponding to the working mode; a first determination module 702 configured to determine a transmission mode of the first target updating file based on the working mode; and a sending updating module 703 configured to send the first target updating file to a non-volatile memory based on the transmission mode, so that the non-volatile memory updates an initial file to a second target updating file. The non-volatile memory stores the initial file, and the second target updating file is used for FPGA updating.

[0117] In an optional embodiment, the GLink bus control system comprises: an FPGA module, a GLink bus chip and a non-volatile memory, the FPGA module is in communication connection with the GLink bus chip and the non-volatile memory respectively, and the working mode comprises: a client service mode, and the working mode of the node to be updated is configured in the GLink bus chip; and the sending update module 703 comprises: a first sending unit, configured to send a first target update file and an update signal to the FPGA module based on the client service mode, so that the FPGA module downloads the first target update file to the non-volatile memory; a first loading unit, configured to control the non-volatile memory to load the first target update file, so that the initial file is updated to a second target update file; and a first updating unit, configured to update the FPGA based on the second target update file.

[0118] In an optional embodiment, the GLink bus control system comprises: an FPGA module, a GLink bus chip and a non-volatile memory, the FPGA module is in communication connection with the GLink bus chip and the non-volatile memory respectively, and the working mode comprises: a client service mode, and the working mode of the node to be updated is configured in the GLink bus chip; and the sending update module 703 comprises: a first sending unit, configured to send a first target update file and an update signal to the FPGA module based on the client service mode, so that the FPGA module downloads the first target update file to the non-volatile memory; a first loading unit, configured to control the non-volatile memory to load the first target update file, so that the initial file is updated to a second target update file; and a first updating unit, configured to update the FPGA based on the second target update file.

[0119] In an optional embodiment, the second updating unit comprises: a first detecting subunit, configured to detect whether a preset condition is met between the first target update file and the second target update file; and an executing subunit, configured to execute the step of updating the FPGA based on the second target update file if the preset condition is met between the first target update file and the second target update file.

[0120] In an optional embodiment, the GLink bus control system further comprises: a computer memory, which is communicatively connected with the FPGA module; wherein, when the number of the first target update files is multiple, the apparatus further comprises: a sending module, configured to control the FPGA module to send the multiple first target update files to the computer memory; and a loading module, configured to control the non-volatile memory to load one of the first target update files, so as to update the initial file to the second target update file.

[0121] In an optional embodiment, the loading module comprises: a determining unit, configured to determine, based on the update signal, the first target update file corresponding to the update signal from the multiple first target update files; and an executing unit, configured to execute the step of controlling the non-volatile memory to load one of the first target update files based on the first target update file corresponding to the update signal, so as to update the initial file to the second target update file.

[0122] Further function descriptions of the above-mentioned modules and units are the same as those of the corresponding embodiments, and will not be repeated here.

[0123] The FPGA update apparatus based on the GLink control system in the embodiment is presented in the form of functional units, wherein the functional units refer to ASIC (Application Specific Integrated Circuit) circuits, processors and memories for executing one or more software or fixed programs, and / or other devices capable of providing the above functions.

[0124] The embodiment of the present application further provides a computer device having the FPGA update apparatus based on the GLink control system. Figure 7 as shown in the above description.

[0125] Please refer to Figure 8 , Figure 8 is a structural schematic diagram of a computer device provided by an optional embodiment of the present application, as shown in Figure 8As shown, the computer device includes one or more processors 10, memory 20, and interfaces 30 for external devices such as a keyboard and a mouse and peripheral devices such as disk devices or other storage devices. One or more busses 10 can be used to implement the interface between the various circuits and components of the computer device. It will be appreciated that the bus 10 can be implemented using any one or more of a variety of bus structures, such as a Peripheral Component Interconnect (PCI) bus, a Bluetooth bus, an Industry Standard Architecture (ISA) bus, an Enhanced ISA bus, an Accelerated Graphics Port (AGP) bus, a Video Electronics Standards Association (VESA) local bus, a Micro Channel Architecture (MCA) bus, a Universal Serial Bus (USB), and the like. Figure 8 The processor 10 is used in the embodiments as an example.

[0126] The processor 10 can be a central processing unit, a network processor, or a combination thereof. The processor 10 can further include a hardware chip. The hardware chip can be an application specific integrated circuit, a programmable logic device, or a combination thereof. The programmable logic device can be a complex programmable logic device, a field programmable logic device, a general array logic, or any combination thereof.

[0127] The memory 20 stores instructions that can be executed by the at least one processor 10, so that the at least one processor 10 can perform the method shown in the above embodiments.

[0128] The memory 20 can include a program region and a data region. The program region can store an operating system and application programs required by at least one function. The data region can store data created by the use of the computer device, and the like. In addition, the memory 20 can include a high-speed random access memory, and can further include a non-transitory memory, such as at least one magnetic disk storage device, a flash memory device, or other non-transitory solid-state memory device. In some alternative embodiments, the memory 20 can optionally include a memory that is remotely arranged with respect to the processor 10, and these remote memories can be connected to the computer device through a network. Examples of the network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and a combination thereof.

[0129] The memory 20 can include a volatile memory, such as a random access memory, and can also include a non-volatile memory, such as a flash memory, a hard disk, or a solid state disk. The memory 20 can further include a combination of the above-mentioned memories.

[0130] The computer device further includes a communication interface 30 for communication with other devices or communication networks.

[0131] The embodiments of the present application further provide a computer readable storage medium, and the method according to the embodiments of the present application can be implemented in hardware, firmware, or recorded in a storage medium, or stored in a remote storage medium or a non-transitory machine readable storage medium and downloaded to a local storage medium through network, so that the method described herein can be processed by such software on a storage medium using a general purpose computer, a special purpose processor, or programmable or special hardware. The storage medium can be a magnetic disk, an optical disk, a read-only memory, a random access memory, a flash memory, a hard disk, or a solid state disk, etc. Further, the storage medium can also include a combination of the above-mentioned memories. It can be understood that the computer, the processor, the microprocessor controller, or the programmable hardware includes a storage component that can store or receive software or computer code, when the software or computer code is accessed and executed by the computer, the processor, or the hardware, the method shown in the above embodiments is implemented.

[0132] Part of the present application can be applied as a computer program product, for example, computer program instructions, when executed by a computer, the operation of the computer can invoke or provide the method and / or technical solutions according to the present application. Those skilled in the art should understand that the form of computer program instructions in computer readable medium includes but is not limited to source file, executable file, installation package file, etc. Correspondingly, the way of computer program instructions executed by computer includes but is not limited to: the computer directly executes the instructions, or the computer compiles the instructions and then executes the corresponding compiled program, or the computer reads and executes the instructions, or the computer reads and installs the instructions and then executes the corresponding installed program. Here, the computer readable medium can be any available computer readable storage medium or communication medium accessible to the computer.

[0133] Although the embodiments of the present application are described in conjunction with the accompanying drawings, various modifications and changes can be made by those skilled in the art without departing from the spirit and scope of the present application, and such modifications and changes fall within the scope defined by the appended claims.

Claims

1. A FPGA updating method based on GLink control system, characterized in that, The GLink bus control system comprises an FPGA module, a GLink bus chip and a non-volatile memory, the FPGA module is in communication connection with the GLink bus chip and the non-volatile memory respectively, the working mode comprises a server service mode or a network monitoring mode, the working mode of a node to be updated is configured in the GLink bus chip, and the method comprises the following steps: obtaining the working mode of the node to be updated and a first target update file corresponding to the working mode; determining the transmission mode of the first target update file based on the working mode; sending the first target update file to the non-volatile memory based on the transmission mode, so that the non-volatile memory updates an initial file to a second target update file; wherein the initial file is stored in the non-volatile memory, the second target update file is used for FPGA update, and the sending of the first target update file to the non-volatile memory based on the transmission mode, so that the non-volatile memory updates the initial file to the second target update file, comprises the following steps: sending a data acquisition instruction to the FPGA module through the GLink bus chip based on the server service mode; based on the data acquisition instruction, detecting whether the node to be updated returns an acknowledgement signal; if the node to be updated returns an acknowledgement signal, sending a first target update file to the FPGA module based on the server service mode, so that the FPGA module downloads the first target update file to the non-volatile memory; controlling the non-volatile memory to load the first target update file, so that the initial file is updated to the second target update file; updating the FPGA based on the second target update file.

2. The FPGA update method based on a GLink control system according to claim 1, characterized in that, The GLink bus control system comprises an FPGA module, a GLink bus chip and the non-volatile memory, the FPGA module is in communication connection with the GLink bus chip and the non-volatile memory respectively, the working mode comprises a client service mode, and the working mode of the node to be updated is configured in the GLink bus chip; wherein the sending of the first target update file to the non-volatile memory based on the transmission mode, so that the non-volatile memory updates the initial file to the second target update file, comprises the following steps: sending a first target update file and an update signal to the FPGA module based on the client service mode, so that the FPGA module downloads the first target update file to the non-volatile memory; controlling the non-volatile memory to load the first target update file, so that the initial file is updated to the second target update file; updating the FPGA based on the second target update file.

3. The FPGA update method based on GLink control system according to claim 1, wherein, The updating of the FPGA based on the second target update file comprises the following steps: detecting whether a preset condition is met between the first target update file and the second target update file; If a preset condition is met between the first target update file and the second target update file, the step of updating the FPGA based on the second target update file is performed.

4. The FPGA update method based on GLink control system according to claim 2, wherein, The GLink bus control system further comprises a computer memory in communication connection with the FPGA module; when the number of the first target update files is multiple, the method further comprises: controlling the FPGA module to send multiple first target update files to the computer memory; controlling the non-volatile memory to load one of the first target update files, so that the initial file is updated to the second target update file.

5. The FPGA update method based on GLink control system according to claim 4, characterized in that, The control of the non-volatile memory to load one of the first target update files, so that the initial file is updated to the second target update file, comprises: determining the first target update file corresponding to the update signal from multiple first target update files based on the update signal; based on the first target update file corresponding to the update signal, the step of controlling the non-volatile memory to load one of the first target update files, so that the initial file is updated to the second target update file.

6. An FPGA update device based on a GLink control system, characterized in that, The GLink bus control system comprises an FPGA module, a GLink bus chip and a non-volatile memory, the FPGA module is in communication connection with the GLink bus chip and the non-volatile memory respectively, the working mode comprises a server service mode or a network monitoring mode, the working mode of the node to be updated is configured in the GLink bus chip, and the device comprises: an acquisition module configured to acquire the working mode of the node to be updated and a first target update file corresponding to the working mode; a first determination module configured to determine a transmission mode of the first target update file based on the working mode; a sending update module configured to send the first target update file to the non-volatile memory based on the transmission mode, so that the non-volatile memory updates an initial file to a second target update file; wherein the initial file is stored in the non-volatile memory, the second target update file is used for FPGA update, and the sending of the first target update file to the non-volatile memory based on the transmission mode, so that the non-volatile memory updates the initial file to the second target update file, comprises: sending a data taking instruction to the FPGA module through the GLink bus chip based on the server service mode; based on the data taking instruction, detecting whether the node to be updated returns an acknowledgement signal; if the node to be updated returns the acknowledgement signal, sending a first target update file to the FPGA module based on the server service mode, so that the FPGA module downloads the first target update file to the non-volatile memory; controlling the non-volatile memory to load the first target update file, so that the initial file is updated to the second target update file; updating the FPGA based on the second target update file.

7. A computer device, comprising: comprises: A memory and a processor, which are connected in communication with each other, the memory storing computer instructions, and the processor executing the computer instructions to perform the FPGA updating method based on the GLink control system according to any one of claims 1 to 5.

8. A computer-readable storage medium, characterized in that, The computer readable storage medium stores computer instructions for causing a computer to perform the FPGA updating method based on the GLink control system according to any one of claims 1 to 5.

9. A computer program product, characterised in that, The computer readable storage medium stores computer instructions for causing a computer to perform the FPGA updating method based on the GLink control system according to any one of claims 1 to 5.

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