Multi-source load auxiliary power supply power balance control system

Abstract

The invention relates to the technical field of electric energy conversion control, and discloses a multi-source load auxiliary power supply power balance control system, which comprises a sampling module, a control module and a modulation module, the sampling module obtains parallel converter branch current and direct current bus voltage; the control module determines a weight by utilizing physical associated association of a bus voltage change gradient and branch current change polarity, corrects a dynamic slope factor determined by a current change rate according to the weight, and performs upper limit clamping on the dynamic slope factor according to a bus voltage margin; according to the invention, the rigid restriction of droop control logic is eliminated, the power deviation generated by asymmetry of feeder impedance is automatically offset while the bus voltage stabilization precision is maintained, and the convergence speed and the certainty of the system during violent load switching are improved.

Description

Technical Field

[0001] This invention relates to a power balancing control system for multi-source load auxiliary power supply, belonging to the field of power conversion control technology. Background Technology

[0002] Current multi-source load auxiliary power supply systems adopt a converter parallel architecture, which is aggregated to the DC bus through feeders. The mainstream method for power distribution between branches is droop control, which simulates the static characteristic of voltage decreasing as current increases. This achieves current sharing between modules without the need for a communication link. However, the internal components of the converter have initial tolerances, and the feeders of each branch have impedance asymmetry due to differences in physical length or contact resistance at connection points, making it impossible for each branch to share the power load according to the preset ratio.

[0003] To address power imbalance caused by asymmetry in physical topology and feeder parameters, existing technologies introduce magnetic balancing elements at the hardware level to achieve forced current sharing. For example, Chinese invention patent CN102457167B discloses a multi-level parallel power converter that couples each switching branch to a common magnetic core through a parallel multi-winding autotransformer, using the electromagnetic induction effect between windings to force equal current in each branch. This approach relies on heavy magnetic components, increasing system size and redundancy, and limiting power density improvement. This type of solution is a rigid balance and does not involve control algorithms to optimize asynchronous sampling frequency and closed-loop response damping. It lacks the capability to handle drastic load switching or heavy-load transient conditions. The logical flexible mechanism adaptively switches the control priority from balance priority to voltage regulation priority, but the system faces the risks of circulating current oscillation and duty cycle saturation runaway. The droop control has rigid constraints, and the power balance and the bus voltage regulation rate are mutually exclusive. When a small droop slope is set to maintain the steady-state accuracy of the bus voltage, the impedance difference between branches causes current deviation. When the slope is increased to force the current to converge, the bus voltage fluctuates violently with the load, which reduces the power supply quality. Conventional improvement approaches introduce high-precision sampling hardware or real-time communication synchronization, which increases the system hardware overhead. Moreover, the phase difference caused by the physical asynchrony of the sampling clocks of each branch control unit causes pseudo-dynamic incremental interference in the logic control, inducing circulating current oscillation within the parallel system.

[0004] Therefore, the technical problem to be solved by this invention is how to construct a logically flexible power allocation mechanism without relying on hardware redundancy and physical synchronization bus, eliminate impedance asymmetry interference and avoid calculation noise generated by asynchronous sampling, construct a self-sensing control architecture based on the correlation between output current change rate and bus voltage characteristics, so that the system can achieve dynamic balance and voltage accuracy balance in the full operating range, and establish self-recovery logic for control stiffness at physical limits. Summary of the Invention

[0005] To address the problems mentioned in the background art, the technical solution of the present invention is as follows: A multi-source load auxiliary power supply power balancing control system, comprising a sampling module, a control module, and a modulation module:

[0006] The sampling module is connected to the parallel converter branch and is used to collect the output current and DC bus voltage of each parallel converter branch;

[0007] The control module includes a physical consistency adjudication unit, a slope calculation unit, and a logic damping gating system. The physical consistency adjudication unit extracts the transient gradient of the DC bus voltage and determines that the power accompaniment criterion is valid when the transient gradient of the DC bus voltage is in the opposite polarity to the output current change direction. It then generates gating weights based on the power accompaniment criterion. The slope calculation unit calculates the initial value of the dynamic slope factor based on the first and second derivatives of the output current and uses the gating weights to weight and correct the initial value of the dynamic slope factor to generate the final dynamic slope factor. When the power accompaniment criterion is not valid, the slope calculation unit reduces the gating weights to suppress the numerical increment of the final dynamic slope factor. The logic damping gating system monitors the voltage margin between the real-time value of the DC bus voltage and a preset undervoltage threshold. Based on the voltage margin, it determines a suppression vector using a preset suppression function and uses the suppression vector to perform real-time clamping on the upper limit of the final dynamic slope factor.

[0008] The modulation module includes a reference voltage reconstruction unit and a drive signal generator. The reference voltage reconstruction unit is used to use the product of the final dynamic slope factor and the real-time current as a virtual voltage drop component, and uses the virtual voltage drop component to perform superposition correction on the reference voltage to generate a corrected reference voltage. The drive signal generator is used to output drive signals to each parallel converter branch according to the corrected reference voltage, and when the voltage margin is lower than the preset safety threshold, it uses the suppression vector to switch the control law of each parallel converter branch from the equalization priority mode to the voltage regulation priority mode.

[0009] Preferably, the control module includes a nonlinear gain operator; the nonlinear gain operator is used to calculate the system average current based on the collected output current of each parallel converter branch, determine the current deviation value of each output current relative to the system average current, and calculate the rate of change of the output current with respect to time; the nonlinear gain operator is also used to determine the reference value of the dynamic slope factor based on the current deviation value and the rate of change through a preset gain mapping rule, and output the reference value to the slope calculation unit as the basis for calculating the initial value.

[0010] Preferably, the control module includes a phase normalization operator; the phase normalization operator is used to determine the time offset of the sampling time of each parallel converter branch relative to the global logic reference scale, using the transient characteristic point of the DC bus voltage as the global logic reference scale, and to perform prediction weight compensation on the rate of change of the output current based on the time offset, so as to eliminate the pseudo dynamic increments of each parallel converter branch caused by the asynchronous sampling clock of the microcontroller.

[0011] Preferably, the modulation module includes a phase interleaving adjustment operator; the phase interleaving adjustment operator is used to extract the deviation value of the final dynamic slope factor between each parallel converter branch, and calculate the pulse width modulation carrier phase offset for each parallel converter branch based on the deviation value, and perform phase rearrangement on the drive signals of different branches to smooth the ripple of the DC bus voltage.

[0012] Preferably, the phase interleaving modulation operator is used at a pulse width modulation frequency not lower than Under the given conditions, the following calculation logic is executed: ,in, For the first Pulse width modulation carrier phase offset of the parallel converter branch; This is the preset phase adjustment gain coefficient; For the first The final dynamic slope factor of the parallel converter branch; This is the arithmetic mean of the final dynamic slope factors of each parallel converter branch.

[0013] Preferably, the physical consistency adjudication unit includes a steady-state arbitration subunit; the steady-state arbitration subunit is used to evaluate the cross-correlation coefficient between the change characteristics of the output current and the change characteristics of the DC bus voltage in the time domain when the output current is lower than a preset light load threshold; the control module is used to lock the final dynamic slope factor to a fixed reference value when the cross-correlation coefficient is lower than a preset correlation threshold.

[0014] Preferably, the modulation module includes an excitation injection unit for periodically superimposing an amplitude not greater than the reference reference voltage onto the corrected reference voltage. The control module includes a parameter identification unit, which is used to obtain the current response characteristics of each parallel converter branch to the small voltage disturbance signal, and determine the drift vector of the feeder impedance in each parallel converter branch based on the current response characteristics, and correct the initial parameters of the control loop of each parallel converter branch according to the drift vector.

[0015] Preferably, the modulation module includes a marginal protection unit for real-time monitoring of the duty cycle value of the drive signal; the control module is used to output a reverse intervention signal to the slope calculation unit to forcibly reduce the final dynamic slope factor when the duty cycle value reaches a preset physical saturation threshold.

[0016] Preferably, the reference voltage reconstruction unit is configured in the voltage reconstruction circuit with a step time of [value missing]. The first-order delay operator is used to insert dead-time compensation in the logic execution sequence to compensate for the phase difference caused by the asynchronous sampling frequency between the branches of the parallel converter and to suppress the endogenous circulating current oscillation.

[0017] Preferably, the sampling module includes a current transformer and a voltage conditioning circuit; the control module and the modulation module are integrated into a digital signal processing chip.

[0018] Compared with the prior art, the beneficial effects of the present invention are:

[0019] 1. In the auxiliary power supply of multi-source loads, the output current change rate is collected to determine the dynamic slope factor. When the branch generates excessive current due to impedance differences in the physical length of the feeder, the virtual voltage drop is used to offset the physical impedance asymmetry, guiding the current to migrate to other branches, maintaining the steady-state accuracy of the bus voltage, and realizing power self-balancing between branches. This solves the technical bottleneck of the mutual constraint between balance and voltage regulation rate in traditional fixed slope droop control. The transient characteristic points of the DC bus voltage are used to establish a global logic reference scale. The phase normalization operator eliminates the phase deviation caused by the asynchronous sampling clock of the microcontroller in parallel branches. The logic prediction weight compensation makes the current change characteristics return to the physical true value, filtering out the pseudo-dynamic incremental interference caused by asynchronous sampling, so that the dynamic slope factor adjustment trajectory has monotonically convergent, avoiding circulating current oscillation and logic resonance caused by high-frequency switching in the parallel system.

[0020] 2. Construct a gating mechanism between DC bus voltage margin, real-time duty cycle, and dynamic slope factor. When multi-source load demand approaches the power supply's carrying capacity limit or the branch duty cycle reaches the saturation boundary, suppress the vector to forcibly reduce the upper limit of slope adjustment. The control mode switches from equalization priority to voltage regulation priority. Physical limits are used to force stiffness self-recovery. The converter is in a closed-loop controlled state during heavy load transients, avoiding the risk of deep bus voltage drop or shutdown caused by control logic saturation. The dynamic slope factor deviation generated by power equalization adjustment is mapped to pulse width modulation carrier phase offset. The phase misalignment between branches is used to reorganize the bus current harmonic vector, realizing the coupling of power distribution and power quality optimization. When performing dynamic equalization tasks, the bus voltage overlap ripple is reduced, and the power supply system's compatibility with high-sensitivity power receiving equipment is improved.

[0021] 3. By utilizing the physical accompaniment of bus voltage fluctuations to determine the authenticity of current characteristics, establish the logical correlation between the direction of output current change and the gradient of bus voltage change. In light load or electromagnetic interference environments, identify non-power accompaniment characteristics and suppress abnormal jumps in slope factors. Ensure that the power balance logic is activated under real energy conversion requirements, improve the operational certainty of the control system's electrical environment, and reduce the heat loss of the auxiliary power system caused by control law malfunctions. Attached Figure Description

[0022] Figure 1 This is a flowchart illustrating the logic calculation architecture and dynamic parameter convergence of the multi-source load auxiliary power supply control system of the present invention.

[0023] Figure 2 This is a statistical chart showing the comparison and experimental verification data of the steady-state performance evolution of bus voltage under variable load conditions of the present invention;

[0024] Figure 3 This is a diagram of the system functional logic integration, operation and maintenance interaction, and multi-source load coupling relationship architecture of the present invention. Detailed Implementation

[0025] The present invention will be described in detail below with reference to the embodiments. It should be noted that the following embodiments are intended to explain the present invention and are not intended to limit the scope of protection of the present invention.

[0026] This invention provides a power balancing control system for a multi-source load auxiliary power supply, comprising a sampling module, a control module, and a modulation module. The sampling module is connected to multiple parallel converter branches to acquire real-time current and DC bus voltage data. The control module determines weights based on the physical correlation between the DC bus voltage change gradient and the polarity of the branch current change, and corrects the dynamic slope factor determined by the current change rate accordingly. Furthermore, it applies an upper limit clamp to the final dynamic slope factor based on the DC bus voltage margin. The modulation module drives the operation of each parallel converter branch based on a reference voltage generated by the corrected final dynamic slope factor, and achieves control through reconfiguration. The control logic eliminates power deviations caused by physical feeder impedance asymmetry, suppressing circulating current oscillations in the parallel system while maintaining DC bus voltage regulation accuracy. To address uneven power distribution in parallel branches due to differences in feeder physical length or contact resistance, the sampling module collects the output current and DC bus voltage of each parallel converter branch. The sampling module includes a current transformer and a voltage conditioning circuit to convert the high-voltage side signal into a voltage quantity recognizable by a digital signal processor. The slope calculation unit in the control module calculates the initial value of the dynamic slope factor based on the first and second derivatives of the output current. When the current of a certain branch... When the slope shows an increasing trend and the rate of change accelerates, the slope calculation unit uses a nonlinear gain operator to determine the reference value of the dynamic slope factor, which is used as the basis for calculating the initial value. This dynamic slope factor is used to form a virtual voltage drop at the logic level to offset the voltage drop deviation caused by the difference in physical impedance of the feeder, guide the current to migrate to other branches with lower load rates, and achieve power self-balancing between branches.

[0027] Calibrate the dynamic slope factor mapping matrix of the nonlinear gain operator In a controlled environment, a programmable electronic load is used to simulate the output current from... When the current is adjusted to its maximum rated current, the slope calculation unit records the first derivative of the parallel converter branch under different current deviations and output current values. The offline sampling points are converted and stored in the digital signal processor's reference lookup table using the least squares fitting algorithm based on the dynamic response data, thus establishing the final dynamic slope factor mapping logic. to The adjustment range is processed using a cubic spline interpolation algorithm to generate a monotonically increasing set of control parameters from offline sampling points, correcting the virtual voltage drop feedback component of the parallel converter branch. Characterization mapping matrix, The first derivative of the output current is represented. In light-load or electromagnetic interference environments, high-frequency fluctuations in the current of a single branch may be caused by sampling noise. To address this challenge, the control module is equipped with a physical consistency arbitration unit to extract the transient gradient of the DC bus voltage. When the transient gradient of the DC bus voltage is in the opposite polarity to the change in the output current, the power accompaniment criterion is determined to be valid. When the output current increases and the DC bus voltage shows a synchronous drop, the system determines that the current change originates from the actual load demand and generates a gating weight based on the power accompaniment criterion. The slope calculation unit uses this gating weight to weight and correct the initial value of the dynamic slope factor. If the current fluctuation and the voltage gradient do not have a physical correlation, for example, if the cross-correlation coefficient is lower than the preset correlation threshold, the steady-state arbitration subunit reduces the gating weight and locks the final dynamic slope factor to a fixed reference value, thereby filtering out logic noise in the sampled signal and maintaining the operational stability of the control system.

[0028] To prevent a deep voltage drop in the bus under heavy load transient conditions due to excessive pursuit of balance, the control module employs logic damping gating and monitors the voltage margin between the real-time DC bus voltage and a preset undervoltage threshold. Based on this voltage margin, a suppression vector is determined using a preset suppression function. This suppression vector is then used to perform real-time clamping on the upper limit of the final dynamic slope factor. To address the risk of bus instability potentially induced by heavy load transients, the reference voltage reconstruction unit in the modulation module adjusts the reference voltage step size in real-time according to the transient voltage drop rate of the DC bus voltage. The system has a preset proportional damping coefficient. The single logic correction amount of the reference voltage Set as absolute value of the rate of change of bus voltage The ratio, when the transient rate of drop of the DC bus voltage is from Increase to At that time, the corresponding reference voltage adjustment step size is changed from Reduced to Through the aforementioned inverse mapping logic, the system limits the frequency of virtual voltage drop fluctuations by increasing control damping when the bus voltage fluctuates drastically, preventing the system from reaching the undervoltage protection threshold. When the DC bus voltage approaches the undervoltage safety red line, the drive signal generator uses a suppression vector to switch the control law of each branch from the equalization priority mode to the voltage regulation priority mode. For the phase deviation caused by the physical asynchrony of the sampling clock of the parallel branch microcontrollers, the control module includes a phase normalization operator. This operator uses the transient characteristic point of the DC bus voltage as a global logical reference scale to determine the time offset of each branch sampling time relative to this scale, and performs predictive weight compensation on the rate of change of the output current based on this time offset. This mechanism eliminates the pseudo-dynamic increments caused by asynchronous sampling, keeping the adjustment trajectory of the dynamic slope factor smooth. Furthermore, the reference voltage reconstruction unit sets a step time of [missing information] in the voltage reconstruction loop. The first-order delay operator is used to insert dead-time compensation in the logic execution sequence to further compensate for the phase difference between branches caused by asynchronous sampling frequencies and suppress circulating current oscillations in parallel systems. In system timing chain calibration, the phase normalization operator obtains the DC bus voltage sampling sequence of the sampling period, searches for and extracts the voltage extreme points of the sequence, and records the corresponding timestamps. Read the first sampling time of branch current of parallel converter Calculate the sampling offset The asynchronous increment is eliminated by weight compensation based on the first derivative of the output current predicted by the offset, and a step duration is set at the end of the logic execution sequence of the drive signal generator. First-order delay operator.

[0029] A dead-time compensation amount, determined by the product of the step duration and the system control frequency, is inserted into the reference voltage reconstruction loop to logically normalize the sampling time of the parallel converter branch, suppressing circulating current oscillations and parasitic fluctuations caused by the asynchronous sampling clock of the microcontroller. For the timestamp of the voltage extreme point, For the first Sampling time for branch roads This refers to the time offset relative to the global reference scale. At the power quality optimization level, the modulation module includes a phase interleaving adjustment operator to extract the deviation value of the final dynamic slope factor between each branch. This operator calculates the pulse width modulation carrier phase offset for each branch based on the deviation value, and smooths the DC bus voltage ripple through phase rearrangement, at a pulse width modulation frequency not lower than... Under these conditions, the phase adjustment logic follows the formula: ,in, For the first Pulse width modulation carrier phase offset of the parallel converter branch; This is the preset phase adjustment gain coefficient; For the first The final dynamic slope factor of the parallel converter branch; The configuration uses the arithmetic mean of the final dynamic slope factors of each parallel converter branch to convert the dynamic components generated by equalization regulation into control variables for ripple cancellation, achieving integrated control of power distribution and power quality. To achieve adaptive compensation for long-term drift of system physical parameters, the modulation module is equipped with an excitation injection unit that periodically superimposes an amplitude not greater than the reference reference voltage onto the corrected reference voltage. The parameter identification unit in the control module obtains the current response characteristics of each branch to the disturbance signal and determines the drift vector of the branch feeder impedance accordingly. The control module corrects the initial parameters of each branch control loop based on the drift vector, thereby offsetting the evolution of physical parameters caused by connector aging or environmental thermal stress without manual calibration. The entire control algorithm and modulation strategy are integrated into the digital signal processing chip. At the same time, the modulation module includes a marginal protection unit that monitors the duty cycle value of the drive signal in real time. When the duty cycle value reaches the preset physical saturation threshold, it outputs a reverse intervention signal to the slope calculation unit to forcibly reduce the final dynamic slope factor and prevent the converter from entering an uncontrolled open-loop state.

[0030] Example 1: The 48V shore-based DC auxiliary power supply system includes a first converter branch and a second converter branch. Due to differences in wiring paths, there are discrepancies in the feeder cables of the two branches. The length deviation, and the output connector of the first converter branch produces The contact impedance drift, when the system input power is When the radar pulse load is applied, the sampling module collects the output current and DC bus voltage of each parallel converter branch, and the control module determines the first derivative of the current of the first converter branch as follows: Furthermore, the second derivative exhibits positive pulsation characteristics. The physical consistency adjudication unit extracts the transient gradient of the DC bus voltage and calculates... for The system confirms that the direction of current increase is consistent with the polarity of voltage drop and generates gating weights. Based on this, the slope calculation unit adjusts the final dynamic slope factor of the first converter branch. Adjusted to The increased virtual voltage drop is used to offset the physical impedance asymmetry, thus reducing the power distribution deviation between the two branches. Internal reduction to the following.

[0031] During continuous load loading, the real-time value of the DC bus voltage drops due to the demand for high-power pulses. Close to the system preset The undervoltage threshold is calculated in real time by the logic damping gating in the control module, which calculates the voltage margin between the DC bus voltage and the preset undervoltage threshold. Based on the suppression function, a suppression vector is determined, clamping the upper limit of the final dynamic slope factor to the current value. To prevent the logic voltage drop from expanding due to continuous power balancing adjustments, the control law switches from a balancing priority mode to a voltage regulation priority mode, ensuring that the DC bus level remains within the safe operating range and preventing the converter duty cycle from reaching the physical saturation threshold and causing regulation failure. The phase interleaving adjustment operator extracts the deviation value of the final dynamic slope factor of each branch and calculates the pulse width modulation carrier phase offset for each branch. The DC bus voltage ripple is reduced by phase rearrangement. Reduce to The following process follows the computational logic: ,in, For the first Pulse width modulation carrier phase offset of the parallel converter branch. The preset phase adjustment gain coefficient, For the first The final dynamic slope factor of the parallel converter branch. The system uses the physical associated characteristics of bus voltage fluctuations to determine current characteristics, and achieves logical compensation for physical parameter deviations by reconstructing the control law slope and carrier phase. This eliminates circulating currents caused by impedance asymmetry while maintaining bus voltage accuracy, and establishes a coordinated control mode for power balance and power quality optimization.

[0032] Example 2: On a 48V shore-based DC auxiliary power supply test platform based on dual-channel parallel Buck converters, the feeder resistances of the first converter branch and the second converter branch are respectively set as follows: and Gaussian white noise with a signal-to-noise ratio of 20dB was superimposed on the experimental signal source to simulate the electromagnetic interference environment of the shore-based power supply; the sampling module was used to... The sampling frequency is used to collect branch current and DC bus voltage; the setting of this sampling frequency balances the accuracy of the sampling data in capturing the transient characteristics of the DC bus voltage with the computational load of the digital signal processing chip; when the spectral bandwidth of the monitored signal is widened due to high-frequency load switching, the sampling frequency tends to be closer to its... The upper limit of the value; the experimental group used a control system, while the control group used a droop control method with a fixed slope, the droop slope being fixed at . The experiment simulated the effect of a programmable electronic load from... Light load Under full-load switching conditions, the current distribution difference of each branch, DC bus voltage ripple, and bus voltage stability were observed under different control strategies.

[0033] After the test started, the load transiently switched from light load to full load. Under light load conditions, the control group experiences a difference in feeder impedance. The test group identified the consistency between the polarity of the current variation and the voltage gradient through the physical consistency adjudication unit. After confirming that the power comorbidity criterion was met, the nonlinear gain of the final dynamic slope factor was released, so that the final dynamic slope factor of the first converter branch was adjusted in real time to the specified value. The system utilizes the increased virtual voltage drop to offset the physical resistance difference, reducing the current deviation to [a certain value]. When entering Under full load conditions, the DC bus voltage ripple of the control group increases with power unevenness to The experimental group used a phase interleaving adjustment operator to convert the final dynamic slope factor deviation generated by the equalization adjustment into a pulse width modulation carrier phase offset. Actual measurement for After phase rearrangement, the bus voltage ripple is suppressed to This study aims to verify the synergistic control effect of power allocation and power quality optimization.

[0034] Table 1: Comparison of operating parameters between the experimental group and the control group

[0035]

[0036] To determine the adjustment boundary of the final dynamic slope factor, boundary state verification was performed on the gain mapping rule of the slope calculation unit, and an out-of-range control group was set. The upper limit of the adjustment of its final dynamic slope factor was set as follows: The setpoint is outside the preset optimal working window; test data shows that when the final dynamic slope factor exceeds Afterwards, although the inter-branch current deviation decreased, the damping ratio of the system closed-loop response decreased, and the DC bus voltage showed a peak-to-peak value during load switching transients. The low-frequency oscillations indicate that the control law's flexible overload leads to stability degradation; the experimental group used logic damping gating to monitor the DC bus voltage margin, and when the DC bus voltage dropped to... At that time, the suppression vector clamps the upper limit of the final dynamic slope factor at... At this point, the system switches from equalization priority mode to voltage regulation priority mode, and the DC bus voltage is at It remains stable under overload impact The undervoltage protection threshold has not been reached.

[0037] Example 3: This example combines Figures 1 to 3 A description of a power balancing control system for a multi-source load auxiliary power supply is provided, such as... Figure 1As shown, the multi-source load auxiliary power supply power balancing control system starts with a sampling module, which is responsible for collecting the output current of each parallel converter branch and the DC bus voltage data flow to the parallel processing branch. The physical consistency adjudication unit extracts the transient gradient of the bus voltage and generates a gating weight according to the power comorbidity criterion. The slope calculation unit then uses the gating weight to perform weighted correction on the initial slope factor generated by the current derivative. The logic damping gating on the other side monitors the voltage margin in real time and uses the suppression vector to perform real-time clamping on the upper limit of the dynamic slope value. The above logic units converge in the dynamic slope factor determination stage to generate control parameters that take into account both power balancing and voltage regulation accuracy. The reference voltage reconstruction unit uses the final slope factor and real-time current to generate a virtual voltage drop and correct the reference reference voltage. Finally, the drive signal generator outputs a drive signal and guides the control law to switch from the balancing priority mode to the voltage regulation priority mode when the voltage margin is lower than the preset safety threshold.

[0038] like Figure 2 As shown, this bar chart quantitatively compares the bus voltage values ​​of the test group and the control group under three load conditions: 10% light load, 100% full load, and 120% overload. The vertical axis represents the bus voltage (V), with a scale range between 35 and 55. Checkerboard-filled bars represent the bus voltage data of the test group, while dotted bars represent the bus voltage data of the control group. The test results show that the voltage drop amplitude of the test group under each load stage is smaller than that of the control group, and it can still maintain the bus voltage above the 42V safety threshold under 120% overload conditions. Figure 3 As shown, the system integrates three core functions: dynamic power balancing, power quality optimization, and maintaining bus voltage regulation accuracy. Dynamic power balancing is supported by two logic units: dynamic slope factor correction and physical consistency criterion adjudication. The power quality optimization function is linked to the carrier phase interleaving and rearrangement logic via a dashed line. Logic damping gating limits act as constraints on the bus voltage regulation accuracy maintenance stage. The system acts on the parallel converter hardware through the output terminal and senses input changes from multi-source load demands in real time.

[0039] Example 4: Under the condition that the 48V shore-based DC auxiliary power supply is in light-load standby mode and there is electromagnetic interference in the environment, the output current of both parallel converter branches is at... to Within the current sampling range, the signal-to-noise ratio of the current sampling signal drops to [a certain value]. The following applies, and the microcontroller sampling clocks of each converter branch exhibit physical asynchronous deviations; the phase normalization operator acquires the sampling sequence of the DC bus voltage within the sampling period, searches for voltage extreme points in the sequence, and records their corresponding timestamps. ; Phase normalization operator reads the first Current sampling time of the parallel converter branch And calculate the sampling offset. The system performs predictive weight compensation on the first and second derivatives of the output current based on the sampling offset. This compensation process adopts a first-order linear Taylor approximation model. By adding a derivative compensation term based on the time offset in the processing logic, the asynchronously acquired current characteristics are reorganized into a quasi-synchronous feature vector.

[0040] The physical consistency adjudication unit maintains a constant output current and the active injection strength is at the nominal value during the power-on self-test phase. To mitigate random noise, the steady-state arbitration subunit calculates the cross-correlation coefficient between the current variation characteristics and the bus voltage sag gradient under this state, and then calculates the maximum observed misjudgment correlation coefficient. The maximum correlation coefficient under measured noise conditions is set as a preset threshold; The preset relevance threshold is then set to... When the branch current fluctuates and the real-time cross-correlation coefficient calculated by the physical consistency adjudication unit is... When the value is below the preset correlation threshold, the system determines that the fluctuation is non-power-related noise. Based on this, the slope calculation unit outputs a suppression weight, locking the final dynamic slope factor at a fixed reference value to avoid unexpected jumps in the control law due to a decrease in signal-to-noise ratio. The excitation injection unit superimposes a constant amplitude onto the reference voltage of each converter branch. For the small-amplitude step disturbance signal, the parameter identification unit extracts the current ramp-up slope using the acquired current response sequence and calculates the feeder impedance drift vector using the following formula: ,in, For the first The feeder impedance drift vector of the parallel converter branch, with dimensions in ohms; This is the nominal value of the feeder inductance, measured in Henry. For the first The average output current of the parallel converter branch, in amperes; The measured rate of change of current after the disturbance is injected is expressed in amperes per second. The initial impedance reference change rate in the control loop is expressed in amperes per second; the parameter identification unit uses the calculated... The impedance compensation parameters in the reference voltage reconstruction unit are updated, and the dynamic convergence performance of the auxiliary power supply system is maintained throughout its entire life cycle by logical compensation for physical deviations caused by cable aging.

[0041] Example 5: The control module uses transconductance characteristic data obtained from offline experiments to establish a reference lookup table for the nonlinear gain operator; under a controlled test environment, the output current is simulated by a programmable load. The process of variation from the rated current to the maximum value is recorded by the slope calculation unit, showing different current deviation values ​​and the first derivative. Based on the dynamic response data, construct the mapping matrix of the final dynamic slope factor. Data elements in the mapping matrix For a specific current deviation gradient, offline sampling points are processed by a cubic spline interpolation algorithm to generate a set of control parameters with monotonically increasing characteristics. This set of control parameters is stored in a digital signal processor as a logical reference to correct the virtual voltage drop feedback components of each parallel converter branch. During the self-test startup phase before the parallel branch output contactor closes, the drive signal generator executes a zero-current baseline calibration procedure. The sampling module... Within a time window, DC bus voltage sampling points are collected, and the physical consistency adjudication unit calculates the mean zero drift under this background noise environment. and variance The system adjusts the preset threshold of the gating weight accordingly, thereby eliminating non-power-related signals generated by hardware noise floor during subsequent operation. During this self-test process, the system synchronously injects a nominal voltage into each parallel converter branch. The pulse test signal is obtained by monitoring the time constant of the rising edge of the electrical feedback signal. The initial prediction weight compensation term of the phase normalization operator is modified to adapt the control logic to the parasitic parameter differences of the physical feeder impedance.

[0042] In the calibration scenario of a 48V shore-based auxiliary power supply with multiple converters operating in parallel, the slope calculation unit determines the set of characteristic parameters of the nonlinear gain operator by executing an offline load characteristic scanning program. This program drives the output current from the rated value. by Step increment traversal to The system measures the range and records the response deviation data between the DC bus voltage sag rate and the output current change rate in real time. It uses a least-squares fitting algorithm to convert the offline sampling points into a reference lookup table stored in the digital signal processor, establishing the final dynamic slope factor adjustment range, which is limited to... to Between; hardware-in-the-loop testing confirmed that when facing excessive current caused by feeder impedance asymmetry, the power distribution error between parallel converter branches is within Converging to the nominal value within the time step The following is how the control logic automatically adapts to differences in physical feeder impedance; in the timing chain calibration procedure during the control system integration phase, the reference voltage reconstruction unit uses measurement tools to obtain the sampling trigger pulse phase deviation of the microcontrollers in each parallel converter branch; when the maximum phase offset caused by physical clock asynchrony is detected, At that time, the system will step for a duration of 10 seconds. A first-order delay operator is configured at the end of the logic execution sequence of the drive signal generator; this first-order delay operator achieves logic normalization of the sampling time by inserting a fixed-period dead-time compensation amount into the reference voltage update command stream, and the specific value of the dead-time compensation amount is determined by the product of the step duration and the system control frequency; the system verifies the timing synchronization performance by monitoring the harmonic distribution of the DC bus current, and the measured data shows that... After delayed step intervention, triggered by asynchronous logic. The amplitude of the circulating current pulsation within the frequency band is from Reduce to The following steps aim to eliminate parasitic oscillations within the parallel system and maintain the monotonic convergence characteristics of the power transfer process.

[0043] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the present invention can be implemented in other specific forms without departing from the spirit or essential characteristics of the present invention.

[0044] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention.

Claims

1. A power balancing control system for multi-source load auxiliary power supply, characterized in that, It includes a sampling module, a control module, and a modulation module: The sampling module is connected to the parallel converter branch and is used to collect the output current and DC bus voltage of each parallel converter branch; The control module includes a physical consistency adjudication unit, a slope calculation unit, and a logic damping gating unit. The physical consistency adjudication unit is used to extract the transient gradient of the DC bus voltage and determine that the power accompaniment criterion is valid when the transient gradient of the DC bus voltage is consistent with the opposite polarity of the output current change direction. It also generates gating weights based on the power accompaniment criterion. The slope calculation unit calculates the initial value of the dynamic slope factor based on the first and second derivatives of the output current, and uses gating weights to weight and correct the initial value of the dynamic slope factor to generate the final dynamic slope factor. When the power accompaniment criterion is not met, the slope calculation unit reduces the gating weights to suppress the numerical increment of the final dynamic slope factor. The logic damping gating is used to monitor the voltage margin between the real-time value of the DC bus voltage and the preset undervoltage threshold, and determines the suppression vector based on the voltage margin using a preset suppression function. The suppression vector is then used to perform real-time clamping on the upper limit of the final dynamic slope factor. The modulation module includes a reference voltage reconstruction unit and a drive signal generator. The reference voltage reconstruction unit is used to use the product of the final dynamic slope factor and the real-time current as a virtual voltage drop component, and uses the virtual voltage drop component to perform superposition correction on the reference voltage to generate a corrected reference voltage. The drive signal generator is used to output drive signals to each parallel converter branch according to the corrected reference voltage, and when the voltage margin is lower than the preset safety threshold, it uses the suppression vector to switch the control law of each parallel converter branch from the equalization priority mode to the voltage regulation priority mode.

2. The multi-source load auxiliary power supply power balancing control system according to claim 1, characterized in that, The control module includes a nonlinear gain operator; the nonlinear gain operator is used to calculate the system average current based on the collected output current of each parallel converter branch, determine the current deviation value of each output current relative to the system average current, and calculate the rate of change of the output current with respect to time. The nonlinear gain operator is also used to determine the reference value of the dynamic slope factor based on the current deviation value and the rate of change through a preset gain mapping rule, and output the reference value to the slope calculation unit as the basis for the calculation of the initial value.

3. The multi-source load auxiliary power supply power balancing control system according to claim 1, characterized in that, The control module includes a phase normalization operator; the phase normalization operator is used to determine the time offset of the sampling time of each parallel converter branch relative to the global logic reference scale, using the transient characteristic point of the DC bus voltage as the global logic reference scale, and to perform prediction weight compensation on the rate of change of the output current based on the time offset.

4. The multi-source load auxiliary power supply power balancing control system according to claim 1, characterized in that, The modulation module includes a phase interleaving adjustment operator; the phase interleaving adjustment operator is used to extract the deviation value of the final dynamic slope factor between each parallel converter branch, and calculate the pulse width modulation carrier phase offset for each parallel converter branch based on the deviation value, and perform phase rearrangement on the drive signals of different branches to smooth the ripple of the DC bus voltage.

5. A multi-source load auxiliary power supply power balancing control system according to claim 4, characterized in that, Phase interleaving modulation operator is used in pulse width modulation frequencies not lower than Under the given conditions, the following calculation logic is executed: ,in, For the first Pulse width modulation carrier phase offset of the parallel converter branch; This is the preset phase adjustment gain coefficient; For the first The final dynamic slope factor of the parallel converter branch; This is the arithmetic mean of the final dynamic slope factors of each parallel converter branch.

6. The multi-source load auxiliary power supply power balancing control system according to claim 1, characterized in that, The physical consistency adjudication unit includes a steady-state arbitration subunit; the steady-state arbitration subunit is used to evaluate the cross-correlation coefficient between the change characteristics of the output current and the change characteristics of the DC bus voltage in the time domain when the output current is lower than the preset light load threshold; the control module is used to lock the final dynamic slope factor to a fixed reference value when the cross-correlation coefficient is lower than the preset correlation threshold.

7. A multi-source load auxiliary power supply power balancing control system according to claim 1, characterized in that, The modulation module includes an excitation injection unit for periodically superimposing an amplitude not exceeding the reference voltage onto the corrected reference voltage. The control module includes a parameter identification unit, which is used to obtain the current response characteristics of each parallel converter branch to the small voltage disturbance signal, and determine the drift vector of the feeder impedance in each parallel converter branch based on the current response characteristics, and correct the initial parameters of the control loop of each parallel converter branch according to the drift vector.

8. A multi-source load auxiliary power supply power balancing control system according to claim 1, characterized in that, The modulation module includes a marginal protection unit for real-time monitoring of the duty cycle value of the drive signal; the control module is used to output a reverse intervention signal to the slope calculation unit to forcibly reduce the final dynamic slope factor when the duty cycle value reaches a preset physical saturation threshold.

9. A multi-source load auxiliary power supply power balancing control system according to claim 1, characterized in that, The reference voltage reconstruction unit is configured with a step time of [value missing] in the voltage reconstruction circuit. The first-order delay operator is used to insert dead-time compensation in the logic execution sequence to compensate for the phase difference caused by the asynchronous sampling frequency between the branches of the parallel converter and to suppress the endogenous circulating current oscillation.

10. A multi-source load auxiliary power supply power balancing control system according to claim 1, characterized in that, The sampling module includes a current transformer and a voltage conditioning circuit; the control module and the modulation module are integrated into the digital signal processing chip.

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