Semiconductor device and method for manufacturing the same

Abstract

Embodiments of the present disclosure provide a semiconductor device and a method for manufacturing the same. The semiconductor device includes: a substrate having a first region, a second region disposed outside the first region, and a third region disposed outside the second region, wherein, in a direction perpendicular to the substrate surface, the surface of the first region is higher than the surface of the second region, and the surface of the second region is higher than the surface of the third region; a gate structure disposed on the substrate surface in the first region; a gate spacer covering the sidewalls of the gate structure and at least covering the substrate surface in the second region; and a source region and a drain region located within the substrate in at least the third region. In a direction perpendicular to the substrate surface, the substrate includes the first region, the second region, and the third region, each with a decreasing surface height. This separates the point of most concentrated current in the substrate from the point of greatest electric field strength in the substrate, thereby reducing the number of hot carriers and thereby lowering the risk of hot carrier injection.

Description

Technical Field

[0001] The present disclosure relates to the field of integrated circuits, and in particular to a semiconductor device and a method for manufacturing the same. Background Art

[0002] Hot carriers are high-energy carriers—those with kinetic energy higher than their average thermal energy. They become hot carriers when they receive significant energy from an external source. For example, under a strong electric field, carriers are continuously accelerated along the direction of the electric field, acquiring significant kinetic energy, forming hot carriers. When these hot carriers gain kinetic energy exceeding the potential barrier, they are injected into the gate dielectric layer. As their energy continues to increase, they break the covalent bonds in the gate oxide layer, creating interfacial defects and damaging the gate dielectric layer. This is the hot carrier injection effect. As the degree of gate dielectric damage increases, the current-voltage characteristics of the semiconductor device change. When the device parameters change beyond a certain limit, the semiconductor device will fail.

[0003] How to reduce the risks brought by the hot carrier injection effect is an urgent problem that needs to be solved. Summary of the Invention

[0004] The technical problem to be solved by the embodiments of the present disclosure is to provide a semiconductor device and a method for manufacturing the same, which can reduce the risk brought by the hot carrier injection effect.

[0005] An embodiment of the present disclosure provides a semiconductor device, including:

[0006] A substrate having a first region, a second region disposed outside the first region, and a third region disposed outside the second region, wherein in a direction perpendicular to a surface of the substrate, a surface of the first region is higher than a surface of the second region, and a surface of the second region is higher than a surface of the third region;

[0007] a gate structure, disposed on the surface of the substrate in the first region;

[0008] a gate spacer isolation layer, covering the sidewalls of the gate structure and at least covering the substrate surface in the second region;

[0009] The source region and the drain region are at least located in the substrate in the third region.

[0010] In some embodiments, a height difference between a surface of the first region and a surface of the second region, and a height difference between a surface of the second region and a surface of the third region are equal.

[0011] In some embodiments, a height difference between a surface of the first region and a surface of the second region is 2.5 nm-3.5 nm, and a height difference between a surface of the second region and a surface of the third region is 2.5 nm-3.5 nm.

[0012] In some embodiments, a lightly doped drain region is further included, and the lightly doped drain region is at least located in the substrate of the second region.

[0013] In some embodiments, the gate structure includes a gate dielectric layer, a gate conductive layer, and a gate capping layer, wherein the gate dielectric layer covers the surface of the substrate in the first region, the gate conductive layer covers a portion of the surface of the gate dielectric layer, the gate capping layer covers the surface of the gate conductive layer, and the gate spacer includes:

[0014] A first spacer spacer covers the sidewalls of the gate covering layer, the sidewalls of the gate conductive layer, and the surface of the gate dielectric layer not covered by the gate conductive layer.

[0015] In some embodiments, the gate spacer further includes: a second spacer covering the sidewalls of the first spacer, the sidewalls of the gate dielectric layer, the sidewalls of the substrate in the first region, and the surface of the substrate in the second region.

[0016] In some embodiments, the gate spacer further comprises:

[0017] The third spacer isolation layer at least covers the sidewalls of the second spacer isolation layer and the sidewalls of the substrate in the second region.

[0018] The present disclosure also provides a method for manufacturing a semiconductor device, which includes:

[0019] Providing a substrate, wherein a gate structure is provided on a surface of the substrate;

[0020] A first region, a second region disposed outside the first region, and a third region disposed outside the second region are formed in the substrate, wherein in a direction perpendicular to the surface of the substrate, a surface of the first region is higher than a surface of the second region, and a surface of the second region is higher than a surface of the third region, the gate structure is disposed on the substrate surface of the first region, and a gate spacer spacer covers a sidewall of the gate structure and at least covers the substrate surface of the second region;

[0021] A source region and a drain region are formed in the substrate, and the source region and the drain region are at least located in the third region.

[0022] In some embodiments, after providing a substrate with a gate structure on a surface of the substrate, the method further includes forming a lightly doped drain region in the substrate.

[0023] In some embodiments, the gate structure includes a gate dielectric layer, a gate conductive layer, and a gate capping layer, the gate dielectric layer covers the surface of the substrate, the gate conductive layer covers a portion of the surface of the gate dielectric layer, the gate capping layer covers the surface of the gate conductive layer, the gate spacer includes a first spacer, and the step of forming a lightly doped drain region in the substrate includes:

[0024] forming a first spacer spacer, wherein the first spacer spacer covers the sidewalls of the gate cover layer, the sidewalls of the gate conductive layer, and a portion of the surface of the gate dielectric layer;

[0025] The substrate is doped with the first sidewall isolation layer, the gate cover layer and the gate conductive layer to form the lightly doped drain region.

[0026] In some embodiments, the step of forming a first region, a second region disposed outside the first region, and a third region disposed outside the second region in the substrate includes:

[0027] removing a portion of the substrate so that the substrate forms a first region covered by the gate structure and a second initial region disposed outside the first region, wherein a surface of the first region is higher than a surface of the second initial region in a direction perpendicular to the surface of the substrate;

[0028] A portion of the substrate is removed in the second initial area so that the substrate forms a second area arranged outside the first area and a third area arranged outside the second area, and in a direction perpendicular to the surface of the substrate, the surface of the first area is higher than the surface of the second area, and the surface of the second area is higher than the surface of the third area.

[0029] In some embodiments, the gate structure includes a gate dielectric layer, a gate conductive layer, and a gate capping layer, the gate dielectric layer covers the surface of the substrate, the gate conductive layer covers a portion of the surface of the gate dielectric layer, the gate capping layer covers the surface of the gate conductive layer, and the gate spacer includes a first spacer. The step of removing a portion of the substrate to form a first region covered by the gate structure and a second initial region disposed outside the first region includes:

[0030] forming a first spacer spacer, wherein the first spacer spacer covers the sidewalls of the gate cover layer, the sidewalls of the gate conductive layer, and a portion of the surface of the gate dielectric layer;

[0031] Using the first sidewall isolation layer, the gate cover layer and the gate conductive layer as shielding, a portion of the gate dielectric layer and the substrate is removed to form the first region and the second initial region. The substrate surface of the first region is covered by the gate dielectric layer.

[0032] In some embodiments, the gate spacer includes a second spacer, and the step of removing a portion of the substrate in the second initial region includes:

[0033] forming a second spacer spacer, wherein the second spacer spacer covers the sidewalls of the first spacer spacer, the sidewalls of the gate dielectric layer, the sidewalls of the substrate in the first region, and a portion of the surface of the substrate in the second initial region;

[0034] The second spacer isolation layer, the first spacer isolation layer and the gate structure are used as shielding to remove a portion of the substrate to form the second region and the third region.

[0035] In some embodiments, the gate spacer includes a third spacer, and the step of forming a source region and a drain region in the substrate includes:

[0036] forming the third spacer isolation layer, wherein the third spacer isolation layer at least covers the sidewalls of the second spacer isolation layer and the sidewalls of the substrate in the second region;

[0037] The substrate is doped with the third spacer isolation layer, the second spacer isolation layer, the first spacer isolation layer and the gate structure as shielding to form the source region and the drain region.

[0038] In some embodiments, the third spacer isolation layer further covers a portion of the surface of the substrate in the third region.

[0039] In some embodiments, the step of providing a substrate, wherein the substrate surface has a gate structure, further comprises: performing ion implantation on the substrate to form a well region, wherein the ion implantation dose is 1*10 12 ~5*10 13 cm -2 .

[0040] The semiconductor device provided by the embodiment of the present disclosure has, in a direction perpendicular to the surface of the substrate, a first region, a second region, and a third region with surface heights decreasing successively, and the gate structure is arranged in the first region with the highest surface height. According to the tip effect, the point with the largest electric field strength in the substrate is the vertex at the junction of the first region and the second region, and the vertex at the junction of the second region and the third region. The position of the point where the current is most concentrated in the substrate is separated from the position where the point with the largest electric field strength in the substrate is located, so that the ionization of particles at the position where the hot carrier injection effect is easily caused is reduced, thereby reducing the number of hot carriers and reducing the risk of the hot carrier injection effect.

[0041] The preparation method provided by the embodiment of the present disclosure can form a first region, a second region and a third region on the substrate with surface heights decreasing successively. The gate structure is arranged in the first region with the highest surface height, so that the position where the current is most concentrated in the substrate is separated from the position where the electric field intensity is the largest in the substrate, thereby reducing the ionization of particles at the position that is prone to hot carrier injection effect, thereby reducing the number of hot carriers and reducing the risk of hot carrier injection effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1 A schematic diagram of a substrate surface and an internal area of ​​a semiconductor device;

[0043] Figure 2 is a schematic cross-sectional view of a semiconductor device provided by an embodiment of the present disclosure;

[0044] Figure 3 yes Figure 2 Schematic diagram of area B in the middle;

[0045] Figure 4 1 is a schematic diagram of the steps of a method for manufacturing a semiconductor device provided by an embodiment of the present disclosure;

[0046] Figures 5A to 5I is a process flow chart of a method for manufacturing a semiconductor device provided in one embodiment of the present disclosure;

[0047] Figure 6 It is a schematic diagram of the substrate surface and the internal area of ​​the substrate of another semiconductor device. DETAILED DESCRIPTION

[0048] The specific embodiments of the semiconductor device and the manufacturing method thereof provided by the present disclosure are described in detail below with reference to the accompanying drawings.

[0049] Reducing the risk of hot carrier injection is a key research topic. The inventors have discovered that in semiconductor devices, the gate structure 110 is located on the surface of the substrate 100, and the gate spacer 140 is located on the sidewalls of the gate structure 110. When a voltage is applied to the gate structure 110, an electric field and current are generated in the substrate 100. If the location of the maximum electric field coincides with the location of the most concentrated current, hot carrier injection is more likely to occur in the overlapping area. Figure 1 is a schematic diagram of the surface of the substrate 100 and the inner area of ​​the substrate 100, as shown in Figure 1 As shown, the surface of the substrate 100 is a flat surface, and the position of the maximum electric field point in the substrate 100 coincides with the position of the most concentrated current point (as shown in FIG. Figure 1 The overlapped region is prone to carrier injection effect.

[0050] In view of this, an embodiment of the present application provides a semiconductor device that can separate the location of the maximum electric field in the substrate from the location of the most concentrated current, thereby reducing the ionization of particles at the location most likely to cause hot carrier injection effects, thereby reducing the number of hot carriers and thus reducing the risk of hot carrier injection effects.

[0051] Figure 2 This is a cross-sectional diagram of a semiconductor device provided by an embodiment of the present disclosure. Figure 2 The semiconductor device includes a substrate 200, a gate structure 210, a gate spacer 240, a source region 250, and a drain region 251. The substrate 200 has a first region 201, a second region 202 disposed outside the first region 201, and a third region 203 disposed outside the second region 202. In a direction perpendicular to the surface of the substrate 200, the surface of the first region 201 is higher than the surface of the second region 202, and the surface of the second region 202 is higher than the surface of the third region 203. The gate structure 210 is disposed on the surface of the substrate 200 in the first region 201. The gate spacer 240 covers the sidewalls of the gate structure 210 and at least covers the surface of the substrate 200 in the second region 202. The source region 250 and the drain region 251 are located within the substrate 200 in at least the third region 203.

[0052] Figure 3 yes Figure 2 See the enlarged diagram of the dotted box B area in the figure. Figure 2 and Figure 3 In the semiconductor device provided by the embodiment of the present disclosure, in the direction perpendicular to the surface of the substrate 200 (eg Figure 2In the Z direction, the substrate 200 has a first region 201, a second region 202, and a third region 203 with decreasing surface heights in sequence. The gate structure 210 is disposed in the first region 201 with the highest surface height. The position of the most concentrated current point in the substrate 200 is as follows: Figure 3 The position indicated by the dotted line A, and according to the tip effect, the point with the maximum electric field strength in the substrate 200 is the vertex at the junction of the first region 201 and the second region 202 (eg Figure 3 The position circled by the dotted box C) and the vertex at the junction of the second area 202 and the third area 203 (as shown in FIG. Figure 3 In the semiconductor device provided by the embodiment of the present disclosure, the position of the most concentrated current point in the substrate 200 is separated from the position of the point with the largest electric field strength in the substrate 200, so that the ionization of particles at the position where the hot carrier injection effect is easily caused is reduced, thereby reducing the number of hot carriers and reducing the risk of the hot carrier injection effect.

[0053] The gate structure 210 is arranged in the first region 201 of the substrate 200. Starting from the gate structure 210, the height of the surface of the substrate 200 decreases successively, that is, in the direction perpendicular to the surface of the substrate 200 (such as the Z direction in the figure), the surface height of the first region 201 of the substrate 200 is the highest, and the surface height of the third region 203 is the lowest.

[0054] The gate structure 210 includes a gate dielectric layer 211 , a gate conductive layer 212 and a gate cover layer 213 . The gate dielectric layer 211 covers the surface of the substrate 200 in the first region 201 , the gate conductive layer 212 covers part of the surface of the gate dielectric layer 211 , and the gate cover layer 213 covers the surface of the gate conductive layer 212 .

[0055] When a voltage is applied to the gate conductive layer 212 to form an inversion layer in the substrate 200, and voltage is applied to the source region 250 and the drain region 251, an electric field and current are generated in the substrate 200. Under the action of a strong electric field, carriers in the substrate 200 are continuously accelerated along the direction of the electric field, thereby gaining significant kinetic energy and forming hot carriers. When the hot carriers gain kinetic energy exceeding the potential barrier, they are injected into the gate dielectric layer 211. As the energy continues to increase, the covalent bonds in the gate dielectric layer 211 may be broken, resulting in interface defects and damage to the gate dielectric layer 211. The semiconductor device provided by the embodiments of the present disclosure utilizes the height difference of the substrate 200 surface to reduce the number of hot carriers and mitigate the impact of hot carriers on the gate dielectric layer 211.

[0056] In some embodiments, the height difference H1 between the surface of the first region 201 and the surface of the second region 202 of the substrate 200, and the height difference H2 between the surface of the second region 202 and the surface of the third region 203 are equal, which can improve the controllability of the electric field intensity distribution and reduce the difficulty of the process. In other embodiments, the height difference H1 between the surface of the first region 201 and the surface of the second region 202 of the substrate 200, and the height difference H2 between the surface of the second region 202 and the surface of the third region 203 of the substrate 200 can also be different. For example, the height difference H1 between the surface of the first region 201 and the surface of the second region 202 of the substrate 200 is greater than the height difference H2 between the surface of the second region 202 and the surface of the third region 203.

[0057] In some embodiments, the height difference H1 between the surface of the first region 201 and the surface of the second region 202 is 2.5nm-3.5nm, so as to take into account the reduction of the number of hot carriers and the performance of the semiconductor device. If the height difference H1 between the surface of the first region 201 and the surface of the second region 202 is too small, the number of carriers will not be effectively reduced. If the height difference H1 between the surface of the first region 201 and the surface of the second region 202 is too large, the electric field distribution will be excessively uneven, and tunneling leakage will easily occur in places where the electric field is too large, affecting the performance of the semiconductor device.

[0058] In some embodiments, the height difference H2 between the surface of the second region 202 and the surface of the third region 203 is 2.5nm-3.5nm, so as to take into account the reduction of the number of hot carriers and the performance of the semiconductor device. If the height difference H2 between the surface of the second region 202 and the surface of the third region 203 is too small, the number of carriers will not be effectively reduced. If the height difference H2 between the surface of the second region 202 and the surface of the third region 203 is too large, the electric field distribution will be excessively uneven, and tunneling leakage will easily occur in places where the electric field is too large, affecting the performance of the semiconductor device.

[0059] In some embodiments, the sidewalls of the first region 201 are inclined, i.e., in the Z direction, the sidewalls of the first region 201 are not perpendicular to the surface of the substrate 200. The sidewalls of the second region 202 are inclined, i.e., in the Z direction, the sidewalls of the second region 202 are not perpendicular to the surface of the substrate 200. In some embodiments, both the sidewalls of the first region 201 and the sidewalls of the second region 202 are inclined. In other embodiments, only one of the sidewalls of the first region 201 and the sidewalls of the second region 202 is inclined.

[0060] In some embodiments, the sidewalls of the first region 201 are vertical sidewalls, that is, in the Z direction, the sidewalls of the first region 201 are perpendicular to the surface of the substrate 200. The sidewalls of the second region 202 are vertical sidewalls, that is, in the Z direction, the sidewalls of the second region 202 are perpendicular to the surface of the substrate 200. In some embodiments, both the sidewalls of the first region 201 and the sidewalls of the second region 202 are vertical sidewalls. In other embodiments, either the sidewalls of the first region 201 or the sidewalls of the second region 202 are vertical sidewalls.

[0061] In some embodiments, the semiconductor device further includes a lightly doped drain (LDD) region 230. The LDD region 230 is located below the gate structure 210 and closely adjacent to the edge of the channel region. It provides an impurity concentration gradient for the drain region 251, acting as a buffer zone for the leakage electric field and effectively mitigating hot carrier effects. In some embodiments, the LDD region 230 is located within the substrate 200 in at least the second region 202. For example, in this embodiment, the LDD region 230 is located in the first region 201, the second region 202, and the third region 203.

[0062] In some embodiments, the gate sidewall isolation layer 240 includes a first sidewall isolation layer 241. The first sidewall isolation layer 241 covers the sidewalls of the gate covering layer 213, the sidewalls of the gate conductive layer 212, and the surface of the gate dielectric layer 211 not covered by the gate conductive layer 212. The first sidewall isolation layer 241 can serve as a protective layer for the gate structure 210. For example, the first sidewall isolation layer 241 can protect the gate structure 210 from being contaminated during processes such as ion implantation. In a direction parallel to the surface of the substrate 200 (such as the X direction in the figure), the gate dielectric layer 211 protrudes beyond the gate conductive layer 212, and the bottom of the first sidewall isolation layer 241 covers the surface of the gate dielectric layer 211. In this embodiment, the material of the first sidewall isolation layer 241 is silicon oxide. In other embodiments, the material of the first sidewall isolation layer 241 can also be silicon nitride or silicon oxynitride.

[0063] In some embodiments, the gate spacer 240 further includes a second spacer 242. The second spacer 242 covers the sidewalls of the first spacer 241, the sidewalls of the gate dielectric layer 211, the sidewalls of the substrate 200 in the first region 201, and the surface of the substrate 200 in the second region 202. The second spacer 242 is used to protect the first spacer 241, the gate dielectric layer 211, the substrate 200 in the first region 201, and the substrate 200 in the second region 202 during semiconductor processing. The material of the second spacer 242 can be silicon oxide, silicon nitride, or silicon oxynitride. In this embodiment, the material of the second spacer 242 is silicon oxide. In some embodiments, the second spacer 242 and the first spacer 241 are made of the same material. In other embodiments, the second spacer spacer 242 and the first spacer spacer 241 may be made of different materials. For example, the second spacer spacer 242 may be made of silicon nitride, and the first spacer spacer 241 may be made of silicon oxide.

[0064] In some embodiments, the gate spacer 240 further includes a third spacer 243. The third spacer 243 covers at least the sidewalls of the second spacer 242 and the sidewalls of the substrate 200 in the second region 202. In this embodiment, the third spacer 243 also covers a portion of the surface of the substrate 200 in the third region 203. The third spacer 243 is used to protect the second spacer 242, the substrate 200 in the second region 202, and the substrate 200 in the third region 203 during semiconductor processing. The material of the third spacer 243 can be silicon oxide, silicon nitride, or silicon oxynitride. In this embodiment, the material of the third spacer 243 is silicon oxide. In some embodiments, the third spacer 243, the second spacer 242, and the first spacer 241 are made of the same material. In other embodiments, the third side wall isolation layer 243, the second side wall isolation layer 242 and the first side wall isolation layer 241 may also be made of different materials. For example, the material of the third side wall isolation layer 243 is silicon oxide, the material of the second side wall isolation layer 242 is silicon nitride, and the material of the first side wall isolation layer 241 is silicon oxide.

[0065] In some embodiments, in a direction parallel to the surface of the substrate 200 (eg Figure 2 In the X direction in FIG, the thickness of the first spacer spacer 241 is less than the thickness of the second spacer spacer 242, and the thickness of the second spacer spacer 242 is less than the thickness of the third spacer spacer 243. For example, in this embodiment, in the direction parallel to the surface of the substrate 200 (such as Figure 2In the X direction (in the X direction in FIG), the thickness of the first spacer 241 is 3-6 nm, the thickness of the second spacer 242 is 8-12 nm, and the thickness of the third spacer 243 is 16-20 nm. The thicknesses refer to the thicknesses at the bottom surfaces of the first spacer 241, the second spacer 242, and the third spacer 243. In some embodiments, the total thickness of the gate spacer 240 needs to meet the device design requirements. If the thicknesses of the first spacer 241 and the second spacer 242 are relatively small, the thickness of the third spacer 243 can be appropriately increased to meet the device design requirements.

[0066] In some embodiments, the semiconductor device further includes a well region 220 , and the lightly doped drain region 230 , the source region 250 , and the drain region 251 are disposed in the well region 220 .

[0067] In some embodiments, the semiconductor device further includes a source and a drain (not shown in the drawings), the source is electrically connected to the source region 550 to electrically lead out the source region 550 , and the drain is electrically connected to the drain region 551 to electrically lead out the drain region 551 .

[0068] The semiconductor device provided by the embodiments of the present disclosure can effectively reduce the number of hot carriers and lower the risk of hot carrier injection effects.

[0069] The embodiments of the present disclosure also provide a method for preparing the above-mentioned semiconductor device. Figure 4 This is a schematic diagram of the steps of the method for preparing a semiconductor device according to an embodiment of the present disclosure. Figure 4 The preparation method includes: step S40, providing a substrate, the substrate surface having a gate structure; step S41, forming a first region, a second region arranged outside the first region, and a third region arranged outside the second region in the substrate, in a direction perpendicular to the substrate surface, the surface of the first region is higher than the surface of the second region, and the surface of the second region is higher than the surface of the third region, the gate structure is arranged on the substrate surface of the first region, the gate sidewall isolation layer covers the sidewall of the gate structure and at least covers the substrate surface of the second region; step S42, forming a source region and a drain region in the substrate, the source region and the drain region are at least located in the third region.

[0070] The preparation method provided by the embodiment of the present disclosure can form a first region, a second region and a third region on the substrate with surface heights decreasing successively. The gate structure is arranged in the first region with the highest surface height, so that the position where the current is most concentrated in the substrate is separated from the position where the electric field intensity is the largest in the substrate, thereby reducing the ionization of particles at the position that is prone to cause hot carrier injection effects, thereby reducing the number of hot carriers and reducing the risk of hot carrier injection effects.

[0071] Figures 5A to 5IThis is a process flow chart of a method for manufacturing a semiconductor device provided in one embodiment of the present disclosure.

[0072] See also Figure 4 and Figure 5A In step S40 , a substrate 500 is provided, and a gate structure 510 is formed on the surface of the substrate 500 .

[0073] The substrate 500 may include a silicon substrate, a germanium (Ge) substrate, a silicon germanium (SiGe) substrate, an SOI substrate, or a GOI (Germanium-on-Insulator) substrate, etc.; the substrate 500 may also be a substrate including other elemental semiconductors or compound semiconductors, such as gallium arsenide, indium phosphide, or silicon carbide, etc. The substrate 500 may also be a stacked structure, such as a silicon / silicon germanium stack, etc.; in addition, the substrate 500 may be an ion-doped substrate, which may be P-type doped or N-type doped; a plurality of peripheral devices, such as field-effect transistors, capacitors, inductors, and / or diodes, may also be formed in the substrate 500. In this embodiment, the substrate 500 is a silicon substrate, which may also include other device structures, such as transistor structures, metal wiring structures, etc., but since they are not related to the embodiments of the present disclosure, they are not shown.

[0074] In this step, the surface of the substrate 500 is a flat surface, that is, a surface perpendicular to the substrate 500 surface (such as Figure 5A In the Z direction, the height of the substrate 500 is the same everywhere on the surface.

[0075] The gate structure 510 includes a gate dielectric layer 511, a gate conductive layer 512, and a gate capping layer 513. In this embodiment, the gate dielectric layer 511 covers the entire surface of the substrate 500, the gate conductive layer 512 covers a portion of the surface of the gate dielectric layer 511, and the gate capping layer 513 covers the surface of the gate conductive layer 512. In other embodiments, the gate dielectric layer 511 may only cover a portion of the surface of the substrate 500. For example, in the X direction, the side surfaces of the gate dielectric layer 511 are flush with the side surfaces of the gate conductive layer 512, and the gate conductive layer 512 covers the entire surface of the gate dielectric layer 511.

[0076] In some embodiments, the gate dielectric layer 511 may be a silicon oxide layer or a high-K dielectric layer, the gate conductive layer 512 may be a polysilicon layer, a composite layer of a titanium nitride layer and a tungsten layer, or a composite layer of a titanium nitride layer and a tungsten layer, or a polysilicon layer, and the gate cap layer 513 may be a silicon nitride layer, a silicon oxide layer, or a silicon oxynitride layer. In this embodiment, the gate dielectric layer 511 is a silicon oxide layer, the gate conductive layer 512 is a composite layer of a polysilicon layer, a titanium nitride layer and a tungsten layer, and the gate cap layer 513 is a silicon nitride layer.

[0077] In some embodiments, before forming the gate structure 510 on the substrate 500, the following steps are further included: performing ion implantation on the substrate 500 to form a well region 520, wherein the ion implantation dose is 1*10 12 ~5*10 13 cm -2 The ion implantation dose is greater than that of conventional semiconductor devices, thereby increasing the threshold voltage of the semiconductor device and reducing the impact of subsequent processes on the threshold voltage of the semiconductor device fabricated by the fabrication method provided by the embodiment of the present disclosure, so that the threshold voltage of the semiconductor device fabricated by the fabrication method provided by the embodiment of the present disclosure meets the design requirements. The well region 520 is a doped region. For example, if P-type impurities are doped on an N-type substrate, a P-well region is formed; if N-type impurities are doped on a P-type substrate, an N-well region is formed.

[0078] In some embodiments, after step S40, the method further includes forming a lightly doped drain region 530 (LDD) in the substrate 500. The lightly doped drain region 530 serves as a buffer zone for the leakage electric field and can effectively alleviate the hot carrier effect.

[0079] As an example, an embodiment of the present disclosure provides a method for forming a lightly doped drain region 530. The method includes:

[0080] See also Figure 5B , forming a first spacer spacer 541. The first spacer spacer 541 covers the sidewalls of the gate cover layer 513, the sidewalls of the gate conductive layer 512, and covers a portion of the surface of the gate dielectric layer 511. The first spacer spacer 541 can be a silicon oxide layer, a silicon nitride layer, or a nitride oxide layer. In this step, the first spacer spacer 541 can be formed using a chemical vapor deposition process, an atomic layer deposition process, or other processes. In this embodiment, the first spacer spacer 541 is formed using an atomic layer deposition process, and the first spacer spacer 541 is a silicon oxide layer.

[0081] See also Figure 5C , using the first spacer spacer 541, the gate cap layer 513, and the gate conductive layer 512 as shielding, the substrate 500 is doped to form a lightly doped drain region 530. The lightly doped drain region 530 is formed in the well region 520. In this step, an ion implantation process can be used to implant ions into the substrate 500 to form the lightly doped drain region 530. The doping concentration of the lightly doped drain region 530 is lower than the doping concentration of the source region 550 and the drain region 551 to be formed subsequently.

[0082] See also Figure 4 and Figure 5FIn step S41, a first region 501, a second region 502 arranged outside the first region 501, and a third region 503 arranged outside the second region 502 are formed in the substrate 500. In a direction perpendicular to the surface of the substrate 500, the surface of the first region 501 is higher than the surface of the second region 502, and the surface of the second region 502 is higher than the surface of the third region 503. The gate structure 510 is arranged on the surface of the substrate 500 in the first region 501, and the gate spacer isolation layer 540 covers the sidewalls of the gate structure 510 and at least covers the surface of the substrate 500 in the second region 502.

[0083] As an example, an embodiment of the present disclosure provides a method for forming a first region 501 , a second region 502 , and a third region 503 in a substrate 500 .

[0084] See also Figure 5D , part of the substrate 500 is removed so that the substrate 500 forms a first region 501 covered by the gate structure 510 and a second initial region 504 arranged outside the first region 501. In the direction perpendicular to the surface of the substrate 500 (such as the Z direction in the figure), the surface of the first region 501 is higher than the surface of the second initial region 504.

[0085] In some embodiments, a first spacer 541 has already been formed during the step of forming the lightly doped drain region 530. In this step, after forming the lightly doped drain region 530, the first spacer 541, gate cap layer 513, and gate conductive layer 512 are used as shields to partially remove the gate dielectric layer 511 and the substrate 500, thereby forming a first region 501 and a second initial region 504. The surface of the substrate 500 in the first region 501 is covered by the gate dielectric layer 511. In some embodiments, the gate dielectric layer 511 covers the entire surface of the substrate 500. In this step, the gate dielectric layer 511 needs to be removed to expose the surface of the substrate 500, while the gate dielectric layer 511 on the bottom surface of the first spacer 541 is not removed. In other embodiments, if the gate dielectric layer 511 does not cover the entire surface of the substrate 500, but only covers the region of the substrate 500 corresponding to the gate conductive layer 512, the step of removing the gate dielectric layer 511 can be omitted, and the substrate 500 can be directly removed.

[0086] Among them, a process combining photolithography and etching can be used to remove the gate dielectric layer 511 and the substrate 500. The area of ​​the substrate 500 blocked by the gate structure 510 and the first sidewall isolation layer 541 is not removed, and serves as the first area 501 of the substrate 500. Other areas outside the first area 501 serve as the second initial area 504.

[0087] In some embodiments, the fabrication method may not include the step of forming the lightly doped drain region 530. In this case, the step of forming the first region 501 and the second initial region 504 on the substrate 500 further includes the step of forming a first spacer 541. The first spacer 541 covers the sidewalls of the gate cap layer 513, the sidewalls of the gate conductive layer 512, and a portion of the surface of the gate dielectric layer 511.

[0088] In the semiconductor structure formed in this step, in the direction perpendicular to the surface of the substrate 500 (eg Figure 5D In the Z direction (in the Z direction), the surface of the first region 501 is higher than the surface of the second initial region 504, that is, in this step, a semiconductor structure is formed in which the surface of the substrate 500 is lowered. In this embodiment, the sidewalls of the first region 501 are naturally inclined sidewalls formed during the process steps. In other embodiments, the etching parameters can be controlled to make the sidewalls of the first region 501 perpendicular to the surface of the substrate 500, that is, the sidewalls of the first region 501 extend along the Z direction.

[0089] See also Figure 5F , a portion of the substrate 500 is removed in the second initial region 504 so that the substrate 500 forms a second region 502 arranged outside the first region 501 and a third region 503 arranged outside the second region 502. In the direction perpendicular to the surface of the substrate 500, the surface of the first region 501 is higher than the surface of the second region 502, and the surface of the second region 502 is higher than the surface of the third region 503.

[0090] In this step, the second spacer isolation layer 542 and the gate structure 510 are used as shielding to remove a portion of the substrate 500 to form a second region 502 and a third region 503 .

[0091] Specifically, see Figure 5E , forming a second spacer spacer 542, the second spacer spacer 542 covers the sidewalls of the first spacer spacer 541, the sidewalls of the gate dielectric layer 511, the sidewalls of the substrate 500 in the first region 501, and a portion of the surface of the substrate 500 in the second initial region 504. The second spacer spacer 542 can be a silicon oxide layer, a silicon nitride layer, or a nitride oxide layer. In this step, the second spacer spacer 542 can be formed by a chemical vapor deposition process, an atomic layer deposition process, or the like. In this embodiment, the second spacer spacer 542 is formed by an atomic layer deposition process, and the second spacer spacer 542 is a silicon oxide layer. In some embodiments, the second spacer spacer 542 and the first spacer spacer 541 are the same material layer. In other embodiments, the second spacer spacer 542 and the first spacer spacer 541 can also be different material layers, for example, the second spacer spacer 542 is a silicon nitride layer, and the first spacer spacer 541 is a silicon oxide layer.

[0092] See also Figure 5F , using the second spacer spacer 542, the first spacer spacer 541, and the gate structure 510 as shielding, a portion of the substrate 500 is removed to form a second region 502 and a third region 503. In this step, an etching process can be used to etch the substrate 500 to remove a portion of the substrate 500. In the areas shielded by the second spacer spacer 542, the first spacer spacer 541, and the gate structure 510, the substrate 500 is not removed, thereby forming the first region 501, the second region 502, and the third region 503 with different surface heights.

[0093] In the semiconductor structure formed in this step, in the direction perpendicular to the surface of the substrate 500 (eg Figure 5F In the Z direction (in the Z direction), the surface of the first region 501 is higher than the surface of the second region 502, and the surface of the second region 502 is higher than the surface of the third region 503. In other words, in this step, a semiconductor structure is formed in which the surface of the substrate 500 is sequentially lowered. In this embodiment, the sidewalls of the second region 502 are naturally inclined sidewalls formed during the process steps. In other embodiments, the etching parameters can be controlled to make the sidewalls of the second region 502 perpendicular to the surface of the substrate 500, that is, the sidewalls of the second region 502 extend along the Z direction.

[0094] In some embodiments, the height difference between the surface of the first region 501 and the surface of the second region 502 and the height difference between the surface of the second region 502 and the surface of the third region 503 are equal, which can reduce the process difficulty and improve the controllability of the process flow.

[0095] Please continue reading Figure 4 and Figure 5H In step S42, a source region 550 and a drain region 551 are formed in the substrate 500. The source region 550 and the drain region 551 are located at least in the third region 503. In some embodiments, an ion implantation process can be used to implant ions into the substrate 500 to form the source region 550 and the drain region 551. The doping concentration of the source region 550 and the drain region 551 is greater than the doping concentration of the lightly doped drain region 530.

[0096] As an example, an embodiment of the present disclosure provides a method for forming a source region 550 and a drain region 551 in a substrate 500. The method includes:

[0097] See also Figure 5G, forming a third spacer spacer 543, the third spacer spacer 543 at least covering the sidewalls of the second spacer spacer 542 and the sidewalls of the substrate 500 in the second region 502. In some embodiments, the third spacer spacer 543 also covers a portion of the surface of the substrate 500. The third spacer spacer 543 may be a silicon oxide layer, a silicon nitride layer, or a nitride oxide layer. In this step, the third spacer spacer 543 may be formed by a chemical vapor deposition process, an atomic layer deposition process, or the like. In this embodiment, the third spacer spacer 543 is formed by an atomic layer deposition process, and the third spacer spacer 543 is a silicon oxide layer. In some embodiments, the third spacer spacer 543, the second spacer spacer 542, and the first spacer spacer 541 are layers of the same material. In other embodiments, the third side wall isolation layer 543, the second side wall isolation layer 542, and the first side wall isolation layer 541 may also be different material layers. For example, the third side wall isolation layer 543 is a silicon oxide layer, the second side wall isolation layer 542 is a silicon nitride layer, and the first side wall isolation layer 541 is a silicon oxide layer.

[0098] See also Figure 5H The substrate 500 is doped with the third spacer spacer 543 , the second spacer spacer 542 , the first spacer spacer 541 and the gate structure 510 as shielding to form a source region 550 and a drain region 551 .

[0099] In the semiconductor device provided by the embodiments of the present disclosure, the region of the substrate 500 corresponding to the gate structure 510 serves as a channel region, the lightly doped drain region 530 is disposed outside the channel region, and the source region 550 and the drain region 551 are disposed outside the lightly doped drain region 530. In some embodiments, the first spacer 541, the second spacer 542, and the third spacer 543 collectively serve as gate spacers 540 to protect the gate structure 510 and the substrate 500.

[0100] In this step, doping is performed in the well region 520 to form a source region 250 and a drain region 251, thereby forming a transistor. For example, N-type impurities are doped in the P-well region to form an N-type source region 250 and a drain region 251, thereby forming an NMOS transistor. P-type impurities are doped in the N-well region to form a P-type source region 250 and a drain region 251, thereby forming a PMOS transistor.

[0101] See also Figure 5IIn some embodiments, an annealing process is performed after doping is performed in the well region 520 to form the source region 250 and the drain region 251 to repair the damage caused by doping to the substrate, and at the same time, the impurity distribution of the source region 250, the drain region 251 and the lightly doped drain region 530 is made more uniform. The impurities in the source region 250 and the drain region 251 will diffuse in the lightly doped drain region 530, and the impurities in the lightly doped drain region 530 will diffuse toward the channel region, so that the lightly doped drain region 530 is located below the gate structure 510 and close to the edge of the channel region.

[0102] In some embodiments, after forming the source region 550 and the drain region 551, a source electrode and a drain electrode may be further formed on the surface of the substrate 500 in the third region 503. The source electrode is electrically connected to the source region 550 to realize electrical extraction of the source region 550, and the drain electrode is electrically connected to the drain region 551 to realize electrical extraction of the drain region 551.

[0103] The method for preparing a semiconductor device provided by the embodiment of the present disclosure can separate the location of the most concentrated current in the substrate 500 from the location of the point with the largest electric field intensity in the substrate 500, thereby reducing the ionization of particles at the location that is prone to cause hot carrier injection effects, thereby reducing the number of hot carriers and reducing the risk of hot carrier injection effects.

[0104] In addition, the preparation method of the semiconductor device provided by the embodiment of the present disclosure forms a lightly doped drain region 530 in the substrate 500 before forming the first region 501, the second region 502 and the third region 503 whose surface heights decrease successively on the substrate 500. Compared with forming the lightly doped drain region 530 after forming the first region 501, the second region 502 and the third region 503 whose surface heights decrease successively on the substrate 500, the preparation method provided by the embodiment of the present disclosure can effectively avoid carrier loss and form a semiconductor device with a higher switching ratio.

[0105] Table 1 is a comparison table of the on / off ratios of the semiconductor device prepared by the preparation method provided by the embodiment of the present disclosure and the semiconductor device provided by the comparative embodiment, wherein the semiconductor device E is a semiconductor device prepared by the preparation method provided by the embodiment of the present disclosure (see Figure 5I ), the preparation method thereof is to form a lightly doped drain region 530 on a substrate 500 and then form a first region 501, a second region 502 and a third region 503 with successively lower surface heights; F semiconductor device is used as a comparative embodiment, which is a semiconductor device having a flat surface of the substrate 100 (see Figure 1 ), the preparation method is to directly form a lightly doped drain region 130 in the substrate 100, and no region with different heights is formed on the surface of the substrate 100; G semiconductor device is used as a comparative embodiment, which is a semiconductor device having a first region 601 and a second region 602 with different heights on the surface of the substrate 600 (see Figure 6), a gate spacer 640 covers the sidewalls of the gate structure 610. The semiconductor device is fabricated by forming a first region 601 and a second region 602, whose surface heights decrease sequentially, within a substrate 600, and then forming a lightly doped drain region 630. As can be seen from Table 1, under conditions of substantially the same threshold voltage, the semiconductor device fabricated using the fabrication method provided in the embodiments of the present application has a higher on-off ratio, significantly improving the performance of the semiconductor device.

[0106] Table 1

[0107] semiconductor devices Threshold voltage (VTG / V) On:off ratio E-semiconductor devices 0.675 1465 F semiconductor devices 0.673 1332 G semiconductor devices 0.674 1150

[0108] The above description is only a preferred embodiment of the present invention. It should be pointed out that ordinary technicians in this technical field can make several improvements and modifications without departing from the principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A semiconductor device, characterized in that: include: A substrate having a first region, a second region disposed outside the first region, and a third region disposed outside the second region, wherein in a direction perpendicular to a surface of the substrate, a surface of the first region is higher than a surface of the second region, and a surface of the second region is higher than a surface of the third region; a gate structure, disposed on the surface of the substrate in the first region; a gate spacer isolation layer, covering the sidewalls of the gate structure and at least covering the substrate surface in the second region; a source region and a drain region, located at least in the substrate of the third region; a lightly doped drain region, located at least in the substrate of the second region; The gate structure includes a gate dielectric layer, a gate conductive layer and a gate covering layer, wherein the gate dielectric layer covers the surface of the substrate in the first region, the gate conductive layer covers a portion of the surface of the gate dielectric layer, the gate covering layer covers the surface of the gate conductive layer, and the gate spacer includes: a first spacer spacer, wherein the first spacer spacer covers the sidewalls of the gate cover layer, the sidewalls of the gate conductive layer, and the surface of the gate dielectric layer not covered by the gate conductive layer; a second spacer isolation layer, covering the sidewalls of the first spacer isolation layer, the sidewalls of the gate dielectric layer, the sidewalls of the substrate in the first region, and the surface of the substrate in the second region; a third spacer isolation layer, covering at least the sidewalls of the second spacer isolation layer and the sidewalls of the substrate in the second region; The lightly doped drain region includes a first surface located below the first sidewall isolation layer, a second surface located below the second sidewall isolation layer, and a third surface located below the third sidewall isolation layer, wherein the first surface is higher than the second surface, and the second surface is higher than the third surface.

2. The semiconductor device according to claim 1, wherein A height difference between a surface of the first region and a surface of the second region, and a height difference between a surface of the second region and a surface of the third region are equal.

3. The semiconductor device according to claim 1, wherein A height difference between a surface of the first region and a surface of the second region is 2.5 nm to 3.5 nm, and a height difference between a surface of the second region and a surface of the third region is 2.5 nm to 3.5 nm.

4. A method for preparing a semiconductor device according to any one of claims 1 to 3, characterized in that: include: Providing a substrate, wherein a gate structure is provided on a surface of the substrate; A first region, a second region disposed outside the first region, and a third region disposed outside the second region are formed in the substrate, wherein in a direction perpendicular to the surface of the substrate, a surface of the first region is higher than a surface of the second region, and a surface of the second region is higher than a surface of the third region, the gate structure is disposed on the substrate surface of the first region, and a gate spacer spacer covers a sidewall of the gate structure and at least covers the substrate surface of the second region; A source region and a drain region are formed in the substrate, and the source region and the drain region are at least located in the third region.

5. The preparation method according to claim 4, wherein The step of providing a substrate, wherein the surface of the substrate has a gate structure, comprises: forming a lightly doped drain region in the substrate.

6. The preparation method according to claim 5, wherein The gate structure includes a gate dielectric layer, a gate conductive layer and a gate covering layer, wherein the gate dielectric layer covers the surface of the substrate, the gate conductive layer covers a portion of the surface of the gate dielectric layer, the gate covering layer covers the surface of the gate conductive layer, and the gate spacer includes a first spacer. The step of forming a lightly doped drain region in the substrate includes: forming a first spacer spacer, wherein the first spacer spacer covers the sidewalls of the gate cover layer, the sidewalls of the gate conductive layer, and a portion of the surface of the gate dielectric layer; The substrate is doped with the first sidewall isolation layer, the gate cover layer and the gate conductive layer as shielding to form the lightly doped drain region.

7. The preparation method according to claim 4, characterized in that The step of forming a first region, a second region disposed outside the first region, and a third region disposed outside the second region in the substrate includes: removing a portion of the substrate so that the substrate forms a first region covered by the gate structure and a second initial region disposed outside the first region, wherein a surface of the first region is higher than a surface of the second initial region in a direction perpendicular to the surface of the substrate; A portion of the substrate is removed in the second initial area so that the substrate forms a second area arranged outside the first area and a third area arranged outside the second area, and in a direction perpendicular to the surface of the substrate, the surface of the first area is higher than the surface of the second area, and the surface of the second area is higher than the surface of the third area.

8. The preparation method according to claim 7, wherein The gate structure includes a gate dielectric layer, a gate conductive layer, and a gate covering layer, wherein the gate dielectric layer covers the surface of the substrate, the gate conductive layer covers a portion of the surface of the gate dielectric layer, the gate covering layer covers the surface of the gate conductive layer, and the gate spacer includes a first spacer. The step of removing a portion of the substrate to form a first region covered by the gate structure and a second initial region disposed outside the first region includes: forming a first spacer spacer, wherein the first spacer spacer covers the sidewalls of the gate cover layer, the sidewalls of the gate conductive layer, and a portion of the surface of the gate dielectric layer; Using the first sidewall isolation layer, the gate cover layer and the gate conductive layer as shielding, a portion of the gate dielectric layer and the substrate is removed to form the first region and the second initial region. The substrate surface of the first region is covered by the gate dielectric layer.

9. The preparation method according to claim 8, wherein The gate spacer isolation layer includes a second spacer isolation layer, and the step of removing a portion of the substrate in the second initial area includes: forming a second spacer spacer, wherein the second spacer spacer covers the sidewalls of the first spacer spacer, the sidewalls of the gate dielectric layer, the sidewalls of the substrate in the first region, and a portion of the surface of the substrate in the second initial region; The second spacer isolation layer, the first spacer isolation layer and the gate structure are used as shielding to remove a portion of the substrate to form the second region and the third region.

10. The preparation method according to claim 9, characterized in that The gate spacer isolation layer includes a third spacer isolation layer, and the step of forming a source region and a drain region in the substrate includes: forming the third spacer isolation layer, wherein the third spacer isolation layer at least covers the sidewalls of the second spacer isolation layer and the sidewalls of the substrate in the second region; The substrate is doped with the third spacer isolation layer, the second spacer isolation layer, the first spacer isolation layer and the gate structure as shielding to form the source region and the drain region.

11. The preparation method according to claim 10, characterized in that The third spacer isolation layer also covers a portion of the surface of the substrate in the third region.

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