Capacitance mismatch testing method, device, equipment, storage medium and computer program product

Abstract

This application discloses a capacitor mismatch testing method, comprising: measuring the actual full-rail amplitude of an analog-to-digital converter (ADC) included in a radio frequency transceiver circuit; determining, based on the actual full-rail amplitude, a mismatch test signal corresponding to each capacitor in an N-bit array of capacitors included in the ADC; performing a test using the mismatch test signal corresponding to each capacitor to obtain a test result corresponding to each capacitor; wherein the test result indicates whether each capacitor is mismatched. This application also discloses a capacitor mismatch testing apparatus, device, storage medium, and computer program product.

Description

Technical Field

[0001] The present application relates to the field of wireless communication technology, and in particular to a capacitance mismatch testing method, apparatus, device, storage medium, and computer program product. Background Art

[0002] With the rapid development of wireless communication technology, wireless communication has been widely used. During the implementation of wireless communication, wireless signal transceiver circuits, for example, have a significant impact on communication applications. In the prior art, wireless signal transceiver circuits in fifth-generation mobile communication technology (5G) terminals and base stations are typically implemented using a zero-IF receiver architecture. During the implementation of a zero-IF receiver architecture, a mixer, local oscillator, intermediate frequency filter, transimpedance amplifier, programmable amplifier, analog-to-digital converter (ADC), and some digital baseband functions are typically integrated into a single chip to create a radio frequency (RF) transceiver chip. The ADC, as a bridge between analog and digital, significantly impacts the performance of the entire link. Successive approximation register (SAR) ADCs (also known as SAR ADCs) offer the advantages of low power consumption and a high sampling rate. Therefore, SAR ADCs are commonly used in the implementation of RF transceiver chips. In application, the successive approximation ADC includes a capacitive digital-to-analog converter (DAC) capacitor array.

[0003] Since the deviation of the maximum capacitance value in the capacitor array of the capacitive DAC has the greatest impact on the output digital signal, in order to ensure that the signal error output by the successive approximation ADC is small, the capacitor mismatch is mainly tested and corrected. The current testing process usually captures the digital spectrum from the digital baseband of the RF transceiver chip for analysis, but the digital spectrum has many harmonics and spurious waves, which are usually contributed by the various modules of the successive approximation ADC. Currently, capacitor mismatch is mainly verified through simulation of analog mismatch and engineering test personnel. However, this method takes several weeks to verify, so the real-time verification is very poor, and subsequent high-real-time optimization cannot be carried out.

[0004] Application Contents

[0005] In order to solve the above technical problems, the present application hopes to provide a capacitance mismatch testing method, device, equipment, storage medium and computer program product, which solves the problem of poor real-time performance of the current capacitance mismatch testing method, proposes a method for real-time capacitance mismatch testing, ensures real-time testing efficiency, and can ensure high real-time optimization of this successive approximation ADC.

[0006] The technical solution of this application is achieved as follows:

[0007] The present application provides a capacitance mismatch testing method, the method comprising:

[0008] Measure the actual full swing of the analog-to-digital converter ADC included in the RF transceiver circuit;

[0009] Determining a mismatch test signal corresponding to each bit of an N-bit array capacitor included in the ADC based on the actual full-rail amplitude;

[0010] A mismatch test signal corresponding to each capacitor is used to perform a test to obtain a test result corresponding to each capacitor; wherein the test result is used to indicate whether each capacitor is mismatched.

[0011] In the above implementation, measuring the actual full swing of the analog-to-digital converter ADC included in the radio frequency transceiver circuit includes:

[0012] Determining an input position of an input test signal set in the radio frequency transceiver circuit;

[0013] determining a swing test signal based on the input position;

[0014] The actual full-rail amplitude is determined based on the swing test signal.

[0015] In the above implementation, determining the swing test signal based on the input position includes:

[0016] If the input position is an analog signal input terminal of the ADC, determining that the swing test signal is composed of a bias voltage and a sinusoidal single-tone signal; wherein the signal frequency of the sinusoidal single-tone signal is within the analog bandwidth of the ADC;

[0017] If the input position is the signal input end of the radio frequency transceiver circuit, it is determined that the swing test signal is composed of a local oscillator single-tone signal and a frequency deviation single-tone signal; wherein the signal frequency of the frequency deviation single-tone signal is the sum of the signal frequency of the local oscillator single-tone signal and the frequency deviation frequency, and the frequency deviation frequency is within the analog bandwidth of the ADC.

[0018] In the above implementation, when the swing test signal is composed of the bias voltage and the sinusoidal single-tone signal, determining the actual full-rail amplitude based on the swing test signal includes:

[0019] When the bias voltage of the swing test signal is set to 0, the swing test signal is input to determine the first amplitude of the sinusoidal single-tone signal; wherein, when the amplitude of the sinusoidal single-tone signal is the first amplitude, the first output amplitude of the output signal of the RF transceiver circuit is less than or equal to the theoretical swing of the ADC signal, and the difference between the theoretical swing and the first output amplitude is within a first preset range;

[0020] When the amplitude of the sinusoidal single-tone signal is set to the first amplitude, the swing test signal is input to determine a first bias sub-voltage and a second bias sub-voltage; wherein, when the amplitude of the sinusoidal single-tone signal is the first amplitude and the bias voltage is the first bias sub-voltage, the second output amplitude of the output signal of the RF transceiver circuit is less than or equal to the theoretical upper edge swing of the ADC signal, and the difference between the theoretical upper edge swing and the second output amplitude is within a second preset range; when the amplitude of the sinusoidal single-tone signal is the first amplitude and the bias voltage is the second bias sub-voltage, the third output amplitude of the output signal of the RF transceiver circuit is greater than or equal to the theoretical lower edge swing of the ADC signal, and the difference between the third output amplitude and the theoretical lower edge swing is within a third preset range;

[0021] The sum of the first amplitude, the first bias sub-voltage, and the second bias sub-voltage is determined to obtain the actual full-rail amplitude.

[0022] In the above implementation, the first amplitude is greater than or equal to 0.5*the theoretical full swing of the ADC, and less than or equal to 0.8*the theoretical full swing of the ADC.

[0023] In the above implementation, when the swing test signal is composed of the local oscillator single-tone signal and the frequency-shifted single-tone signal, determining the actual full-rail amplitude based on the swing test signal includes:

[0024] The local oscillator single-tone signal is set to zero, the swing test signal is input, the amplitude of the frequency-deviation single-tone signal is adjusted, and the actual full swing of the frequency-deviation single-tone signal is determined; wherein, when the local oscillator single-tone signal is zero and the amplitude of the frequency-deviation single-tone signal is the actual full swing, the difference between the fourth output amplitude of the output signal of the RF transceiver circuit and the theoretical upper swing or the theoretical lower swing of the corresponding ADC signal is within a fourth preset range.

[0025] In the above implementation, the actual full-rail amplitude is greater than or equal to 0.5*the theoretical full-rail amplitude of the ADC.

[0026] In the above implementation, determining the mismatch test signal corresponding to each bit of the N-bit array capacitor included in the ADC based on the actual full-swing amplitude includes:

[0027] Based on the actual full-rail amplitude, determining a first signal for operating all capacitors corresponding to the i-th position and the i+1-th position and thereafter; wherein i=1, 2, ..., m, i=1 corresponds to the maximum capacitance position in the N-bit array capacitor, i=2 corresponds to the second largest capacitance position in the N-bit array capacitor, and so on, and m is an integer less than or equal to N;

[0028] Based on the actual full-rail amplitude, a second signal for operating all capacitors corresponding to the i-th capacitor and thereafter is determined; wherein the mismatch test signal corresponding to the i-th capacitor includes the first signal and the second signal.

[0029] In the above implementation scheme, when the mth capacitor is tested, the analysis value corresponding to the parameter to be analyzed of the output signal of the RF transceiver circuit is greater than or equal to the first threshold value, and when the m+1th capacitor is tested, the analysis value corresponding to the parameter to be analyzed is less than the first threshold value.

[0030] In the above implementation, when the swing test signal is composed of a bias voltage and a sinusoidal single-tone signal, when n=1, the bias voltage included in the first signal is the sum of the first bias sub-voltage and the second bias sub-voltage; when n=2, 3, ..., m, the bias voltage included in the first signal is p*1 / 2n-1*the actual full swing, where p is any value selected from the union of the calculated values ​​of (2X-1) and -(2X-1) when X starts from 1 to 2n-2;

[0031] When n=1, 2, ..., m, the amplitude of the sinusoidal single-tone signal included in the first signal and the second signal is the first preset coefficient * 1 / 2n * the actual full swing, and the bias voltage included in the second signal is q*1 / 2n* the actual full swing, where q is any value selected from the union of the calculated values ​​of (2X-1) and -(2X-1) when X starts from 1 to 2n-1.

[0032] In the above implementation, when n is greater than or equal to 2, before performing the test using the mismatch test signal corresponding to each capacitor and obtaining the test result corresponding to each capacitor, the method further includes:

[0033] The amplitude of the sinusoidal single-tone signal is input as the first preset coefficient * 1 / 2n-1 * the actual full swing, and the bias voltage is p*1 / 2n-1 * the actual full swing verification signal, and the first analysis value of the parameter to be analyzed of the output signal of the RF transceiver circuit is obtained.

[0034] In the above implementation, when the swing test signal is composed of a local oscillator single-tone signal and a frequency-shifted single-tone signal, determining the second signal for operating all capacitors corresponding to the i-th position and thereafter based on the actual full swing includes:

[0035] Based on the actual full-rail amplitude, determining a second amplitude of the frequency-shifted single-tone signal that causes all capacitors corresponding to the i-th position and thereafter to operate; wherein the second amplitude is smaller than the actual full-rail amplitude, and the second amplitude is adjusted according to a first preset step;

[0036] The input amplitude is the frequency-deviation single-tone signal of the second amplitude, and the amplitude of the local oscillator single-tone signal is continuously increased according to the second preset step to determine the third amplitude of the local oscillator single-tone signal; wherein, the amplitude of the frequency-deviation single-tone signal of the second signal is the second amplitude, the amplitude of the local oscillator single-tone signal is the third amplitude, the signal upper edge of the output signal of the RF transceiver circuit remains unchanged, and the parameter change value of the parameter to be analyzed of the output signal of the RF transceiver circuit is greater than or equal to the second threshold for the first time.

[0037] In the above implementation, determining the first signal for operating all capacitors corresponding to the i-th bit and the i+1-th bit onwards based on the actual full rail includes:

[0038] When it is determined that the second signal is input, determining a first signal falling edge amplitude of an output signal of the radio frequency transceiver circuit;

[0039] Determining that the amplitude of the frequency-deviation single-tone signal included in the first signal is a fourth amplitude; wherein the fourth amplitude is an amplitude corresponding to before determining that the amplitude of the frequency-deviation single-tone signal is the second amplitude;

[0040] The frequency-deviation single-tone signal having an input amplitude of the fourth amplitude is input, and the amplitude of the local oscillator single-tone signal is continuously lowered according to a third preset step to determine a fifth amplitude of the local oscillator single-tone signal; wherein, when the amplitude of the frequency-deviation single-tone signal of the second signal is the fourth amplitude and the amplitude of the local oscillator single-tone signal is the fifth amplitude, the second signal lower edge amplitude of the output signal of the RF transceiver circuit is greater than or equal to the first signal lower edge amplitude, and the difference between the second signal lower edge amplitude and the first signal lower edge amplitude is within a fifth preset range.

[0041] In the above implementation, the method of performing the test using the mismatch test signal corresponding to each capacitor to obtain the test result corresponding to each capacitor includes:

[0042] Inputting a first signal corresponding to the i-th capacitor to the radio frequency transceiver circuit, and obtaining a second analysis value of the parameter to be analyzed of the output signal of the radio frequency transceiver circuit for the i-th capacitor;

[0043] Inputting a second signal corresponding to the i-th capacitor into the radio frequency transceiver circuit to obtain a third analysis value of the parameter to be analyzed for the i-th capacitor;

[0044] A test result of the i-th capacitor is obtained based on the second analysis value of the i-th capacitor and the third analysis value of the i-th capacitor.

[0045] In the above implementation, the parameters to be analyzed include one or more of the following parameters: signal frequency deviation parameter, harmonic parameter, and spurious power parameter.

[0046] In the above implementation scheme, the RF transceiver circuit also includes a correction capacitor connected in parallel with the N-bit array capacitor, the capacitance value of the correction capacitor is greater than or equal to the theoretical capacitance value of the second largest capacitor in the N-bit array capacitor, and the capacitance value of the correction capacitor is less than or equal to the theoretical capacitance value of the largest capacitor in the N-bit array capacitor.

[0047] In the above implementation, when the j-th capacitor is working, the method further includes:

[0048] If it is determined that the actual capacitance value of the j-th capacitor is less than or equal to the theoretical capacitance value of the j-th capacitor, the correction capacitor is controlled not to be connected to the circuit, and a capacitor is selected to match the theoretical capacitance value of the j-th capacitor to operate as a target capacitance; where j=1, 2, ..., N, and the target capacitance includes at least the j-th capacitor;

[0049] If it is determined that the actual capacitance value of the j-th capacitor is greater than the theoretical capacitance value of the j-th capacitor, at least the correction capacitor is controlled to be connected to the circuit for operation.

[0050] The present application provides a capacitance mismatch testing device, the device comprising: a measuring unit, a determining unit and a testing unit; wherein:

[0051] The measuring unit is used to measure the actual full swing of the analog-to-digital converter ADC included in the radio frequency transceiver circuit;

[0052] The determining unit is configured to determine, based on the actual full rail, a mismatch test signal corresponding to each bit of the N-bit array capacitor included in the ADC;

[0053] The testing unit is used to perform testing using a mismatch test signal corresponding to each bit of the capacitor to obtain a test result corresponding to each bit of the capacitor; wherein the test result is used to indicate whether each bit of the capacitor is mismatched.

[0054] The present application provides a capacitance mismatch testing device, the device comprising: a memory, a processor, and a communication bus; wherein:

[0055] The memory is used to store executable instructions;

[0056] The communication bus is used to realize the communication connection between the processor and the memory;

[0057] The processor is configured to execute the capacitance mismatch test program stored in the memory to implement the steps of any one of the above capacitance mismatch test methods.

[0058] The present application provides a storage medium, on which a capacitance mismatch test program is stored. When the capacitance mismatch test program is executed by a processor, the steps of any of the above-mentioned capacitance mismatch test methods are implemented.

[0059] The present application provides a computer program product, comprising a computer program, which implements the steps of any one of the above-mentioned capacitance mismatch testing methods when executed by a processor.

[0060] The embodiments of the present application provide a capacitor mismatch testing method, apparatus, device, storage medium, and computer program product. After measuring the actual full-rail swing of an ADC included in a radio frequency transceiver circuit, the method determines, based on the actual full-rail swing, a mismatch test signal corresponding to each bit of an N-bit array capacitor included in the ADC, and then uses the mismatch test signal corresponding to each bit of the capacitor to perform testing, obtaining a test result corresponding to each bit of the capacitor. In this way, the method solves the problem of poor real-time performance of current capacitor mismatch testing methods and proposes a method for performing capacitor mismatch testing in real time, ensuring real-time testing efficiency and enabling high real-time optimization of successive approximation ADCs. BRIEF DESCRIPTION OF THE DRAWINGS

[0061] Figure 1 A flow chart of a capacitance mismatch testing method provided in an embodiment of the present application;

[0062] Figure 2 A flow chart of another capacitance mismatch testing method provided in an embodiment of the present application;

[0063] Figure 3 A schematic diagram of the structure of a typical zero-IF receiver architecture provided in an embodiment of the present application;

[0064] Figure 4 A schematic diagram of the structure of a capacitive N-bits DAC provided in an embodiment of the present application;

[0065] Figure 5 A test configuration diagram provided for an embodiment of the present application;

[0066] Figure 6 Another test configuration diagram provided for an embodiment of the present application;

[0067] Figure 7 A schematic diagram of a correction circuit structure provided in an embodiment of the present application;

[0068] Figure 8 A schematic diagram of a capacitance mismatch test device provided in an embodiment of the present application

[0069] Figure 9 A schematic structural diagram of a capacitance mismatch testing device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0070] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application.

[0071] The embodiment of the present application provides a capacitance mismatch test method, referring to Figure 1 As shown, the method is applied to a capacitance mismatch test device, and the method comprises the following steps:

[0072] Step 101: Measure the actual full swing of an analog-to-digital converter ADC included in a radio frequency transceiver circuit.

[0073] In an embodiment of the present application, the capacitance mismatch test equipment can be a test device independent of the radio frequency transceiver circuit. The radio frequency transceiver circuit, including the analog-to-digital converter (ADC), is typically included in a device with signal transceiver functions, such as a base station or an internet communication terminal. The capacitance mismatch test equipment measures the actual full-rail amplitude of the ADC included in the radio frequency transceiver circuit. The measurement method can be to input different signals and detect the output signal to determine the actual full-rail amplitude of the ADC.

[0074] Step 102 : Determine a mismatch test signal corresponding to each bit of the N-bit array capacitor included in the ADC based on the actual full-rail amplitude.

[0075] In an embodiment of the present application, the capacitance mismatch testing device determines a mismatch test signal for performing a mismatch test on each capacitance of the N-bit array included in the ADC based on the actual full-swing amplitude measured and the working characteristics of each capacitance of the N-bit array included in the ADC.

[0076] Step 103: Perform a test using a mismatch test signal corresponding to each bit of capacitance to obtain a test result corresponding to each bit of capacitance.

[0077] The test result is used to indicate whether each bit capacitor is mismatched.

[0078] In the embodiment of the present application, a mismatch test signal corresponding to each capacitor is input to the RF transceiver circuit, and detection and analysis are performed based on the output results of the RF transceiver circuit to determine whether each capacitor is mismatched and obtain the corresponding test results. In this way, the RF transceiver circuit can be tested in real time using the above-mentioned test method, effectively shortening the test process, simplifying the test process, reducing the manpower and material resources spent during the test process, and improving the test efficiency of the RF transceiver circuit.

[0079] The capacitor mismatch testing method provided in an embodiment of the present application measures the actual full-rail swing of an ADC included in a radio frequency transceiver circuit, and then determines, based on the actual full-rail swing, a mismatch test signal corresponding to each bit of an N-bit array capacitor included in the ADC. The mismatch test signal corresponding to each bit of the capacitor is then used to perform testing to obtain a test result corresponding to each bit of the capacitor. Thus, by analyzing the mismatch test signal corresponding to each bit of the N-bit array capacitor included in the ADC based on the actual full-rail swing of the ADC included in the radio frequency transceiver circuit, the mismatch test signal corresponding to each bit of the capacitor is then tested and analyzed to determine a test result corresponding to each bit of the capacitor. This solves the problem of poor real-time performance of current capacitor mismatch testing methods and provides a method for performing real-time capacitor mismatch testing, ensuring real-time testing efficiency and enabling high real-time optimization of successive approximation ADCs.

[0080] Based on the above embodiments, the embodiments of the present application provide a capacitance mismatch test method, referring to Figure 2 As shown, the method is applied to a capacitance mismatch test device, and the method comprises the following steps:

[0081] Step 201: Determine an input position of an input test signal set in a radio frequency transceiver circuit.

[0082] In an embodiment of the present application, the radio frequency transceiver circuit is tested to determine an input position reserved in the radio frequency transceiver circuit for inputting a test signal.

[0083] Step 202: Determine a swing test signal based on the input position.

[0084] In the embodiment of the present application, the swing test signal inputted at different input positions is different. Therefore, after determining the input position where the input test signal is obtained, it is possible to determine that the corresponding swing test signal is obtained.

[0085] Step 203: Determine the actual full swing based on the swing test signal.

[0086] In an embodiment of the present application, swing test signals of different amplitudes are input to the RF transceiver circuit from an input position, the output signal of the RF transceiver circuit is detected, and the actual full swing of the ADC is obtained by analysis.

[0087] Step 204 : Determine a mismatch test signal corresponding to each bit of the N-bit array capacitor included in the ADC based on the actual full-rail amplitude.

[0088] In an embodiment of the present application, according to the actual full-rail amplitude determined, based on the capacitance operating characteristics of the N-bit array capacitor included in the ADC, a mismatch test signal for each bit capacitor is determined, and the mismatch test signal for each bit capacitor has a correlation with the actual full-rail amplitude.

[0089] Step 205 : Perform a test using the mismatch test signal corresponding to each bit of capacitance to obtain a test result corresponding to each bit of capacitance.

[0090] The test result is used to indicate whether each bit capacitor is mismatched.

[0091] In an embodiment of the present application, a mismatch test signal corresponding to each bit of capacitor is input, a mismatch test is performed on each bit of capacitor, and an output result corresponding to the mismatch test signal of each bit of capacitor is obtained. Based on the output result corresponding to the mismatch test signal of each bit of capacitor, analysis is performed to determine the test result corresponding to each bit of capacitor.

[0092] Based on the above embodiment, in other embodiments of the present application, step 202 may be implemented by step 202a or step 202b:

[0093] Step 202a: If the input position is the analog signal input terminal of the ADC, determine whether the swing test signal is composed of a bias voltage and a sinusoidal single-tone signal.

[0094] The signal frequency of the sinusoidal single-tone signal is within the analog bandwidth of the ADC.

[0095] In an embodiment of the present application, when the input position of the reserved test signal is the model signal input terminal of the ADC, it is determined that the swing test signal to be input is composed of a bias voltage and a sinusoidal single-tone signal, which can be expressed as DC+A*sinωt, wherein DC is the bias voltage, A*sinωt is the sinusoidal single-tone signal, A is the amplitude of the sinusoidal single-tone signal, and ω is the angular frequency of the sinusoidal single-tone signal, and its value range is within the analog bandwidth of the ADC.

[0096] Step 202b: If the input position is the signal input end of the radio frequency transceiver circuit, determine that the swing test signal is composed of a local oscillator single tone signal and a frequency deviation single tone signal.

[0097] The signal frequency of the frequency-deviation single-tone signal is the sum of the signal frequency of the local oscillator single-tone signal and the frequency-deviation frequency, and the frequency-deviation frequency is within the analog bandwidth of the ADC.

[0098] In the embodiment of the present application, when the RF transceiver circuit does not pre-set a signal input terminal for external input signal at the analog signal input terminal of the ADC, it is determined that the test signal can only be input from the signal input terminal of the RF transceiver circuit. At this time, the input position can be determined to be the signal input terminal of the RF transceiver circuit. In this way, the swing test signal for this type of RF transceiver circuit needs to include a local oscillator single-tone signal and a frequency deviation single-tone signal, which can be recorded as A for example. LO Sinw LO *t+A Bias Sin(w Bias +w LO )*t, where A LO is the swing of the local oscillator single tone signal, w LO is the angular frequency of the local oscillator single tone signal, A Bias is the amplitude of the frequency-shifted single-tone signal, w Bias is the angular frequency of the frequency-shifted single-tone signal, w Bias The value is within the bandwidth of the RF transceiver circuit.

[0099] Based on the above embodiment, in other embodiments of the present application, when the swing test signal consists of a bias voltage and a sinusoidal single-tone signal, step 203 can be implemented by steps 203a to 203c:

[0100] Step 203a: When the bias voltage of the swing test signal is set to 0, the swing test signal is input to determine the first amplitude of the sinusoidal single tone signal.

[0101] When the amplitude of the sinusoidal single-tone signal is a first amplitude, the first output amplitude of the output signal of the RF transceiver circuit is less than or equal to the theoretical swing of the ADC signal, and the difference between the theoretical swing and the first output amplitude is within a first preset range.

[0102] In an embodiment of the present application, when performing an actual full-swing measurement of an ADC when the swing test signal is composed of a bias voltage and a sinusoidal single-tone signal, that is, when the input position is the analog signal input terminal of an ADC, the bias voltage of the swing test signal is first set to 0 V, that is, when the swing test signal only includes the sinusoidal single-tone signal, the signal amplitude of the sinusoidal single-tone signal is continuously adjusted, the signal amplitude of the ADC output signal is observed, and when the signal amplitude of the ADC output signal is less than or equal to the theoretical swing of the ADC signal, and the difference between the theoretical swing and the first output amplitude is within a first preset range, the signal amplitude of the input signal at this time is determined to obtain a first amplitude of the sinusoidal single-tone signal. The first preset range is an empirical value obtained based on a large number of experiments, indicating that the difference between the theoretical swing and the first output amplitude is small, that is, the first output amplitude is very close to the theoretical swing.

[0103] When determining the first amplitude of the sinusoidal single-tone signal, the signal swing of the input swing test signal is gradually reduced from the maximum value according to a preset step. The maximum value of the signal swing of the input swing test signal can be, for example, 0.8*the theoretical full swing of the ADC, and the minimum value can be 0.5*the theoretical full swing of the ADC. The preset step can be determined according to the specific circuit characteristics of the RF transceiver circuit or specific test requirements.

[0104] Step 203b: When the amplitude of the sinusoidal single-tone signal is set to a first amplitude, a swing test signal is input to determine a first bias sub-voltage and a second bias sub-voltage.

[0105] Among them, when the amplitude of the sinusoidal single-tone signal is the first amplitude and the bias voltage is the first bias sub-voltage, the second output amplitude of the output signal of the RF transceiver circuit is less than or equal to the theoretical upper edge swing of the ADC signal, and the difference between the theoretical upper edge swing and the second output amplitude is within a second preset range. When the amplitude of the sinusoidal single-tone signal is the first amplitude and the bias voltage is the second bias sub-voltage, the third output amplitude of the output signal of the RF transceiver circuit is greater than or equal to the theoretical lower edge swing of the ADC signal, and the difference between the third output amplitude and the theoretical lower edge swing is within a third preset range.

[0106] In the embodiment of the present application, the second preset range and the third preset range are both empirical values ​​obtained based on a large number of experiments and can be adjusted according to actual conditions. When it is determined that the amplitude of the sinusoidal single-tone signal is the first amplitude, the amplitude of the sinusoidal single-tone signal is set to the first amplitude and maintained at the first amplitude. Then, the bias voltage of the swing test signal is determined. By adjusting the bias voltage step by step according to a certain rule, the bias voltage is input from the ADC analog signal input end to the radio frequency transceiver circuit to determine the output signal of the ADC. When it is detected that the second output amplitude of the ADC output signal is close to the theoretical upper edge swing of the ADC signal, that is, the second output amplitude is less than or equal to the theoretical upper edge swing of the ADC signal, and the difference between the theoretical upper edge swing and the second output amplitude is within the second preset range, the voltage value corresponding to the bias voltage of the swing test signal at this time is determined to be the first bias sub-voltage. Similarly, when it is detected that the third output amplitude of the ADC output signal is close to the theoretical lower edge swing of the ADC signal, that is, the third output amplitude is greater than or equal to the theoretical upper edge swing of the ADC signal, and the difference between the theoretical lower edge swing and the third output amplitude is within a third preset range, it is determined that the voltage value corresponding to the bias voltage of the swing test signal at this time is the second bias sub-voltage.

[0107] When determining the second output amplitude, the bias voltage can be adjusted by increasing the bias voltage starting from 0 in a positive direction, for example, by increasing the bias voltage in steps greater than 0, until the amplitude of the output signal of the RF transceiver circuit is less than or equal to the theoretical upper edge swing of the ADC signal, and the difference between the theoretical upper edge swing and the second output amplitude is within a second preset range, and the corresponding input bias voltage is determined to be the first bias sub-voltage. Correspondingly, when determining the third output amplitude, the bias voltage can be adjusted by decreasing the bias voltage starting from 0 in a negative direction, for example, by decreasing the bias voltage in steps less than 0, and the bias voltage of the swing test signal is adjusted until the amplitude of the output signal of the RF transceiver circuit is greater than or equal to the theoretical upper edge swing of the ADC signal, and the difference between the theoretical lower edge swing and the third output amplitude is within a third preset range, and the corresponding input bias voltage is determined to be the second bias sub-voltage.

[0108] Step 203c: Determine the sum of the first amplitude, the first bias sub-voltage, and the second bias sub-voltage to obtain an actual full-rail amplitude.

[0109] The first amplitude is greater than or equal to 0.5*the theoretical full swing of ADC, and less than or equal to 0.8*the theoretical full swing of ADC.

[0110] In the embodiment of the present application, after determining the first amplitude, the first bias sub-voltage, and the second bias sub-voltage, it can be determined that the actual full swing corresponding to the swing test signal is the sum of the first amplitude, the first bias sub-voltage, and the second bias sub-voltage.

[0111] Based on the foregoing embodiment, in other embodiments of the present application, when the amplitude test signal is composed of a local oscillator single-tone signal and a frequency deviation single-tone signal, step 203 can be implemented by step 203d:

[0112] Step 203d: Set the local oscillator single-tone signal to zero, input the swing test signal, adjust the amplitude of the frequency-deviation single-tone signal, and determine the actual full swing amplitude of the frequency-deviation single-tone signal.

[0113] When the local oscillator single-tone signal is zero and the amplitude of the frequency-deviation single-tone signal is an actual full-rail amplitude, a difference between a fourth output amplitude of the output signal of the RF transceiver circuit and a theoretical upper swing amplitude or a theoretical lower swing amplitude of the corresponding ADC signal is within a fourth preset range. The actual full-rail amplitude is greater than or equal to 0.5*the theoretical full-rail amplitude of the ADC.

[0114] In an embodiment of the present application, when the amplitude test signal is composed of a local oscillator single-tone signal and a frequency-shifted single-tone signal, it is first necessary to determine the actual full swing of the frequency-shifted single-tone signal, and then determine the relevant characteristic parameters of the local oscillator single-tone signal. When determining the actual full swing of the frequency-shifted single-tone signal, the local oscillator single-tone signal is first set to 0, that is, the input amplitude test signal at this time only includes the frequency-shifted single-tone signal. At this time, the amplitude test signal including only the frequency-shifted single-tone signal is input to the signal input end of the radio frequency transceiver circuit, and the amplitude of the frequency-shifted single-tone signal is continuously adjusted according to a certain step until the amplitude of the output signal of the radio frequency transceiver circuit touches the theoretical upper swing of the ADC signal or the lower swing of the amplitude touches the theoretical lower swing of the ADC signal. That is, when the difference between the fourth output amplitude and the corresponding theoretical upper swing or theoretical lower swing of the ADC signal is within a fourth preset range, it is determined that the amplitude of the input signal at this time is the actual full swing of the frequency-shifted single-tone signal. The fourth preset range is an empirical value obtained based on a large number of experiments and can be continuously adjusted according to actual conditions.

[0115] When determining the actual full swing of a frequency-deviation single-tone signal, an amplitude test signal including only the frequency-deviation single-tone signal is input to the signal input terminal of the RF transceiver circuit, and the amplitude of the frequency-deviation single-tone signal is continuously adjusted according to a certain step. The adjustment process can start from 0.5*the theoretical full swing of the ADC, and continuously adjust the amplitude of the frequency-deviation single-tone signal according to a certain preset value to see whether the relationship between the amplitude of the corresponding output signal and the theoretical upper swing or the theoretical lower swing of the ADC signal meets the above conditions.

[0116] Based on the above embodiment, in other embodiments of the present application, step 204 can be implemented by steps 204a to 204b:

[0117] Step 204a: Based on the actual full rail amplitude, determine a first signal for operating all capacitors corresponding to the i-th bit and the (i+1)-th bit and thereafter.

[0118] Wherein, i=1, 2, ..., m, i=1 corresponds to the maximum capacitance bit in the N-bit array capacitor, i=2 corresponds to the second largest capacitance bit in the N-bit array capacitor, and so on, and m is an integer less than or equal to N.

[0119] In the embodiment of the present application, the actual full swing of the swing test signal is determined to determine a voltage signal to ensure normal operation of each capacitor to be analyzed and the capacitor adjacent to the next capacitor, thereby obtaining a first signal.

[0120] Step 204b: Based on the actual full rail amplitude, determine a second signal for operating all capacitors corresponding to the i-th bit and thereafter.

[0121] The mismatch test signal corresponding to the i-th capacitor includes a first signal and a second signal.

[0122] In the embodiment of the present application, a voltage signal that ensures normal operation of all capacitors following each capacitor to be analyzed is determined based on the actual full swing of the swing test signal to obtain a second signal.

[0123] In other embodiments of the present application, the process of determining the m value is: when the m-th capacitor is tested, the analysis value corresponding to the parameter to be analyzed of the output signal of the RF transceiver circuit is greater than or equal to the first threshold; when the m+1-th capacitor is tested, the analysis value corresponding to the parameter to be analyzed is less than the first threshold.

[0124] In the embodiment of the present application, m represents the order of the capacitor corresponding to the parameter to be analyzed in the output signal corresponding to the highest bit of the capacitor in the RF transceiver circuit after testing, and the analysis value corresponding to the parameter to be analyzed is greater than or equal to the first threshold value, and when testing the capacitor subsequent to the highest bit, the analysis value corresponding to the parameter to be analyzed is less than the first threshold value. The parameter to be analyzed may be, for example, a harmonic parameter or a spurious parameter, and the corresponding first threshold value may be the noise floor of the RF transceiver circuit.

[0125] In other embodiments of the present application, when the swing test signal consists of a bias voltage and a sinusoidal single-tone signal, when n=1, the bias voltage included in the first signal is the sum of the first bias sub-voltage and the second bias sub-voltage, and when n=2, 3, ..., m, the bias voltage included in the first signal is p*1 / 2 n-1 *Actual full swing, p is X value from 1 to 2 n-2 When , any value selected from the union of the calculated values ​​of (2X-1) and -(2X-1);

[0126] When n=1, 2, ..., m, the amplitude of the sinusoidal single tone signal included in the first signal and the second signal is the first preset coefficient * 1 / 2 n*The actual full swing, the second signal includes the bias voltage q*1 / 2 n *Actual full swing, q is X value from 1 to 2 n-1 When , any value selected from the union of the calculated values ​​of (2X-1) and -(2X-1).

[0127] In other embodiments of the present application, when n is greater than or equal to 2, the capacitance mismatch testing device is further configured to perform step 206 before performing step 205:

[0128] Step 206: The amplitude of the input sinusoidal tone signal is the first preset coefficient*1 / 2 n-1 *The actual full swing and bias voltage is p*1 / 2 n-1 *A verification signal of the actual full swing is used to obtain a first analysis value of the parameter to be analyzed of the output signal of the RF transceiver circuit.

[0129] In the embodiment of the present application, the first preset coefficient is an empirical value obtained based on a large number of experiments, for example, the value can be 0.8. The amplitude of the sinusoidal single tone signal is the first preset coefficient * 1 / 2 n-1 *The actual full swing and bias voltage is p*1 / 2 n-1 *A verification signal of the actual full swing is used to ensure that the remaining capacitors except the current analysis capacitor and the capacitor after the current analysis capacitor are working normally. In this way, by comparing the first analysis value with the corresponding analysis values ​​obtained when the current analysis capacitor and the remaining capacitors after the current analysis capacitor are working, the influence of the current analysis capacitor on the RF transceiver circuit can be determined. Similarly, by comparing the first analysis value with the corresponding analysis values ​​obtained when the capacitor after the current analysis capacitor and all capacitors after the current analysis capacitor are working, the influence of the capacitor after the current analysis capacitor on the RF transceiver circuit can be determined, and then subsequent compensation for the influence can be performed based on the determined influence.

[0130] Based on the above embodiment, in other embodiments of the present application, when the amplitude test signal is composed of a local oscillator single tone signal and a frequency deviation single tone signal, step 204b can be implemented by steps a11 to a12:

[0131] Step a11: Based on the actual full-rail amplitude, determine the second amplitude of the frequency-shifted single-tone signal that causes all capacitors corresponding to the i-th bit and thereafter to operate.

[0132] The second amplitude is smaller than the actual full swing amplitude, and the second amplitude is obtained by adjusting according to the first preset step.

[0133] In the embodiments of the present application, the first preset step size can be an empirical value obtained through extensive experimentation and can be determined based on actual application scenarios. In some application scenarios, this can also be determined by factors such as the test environment, and is not specifically limited herein. Correspondingly, the first preset step size can be a negative value, i.e., to reduce the amplitude of the frequency-deviation single-tone signal.

[0134] Step a12: input a frequency-shifted single-tone signal with a second amplitude, continuously increase the amplitude of the local oscillator single-tone signal according to a second preset step, and determine to obtain a third amplitude of the local oscillator single-tone signal.

[0135] Among them, the amplitude of the frequency-deviation single-tone signal of the second signal is the second amplitude, the amplitude of the local oscillator single-tone signal is the third amplitude, the signal upper edge of the output signal of the RF transceiver circuit remains unchanged, and the parameter change value of the parameter to be analyzed of the output signal of the RF transceiver circuit is greater than or equal to the second threshold for the first time.

[0136] In an embodiment of the present application, the second preset step can be an amplitude adjustment experience value obtained based on a large number of experiments, and can be determined according to the actual application scenario, and is not specifically limited here. When the amplitude of the frequency-deviation single-tone signal is the second amplitude, the local oscillator single-tone signal is continuously raised according to the second preset until the upper edge of the signal output by the RF transceiver circuit remains unchanged, and when the parameter change value of the parameter to be analyzed of the output signal of the RF transceiver circuit is greater than or equal to the second threshold for the first time, the corresponding second amplitude and third amplitude at this time are determined to obtain the final second signal.

[0137] Based on the above embodiment, in other embodiments of the present application, step 204a can be implemented by steps b11 to b13:

[0138] Step b11: When the second signal is input, the amplitude of the first signal falling edge of the output signal of the radio frequency transceiver circuit is determined.

[0139] Step b12: Determine that the amplitude of the frequency-shifted single-tone signal included in the first signal is a fourth amplitude.

[0140] The fourth amplitude is an amplitude corresponding to the amplitude before the second amplitude is determined to be the amplitude of the frequency-shifted single-tone signal.

[0141] In the embodiment of the present application, the fourth amplitude is the initial amplitude of the corresponding frequency-deviant single-tone signal recorded before the second amplitude is determined for the frequency-deviant single-tone signal.

[0142] Step b13: input a frequency-shifted single-tone signal having a fourth amplitude, and continuously reduce the amplitude of the local oscillator single-tone signal according to a third preset step to determine a fifth amplitude of the local oscillator single-tone signal.

[0143] Among them, when the amplitude of the frequency-deviation single-tone signal of the second signal is the fourth amplitude and the amplitude of the local oscillator single-tone signal is the fifth amplitude, the second signal lower edge amplitude of the output signal of the RF transceiver circuit is greater than or equal to the first signal lower edge amplitude, and the difference between the second signal lower edge amplitude and the first signal lower edge amplitude is within the fifth preset range.

[0144] In an embodiment of the present application, the third preset step can be an empirical value of step adjustment obtained based on a large number of experiments, or an empirical value determined based on a test environment, which is determined by the actual situation and is not specifically limited here. The fifth preset range is an empirical value obtained based on a large number of experiments. The amplitude of the frequency-deviation single-tone signal is set to a fourth amplitude, and then the amplitude of the local oscillator single-tone signal is gradually reduced and adjusted according to the preset third preset step, until the second signal lower edge of the output signal of the RF transceiver circuit is close to the first signal lower edge, that is, the second signal lower edge amplitude is greater than or equal to the first signal lower edge amplitude, and the difference between the second signal lower edge amplitude and the first signal lower edge amplitude is within the fifth preset range.

[0145] Based on the above embodiment, in other embodiments of the present application, step 205 can be implemented by steps 205a to 205c:

[0146] Step 205a: input a first signal corresponding to the i-th capacitor to the RF transceiver circuit to obtain a second analysis value of the parameter to be analyzed of the output signal of the RF transceiver circuit for the i-th capacitor.

[0147] The parameters to be analyzed include one or more of the following parameters: signal frequency deviation parameter, harmonic parameter, and spurious power parameter.

[0148] In an embodiment of the present application, the first signal corresponding to the test of the i-th capacitance is input to the RF transceiver circuit at the input position, and the second analysis value corresponding to the parameter to be analyzed included in the output signal of the RF transceiver circuit is detected.

[0149] Step 205b: input the second signal corresponding to the i-th capacitor to the radio frequency transceiver circuit to obtain a third analysis value of the parameter to be analyzed for the i-th capacitor.

[0150] In the embodiment of the present application, the second signal corresponding to the test of the i-th capacitance is input to the radio frequency transceiver circuit at the input position to obtain a third analysis value corresponding to the parameter to be analyzed.

[0151] Step 205c: Obtain a test result of the i-th capacitor based on the second analysis value of the i-th capacitor and the third analysis value of the i-th capacitor.

[0152] In an embodiment of the present application, a one-to-one comparison analysis is performed on the second analysis value and the third analysis value corresponding to the i-th capacitor. For example, the test result of the i-th capacitor is determined based on the difference between the second analysis value and the third analysis value. The test result includes whether the i-th capacitor is mismatched or not mismatched, that is, the i-th capacitor is normal.

[0153] Exemplarily, when the second analysis value includes: A1, B1, C1, and the third analysis value includes A2, B2, C2, the relationships between A1 and A2, B1 and B2, and C1 and C2 are compared respectively, and the test result is determined based on the comparison results of these three parameters; wherein A is used to represent the signal frequency deviation parameter, B is used to represent the harmonic parameter, and C is used to represent the spurious power parameter.

[0154] Based on the above embodiment, in other embodiments of the present application, the RF transceiver circuit further includes a correction capacitor connected in parallel with the N-bit array capacitor, wherein the capacitance value of the correction capacitor is greater than or equal to the theoretical capacitance value of the second largest capacitor in the N-bit array capacitor, and the capacitance value of the correction capacitor is less than or equal to the theoretical capacitance value of the largest capacitor in the N-bit array capacitor. Accordingly, when the j-th capacitor is working, the capacitance mismatch test device is further configured to perform step 207 or step 208:

[0155] Step 207: If it is determined that the actual capacitance value of the j-th capacitor is less than or equal to the theoretical capacitance value of the j-th capacitor, the correction capacitor is controlled not to be connected to the circuit, and a capacitor is selected to match the theoretical capacitance value of the j-th capacitor to operate at a target capacitance.

[0156] Wherein, j=1, 2, ..., N, and the target capacitance includes at least the j-th capacitance.

[0157] In the embodiment of the present application, when it is determined that the actual capacitance value of the j-th capacitor is less than or equal to the theoretical capacitance value of the j-th capacitor, it is determined that the j-th capacitor is normal and no mismatch occurs. In this way, there is no need to perform capacitance correction on the j-th capacitor. Therefore, the switch connecting the correction capacitor in parallel with the N-bit array capacitor can be disconnected so that the correction capacitor is not connected to the circuit. At this time, the RF transceiver circuit can select the target capacitor that matches the theoretical capacitance value of the j-th capacitor according to the original working condition and operate.

[0158] Step 208: If it is determined that the actual capacitance value of the j-th capacitor is greater than the theoretical capacitance value of the j-th capacitor, at least control the correction capacitor to be connected to the circuit to operate.

[0159] In an embodiment of the present application, when it is determined that the actual capacitance value of the j-th capacitor is greater than the theoretical capacitance value of the j-th capacitor, it can be determined that there is a mismatch in the j-th capacitor at this time. Therefore, the j-th capacitor needs to be corrected. At this time, the switch connecting the correction capacitor and the N-bit array capacitor in parallel can be controlled to be closed, so as to control the correction capacitor to be connected to the radio frequency transceiver circuit to work. In this way, the capacitance value of the j-th capacitor can be reduced by parallel connection so that its theoretical capacitance can be matched.

[0160] Based on the above embodiments, the present application provides a typical zero intermediate frequency receiver architecture, such as Figure 3 As shown, it at least includes: RF filter, RF amplifier, mixer, local oscillator, intermediate frequency filter, transimpedance amplifier, programmable amplifier, analog-to-digital converter ADC and digital baseband function; wherein, the mixer, local oscillator, intermediate frequency filter, transimpedance amplifier, programmable amplifier, analog-to-digital converter ADC and part of the digital baseband function can be integrated into one chip, which is usually called a zero intermediate frequency RF transceiver chip. Among them, in the operation process of a typical successive approximation ADC, the analog signal is maintained by a capacitor and compared with different reference voltages one by one, so that the final required accuracy (which is also the achievable accuracy) is finally obtained by binary division, and the digital register (buffer) records the result of each comparison and finally outputs a digital signal. The overall comparison operation is controlled by the logic unit of the ADC. Among them, the capacitive N-bits DAC is used to realize the generation of different references. Generally, a capacitor array is used to realize the capacitive DAC, such as Figure 4 The figure shows a schematic diagram of a 16-bit capacitive DAC. The comparison process can be implemented as follows: First, all capacitors are charged with analog inputs through switches. in , the common terminal (CT) is grounded; secondly, CT is disconnected and all capacitors are grounded, at this time CT = -V in ; Third, the most significant bit (MSB) capacitor is connected to the reference voltage V REF The rest remain grounded. Since the MSB capacitance value is the same as the other parallel capacitance values, according to the capacitance voltage divider theorem, CT = -V in +0.5*V REF , through the comparator, which can also be called an op amp comparison CT and 0, that is, V in and 0.5*V REF Similarly, compare the next largest bit in turn, and the next largest capacitor is connected to the reference voltage V REF , and so on until the least significant bit (LSB), each bit is divided according to the capacitance value, CT n =-V in +0.5 n*V REF , where the second largest digit is recorded as n=2, and so on.

[0161] Based on the aforementioned circuit architecture, the present invention provides a capacitance mismatch test method, which can be applied to Figure 5 In the test configuration shown, a biased single-tone signal is input to the test bit from the ADC analog side, and the signal is captured at the test bit in the digital part. The input signal is DC + A*sinωt, where DC is the set bias voltage, A is the amplitude of the sinusoidal single-tone signal, and ω is the sinusoidal signal frequency. In the test, the sinusoidal signal frequency is set within the analog bandwidth of the ADC. The corresponding implementation process can be shown as follows:

[0162] Step 1: Measure the actual full swing of the ADC.

[0163] The ADC full-swing test can be performed by adjusting the bias voltage DC and the sine amplitude A. The specific implementation process can be:

[0164] Step 1.1: Determine the sinusoidal amplitude A1 of the test signal.

[0165] Among them, FS design The ADC's designed full-rail amplitude (FS_design) is obtained through ADC design, i.e., the theoretical full-rail amplitude of the ADC. The test signal's sinusoidal amplitude A1 is obtained by taking values ​​from (0.5*FS_design, 0.8*FS_design) in descending order according to preset step sizes.

[0166] Step 1.2: Set the test signal's DC to 0 and the test signal's sinusoidal amplitude A to A1. Test whether the RF transceiver circuit's output signal reaches the ADC's theoretical full-swing range in the current state. If it does not, determine that the sinusoidal amplitude A is A1 and proceed to step 1.3. If it does, proceed to step 1.1.

[0167] When both of the above conditions are not met, the ADC working state needs to be determined.

[0168] Step 1.3, adjust DC upwards, and obtain the test signal by adjusting the sine amplitude A1 of the test signal in step 1.1. Input the test signal to the RF transceiver circuit until the output signal touches the upper edge of the ADC full swing, and record the corresponding bias voltage DC at this time. u .

[0169] Among them, the upper edge of the full swing is FS u =0.5*A1+DC u .

[0170] Step 1.4: Adjust the DC voltage downward and obtain the test signal by adjusting the sine amplitude A1 of the test signal in step 1.1 until it touches the lower edge of the ADC full swing. Record the corresponding bias voltage DC at this time. d .

[0171] Among them, the lower edge of the full swing is FS d =0.5*A1+DC d .

[0172] Step 1.5: Determine the actual full swing of the ADC as FS all =A1+DC u +DC d .

[0173] Step 2: Maximum bit MSB capacitor array mismatch test.

[0174] Here, it is recorded as the first test, m = 1. The specific implementation process is as follows:

[0175] Step 2.1: Set the first test signal, input the first test signal to the ADC, capture and process the digital signal through the digital baseband, and record the digital signal spectrum, harmonic power, and spurious power.

[0176] Here, let the amplitude of the sinusoidal signal in the first test signal be A=0.8*1 / 2 m *FS all , m=1, bias voltage DC1=DC u +DC d The first test signal ensures that all capacitor arrays except the second largest bit are involved in the work, that is, the capacitors after the largest bit and the second largest bit are all working to contribute harmonic and spurious wave components.

[0177] Step 2.2: Set the second test signal, input the second test signal to the ADC, capture and process the digital signal through the digital baseband, and record the digital signal spectrum, harmonic power, and spurious power.

[0178] The amplitude of the sinusoidal signal of the second test signal is the same as that of the first test signal, which is 0.8*1 / 2 m *FS all , bias voltage is DC2=n*1 / 2 m *FS all ;in, That is, the value of n is 1 or -1. The second test signal ensures that all capacitor arrays except the largest bit are in operation, that is, all capacitors after the largest bit capacitor are in operation.

[0179] Step 2.3: By comparing the digital signal spectrum, harmonic power, and spurious power obtained in step 2.2 and step 2.1, the mismatch test result of the maximum bit capacitance can be obtained.

[0180] For example, the harmonic power and spurious power obtained in step 2.2 can be subtracted from the corresponding harmonic power and spurious power obtained in step 2.1. This means the maximum capacitance minus the next-largest capacitance. If the difference after subtraction is greater than a certain threshold, it indicates that the maximum capacitance has a significant impact on the RF transceiver circuit, indicating a maximum capacitance mismatch. Specifically, when optimizing the capacitor array described later, this method can be used to find the most appropriate capacitor configuration without specifying the next-largest capacitance.

[0181] Step 3: Second largest capacitor array mismatch test.

[0182] Step 3.1. Set the verification signal, input the verification signal to the ADC, capture and process the digital signal through the digital baseband, and record the digital signal spectrum, harmonic power, and spurious power.

[0183] Here, let the amplitude of the sinusoidal signal in the verification signal be A=0.8*1 / 2 (m-1) *FS all , bias voltage DC=n*1 / 2 (m -1) *FS all ,in, U is a number selected from the set after the union operation.

[0184] Step 3.2: Set the third test signal, input the third test signal to the ADC, capture and process the digital signal through the digital baseband, and record the digital signal spectrum, harmonic power, and spurious power.

[0185] Here, let the sine signal amplitude of the third test signal be A=0.8*1 / 2 m *FS all , bias voltage DC3=n*1 / 2 (m-1) *FS all ,in, Comparing the data in 3.1, we can see the impact of signal amplitude reduction on related harmonics and spurious power. In this way, all capacitor arrays in the RF transceiver circuit, except for the largest bit and the second-largest bit, are guaranteed to participate in the operation.

[0186] Step 3.3: Set the fourth test signal, input the fourth test signal to the ADC, capture and process the digital signal through the digital baseband, and record the digital signal spectrum, harmonic power, and spurious power.

[0187] Here, let the sine signal amplitude of the third test signal be A=0.8*1 / 2 m *FSall , bias voltage DC4=n*1 / 2 m *FS all ,in, In this way, it can be ensured that all capacitor arrays except the largest bit and the second largest bit participate in the work.

[0188] Step 3.4: By comparing the harmonic and stray power values ​​from Step 3.3 and Step 3.2, you can determine the effect of the second-largest capacitor minus the second-largest capacitor, thus obtaining the test result for the second-largest capacitor. In some scenarios, the harmonic and stray power values ​​from Step 3.1 can be used to compensate for the harmonic and stray power values ​​from Step 3.2, reducing their impact on the relevant harmonics and stray power.

[0189] Step 4: perform mismatch test on the remaining capacitor arrays.

[0190] The implementation process can refer to the specific implementation process in step 3, which will not be described in detail here.

[0191] It should be noted that since smaller capacitors contribute less to harmonics and spurious signals, the harmonics and spurious signals contributed by smaller capacitors can be ignored. The appropriate position can be determined based on computing and time resources. For example, when calibrating a capacitor and performing spectrum analysis, if the harmonics and spurious signals are below the noise floor, the mismatch test can be terminated.

[0192] Based on the above embodiments, the present application also provides a capacitance mismatch test method, which can be applied to Figure 6 As shown in the test configuration diagram, since the integrated chip ADC is a circuit module in the zero-IF RF transceiver chip, it is usually impossible to set the test bit separately on the analog input side of the ADC. Instead, the test signal can be input from the RF part. The corresponding test signal selection consists of two sinusoidal single-tone signals: 1. The frequency of the local oscillator single-tone signal is the local oscillator frequency ω LO , with an amplitude of A LO ; 2. The frequency of the frequency deviation single tone signal is the local oscillator plus the deviation frequency ω LO +ω Bias , where ω Bias Within the bandwidth, the amplitude is A Bias In this way, adjusting the amplitude of the local oscillator single-tone signal corresponds to adjusting the bias voltage in the above scheme, but only positive voltage can be achieved. Adjusting the amplitude of the frequency-shifted single-tone signal corresponds to adjusting the amplitude of the sinusoidal signal in the above scheme. Based on this, the corresponding implementation process of the automated test ADC can be achieved by referring to the following steps:

[0193] Step 1: Measure the actual full swing of the ADC.

[0194] The actual implementation process of measuring the actual full swing of the ADC can be:

[0195] Step a: Set the test signal to include only the frequency-shifted single-tone signal, that is, the amplitude of the current local oscillator single-tone signal is 0. Correspondingly, control the amplitude of the test signal A. Bias From FS design *0.5 gradually increases until the amplitude of the output signal at the signal output end of the RF transceiver circuit reaches the theoretical full swing of the ADC. When the amplitude of the output signal reaches the theoretical full swing of the ADC, record the signal amplitude of the current input signal of the test signal A. Bias1 .

[0196] Step b: reduce the frequency deviation tone amplitude ABias by the first preset interval, and correspondingly increase the local oscillator tone signal amplitude A according to the second preset interval. LO , so that the output signal rising edge remains the same. When the harmonics and spurious waves show obvious changes, record the signal falling edge position, as well as the spectrum of harmonics and spurious waves and the amplitude of the local oscillator tone signal at this time.

[0197] Step c: Keep the frequency deviation tone amplitude corresponding to the lower edge position of the signal obtained in step b unchanged, and reduce the amplitude of the local oscillator tone signal A according to the third preset interval. LO , so that the output signal 0 point position is at or as close as possible to the signal lower edge position recorded in step b, and record the spectrum conditions such as harmonics and spurious and the amplitude of the local oscillator single tone signal at this time.

[0198] Step d: Calculate the signal amplitude A Bias1 The actual full swing amplitude of the ADC is obtained by combining the amplitude of the local oscillator single tone signal obtained in step b and step c respectively.

[0199] Correspondingly, the subsequent process of performing mismatch testing on each capacitor can refer to the specific implementation process corresponding to steps 2 to 4 in the above embodiment, which will not be described in detail here.

[0200] based on Figure 5 and Figure 6 The test configuration diagram shown in the figure corresponds to the application scenario. The embodiment of the present application provides a correction method corresponding to the capacitor test mismatch. Correspondingly, a correction capacitor can be connected in parallel at the N-bit array capacitor included in the radio frequency transceiver circuit. The circuit structure diagram between the corresponding correction capacitor Ca and the N-bit array capacitor can be as shown in FIG. Figure 7 As shown, a floating position is set for the correction capacitor Ca and the N-bit array capacitor. In some existing N-bit array capacitor circuits, if there is no floating position, the correction capacitor Ca may not be set to a floating position. Figure 7 In the circuit shown, when implementing capacitance correction, the capacitance of the correction capacitor is set to the theoretical capacitance of the MSB capacitor. nC. The voltage across the MSB is connected to the reference voltage V REF , the correction when the MSB capacitor is mismatched is used as an example to illustrate the corresponding correction process.

[0201] (1) When the actual capacitance value of the MSB capacitor is 2 times greater than its theoretical capacitance value n When C is small, the capacitance value of each position is adjusted to match the capacitance value of each position. The capacitance value that is not connected is placed in the floating position, and the Ca capacitor is also placed in the floating position. Therefore, after the other position capacitors are connected in parallel, the capacitance value range is [1,2 n ]*C, the step is 1C, so it has a very wide adjustment range and fine steps.

[0202] (2) When the actual capacitance value of the MSB capacitor is 2 n When C is large, the capacitance value of the position is adjusted to match, the unconnected capacitance value is placed in the floating position, and the Ca capacitor is connected to the circuit. Therefore, after the other position capacitors are connected in parallel, the capacitance value range is [2 n +1,2 (n+1) ]*C, the step is 1C, so it has a very wide adjustment range of 100% and fine steps.

[0203] Similarly, when calibrating the second largest capacitor, the theoretical capacitance value of the second largest capacitor should be 2 (n-1) C, the remaining capacitance values ​​after adding them in parallel are (2 2 -1)*2 (n-1) *C.

[0204] When the second largest capacitor is connected to the reference voltage VREF, assuming that the second largest capacitor is mismatched, when the actual capacitance value of the second largest capacitor is 2 times greater than the theoretical capacitance value, (n-1) * When C is small, the capacitance value of each position is adjusted to match the capacitance value. The unconnected capacitance value is placed in the floating position, and the Ca capacitor is also placed in the floating position. Therefore, after the other capacitances are connected in parallel, the capacitance value range is [1, (2 2 -1)*2 (n-1) ]*Select within C, the step is 1C.

[0205] When the actual capacitance value of the second largest capacitor is 2 (n-1) * When C is large, the capacitance value of the position is adjusted to match, the unconnected capacitance value is placed in the floating position, and the Ca capacitor is connected to the circuit. Therefore, after the other position capacitors are connected in parallel, the capacitance value range can be [(2 2 -1)*2 n-1 ,(2 2 +1)*2 n-1 ]*Select within C, the step is 1C.

[0206] It should be noted that, for the description of the same steps and contents in this embodiment as those in other embodiments, reference can be made to the description in other embodiments and will not be repeated here.

[0207] The capacitor mismatch testing method provided in an embodiment of the present application measures the actual full-rail swing of an ADC included in a radio frequency transceiver circuit, and then determines, based on the actual full-rail swing, a mismatch test signal corresponding to each bit of an N-bit array capacitor included in the ADC. The mismatch test signal corresponding to each bit of the capacitor is then used to perform testing to obtain a test result corresponding to each bit of the capacitor. Thus, by analyzing the mismatch test signal corresponding to each bit of the N-bit array capacitor included in the ADC based on the actual full-rail swing of the ADC included in the radio frequency transceiver circuit, the mismatch test signal corresponding to each bit of the capacitor is then tested and analyzed to determine a test result corresponding to each bit of the capacitor. This solves the problem of poor real-time performance of current capacitor mismatch testing methods and provides a method for performing real-time capacitor mismatch testing, ensuring real-time testing efficiency and enabling high real-time optimization of successive approximation ADCs.

[0208] Based on the above embodiments, the embodiments of the present application provide a capacitance mismatch test device, which can be applied to Figures 1-2 In the capacitance mismatch test method provided in the corresponding embodiment, refer to Figure 8 As shown, the capacitance mismatch test device 3 may include: a measuring unit 31, a determining unit 32 and a testing unit 33; wherein:

[0209] The measuring unit 31 is configured to measure the actual full swing of the analog-to-digital converter ADC included in the radio frequency transceiver circuit;

[0210] A determining unit 32 is configured to determine a mismatch test signal corresponding to each bit of an N-bit array capacitor included in the ADC based on the actual full rail;

[0211] The testing unit 33 is configured to perform a test using a mismatch test signal corresponding to each bit of the capacitor to obtain a test result corresponding to each bit of the capacitor; wherein the test result is used to indicate whether each bit of the capacitor is mismatched.

[0212] In other embodiments of the present application, the measuring unit includes: a first determination module, a second determination module, and a third determination module; wherein:

[0213] A first determining module is used to determine an input position of an input test signal set in the radio frequency transceiver circuit;

[0214] A second determination module is used to determine a swing test signal based on the input position;

[0215] The third determining module is configured to determine an actual full swing amplitude based on the swing amplitude test signal.

[0216] In other embodiments of the present application, the second determining module is specifically configured to implement the following steps:

[0217] If the input location is an analog signal input terminal of an ADC, determine that the swing test signal consists of a bias voltage and a sinusoidal single-tone signal; wherein the signal frequency of the sinusoidal single-tone signal is within the analog bandwidth of the ADC;

[0218] If the input position is the signal input end of the RF transceiver circuit, determine that the swing test signal is composed of a local oscillator single-tone signal and a frequency deviation single-tone signal; wherein the signal frequency of the frequency deviation single-tone signal is the sum of the signal frequency of the local oscillator single-tone signal and the frequency deviation frequency, and the frequency deviation frequency is within the analog bandwidth of the ADC.

[0219] In other embodiments of the present application, when the swing test signal consists of a bias voltage and a sinusoidal single-tone signal, the third determination module is specifically configured to implement the following steps:

[0220] When the bias voltage of the swing test signal is set to 0, the swing test signal is input to determine the first amplitude of the sinusoidal single-tone signal; wherein, when the amplitude of the sinusoidal single-tone signal is the first amplitude, the first output amplitude of the output signal of the RF transceiver circuit is less than or equal to the theoretical swing amplitude of the ADC signal, and the difference between the theoretical swing amplitude and the first output amplitude is within a first preset range;

[0221] When the amplitude of the sinusoidal single-tone signal is set to a first amplitude, an amplitude swing test signal is input to determine a first bias sub-voltage and a second bias sub-voltage; wherein, when the amplitude of the sinusoidal single-tone signal is the first amplitude and the bias voltage is the first bias sub-voltage, the second output amplitude of the output signal of the RF transceiver circuit is less than or equal to the theoretical upper edge swing of the ADC signal, and the difference between the theoretical upper edge swing and the second output amplitude is within a second preset range; when the amplitude of the sinusoidal single-tone signal is the first amplitude and the bias voltage is the second bias sub-voltage, the third output amplitude of the output signal of the RF transceiver circuit is greater than or equal to the theoretical lower edge swing of the ADC signal, and the difference between the third output amplitude and the theoretical lower edge swing is within a third preset range;

[0222] The sum of the first amplitude, the first bias sub-voltage, and the second bias sub-voltage is determined to obtain an actual full-rail amplitude.

[0223] In other embodiments of the present application, the first amplitude is greater than or equal to 0.5*the theoretical full swing of ADC, and less than or equal to 0.8*the theoretical full swing of ADC.

[0224] In other embodiments of the present application, when the amplitude test signal is composed of a local oscillator single-tone signal and a frequency deviation single-tone signal, the third determination module is specifically configured to implement the following steps:

[0225] The local oscillator single-tone signal is set to zero, an amplitude test signal is input, the amplitude of the frequency-deviation single-tone signal is adjusted, and the actual full-swing amplitude of the frequency-deviation single-tone signal is determined; wherein, when the local oscillator single-tone signal is zero and the amplitude of the frequency-deviation single-tone signal is the actual full-swing amplitude, the difference between the fourth output amplitude of the output signal of the RF transceiver circuit and the theoretical upper swing amplitude or the theoretical lower swing amplitude of the corresponding ADC signal is within a fourth preset range.

[0226] In other embodiments of the present application, the actual full-rail amplitude is greater than or equal to 0.5*the theoretical full-rail amplitude of ADC.

[0227] In other embodiments of the present application, the determining unit includes: a fourth determining module; wherein:

[0228] a fourth determining module, configured to determine, based on the actual full-swing amplitude, a first signal for operating all capacitors corresponding to the i-th position and the i+1-th position and thereafter; wherein i=1, 2, ..., m, i=1 corresponds to the maximum capacitance position in the N-bit array capacitor, i=2 corresponds to the second largest capacitance position in the N-bit array capacitor, and so on, and m is an integer less than or equal to N;

[0229] The fourth determination module is further configured to determine, based on the actual full swing, a second signal for operating all capacitors corresponding to the i-th capacitor and thereafter; wherein the mismatch test signal corresponding to the i-th capacitor includes the first signal and the second signal.

[0230] In other embodiments of the present application, when the mth capacitor is tested, the analysis value corresponding to the parameter to be analyzed of the output signal of the RF transceiver circuit is greater than or equal to the first threshold value; when the m+1th capacitor is tested, the analysis value corresponding to the parameter to be analyzed is less than the first threshold value.

[0231] In other embodiments of the present application, when the swing test signal consists of a bias voltage and a sinusoidal single-tone signal, when n=1, the bias voltage included in the first signal is the sum of the first bias sub-voltage and the second bias sub-voltage, and when n=2, 3, ..., m, the bias voltage included in the first signal is p*1 / 2 n-1 *Actual full swing, p is X value from 1 to 2 n-2 When , any value selected from the union of the calculated values ​​of (2X-1) and -(2X-1);

[0232] When n=1, 2, ..., m, the amplitude of the sinusoidal single tone signal included in the first signal and the second signal is the first preset coefficient * 1 / 2 n *The actual full swing, the second signal includes the bias voltage q*1 / 2 n *Actual full swing, q is X value from 1 to 2 n-1 When , any value selected from the union of the calculated values ​​of (2X-1) and -(2X-1).

[0233] In other embodiments of the present application, when n is greater than or equal to 2, the capacitance mismatch testing device further includes an input unit before the testing unit; wherein:

[0234] Input unit, used to input the amplitude of the sinusoidal tone signal to be the first preset coefficient * 1 / 2 n-1 *The actual full swing and bias voltage is p*1 / 2 n-1 *A verification signal of the actual full swing is used to obtain a first analysis value of the parameter to be analyzed of the output signal of the RF transceiver circuit.

[0235] In other embodiments of the present application, when the amplitude test signal is composed of a local oscillator single-tone signal and a frequency deviation single-tone signal, the fourth determination module is specifically configured to implement the following steps:

[0236] Determining, based on the actual full-rail amplitude, a second amplitude of the frequency-shifted single-tone signal that causes all capacitors corresponding to the i-th position and thereafter to operate; wherein the second amplitude is smaller than the actual full-rail amplitude and is obtained by adjusting the second amplitude according to the first preset step;

[0237] A frequency-deviation single-tone signal with a second amplitude is input, and the amplitude of the local oscillator single-tone signal is continuously increased according to a second preset step to determine a third amplitude of the local oscillator single-tone signal; wherein the amplitude of the frequency-deviation single-tone signal of the second signal is the second amplitude, the amplitude of the local oscillator single-tone signal is the third amplitude, the signal upper edge of the output signal of the radio frequency transceiver circuit remains unchanged, and the parameter change value of the parameter to be analyzed of the output signal of the radio frequency transceiver circuit is greater than or equal to the second threshold for the first time.

[0238] In other embodiments of the present application, the fourth determining module is further configured to implement the following steps:

[0239] When the second signal is input, the amplitude of the first signal falling edge of the output signal of the radio frequency transceiver circuit is determined;

[0240] Determining that the amplitude of the frequency-deviation single-tone signal included in the first signal is a fourth amplitude; wherein the fourth amplitude is an amplitude corresponding to the amplitude before determining that the amplitude of the frequency-deviation single-tone signal is the second amplitude;

[0241] A frequency-deviation single-tone signal with a fourth amplitude is input, and the amplitude of the local oscillator single-tone signal is continuously lowered according to a third preset step to determine a fifth amplitude of the local oscillator single-tone signal; wherein, when the amplitude of the frequency-deviation single-tone signal of the second signal is the fourth amplitude and the amplitude of the local oscillator single-tone signal is the fifth amplitude, the second signal lower edge amplitude of the output signal of the RF transceiver circuit is greater than or equal to the first signal lower edge amplitude, and the difference between the second signal lower edge amplitude and the first signal lower edge amplitude is within a fifth preset range.

[0242] In other embodiments of the present application, the test unit includes: an input module and a obtaining module; wherein:

[0243] An input module, configured to input a first signal corresponding to the i-th capacitor to the radio frequency transceiver circuit, and obtain a second analysis value of the parameter to be analyzed of the output signal of the radio frequency transceiver circuit for the i-th capacitor;

[0244] The input module is further configured to input a second signal corresponding to the i-th capacitor to the radio frequency transceiver circuit to obtain a third analysis value of the parameter to be analyzed for the i-th capacitor;

[0245] The obtaining module is configured to obtain a test result of the i-th capacitor based on the second analysis value of the i-th capacitor and the third analysis value of the i-th capacitor.

[0246] In other embodiments of the present application, the parameters to be analyzed include one or more of the following parameters: signal frequency deviation parameters, harmonic parameters, and spurious power parameters.

[0247] In other embodiments of the present application, the RF transceiver circuit also includes a correction capacitor connected in parallel with the N-bit array capacitor, the capacitance value of the correction capacitor is greater than or equal to the theoretical capacitance value of the second largest capacitor in the N-bit array capacitor, and the capacitance value of the correction capacitor is less than or equal to the theoretical capacitance value of the largest capacitor in the N-bit array capacitor.

[0248] In other embodiments of the present application, when the j-th capacitor is working, the capacitance mismatch testing device further includes a processing unit; wherein:

[0249] a processing unit configured to, if it is determined that the actual capacitance value of the j-th capacitor is less than or equal to the theoretical capacitance value of the j-th capacitor, control the correction capacitor to not be connected to the circuit, and select a capacitor to match the theoretical capacitance value of the j-th capacitor to operate as a target capacitance; wherein j = 1, 2, ..., N, and the target capacitance includes at least the j-th capacitor;

[0250] The processing unit is further configured to at least control the correction capacitor to connect to the circuit to operate if it is determined that the actual capacitance value of the j-th capacitor is greater than the theoretical capacitance value of the j-th capacitor.

[0251] It should be noted that the specific implementation process of information interaction between the units and modules included in the capacitance mismatch test device in this embodiment can be referred to Figures 1-2 The implementation process of the capacitance mismatch testing method provided in the corresponding embodiment will not be repeated here.

[0252] The capacitor mismatch test device provided in an embodiment of the present application measures the actual full-rail swing of the ADC included in the radio frequency transceiver circuit, and then determines the mismatch test signal corresponding to each bit of the N-bit array capacitor included in the ADC based on the actual full-rail swing. The mismatch test signal corresponding to each bit of the capacitor is then used to perform testing to obtain a test result corresponding to each bit of the capacitor. In this way, the mismatch test signal corresponding to each bit of the N-bit array capacitor included in the ADC is analyzed based on the actual full-rail swing of the ADC included in the radio frequency transceiver circuit, and then the mismatch test signal corresponding to each bit of the capacitor is tested and analyzed to determine the test result corresponding to each bit of the capacitor. This solves the problem of poor real-time performance of current capacitor mismatch test methods and provides a method for performing real-time capacitor mismatch testing, ensuring real-time testing efficiency and ensuring high real-time optimization for successive approximation ADCs.

[0253] Based on the above embodiments, the embodiments of the present application provide a capacitance mismatch test device, which can be applied to Figures 1-2 In the capacitance mismatch test method provided in the corresponding embodiment, refer to Figure 9 As shown, the capacitance mismatch test device 4 may include: a memory 41, a processor 42 and a communication bus 43; wherein:

[0254] Memory 41, used for storing executable instructions;

[0255] A communication bus 43 is used to implement communication between the processor 42 and the memory 41;

[0256] The processor 42 is used to execute the capacitance mismatch test program stored in the memory, so as to achieve the following Figures 1-2 The implementation process of the capacitance mismatch testing method provided in the corresponding embodiment will not be repeated here.

[0257] Based on the above embodiments, the embodiments of the present application provide a computer-readable storage medium, referred to as a storage medium, which stores one or more programs, which can be executed by one or more processors to implement the reference Figures 1-2 The implementation process of the capacitance mismatch testing method provided in the corresponding embodiment will not be repeated here.

[0258] Based on the above embodiments, the embodiments of the present application provide a computer program product, including a computer program, which implements the following when executed by the processor 42 of the capacitance mismatch test device 4: Figures 1-2 The implementation process of the capacitance mismatch testing method provided in the corresponding embodiment will not be repeated here.

[0259] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of hardware embodiments, software embodiments, or embodiments combining software and hardware. Furthermore, the present application may adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to magnetic disk storage and optical storage, etc.) containing computer-usable program code.

[0260] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the steps in the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0261] These computer program instructions may also be stored in a computer readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 a process or multiple processes and / or boxes Figure 1 The function specified in one or more boxes.

[0262] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operational steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing the instructions executed on the computer or other programmable device for implementing the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0263] The above description is merely a preferred embodiment of the present application and is not intended to limit the scope of protection of the present application.

Claims

1. A capacitance mismatch testing method, characterized in that: The method comprises: Measuring an output signal of a radio frequency transceiver circuit when a swing test signal is input thereto, and determining an actual full swing of an analog-to-digital converter (ADC) included in the radio frequency transceiver circuit based on the output signal; wherein the actual full swing of the ADC is the maximum output voltage corresponding to the ADC when operating under the swing test signal; Determining a mismatch test signal corresponding to each capacitor in the N-bit array capacitor included in the ADC based on the actual full-swing amplitude and the characteristics of each capacitor in the N-bit array capacitor included in the ADC; wherein, when the mismatch test signal corresponding to each capacitor is input into the radio frequency transceiver circuit, the corresponding capacitor and other capacitors associated with the corresponding capacitor are operated; A mismatch test signal corresponding to each capacitor is used to perform a test to obtain a test result corresponding to each capacitor; wherein the test result is used to indicate whether each capacitor is mismatched.

2. The method according to claim 1, characterized in that The measuring an output signal of a radio frequency transceiver circuit when a swing test signal is inputted, and determining an actual full swing of an analog-to-digital converter ADC included in the radio frequency transceiver circuit based on the output signal, comprises: Determining an input position of an input test signal set in the radio frequency transceiver circuit; determining a swing test signal based on the input position; The swing test signal is input at the input position, and the actual full swing is determined based on the output signal.

3. The method according to claim 2, characterized in that The step of determining a swing test signal based on the input position includes: If the input position is an analog signal input terminal of the ADC, determining that the swing test signal is composed of a bias voltage and a sinusoidal single-tone signal; wherein the signal frequency of the sinusoidal single-tone signal is within the analog bandwidth of the ADC; If the input position is the signal input end of the radio frequency transceiver circuit, it is determined that the swing test signal is composed of a local oscillator single-tone signal and a frequency deviation single-tone signal; wherein the signal frequency of the frequency deviation single-tone signal is the sum of the signal frequency of the local oscillator single-tone signal and the frequency deviation frequency, and the frequency deviation frequency is within the analog bandwidth of the ADC.

4. The method according to claim 3, characterized in that When the swing test signal is composed of the bias voltage and the sinusoidal single-tone signal, inputting the swing test signal at the input position and determining the actual full-rail amplitude based on the output signal include: When the bias voltage of the swing test signal is set to 0, the swing test signal is input to determine the first amplitude of the sinusoidal single-tone signal; wherein, when the amplitude of the sinusoidal single-tone signal is the first amplitude, the first output amplitude of the output signal of the RF transceiver circuit is less than or equal to the theoretical swing of the ADC signal, and the difference between the theoretical swing and the first output amplitude is within a first preset range; When the amplitude of the sinusoidal single-tone signal is set to the first amplitude, the swing test signal is input to determine a first bias sub-voltage and a second bias sub-voltage; wherein, when the amplitude of the sinusoidal single-tone signal is the first amplitude and the bias voltage is the first bias sub-voltage, the second output amplitude of the output signal of the RF transceiver circuit is less than or equal to the theoretical upper edge swing of the ADC signal, and the difference between the theoretical upper edge swing and the second output amplitude is within a second preset range; when the amplitude of the sinusoidal single-tone signal is the first amplitude and the bias voltage is the second bias sub-voltage, the third output amplitude of the output signal of the RF transceiver circuit is greater than or equal to the theoretical lower edge swing of the ADC signal, and the difference between the third output amplitude and the theoretical lower edge swing is within a third preset range; The sum of the first amplitude, the first bias sub-voltage, and the second bias sub-voltage is determined to obtain the actual full-rail amplitude.

5. The method according to claim 4, characterized in that The first amplitude is greater than or equal to 0.5*the theoretical full swing of the ADC, and less than or equal to 0.8*the theoretical full swing of the ADC.

6. The method according to claim 3, characterized in that When the swing test signal is composed of the local oscillator single-tone signal and the frequency-shifted single-tone signal, inputting the swing test signal at the input position and determining the actual full-rail amplitude based on the output signal include: The local oscillator single-tone signal is set to zero, the swing test signal is input, the amplitude of the frequency-deviation single-tone signal is adjusted, and the actual full swing of the frequency-deviation single-tone signal is determined; wherein, when the local oscillator single-tone signal is zero and the amplitude of the frequency-deviation single-tone signal is the actual full swing, the difference between the fourth output amplitude of the output signal of the RF transceiver circuit and the theoretical upper swing or the theoretical lower swing of the corresponding ADC signal is within a fourth preset range.

7. The method according to claim 6, characterized in that The actual full-rail amplitude is greater than or equal to 0.5*the theoretical full-rail amplitude of the ADC.

8. The method according to claim 2, characterized in that The determining, based on the actual full-swing amplitude and the characteristics of each bit of the N-bit array capacitor included in the ADC, a mismatch test signal corresponding to each bit of the N-bit array capacitor included in the ADC, comprises: Based on the actual full-rail amplitude, determining a first signal for operating all capacitors corresponding to the i-th position and the i+1-th position and thereafter; wherein i=1, 2, ..., m, i=1 corresponds to the maximum capacitance position in the N-bit array capacitor, i=2 corresponds to the second largest capacitance position in the N-bit array capacitor, and so on, and m is an integer less than or equal to N; Based on the actual full-rail amplitude, a second signal for operating all capacitors corresponding to the i-th capacitor and thereafter is determined; wherein the mismatch test signal corresponding to the i-th capacitor includes the first signal and the second signal.

9. The method according to claim 8, characterized in that When testing the mth capacitor, the analysis value corresponding to the parameter to be analyzed of the output signal of the RF transceiver circuit is greater than or equal to the first threshold; when testing the m+1th capacitor, the analysis value corresponding to the parameter to be analyzed is less than the first threshold.

10. The method according to claim 8, characterized in that In the case where the swing test signal is composed of a bias voltage and a sinusoidal single-tone signal, when n=1, the bias voltage included in the first signal is the sum of the first bias sub-voltage and the second bias sub-voltage; when n=2, 3, ..., m, the bias voltage included in the first signal is p*1 / 2 n-1 *The actual full swing, p is the value of X from 1 to 2 n-2 When , any value selected from the union of the calculated values ​​of (2X-1) and -(2X-1); When n=1, 2, ..., m, the amplitude of the sinusoidal tone signal included in the first signal and the second signal is the first preset coefficient*1 / 2 n *The actual full swing, the bias voltage included in the second signal is q*1 / 2 n *The actual full swing, q is X from 1 to 2 n-1 When , any value selected from the union of the calculated values ​​of (2X-1) and -(2X-1).

11. The method according to claim 10, characterized in that When n is greater than or equal to 2, before performing the test using the mismatch test signal corresponding to each capacitor and obtaining the test result corresponding to each capacitor, the method further includes: The amplitude of the input sinusoidal tone signal is the first preset coefficient * 1 / 2 n-1 *The actual full-rail and bias voltage are p*1 / 2 n-1 * the actual full-swing verification signal, and obtain a first analysis value of the parameter to be analyzed of the output signal of the radio frequency transceiver circuit.

12. The method according to claim 8, characterized in that When the swing test signal is composed of a local oscillator single-tone signal and a frequency-shifted single-tone signal, determining, based on the actual full swing, a second signal for operating all capacitors corresponding to and subsequent to the i-th bit includes: Based on the actual full-rail amplitude, determining a second amplitude of the frequency-shifted single-tone signal that causes all capacitors corresponding to the i-th position and thereafter to operate; wherein the second amplitude is smaller than the actual full-rail amplitude, and the second amplitude is adjusted according to a first preset step; The input amplitude is the frequency-deviation single-tone signal of the second amplitude, and the amplitude of the local oscillator single-tone signal is continuously increased according to the second preset step to determine the third amplitude of the local oscillator single-tone signal; wherein, the amplitude of the frequency-deviation single-tone signal of the second signal is the second amplitude, the amplitude of the local oscillator single-tone signal is the third amplitude, the signal upper edge of the output signal of the RF transceiver circuit remains unchanged, and the parameter change value of the parameter to be analyzed of the output signal of the RF transceiver circuit is greater than or equal to the second threshold for the first time.

13. The method according to claim 12, characterized in that The determining, based on the actual full rail, a first signal for operating all capacitors corresponding to the i-th bit and subsequent to the i+1-th bit, includes: When it is determined that the second signal is input, determining a first signal falling edge amplitude of an output signal of the radio frequency transceiver circuit; Determining that the amplitude of the frequency-deviation single-tone signal included in the first signal is a fourth amplitude; wherein the fourth amplitude is an amplitude corresponding to before determining that the amplitude of the frequency-deviation single-tone signal is the second amplitude; The frequency-deviation single-tone signal having an input amplitude of the fourth amplitude is input, and the amplitude of the local oscillator single-tone signal is continuously lowered according to a third preset step to determine a fifth amplitude of the local oscillator single-tone signal; wherein, when the amplitude of the frequency-deviation single-tone signal of the second signal is the fourth amplitude and the amplitude of the local oscillator single-tone signal is the fifth amplitude, the second signal lower edge amplitude of the output signal of the RF transceiver circuit is greater than or equal to the first signal lower edge amplitude, and the difference between the second signal lower edge amplitude and the first signal lower edge amplitude is within a fifth preset range.

14. The method according to any one of claims 8 to 13, characterized in that The testing is performed using the mismatch test signal corresponding to each capacitor to obtain a test result corresponding to each capacitor, including: Inputting a first signal corresponding to the i-th capacitor to the radio frequency transceiver circuit, and obtaining a second analysis value of the parameter to be analyzed of the output signal of the radio frequency transceiver circuit for the i-th capacitor; Inputting a second signal corresponding to the i-th capacitor into the radio frequency transceiver circuit to obtain a third analysis value of the parameter to be analyzed for the i-th capacitor; A test result of the i-th capacitor is obtained based on the second analysis value of the i-th capacitor and the third analysis value of the i-th capacitor.

15. The method according to claim 12, characterized in that The parameters to be analyzed include one or more of the following parameters: signal frequency deviation parameter, harmonic parameter, and spurious power parameter.

16. The method according to claim 1, wherein The RF transceiver circuit also includes a correction capacitor connected in parallel with the N-bit array capacitor, the capacitance value of the correction capacitor is greater than or equal to the theoretical capacitance value of the second largest capacitor in the N-bit array capacitor, and the capacitance value of the correction capacitor is less than or equal to the theoretical capacitance value of the largest capacitor in the N-bit array capacitor.

17. The method according to claim 16, characterized in that When the j-th capacitor is working, the method further includes: If it is determined that the actual capacitance value of the j-th capacitor is less than or equal to the theoretical capacitance value of the j-th capacitor, the correction capacitor is controlled not to be connected to the circuit, and a capacitor is selected to match the theoretical capacitance value of the j-th capacitor to operate as a target capacitance; where j=1, 2, ..., N, and the target capacitance includes at least the j-th capacitor; If it is determined that the actual capacitance value of the j-th capacitor is greater than the theoretical capacitance value of the j-th capacitor, at least the correction capacitor is controlled to be connected to the circuit for operation.

18. A capacitance mismatch test device, characterized in that: The device comprises: a measuring unit, a determining unit and a testing unit; wherein: The measuring unit is configured to measure an output signal of the radio frequency transceiver circuit when a swing test signal is input thereto, and determine an actual full swing of an analog-to-digital converter ADC included in the radio frequency transceiver circuit based on the output signal; wherein the actual full swing of the ADC is a maximum output voltage corresponding to the ADC when operating under the swing test signal; The determining unit is configured to determine a mismatch test signal corresponding to each capacitor in the N-bit array capacitor included in the ADC based on the actual full-swing amplitude and the characteristics of each capacitor in the N-bit array capacitor included in the ADC; wherein, when the mismatch test signal corresponding to each capacitor is input into the RF transceiver circuit, the corresponding capacitor and other capacitors associated with the corresponding capacitor are operated; The testing unit is used to perform testing using a mismatch test signal corresponding to each bit of the capacitor to obtain a test result corresponding to each bit of the capacitor; wherein the test result is used to indicate whether each bit of the capacitor is mismatched.

19. A capacitance mismatch test device, characterized in that: The device comprises: a memory, a processor and a communication bus; wherein: The memory is used to store executable instructions; The communication bus is used to realize the communication connection between the processor and the memory; The processor is configured to execute the capacitance mismatch test program stored in the memory to implement the steps of the capacitance mismatch test method according to any one of claims 1 to 17.

20. A storage medium, characterized in that The storage medium stores a capacitance mismatch test program, which, when executed by a processor, implements the steps of the capacitance mismatch test method according to any one of claims 1 to 17.

21. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the computer program implements the steps of the capacitance mismatch testing method according to any one of claims 1 to 17.

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