A readout circuit based on embedded CCIA and hybrid DSM

Abstract

The present invention discloses a readout circuit based on an embedded CCIA and a hybrid DSM. The readout circuit includes an embedded CCIA and a hybrid DSM. The embedded CCIA is embedded in the loop of the hybrid DSM, and the virtual ground point of the embedded CCIA serves as the summing node for the input differential signal and the feedback differential signal. The hybrid DSM includes an RC integrator, a first SC integrator, a second SC integrator, a 1.5-bit quantizer, and a feedback DAC. The RC integrator is a CT integrator, which reduces the bandwidth requirements for the CCIA; the SC integrator is a DT integrator, which reduces sensitivity to excessive loop delay and RC coefficient variations, reduces the impact of PVT, and improves the robustness of the ROIC. The hybrid DSM facilitates the implementation of a high-efficiency, high-precision readout circuit.

Description

Technical Field

[0001] The invention belongs to the field of readout integrated circuits, and in particular relates to a readout circuit based on an embedded CCIA and a hybrid DSM. Background Art

[0002] A readout integrated circuit (ROIC) is a key circuit module that converts a sensor's analog signal into a digital signal. High-precision ROICs feature low noise, low offset, and high energy efficiency, making them widely used in various sensor systems in consumer electronics, medical devices, industrial automation, and other fields for signal amplification and digitization. Because the input voltage signal is typically only a few tens of millivolts, an ROIC typically includes an instrumentation amplifier (IA) and a high-precision analog-to-digital converter (ADC), typically a Delta-Sigma modulator (DSM). The IA amplifies the input signal to a level compatible with the ADC's typical input range, while the ADC quantizes the analog signal into a digital output.

[0003] As the first stage of an ROIC, the IA defines the ROIC's input characteristics, such as input-referred noise, offset, gain accuracy, and input impedance. Furthermore, the ROIC's energy efficiency is often determined by its IA. Currently, a variety of IA structures exist, including switched-capacitor (SC) IAs, three-opamp (Opamp) IAs, current-feedback (CF) IAs, and resistive-feedback (RF) IAs. SCIAs utilize switched-capacitor technology to achieve high-precision and high-linearity signal amplification, but their energy efficiency is low due to noise aliasing and the need for additional, high-power input buffers to increase input impedance. A three-opamp IA consists of three operational amplifiers: the first op amp buffers the input signal, the second performs differential amplification, and the third provides the output stage. Although it has high input impedance, it requires two high-gain, low-noise amplifiers, resulting in high power consumption. CFIA uses current feedback technology to achieve signal amplification, but it still has two noise-critical input stages, which limits energy efficiency. RFIA achieves signal amplification by introducing a feedback resistor between the input and output. It has a simple structure and low power consumption, but there is a trade-off between noise and input impedance.

[0004] CCIA uses capacitors to isolate DC bias voltage while transmitting AC signals, and has good energy efficiency and gain accuracy. Reference [1] connects a discrete-time (DT) DSM after CCIA to achieve high-precision ROIC. The disadvantage of the ROIC in reference [1] is that the IA is outside the loop of the DSM, resulting in the gain error of the ROIC not only coming from the CCIA but also from the DSM. The high-precision ROIC is composed of two high-precision circuit modules, and the design complexity is high. In addition, the SC integrator of the DTDSM will introduce the problem of noise aliasing. In order to avoid the SC integrator integrating the output glitches of the CCIA, the output of the CCIA must be completely stable, which puts higher requirements on the bandwidth of the CCIA, thereby limiting the energy efficiency. Reference [2] connects a continuous-time (CT) DSM after CCIA. The CTDSM does not have the problem of noise aliasing. At the same time, it is easier for CCIA to drive resistive loads. The disadvantages of reference [2] are the same as those of reference [1]. Both require the design of a high-precision CCIA and a high-precision DSM to achieve high-precision ROIC, and the design complexity is high. In addition, CTDSM is more sensitive to excessive loop delay, resistor-and-capacitor (RC) coefficient changes, etc., and requires additional circuits for compensation and calibration. In order to avoid integrating the output glitch of CCIA, reference [2] connects the input of CTDSM to the common mode voltage through a dead-band (DB) switch when chopping occurs, and then connects it to the output of CCIA when the glitch disappears. On the one hand, since only the input signal is DBed, the gain of ROIC is reduced; on the other hand, since the sampling frequency of ROIC is much higher than the chopping frequency and DB frequency, non-uniform sampling will reduce the resolution of DSM, and complex technology is required to reconstruct the resolution. Reference [3] embeds CCIA in the CTDSM loop, reducing the design requirements for CCIA gain and linearity, and the gain accuracy of ROIC only depends on CCIA, simplifying the design complexity. However, in reference [3], in order to avoid causing quantization noise aliasing, the chopping frequency is set to half of the ROIC sampling frequency. The high chopping frequency will reduce the equivalent input impedance of ROIC, reduce the output impedance of the amplifier in CCIA, and the residual offset voltage will be relatively large. In addition, reference [3] uses a 6-bit quantizer to reduce DSM quantization noise and improve the dynamic range of DSM, but requires dynamic element matching (DEM) technology to improve the linearity of the multi-bit DAC, which adds additional circuits and power consumption. Reference [4] uses a return-to-zero (RZ) digital-to-analog converter (DAC) and a single-bit quantizer based on reference [3].By allowing the chopping to occur during the RZ phase of the DAC, quantization noise aliasing is avoided, and the chopping frequency can be much lower than the sampling frequency of the ROIC. A one-bit quantizer is inherently linear and does not require the use of techniques such as DEM. The disadvantage of the literature [4] is that the RZ DAC contributes noise during the entire cycle but only contributes signal during half the cycle, resulting in the effective input signal amplitude being reduced by half. Moreover, under process, voltage, and temperature (PVT) variations, the RZ DAC pulse width variation will reduce the gain accuracy of the ROIC. In addition, the one-bit quantizer will limit the quantization noise and dynamic range of the DSM, and at the same time place higher requirements on the output swing of the CCIA.

[0005] The references cited above are as follows:

[0006] [1] J.Jun, S.Park, J.Kang, and S.Kim, "A 22-bit Read-Out IC With 7-ppm INLand Sub-100-$\mu$Hz1 / $f$Corner for DC Measurement Systems," IEEE J.Solid-StateCircuits, vol.54, no.11, pp.3086–3096, Nov.2019, doi:10.1109 / JSSC.2019.2934817.

[0007] [2]H.Jiang, S.Nihtianov, and KAAMakinwa, "An Energy-Efficient 3.7-nV / $\surd$Hz Bridge Readout IC With a Stable Bridge Offset Compensation Scheme," IEEE J.Solid-State Circuits, vol.54, no.3, pp.856–864, Mar.2019, doi:10.1109 / JSSC.2018.2885556.

[0008] [3]H.Chandrakumar and D.Markovic, "A 15.2-ENOB 5-kHz BW 4.5-$\mu$WChopped CT$\Delta\Sigma$-ADC for Artifact-Tolerant Neural Recording FrontEnds," IEEE J.Solid-State Circuits, vol.53, no.12, pp.3470–3483, Dec.2018, doi:10.1109 / JSSC.2018.2876468.

[0009] [4]H.Jiang, C.Ligouras, S.Nihtianov, and KAAMakinwa, “A 4.5nV / √HzCapacitively Coupled Continuous-Time Sigma-Delta Modulator with an Energy-Efficient Chopping Scheme,” IEEE Solid-State Circuits Lett., vol.1, no.1, pp.18–21, Jan.2018, doi:10.1109 / LSSC.2018.2803447. Summary of the Invention

[0010] The purpose of the present invention is to solve the problems existing in the prior art and provide a readout circuit based on embedded CCIA and hybrid DSM.

[0011] The specific technical solutions adopted in the present invention are as follows:

[0012] A readout circuit based on an embedded CCIA and a hybrid DSM, comprising an embedded CCIA and a hybrid DSM;

[0013] The embedded CCIA is embedded in the loop of the hybrid DSM, and the virtual ground point of the embedded CCIA is used as a summing node for the input differential signal and the feedback differential signal;

[0014] The hybrid DSM includes an RC integrator, a first SC integrator, a second SC integrator, a 1.5-bit quantizer, and a feedback DAC;

[0015] The input differential signal of the readout circuit and the feedback differential signal output by the feedback DAC are input into the embedded CCIA for summing and amplification, and a first intermediate differential signal is output;

[0016] The first intermediate differential signal output by the embedded CCIA is connected to the DB control clock φ DB input the RC integrator together and output a second intermediate differential signal;

[0017] The second intermediate differential signal output by the RC integrator is input into the first SC integrator together with the two-phase non-overlapping clocks φ1 and φ2. The second intermediate differential signal is sampled and integrated under the control of the two-phase non-overlapping clocks φ1 and φ2 to output a third intermediate differential signal.

[0018] The third intermediate differential signal output by the first SC integrator is input to the second SC integrator together with the two-phase non-overlapping clocks φ1 and φ2. The second SC integrator samples and integrates the third intermediate differential signal under the control of the two-phase non-overlapping clocks φ1 and φ2. The second intermediate differential signal output by the RC integrator and the third intermediate differential signal output by the first SC integrator are summed to output a fourth intermediate differential signal.

[0019] The fourth intermediate differential signal output by the second SC integrator is input to a 1.5-bit quantizer together with the clock φ1. The 1.5-bit quantizer is controlled by the clock φ1 to quantize the fourth intermediate differential signal output by the second SC integrator, and finally obtains a 2-bit digital output signal. The 2-bit digital output signal serves as the final output of the readout circuit and controls the positive and negative of the differential signal output by the feedback DAC. The 2-bit digital output signal is coupled with the control clock φ1 of the RZ DAC. RZ , Chopper clock φ CHOP , DAC reference differential signal V REFP and V REFN They are input together into the feedback DAC to generate the feedback differential signal.

[0020] Preferably, in the timing diagram adopted by the readout circuit, the control clock φ of the DB switch is DB 、RZ DAC control clock φ RZ , Chopper clock φ CHOP , two-phase non-overlapping clocks φ1 and φ2 satisfy:

[0021] φ DB The frequency is equal to the ROIC sampling frequency, φ DB The pulse width is less than 50% of the ROIC sampling period;

[0022] φ RZ The frequency is equal to the ROIC sampling frequency, φ RZ The rising edge of φ DB After the rising edge, and φ RZ The pulse width is less than φ DB Pulse width;

[0023] φ CHOP The frequency is equal to 1 / 2 of the ROIC sampling frequencyN , where N is a positive integer; φ CHOP Both the rising and falling edges of RZ =1 period;

[0024] φ1 and φ2 do not overlap, and their frequencies are equal to the ROIC sampling frequency; φ DB =1 must occur during the period when φ1=1 or φ2=1.

[0025] Preferably, the φ DB The pulse width is 25% of the ROIC sampling period.

[0026] As a preference, the φ RZ The pulse width is φ DB 10% of the pulse width.

[0027] As a preference, N=3,φ CHOP The frequency is equal to 1 / 8 of the ROIC sampling frequency.

[0028] Preferably, the embedded CCIA includes a first input capacitor (C IN1 ), the second input capacitor (C IN2 ), the first feedback capacitor (C FB1 ), the second feedback capacitor (C FB2 ), a first chopping switch (CHOP1), a third chopping switch (CHOP3) and a first operational amplifier (OTA1);

[0029] The feedback DAC includes a first DAC capacitor (C DAC1 ), the second DAC capacitor (C DAC2 ) and a second chopping switch (CHOP2);

[0030] The input of the first chopper switch (CHOP1) is the external input differential signal V IN and V IP and chopper clock φ CHOP ;

[0031] The first input capacitor (C IN1 ) having a lower plate connected to an output terminal of a first chopping switch (CHOP1) and an upper plate connected to a positive input terminal of a first operational amplifier (OTA1);

[0032] The second input capacitor (C IN2 ) has a lower plate connected to the other output terminal of the first chopper switch (CHOP1), and an upper plate connected to the negative input terminal of the first operational amplifier (OTA1);

[0033] The positive output terminal and the negative output terminal of the first operational amplifier (OTA1) are respectively connected to two input terminals of a third chopping switch (CHOP3);

[0034] The first feedback capacitor (C FB1 ) is connected to the positive input terminal of the first operational amplifier (OTA1), and the lower plate is connected to an output terminal V of the third chopper switch (CHOP3) CCAN ;

[0035] The second feedback capacitor (C FB2 ) The upper plate is connected to the negative input terminal of the first operational amplifier (OTA1), and the lower plate is connected to the other output terminal V of the third chopper switch (CHOP3). CCAP ;

[0036] The first input of the second chopping switch (CHOP2) is the differential off-chip reference signal V REFP and V REFN The second input is the quantization result B1B0 of the 1.5-bit quantizer, and the third input is the control clock φ of the RZ DAC. RZ , the fourth input is the chopping clock φ CHOP ;

[0037] The first DAC capacitor (C DAC1 ) the upper plate is connected to the positive input terminal of the first operational amplifier (OTA1), and the lower plate is connected to the output of the second chopper switch (CHOP2);

[0038] The second DAC capacitor (C DAC2 ) The upper plate is connected to the negative input terminal of the first operational amplifier (OTA1), and the lower plate is connected to the output of the second chopper switch (CHOP2).

[0039] Preferably, the RC integrator circuit includes a first integrating resistor (R INT1 ), the second integrating resistor (R INT2 ), the first integrating capacitor (C INT1 ), the second integrating capacitor (C INT2 ), the first auxiliary resistor (R AUX1 ), the second auxiliary resistor (R AUX2 ), a second operational amplifier (OTA2), a first switch (S1), a second switch (S2), a third switch (S3), a fourth switch (S4), a fifth switch (S5), a sixth switch (S6), a seventh switch (S7), and an eighth switch (S8);

[0040] The first integrating resistor (R INT1 ) is connected to an output terminal V of the third chopper switch (CHOP3) CCAP , the other end is connected to the positive input terminal of the second operational amplifier (OTA2) through a seventh switch (S7);

[0041] The second integrating resistor (RINT2 ) is connected to the other output terminal V of the third chopper switch (CHOP3) CCAN , the other end is connected to the negative input terminal of the second operational amplifier (OTA2) through an eighth switch (S8);

[0042] The first integrating capacitor (C INT1 ) is connected to the positive input terminal of the second operational amplifier (OTA2), and the lower plate is connected to the negative output terminal V of the second operational amplifier (OTA2) INTN1 ;

[0043] The second integrating capacitor (C INT2 ) is connected to the negative input terminal of the second operational amplifier (OTA2), and the lower plate is connected to the positive output terminal V of the second operational amplifier (OTA2) INTP1 ;

[0044] The first auxiliary resistor (R AUX1 ) and the second auxiliary resistor (R AUX2 ) are connected to the external input signal VCM, the first auxiliary resistor (R AUX1 ) is connected to one end of the fourth switch (S4) and one end of the fifth switch (S5), and the second auxiliary resistor (R AUX2 ) is connected to one end of the second switch (S2) and one end of the sixth switch (S6), the other end of the second switch (S2) and the other end of the fourth switch (S4) are both connected to the off-chip input signal VCM, the other end of the fifth switch (S5) is connected to the negative input end of the second operational amplifier (OTA2), and the other end of the sixth switch (S6) is connected to the positive input end of the second operational amplifier (OTA2);

[0045] One end of the first switch (S1) and one end of the third switch (S3) are both connected to the off-chip input signal VCM, and the other end of the first switch (S1) is connected to the first integrating resistor (R INT1 ), the other end of the third switch (S3) is connected to the second integral resistor (R INT2 ) at the other end.

[0046] Preferably, the first SC integrator includes a first sampling capacitor (C S1 ), the second sampling capacitor (C S2 ), the third integrating capacitor (C INT3 ), the fourth integrating capacitor (C INT4 ), the third operational amplifier (OTA3), the ninth switch (S9), the tenth switch (S 10 ), the eleventh switch (S 11 ), the twelfth switch (S 12 ), the thirteenth switch (S 13 ), the fourteenth switch (S14 ), the fifteenth switch (S 15 );

[0047] One end of the ninth switch (S9) is connected to the positive output terminal V of the second operational amplifier (OTA2) INTP1 , the other end is connected to the eleventh switch (S 11 ) and the first sampling capacitor (C S1 )'s lower plate;

[0048] The tenth switch (S 10 ) is connected to the negative output terminal V of the second operational amplifier (OTA2) INTN1 , the other end is connected to the eleventh switch (S 11 ) and the other end of the second sampling capacitor (C S2 )'s lower plate;

[0049] The first sampling capacitor (C S1 ) is connected to the upper plate of the twelfth switch (S 12 ) and the fourteenth switch (S 14 ) at one end;

[0050] The second sampling capacitor (C S2 ) is connected to the upper plate of the thirteenth switch (S 13 ) and the fifteenth switch (S 15 ) at one end;

[0051] The twelfth switch (S 12 ) and the other end of the thirteenth switch (S 13 ) are connected to the off-chip input signal VCM;

[0052] The fourteenth switch (S 14 ) and the other end of the third integrating capacitor (C INT3 ) are connected to the positive input terminal of the third operational amplifier (OTA3);

[0053] The fifteenth switch (S 15 ) and the other end of the fourth integrating capacitor (C INT4 ) are connected to the negative input terminal of the third operational amplifier (OTA3);

[0054] The third integrating capacitor (C INT3 ) is connected to the negative output terminal V of the third operational amplifier (OTA3) INTN2 ;

[0055] The fourth integrating capacitor (C INT4 ) is connected to the positive output terminal V of the third operational amplifier (OTA3) INTP2 .

[0056] Preferably, the second SC integrator includes a first summing capacitor (C ADD1 ), the second summing capacitor (C ADD2 ), the third summing capacitor (C ADD3 ), the fourth summing capacitor (C ADD4 ), the third sampling capacitor (C S3 ), the fourth sampling capacitor (C S4 ), the fifth integrating capacitor (C INT5 ), the sixth integral capacitor (C INT6 ), the fourth operational amplifier (OTA4), the sixteenth switch (S 16 ), the seventeenth switch (S 17 ), the eighteenth switch (S 18 ), the nineteenth switch (S 19 ), the twentieth switch (S 20 ), the twenty-first switch (S 21 ) and the twenty-second switch (S 22 );

[0057] The sixteenth switch (S 16 ) is connected to the positive output terminal V of the third operational amplifier (OTA3) INTP2 , the other end is connected to the eighteenth switch (S 18 ) and the third sampling capacitor (C S3 )'s lower plate;

[0058] The seventeenth switch (S 17 ) is connected to the negative output terminal V of the third operational amplifier (OTA3) INTN2 , the other end is connected to the eighteenth switch (S 18 ) and the other end of the fourth sampling capacitor (C S4 )'s lower plate;

[0059] The third sampling capacitor (C S3 ) is connected to the upper plate of the twenty-first switch (S 21 ) and one end of the nineteenth switch (S 19 ) at one end;

[0060] The fourth sampling capacitor (C S4 ) is connected to the upper plate of the 22nd switch (S 22 ) one end and the twentieth switch (S 20 ) at one end;

[0061] The nineteenth switch (S 19 ) and the other end of the 20th switch (S 20 ) are connected to the off-chip input signal VCM;

[0062] The first summing capacitor (C ADD1 ) is connected to the positive output terminal V of the second operational amplifier (OTA2) INTP1 ;

[0063] The second summing capacitor (C ADD2 ) is connected to the positive output terminal V of the third operational amplifier (OTA3) INTP2 ;

[0064] The third summing capacitor (C ADD3 ) is connected to the negative output terminal V of the third operational amplifier (OTA3) INTN2 ;

[0065] The fourth summing capacitor (C ADD4 ) is connected to the negative output terminal V of the second operational amplifier (OTA2) INTN1 ;

[0066] The fifth integrating capacitor (C INT5 ) is connected to the negative output terminal V of the fourth operational amplifier (OTA4) INTN3 ;

[0067] The sixth integral capacitor (C INT6 ) is connected to the positive output terminal V of the fourth operational amplifier (OTA4) INTP3 ;

[0068] The positive input terminal of the fourth operational amplifier (OTA4) is also connected to the twenty-first switch (S 21 ) and the other end of the first summing capacitor (C ADD1 )'s upper plate, the second summing capacitor (C ADD2 ) and the fifth integrating capacitor (C INT5 ) of the upper plate;

[0069] The negative input terminal of the fourth operational amplifier (OTA4) is also connected to the twenty-second switch (S 22 ) and the other end of the third summing capacitor (C ADD3 )'s upper plate, the fourth summing capacitor (C ADD4 ) and the sixth integrating capacitor (C INT6 )'s upper plate.

[0070] Preferably, the 1.5-bit quantizer includes a first dual differential comparator (COMP1) and a second dual differential comparator (COMP2); the first differential input pair of the first dual differential comparator (COMP1) is the positive output terminal V of the fourth operational amplifier (OTA4) INTP3 signal and the negative output terminal V of the fourth operational amplifier (OTA4) INTN3 signal, the second differential input pair is the off-chip reference signal VCP and V CN , outputs a 1-bit digital signal B1; the first differential input pair of the second dual differential comparator (COMP1) is the positive output signal V of the fourth operational amplifier (OTA4) INTP3 and the negative output terminal V of the fourth operational amplifier (OTA4) INTN3 signal, the second differential input pair is the off-chip reference signal V CN and V CP , output 1-bit digital signal B0.

[0071] Compared with the prior art, the present invention has the following beneficial effects:

[0072] In the prior art, the DTDSM used has high requirements for CCIA bandwidth, which limits energy efficiency; while the CTDSM used is sensitive to excessive loop delay and changes in RC coefficients, requiring additional circuits for compensation and calibration. At the same time, the IA is outside the DSM loop, resulting in the system gain error of the ROIC not only coming from the IA but also from the DSM. The high-precision ROIC is composed of two high-precision circuit modules, and the design complexity is high. The present invention proposes a high-precision ROIC based on an embedded CCIA and a hybrid DSM, which reduces the design complexity of the ROIC at the system level. The CCIA and DSM are in the same loop, which reduces the requirements for CCIA gain and linearity. At the same time, the CCIA provides a gain stage, which reduces the requirements for DSM noise and offset. In addition, the gain accuracy of the ROIC depends only on the CCIA, which is conducive to the realization of a high-precision ROIC. This structure uses a hybrid DSM. The first-stage integrator is a CT integrator, which reduces the bandwidth requirement for CCIA. The subsequent integrator is a DT integrator, which reduces the sensitivity to excessive loop delay and RC coefficient changes, and can reduce the impact of PVT, improve the robustness of ROIC, and facilitate the realization of high-efficiency ROIC.

[0073] In the prior art, only the input signal is DBed. During the DB period, useful signal information is lost for several sampling clock cycles, reducing the effective gain of the ROIC. This invention proposes a solution that DBs both the input and feedback signals simultaneously. This solution, achieved through simple switching and timing, avoids the loss of useful signal information during the DB period and maintains the effective gain of the ROIC.

[0074] In existing technologies, the DB frequency is much lower than the ROIC sampling frequency. Non-uniform sampling reduces the resolution of the DSM and requires complex techniques to reconstruct the resolution. This invention proposes a solution that synchronizes the DB frequency with the ROIC sampling frequency, ensuring uniform sampling and avoiding the DSM resolution degradation caused by non-uniform sampling, thus reducing the difficulty of digital signal processing.

[0075] In the prior art, RZ DACs are used to suppress quantization noise aliasing, which limits the effective input signal amplitude. The present invention proposes a small pulse width RZ DAC to solve the quantization noise aliasing problem, reducing the effective input signal amplitude to within 10% with minimal additional circuit cost.

[0076] In the prior art, the variation of RZ DAC pulse width affects the system accuracy of ROIC. This invention proposes a solution that combines the pulse width of RZ DAC with DB technology, making the gain accuracy of ROIC independent of the variation of RZ DAC pulse width, thereby improving the gain accuracy of ROIC.

[0077] In existing technologies, multi-bit quantization requires techniques such as DEM to improve the linearity of multi-bit DACs, resulting in high design complexity. While single-bit quantizers offer high linearity, they are limited in other areas, such as quantization noise and dynamic range. This invention proposes using a 1.5-bit quantizer in the ROIC. The DAC has only one capacitor, resulting in inherent linearity. This reduces quantization noise, improves the ROIC dynamic range, and reduces the design requirements for CCIA output swing. BRIEF DESCRIPTION OF THE DRAWINGS

[0078] Figure 1 It is the overall structure of ROIC;

[0079] Figure 2 This is the timing diagram of ROIC;

[0080] Figure 3 This is the circuit diagram of the embedded CCIA and feedback DAC;

[0081] Figure 4 This is the circuit diagram of the RC integrator;

[0082] Figure 5 is the circuit diagram of the first SC integrator;

[0083] Figure 6 is the circuit diagram of the second SC integrator;

[0084] Figure 7 This is the circuit diagram of a 1.5-bit quantizer. DETAILED DESCRIPTION

[0085] In order to make the above-mentioned objects, features and advantages of the present invention more clearly understood, the specific embodiments of the present invention are described in detail below with reference to the accompanying drawings. In the following description, many specific details are set forth to facilitate a full understanding of the present invention. However, the present invention can be implemented in many other ways than those described herein, and those skilled in the art can make similar improvements without violating the connotation of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed below. The technical features in the various embodiments of the present invention can be combined accordingly without conflicting with each other.

[0086] In the description of the present invention, it should be understood that the terms "first" and "second" are used solely for descriptive purposes and are not to be construed as indicating or implying relative importance or implicitly specifying the number of technical features being described. Therefore, features defined as "first" or "second" may explicitly or implicitly include at least one of such features.

[0087] In a preferred embodiment of the present invention, a high-precision, high-energy-efficiency readout circuit (ROIC) based on an embedded CCIA and a hybrid DSM is provided, which reduces the design complexity of the ROIC at the system level. Specifically, the present invention proposes a solution for simultaneously DBing the input signal and the feedback signal to avoid reducing the effective gain of the ROIC; proposes setting the DB frequency to be the same as the ROIC sampling frequency to ensure uniform sampling, thereby simplifying the digital processing of the ROIC output signal; proposes a small-pulse-width RZ DAC, which allows the chopping frequency to be much lower than the ROIC sampling frequency, while suppressing quantization noise aliasing and avoiding a significant reduction in the effective input signal amplitude; proposes combining RZ pulse width variation with DB technology to prevent RZ DAC pulse width variation from affecting ROIC gain accuracy; and proposes a 1.5-bit quantizer, which avoids the use of multi-bit quantization, simplifies design complexity, and simultaneously breaks through the limitation of single-bit quantization, reduces quantization noise, and improves dynamic range.

[0088] like Figure 1As shown, the basic working principle of a readout circuit ROIC based on an embedded CCIA and a hybrid DSM in an embodiment of the present invention is demonstrated. The ROIC includes an embedded CCIA and a hybrid DSM. The embedded CCIA is embedded in the loop of the hybrid DSM, and the virtual ground point of the embedded CCIA is used as the summing node of the input differential signal and the feedback differential signal. The hybrid DSM includes an RC integrator (INT1), a first SC integrator (INT2), a second SC integrator (INT3), a 1.5-bit quantizer, and a feedback DAC. Among them, the RC integrator is a CT integrator, which reduces the bandwidth requirement for the CCIA; the SC integrator is a DT integrator, which reduces the sensitivity to excessive loop delay and RC coefficient changes, and can reduce the impact of PVT, thereby improving the robustness of the ROIC. The hybrid DSM is conducive to achieving high-efficiency and high-precision ROIC. The basic signal processing flow of each module in the embedded CCIA and hybrid DSM is as follows:

[0089] The input differential signal of the readout circuit and the feedback differential signal output by the feedback DAC are input into the embedded CCIA for summing and amplification, and a first intermediate differential signal is output;

[0090] The first intermediate differential signal output by the embedded CCIA is connected to the DB control clock φ DB input the RC integrator together and output a second intermediate differential signal;

[0091] The second intermediate differential signal output by the RC integrator (INT1) is input into the first SC integrator together with the two-phase non-overlapping clocks φ1 and φ2. The second intermediate differential signal is sampled and integrated under the control of the two-phase non-overlapping clocks φ1 and φ2 to output a third intermediate differential signal.

[0092] The third intermediate differential signal output by the first SC integrator is input to the second SC integrator together with the two-phase non-overlapping clocks φ1 and φ2. The second SC integrator samples and integrates the third intermediate differential signal under the control of the two-phase non-overlapping clocks φ1 and φ2. The second intermediate differential signal output by the RC integrator and the third intermediate differential signal output by the first SC integrator are summed to output a fourth intermediate differential signal.

[0093] The fourth intermediate differential signal output by the second SC integrator is input to a 1.5-bit quantizer together with the clock φ1. The 1.5-bit quantizer is controlled by the clock φ1 to quantize the fourth intermediate differential signal output by the second SC integrator, and finally obtains a 2-bit digital output signal. The 2-bit digital output signal serves as the final output of the readout circuit and controls the positive and negative of the differential signal output by the feedback DAC. The 2-bit digital output signal is coupled with the control clock φ1 of the RZ DAC. RZ , Chopper clock φ CHOP , DAC reference differential signal V REFP and VREFN They are input together into the feedback DAC to generate the feedback differential signal.

[0094] like Figure 2 As stated, demonstrated Figure 1 The timing diagram used by the ROIC. In this timing diagram, the control clock φ of the DB switch DB 、RZ DAC control clock φ RZ , Chopper clock φ CHOP , two-phase non-overlapping clocks φ1 and φ2 satisfy: φ DB The frequency is equal to the ROIC sampling frequency, φ DB The pulse width is 50% of the ROIC sampling period; RZ The frequency is equal to the ROIC sampling frequency, φ RZ The rising edge of φ DB After the rising edge, and φ RZ The pulse width is less than φ DB Pulse width; φ CHOP The frequency is equal to 1 / 2 of the ROIC sampling frequency N , where N is a positive integer; φ CHOP Both the rising and falling edges of RZ =1 period; φ1 and φ2 do not overlap, and their frequencies are equal to the ROIC sampling frequency; φ DB =1 must occur during the period when φ1=1 or φ2=1.

[0095] In an embodiment of the present invention, the parameters in the above timing diagram are further preferably: DB The pulse width is 25% of the ROIC sampling period; RZ The pulse width is φ DB 10% of pulse width; N = 3, φ CHOP The frequency is equal to 1 / 8 of the ROIC sampling frequency; DB =1 occurs during the period of φ1=1. Therefore, the control clock φ of the RZ DAC RZ , whose frequency is equal to the ROIC sampling frequency and whose pulse width is 10% of the sampling period, so the effective amplitude of the input signal is only reduced by 10%. RZ =1, the feedback signal of the DAC returns to zero, and the feedback signal does not contain high-frequency quantization noise; when φ RZ = 0, CCIA amplifies the input signal and feedback signal normally. CHOP is the chopping frequency, φ CHOP The rising and falling edges occur at φ RZ = 1, no quantization noise aliasing will be caused, so the chopping frequency can be much lower than the sampling frequency of ROIC.

[0096] For the control clock φ of the DB switchDB , when φ DB =1, the input of the RC integrator is connected to the common mode voltage VCM, and since the output signal V CCAP and V CCAN The input signal and the feedback signal are included in it, which is equivalent to DB the input signal and the feedback signal at the same time. When the CCIA output is completely stable, φ DB = 0, at this time the input signal of RC is the input signal and feedback signal after CCIA amplification, so the DB solution proposed in this invention does not reduce the effective gain of ROIC. In order to avoid losing useful information during DB, φ DB The frequency of is the same as the sampling frequency of ROIC, which also ensures uniform sampling, so no complex technology is needed to reconstruct the resolution of the output signal of ROIC. DB The pulse width is greater than φ RZ The pulse width, so even if φ RZ The pulse width of the φ is affected by PVT and changes. The signal seen by the RC integrator is still the input signal and feedback signal after CCIA amplification. RZ The change of pulse width will not affect the gain accuracy of ROIC. On the other hand, in order to ensure that the SC integrator can sample the correct output of the RC integrator, φ DB The pulse width needs to be less than 0.5 times the ROIC sampling period.

[0097] The two-phase, non-overlapping clocks φ1 and φ2 control the normal operation of the first and second SC integrators, with a frequency equal to the ROIC sampling frequency. φ1 also serves as the control clock for the quantizer. When the SC integrator output stabilizes, φ1 controls the quantizer to quantize the SC integrator output signal to produce a two-bit digital output, B1B0.

[0098] The above 1.5-bit quantizer will quantize the range ±(V CP -V CN ) is divided into three intervals, corresponding to the three quantized outputs B1B0 = 11, 01, and 00. The positive or negative nature of the DAC feedback signal is determined by B1B0. If B1B0 = 11, the DAC feedback negative reference signal (V REFN -V REFP ); If B1B0=01, DAC feedback is 0; If B1B0=00, DAC feedback is positive reference signal (V REFP -φ REFN ).

[0099] like Figure 3 The embedded CCIA includes a first input capacitor (C IN1 ), the second input capacitor (CIN2 ), the first feedback capacitor (C FB1 ), the second feedback capacitor (C FB2 ), a first chopping switch (CHOP1), a third chopping switch (CHOP3) and a first operational amplifier (OTA1); the feedback DAC includes a first DAC capacitor (C DAC1 ), the second DAC capacitor (C DAC2 ) and the second chopper switch (CHOP2). The specific structures of the two are as follows:

[0100] The input of the first chopper switch (CHOP1) is the external input differential signal V IN and V IP and chopper clock φ CHOP ;

[0101] The first input capacitor (C IN1 ) is connected to an output terminal of the first chopper switch (CHOP1), and the upper plate is connected to the positive input terminal V of the first operational amplifier (OTA1). CCAP ;

[0102] The second input capacitor (C IN2 ) is connected to the other output terminal of the first chopper switch (CHOP1), and the upper plate is connected to the negative input terminal V of the first operational amplifier (OTA1). CCAN ;

[0103] The positive output terminal and the negative output terminal of the first operational amplifier (OTA1) are respectively connected to two input terminals of a third chopping switch (CHOP3);

[0104] The first feedback capacitor (C FB1 ) is connected to the positive input terminal of the first operational amplifier (OTA1), and the lower plate is connected to an output terminal V of the third chopper switch (CHOP3) CCAN ;

[0105] The second feedback capacitor (C FB2 ) The upper plate is connected to the negative input terminal of the first operational amplifier (OTA1), and the lower plate is connected to the other output terminal V of the third chopper switch (CHOP3). CCAP ;

[0106] The first input of the second chopping switch (CHOP2) is the differential off-chip reference signal V REFP and V REFN The second input is the quantization result B1B0 of the 1.5-bit quantizer, and the third input is the control clock φ of the RZ DAC. RZ , the fourth input is the chopping clock φ CHOP ;

[0107] The first DAC capacitor (C DAC1 ) the upper plate is connected to the positive input terminal of the first operational amplifier (OTA1), and the lower plate is connected to the output of the second chopper switch (CHOP2);

[0108] The second DAC capacitor (C DAC2 ) The upper plate is connected to the negative input terminal of the first operational amplifier (OTA1), and the lower plate is connected to the output of the second chopper switch (CHOP2).

[0109] Therefore, the first operational amplifier (OTA1) has a total of six inputs, the first input being the first input capacitor (C IN1 ) of the upper plate signal, and the second input is the second input capacitor (C IN2 ) of the upper plate signal, and the third input is the first feedback capacitor (C FB1 ) of the upper plate signal, and the fourth input is the second feedback capacitor (C FB2 ) of the upper plate signal, and the fifth input is the first DAC capacitor (C DAC1 ) of the upper plate signal, and the sixth input is the second DAC capacitor (C DAC2 )'s upper plate signal.

[0110] Continue to see Figure 3 As shown in the circuit module, the virtual ground of CCIA is used as the summing node of the input signal and the feedback DAC signal. The output signal of CCIA is: V CCAP -V CCAN =A CCIA ·[(V IP -V IN )±(V REFP -V REFN )], where A CCIA is the CCIA gain, (V CCAP -V CCAN ) is the differential output signal of CCIA, (V IP -V IN ) is the differential input signal, V REFP and V REFN is the reference signal of DAC. RZ =1, the feedback signal of the DAC returns to zero. At this time, the feedback signal does not contain high-frequency quantization noise. RZ The pulse width is only 10% of the sampling period, so the effective input signal amplitude is only reduced by 10%; when φ RZ =0, the DAC feedback signal ±(V REFP -V REFN ) is controlled by the digital output signal of ROIC. If B1B0=11, DAC feedback negative reference signal (V REFN -V REFP); If B1B0=01, DAC feedback is 0; If B1B0=00, DAC feedback is positive reference signal (V REFP -V REFN ).exist Figure 3 In, φ CHOP is the chopping clock, φ CHOP The rising and falling edges occur at φ RZ = 1, no quantization noise aliasing will be caused, so the chopping frequency can be much lower than the sampling frequency of ROIC.

[0111] like Figure 4 As shown in FIG, a schematic diagram of an RC integrator circuit is shown. The RC integrator circuit includes a first integrating resistor (R INT1 ), the second integrating resistor (R INT2 ), the first integrating capacitor (C INT1 ), the second integrating capacitor (C INT2 ), the first auxiliary resistor (R AUX1 ), the second auxiliary resistor (R AUX2 ), second operational amplifier (OTA2), first switch (S1), second switch (S2), third switch (S3), fourth switch (S4), fifth switch (S5), sixth switch (S6), seventh switch (S7), and eighth switch (S8), the specific connection method is as follows:

[0112] The first integrating resistor (R INT1 ) is connected to an output terminal V of the third chopper switch (CHOP3) CCAP , the other end is connected to the positive input terminal of the second operational amplifier (OTA2) through a seventh switch (S7);

[0113] The second integrating resistor (R INT2 ) is connected to the other output terminal V of the third chopper switch (CHOP3) CCAN , the other end is connected to the negative input terminal of the second operational amplifier (OTA2) through an eighth switch (S8);

[0114] The first integrating capacitor (C INT1 ) is connected to the positive input terminal of the second operational amplifier (OTA2), and the lower plate is connected to the negative output terminal V of the second operational amplifier (OTA2) INTN1 ;

[0115] The second integrating capacitor (C INT2 ) is connected to the negative input terminal of the second operational amplifier (OTA2), and the lower plate is connected to the positive output terminal V of the second operational amplifier (OTA2) INTP1 ;

[0116] The first auxiliary resistor (R AUX1) and the second auxiliary resistor (R AUX2 ) are connected to the external input signal VCM, the first auxiliary resistor (R AUX1 ) is connected to one end of the fourth switch (S4) and one end of the fifth switch (S5), and the second auxiliary resistor (R AUX2 ) is connected to one end of the second switch (S2) and one end of the sixth switch (S6), the other end of the second switch (S2) and the other end of the fourth switch (S4) are both connected to the off-chip input signal VCM, the other end of the fifth switch (S5) is connected to the negative input end of the second operational amplifier (OTA2), and the other end of the sixth switch (S6) is connected to the positive input end of the second operational amplifier (OTA2);

[0117] One end of the first switch (S1) and one end of the third switch (S3) are both connected to the off-chip input signal VCM, and the other end of the first switch (S1) is connected to the first integrating resistor (R INT1 ), the other end of the third switch (S3) is connected to the second integral resistor (R INT2 ) at the other end.

[0118] Therefore, the second operational amplifier (OTA2) has a total of six inputs, the first input is the output of the fifth switch (S5), the second input is the output of the sixth switch (S6), the third input is the output of the seventh switch (S7), the fourth input is the output of the eighth switch (S8), and the fifth input is the output of the first integrating capacitor (C INT1 ) of the upper plate signal, and the sixth input is the second integrating capacitor (C INT2 )'s upper plate signal.

[0119] Continue to see Figure 4 As shown, in this circuit module, when φ DB =1, S 1,3,5,6 conduction, S 2,4,7,8 When the CCIA is turned off, the input of the RC integrator is connected to the common mode voltage VCM, and the load resistor of the CCIA is also connected to VCM. Since the output signal of the CCIA contains both the input signal and the feedback signal, it is equivalent to DB the input signal and the feedback signal at the same time. When the CCIA output is completely stable, φ DB =0, S 1,3,5,6 Shutdown, S 2,4,7,8 The input signal of the RC integrator is the input signal and feedback signal after CCIA amplification. Therefore, the DB scheme proposed in this invention does not reduce the effective gain of ROIC. In order to avoid losing useful information during DB, φ DB The frequency of is the same as the sampling frequency of ROIC, which also ensures uniform sampling, so no complex technology is needed to reconstruct the resolution of the output signal of ROIC.DB The pulse width is greater than φ RZ The pulse width, so even if φ RZ The pulse width of the φ is affected by PVT and changes. The signal seen by the RC integrator is still the input signal and feedback signal after CCIA amplification. RZ Pulse width changes do not affect the gain accuracy of the ROIC.

[0120] like Figure 5 As shown in FIG, a schematic diagram of a first SC integrator circuit is shown. The first SC integrator includes a first sampling capacitor (C S1 ), the second sampling capacitor (C S2 ), the third integrating capacitor (C INT3 ), the fourth integrating capacitor (C INT4 ), the third operational amplifier (OTA3), the ninth switch (S9), the tenth switch (S 10 ), the eleventh switch (S 11 ), the twelfth switch (S 12 ), the thirteenth switch (S 13 ), the fourteenth switch (S 14 ), the fifteenth switch (S 15 ), the specific connection method is as follows:

[0121] One end of the ninth switch (S9) is connected to the positive output terminal V of the second operational amplifier (OTA2) INTP1 , the other end is connected to the eleventh switch (S 11 ) and the first sampling capacitor (C S1 ) of the lower plate, the tenth switch (S 10 ) is connected to the negative output terminal V of the second operational amplifier (OTA2) INTN1 , the other end is connected to the eleventh switch (S 11 ) and the other end of the second sampling capacitor (C S2 ) of the lower plate, the first sampling capacitor (C S1 ) is connected to the upper plate of the twelfth switch (S 12 ) and the fourteenth switch (S 14 ) one end, the second sampling capacitor (C S2 ) is connected to the upper plate of the thirteenth switch (S 13 ) and the fifteenth switch (S 15 ) one end, the twelfth switch (S 12 ) and the other end of the thirteenth switch (S 13 ) are connected to the external input signal VCM, the fourteenth switch (S 14 ) and the other end of the third integrating capacitor (C INT3) are connected to the positive input terminal of the third operational amplifier (OTA3), the fifteenth switch (S 15 ) and the other end of the fourth integrating capacitor (C INT4 ) are connected to the negative input terminal of the third operational amplifier (OTA3), and the third integrating capacitor (C INT3 ) is connected to the negative output terminal V of the third operational amplifier (OTA3) INTN2 , the fourth integrating capacitor (C INT4 ) is connected to the positive output terminal V of the third operational amplifier (OTA3) INTP2 .

[0122] Therefore, the third operational amplifier (OTA3) comprises four inputs in total, the first input being the fourteenth switch (S 14 ) output, the second input is the fifteenth switch (S 15 ) output, the third input is the third integrating capacitor (C INT3 ) of the upper plate signal, the fourth input is the fourth integrating capacitor (C INT4 )'s upper plate signal.

[0123] Continue to see Figure 5 As shown, the integration coefficient of the first SC integrator is determined by the capacitance ratio C S1(2) / C INT3(4) Implementation, good robustness. Figure 2 The two-phase non-overlapping clocks φ1 and φ2 in can be used to control the normal operation of the first SC integrator. When φ1 = 1, the switch S 9,10,12,13 On, switch S 11,14,15 When φ2=1, the switch S 9,10,12,13 Turn off, switch S 11,14,15 The first SC integrator integrates the first SC and the whole process repeats in a cycle.

[0124] like Figure 6 FIG. 1 shows a schematic diagram of a second SC integrator circuit. The second SC integrator includes a first summing capacitor (C ADD1 ), the second summing capacitor (C ADD2 ), the third summing capacitor (C ADD3 ), the fourth summing capacitor (C ADD4 ), the third sampling capacitor (C S3 ), the fourth sampling capacitor (C S4 ), the fifth integrating capacitor (C INT5 ), the sixth integral capacitor (C INT6 ), the fourth operational amplifier (OTA4), the sixteenth switch (S 16 ), the seventeenth switch (S 17 ), the eighteenth switch (S18 ), the nineteenth switch (S 19 ), the twentieth switch (S 20 ), the twenty-first switch (S 21 ) and the twenty-second switch (S 22 ), the specific connection method is as follows:

[0125] The sixteenth switch (S 16 ) is connected to the positive output terminal V of the third operational amplifier (OTA3) INTP2 , the other end is connected to the eighteenth switch (S 18 ) and the third sampling capacitor (C S3 ) of the lower plate, the seventeenth switch (S 17 ) is connected to the negative output terminal V of the third operational amplifier (OTA3) INTN2 , the other end is connected to the eighteenth switch (S 18 ) and the other end of the fourth sampling capacitor (C S4 ) of the lower plate, the third sampling capacitor (C S3 ) is connected to the upper plate of the twenty-first switch (S 21 ) and one end of the nineteenth switch (S 19 ) one end, the fourth sampling capacitor (C S4 ) is connected to the upper plate of the 22nd switch (S 22 ) one end and the twentieth switch (S 20 ) one end, the nineteenth switch (S 19 ) and the other end of the 20th switch (S 20 ) are connected to the off-chip input signal VCM, the first summing capacitor (C ADD1 ) is connected to the positive output terminal V of the second operational amplifier (OTA2) INTP1 , the second summing capacitor (C ADD2 ) is connected to the positive output terminal V of the third operational amplifier (OTA3) INTP2 , the third summing capacitor (C ADD3 ) is connected to the negative output terminal V of the third operational amplifier (OTA3) INTN2 , the fourth summing capacitor (C ADD4 ) is connected to the negative output terminal V of the second operational amplifier (OTA2) INTN1 , the fifth integrating capacitor (C INT5 ) is connected to the negative output terminal V of the fourth operational amplifier (OTA4) INTN3 , the sixth integral capacitor (C INT6 ) is connected to the positive output terminal V of the fourth operational amplifier (OTA4) INTP3 The positive input terminal of the fourth operational amplifier (OTA4) is also connected to the twenty-first switch (S21 ) and the other end of the first summing capacitor (C ADD1 )'s upper plate, the second summing capacitor (C ADD2 ) and the fifth integrating capacitor (C INT5 ) of the upper plate, the negative input terminal of the fourth operational amplifier (OTA4) is connected to the twenty-second switch (S 22 ) and the other end of the third summing capacitor (C ADD3 )'s upper plate, the fourth summing capacitor (C ADD4 ) and the sixth integrating capacitor (C INT6 )'s upper plate.

[0126] Continue to see Figure 6 As shown, the second SC integrator can sample and integrate the output of the first SC integrator and sum the output of the RC integrator and the output of the first integrator. The integration coefficient of the first SC integrator is determined by the capacitance ratio C S3(4) / C INT5(6) The summation coefficient of the RC integrator is determined by the capacitance ratio C ADD1(4) / C INT5(6) The summation coefficient of the first SC integrator is determined by the capacitance ratio C ADD2(3) / C INT5(6) accomplish. Figure 2 Where φ1 and φ2 are two-phase non-overlapping clocks used to control the normal operation of the second SC integrator. When φ1 = 1, the switch S 16,17,19,20 On, switch S 18,21,22 When φ2=1, the switch S 16,17,19,20 Turn off, switch S 18,21,22 The second SC integrator is turned on and integrates. At the same time, the DSM feedforward summation is completed in the third-stage integrator by reusing the operational amplifier (OTA4) in the second SC integrator. The entire process is cyclical. 1D and φ 2D They are the delayed clocks of φ1 and φ2, respectively, used to reduce charge injection.

[0127] like Figure 7 FIG1 shows a schematic diagram of a 1.5-bit quantizer. The 1.5-bit quantizer includes a first dual differential comparator (COMP1) and a second dual differential comparator (COMP2); the first differential input pair of the first dual differential comparator (COMP1) is the positive output terminal V of the fourth operational amplifier (OTA4). INTP3 signal and the negative output terminal V of the fourth operational amplifier (OTA4) INTP3 signal, the second differential input pair is the off-chip reference signal V CP and V CN, outputs a 1-bit digital signal B1; the first differential input pair of the second dual differential comparator (COMP1) is the positive output signal V of the fourth operational amplifier (OTA4) INTP3 and the negative output terminal V of the fourth operational amplifier (OTA4) INTP3 signal, the second differential input pair is the off-chip reference signal V CN and V CP , output 1-bit digital signal B0.

[0128] Continue to see Figure 7 As shown, the control clock of the 1.5-bit quantizer is φ1. When the output of the SC integrator is stable, φ1 controls the quantizer to quantize the output signal of the second SC integrator to obtain a 2-bit digital output B1B0. The 1.5-bit quantizer divides the quantization range into three intervals, corresponding to the three quantized outputs B1B0 = 11, 01, and 00 respectively. If V INTP3 >V CP , V INTN3 <V CN ,B1B0=11;if V INTN3 >V CP , V INTP3 <V CN ,B1B0=00; otherwise, B1B0=01.

[0129] In summary, a high-precision ROIC based on an embedded CCIA and a hybrid DSM is proposed, which reduces ROIC design complexity at the system level. The CCIA and DSM are located in the same loop, reducing the CCIA gain and linearity requirements. The CCIA also provides a gain stage, reducing the DSM noise and offset requirements. Furthermore, the ROIC's gain accuracy depends solely on the CCIA, facilitating the implementation of a high-precision ROIC. This architecture utilizes a hybrid DSM, with a CT integrator as the first-stage integrator, reducing the CCIA's bandwidth requirements. The subsequent integrator is a DT integrator, reducing sensitivity to excessive loop delay and RC coefficient variations. It also mitigates the effects of PVT, improving the ROIC's robustness and facilitating the implementation of a highly energy-efficient ROIC.

[0130] The solution of DBing the input signal and the feedback signal simultaneously proposed in the present invention can be realized by simple switches and timing, thereby avoiding the loss of useful signal information during the DB period and maintaining the effective gain of the ROIC.

[0131] The solution proposed in the present invention of synchronizing the DB frequency with the ROIC sampling frequency ensures uniform sampling, avoids the problem of reduced DSM resolution caused by non-uniform sampling, and reduces the difficulty of digital signal processing.

[0132] The small pulse width RZ DAC proposed in the present invention is used to solve the quantization noise aliasing problem, so that the chopping frequency can be much lower than the ROIC sampling frequency, and the effective input signal amplitude is reduced within 10%, with extremely low additional circuit cost.

[0133] The solution proposed in the present invention combines the pulse width of the RZ DAC with the DB technology, so that the gain accuracy of the ROIC is independent of the change of the pulse width of the RZ DAC, thereby improving the gain accuracy of the ROIC.

[0134] The present invention proposes using a 1.5-bit quantizer in the ROIC and having only one capacitor in the DAC, which has inherent linearity, reduces quantization noise, improves the ROIC dynamic range, and reduces the design requirements for the CCIA output swing.

[0135] The embodiment described above is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Persons skilled in the art may make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, any technical solution obtained by equivalent substitution or equivalent transformation falls within the scope of protection of the present invention.

Claims

1. A readout circuit based on embedded CCIA and hybrid DSM, characterized in that: Including embedded CCIA and hybrid DSM; The embedded CCIA is embedded in the loop of the hybrid DSM, and the virtual ground point of the embedded CCIA is used as a summing node for the input differential signal and the feedback differential signal; The hybrid DSM includes an RC integrator, a first SC integrator, a second SC integrator, a 1.5-bit quantizer, and a feedback DAC; The input differential signal of the readout circuit and the feedback differential signal output by the feedback DAC are input into the embedded CCIA for summing and amplification, and a first intermediate differential signal is output; The first intermediate differential signal output by the embedded CCIA is connected to the DB control clock input the RC integrator together and output a second intermediate differential signal; The second intermediate differential signal output by the RC integrator is the same as the two-phase non-overlapping clock and input to the first SC integrator, in two-phase non-overlapping clock and sampling and integrating the second intermediate differential signal under the control of , and outputting a third intermediate differential signal; The third intermediate differential signal output by the first SC integrator is the same as the two-phase non-overlapping clock and input to the second SC integrator, with two non-overlapping clocks and sampling and integrating the third intermediate differential signal under the control of , and summing the second intermediate differential signal output by the RC integrator and the third intermediate differential signal output by the first SC integrator to output a fourth intermediate differential signal; The fourth intermediate differential signal output by the second SC integrator is together with the input of the 1.5-bit quantizer, which is clocked by The 1.5-bit quantizer is controlled to quantize the fourth intermediate differential signal output by the second SC integrator, and finally a 2-bit digital output signal is obtained; the 2-bit digital output signal is used as the final output of the readout circuit, and the positive and negative of the differential signal output by the feedback DAC is controlled at the same time; the 2-bit digital output signal is synchronized with the control clock of the RZ DAC. , Chopper Clock , DAC reference differential signal and Input them together into the feedback DAC to generate a feedback differential signal; The embedded CCIA includes a first input capacitor ( )、Second input capacitor( ), the first feedback capacitor ( )、Second feedback capacitor( ), a first chopping switch (CHOP1), a third chopping switch (CHOP3) and a first operational amplifier (OTA1); The feedback DAC includes a first DAC capacitor ( ), the second DAC capacitor ( ) and the second chopping switch (CHOP2); The input of the first chopping switch (CHOP1) is the external input differential signal and and chopper clock ; The first input capacitor ( ) is connected to an output terminal of a first chopper switch (CHOP1), and its upper plate is connected to a positive input terminal of a first operational amplifier (OTA1); The second input capacitor ( ) is connected to the other output terminal of the first chopper switch (CHOP1), and the upper plate is connected to the negative input terminal of the first operational amplifier (OTA1); A positive output terminal and a negative output terminal of the first operational amplifier (OTA1) are respectively connected to two input terminals of a third chopping switch (CHOP3); The first feedback capacitor ( ) is connected to the positive input of the first operational amplifier (OTA1), and the lower plate is connected to an output of the third chopper switch (CHOP3). ; The second feedback capacitor ( ) The upper plate is connected to the negative input of the first operational amplifier (OTA1), and the lower plate is connected to the other output of the third chopper switch (CHOP3) ; The first input of the second chopping switch (CHOP2) is a differential off-chip reference signal. and The second input is the quantization result of the 1.5-bit quantizer. , the third input is the control clock of RZ DAC , the fourth input is the chopping clock ; First DAC capacitor ( ) The upper plate is connected to the positive input of the first operational amplifier (OTA1), and the lower plate is connected to the output of the second chopper switch (CHOP2); Second DAC capacitor ( ) The upper plate is connected to the negative input of the first operational amplifier (OTA1), and the lower plate is connected to the output of the second chopper switch (CHOP2).

2. The readout circuit based on embedded CCIA and hybrid DSM according to claim 1, wherein: In the timing diagram of the readout circuit, the control clock of the DB switch is , RZ DAC control clock , Chopper Clock , two-phase non-overlapping clock and satisfy: The frequency is equal to the ROIC sampling frequency, The pulse width is less than 50% of the ROIC sampling period; The frequency is equal to the ROIC sampling frequency, The rising edge must occur at After the rising edge, and The pulse width is less than Pulse width; The frequency is equal to the ROIC sampling frequency , where N is a positive integer; Both the rising and falling edges must occur at period; and They do not overlap with each other, and their frequencies are equal to the ROIC sampling frequency; =1 must occur in During or period.

3. The readout circuit based on embedded CCIA and hybrid DSM according to claim 2, characterized in that: described The pulse width is 25% of the ROIC sampling period.

4. The readout circuit based on embedded CCIA and hybrid DSM according to claim 2, wherein: described The pulse width is 10% of the pulse width.

5. The readout circuit based on embedded CCIA and hybrid DSM according to claim 2, wherein: Said N=3, The frequency is equal to 1 / 8 of the ROIC sampling frequency.

6. The readout circuit based on embedded CCIA and hybrid DSM according to claim 1, wherein: The RC integrator circuit includes a first integrating resistor ( )、Second integration resistor( )、the first integrating capacitor( )、the second integrating capacitor( )、First auxiliary resistor( )、Second auxiliary resistor( ), the second operational amplifier (OTA2), the first switch ( ), the second switch ( )、The third switch( )、The fourth switch( )、The fifth switch( )、The sixth switch( )、The seventh switch( )、Eighth switch( ); The first integrating resistor ( ) is connected to one output terminal of the third chopper switch (CHOP3) , the other end passes through the seventh switch ( ) is connected to the positive input terminal of the second operational amplifier (OTA2); The second integrating resistor ( ) is connected to the other output terminal of the third chopper switch (CHOP3) , the other end passes through the eighth switch ( ) is connected to the negative input terminal of the second operational amplifier (OTA2); The first integrating capacitor ( ) is connected to the positive input terminal of the second operational amplifier (OTA2), and the lower plate is connected to the negative output terminal of the second operational amplifier (OTA2) ; The second integrating capacitor ( ) is connected to the negative input terminal of the second operational amplifier (OTA2), and the lower plate is connected to the positive output terminal of the second operational amplifier (OTA2) ; The first auxiliary resistor ( ) one end of the second auxiliary resistor ( ) are connected to the external input signal VCM, the first auxiliary resistor ( ) is connected to the other end of the fourth switch ( ) one end and the fifth switch ( ) one end, the second auxiliary resistor ( ) is connected to the other end of the second switch ( ) one end and the sixth switch ( ) one end, the second switch ( ) and the other end of the fourth switch ( ) are connected to the external input signal VCM, the fifth switch ( ) is connected to the negative input terminal of the second operational amplifier (OTA2), and the sixth switch ( ) is connected to the positive input terminal of the second operational amplifier (OTA2); First switch ( ) one end and the third switch ( ) are connected to the external input signal VCM, the first switch ( ) is connected to the other end of the first integrating resistor ( ) on the other end, the third switch ( ) is connected to the other end of the second integrating resistor ( ) on the other end.

7. The readout circuit based on embedded CCIA and hybrid DSM according to claim 1, wherein: The first SC integrator includes a first sampling capacitor ( )、the second sampling capacitor( )、the third integrating capacitor( )、the fourth integrating capacitor( ), the third operational amplifier (OTA3), the ninth switch ( )、The tenth switch( )、The eleventh switch ( )、The twelfth switch( )、The thirteenth switch( )、The fourteenth switch( )、The fifteenth switch( ); Ninth switch ( ) is connected to the positive output terminal of the second operational amplifier (OTA2) , the other end is connected to the eleventh switch ( ) and one end of the first sampling capacitor ( ) of the lower plate; The tenth switch ( ) is connected to the negative output terminal of the second operational amplifier (OTA2) , the other end is connected to the eleventh switch ( ) and the other end of the second sampling capacitor ( ) of the lower plate; The first sampling capacitor ( ) is connected to the upper plate of the twelfth switch ( ) and one end of the fourteenth switch ( ) at one end; The second sampling capacitor ( ) is connected to the upper plate of the thirteenth switch ( ) one end and the fifteenth switch ( ) at one end; 12th switch ( ) and the other end of the thirteenth switch ( ) are connected to the off-chip input signal VCM; The fourteenth switch ( ) and the other end of the third integrating capacitor ( ) are connected to the positive input terminal of the third operational amplifier (OTA3); The fifteenth switch ( ) and the other end of the fourth integrating capacitor ( ) are connected to the negative input terminal of the third operational amplifier (OTA3); The third integrating capacitor ( ) is connected to the negative output terminal of the third operational amplifier (OTA3) ; The fourth integrating capacitor ( ) is connected to the positive output terminal of the third operational amplifier (OTA3) .

8. The readout circuit based on embedded CCIA and hybrid DSM according to claim 1, wherein: The second SC integrator includes a first summing capacitor ( ), the second summing capacitor ( ), the third summing capacitor ( ), the fourth summing capacitor ( )、the third sampling capacitor( )、the fourth sampling capacitor( )、The fifth integrating capacitor( )、the sixth integral capacitor( ), the fourth operational amplifier (OTA4), the sixteenth switch ( )、Switch 17( )、Eighteenth switch( )、Nineteenth switch( )、The 20th switch( )、Twenty-first switch( ) and the twenty-second switch ( ); 16th switch ( ) is connected to the positive output terminal of the third operational amplifier (OTA3) , the other end is connected to the eighteenth switch ( ) one end and the third sampling capacitor ( ) of the lower plate; Seventeenth switch ( ) is connected to the negative output terminal of the third operational amplifier (OTA3) , the other end is connected to the eighteenth switch ( ) and the other end of the fourth sampling capacitor ( ) of the lower plate; The third sampling capacitor ( ) is connected to the upper plate of the twenty-first switch ( ) and one end of the nineteenth switch ( ) at one end; The fourth sampling capacitor ( ) is connected to the upper plate of the 22nd switch ( ) one end and the twentieth switch ( ) at one end; 19th switch ( ) and the other end of the 20th switch ( ) are connected to the off-chip input signal VCM; The first summing capacitor ( ) is connected to the positive output terminal of the second operational amplifier (OTA2) ; The second summing capacitor ( ) is connected to the positive output terminal of the third operational amplifier (OTA3) ; The third summing capacitor ( ) is connected to the negative output terminal of the third operational amplifier (OTA3) ; The fourth summing capacitor ( ) is connected to the negative output terminal of the second operational amplifier (OTA2) ; The fifth integrating capacitor ( ) is connected to the negative output terminal of the fourth operational amplifier (OTA4) ; The sixth integrating capacitor ( ) is connected to the positive output terminal of the fourth operational amplifier (OTA4) ; The positive input terminal of the fourth operational amplifier (OTA4) is also connected to the twenty-first switch ( ) and the other end of the first summing capacitor ( )'s upper plate, the second summing capacitor ( ) of the upper plate and the fifth integrating capacitor ( ) of the upper plate; The negative input terminal of the fourth operational amplifier (OTA4) is also connected to the twenty-second switch ( ) and the other end of the third summing capacitor ( )'s upper plate, the fourth summing capacitor ( ) of the upper plate and the sixth integrating capacitor ( )'s upper plate.

9. The readout circuit based on embedded CCIA and hybrid DSM according to claim 1, wherein: The 1.5-bit quantizer includes a first dual differential comparator (COMP1) and a second dual differential comparator (COMP2); the first differential input pair of the first dual differential comparator (COMP1) is the positive output terminal of the fourth operational amplifier (OTA4) signal and the negative output of the fourth operational amplifier (OTA4) signal, the second differential input pair is an off-chip reference signal and , output 1-bit digital signal The first differential input pair of the second dual differential comparator (COMP1) is the positive output signal of the fourth operational amplifier (OTA4). and the negative output of the fourth operational amplifier (OTA4) signal, the second differential input pair is an off-chip reference signal and , output 1-bit digital signal .

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