A power management device and a computer system

Abstract

The present invention discloses a power management device and a computer system. By integrating a power output module, a controller, a first switch circuit and a second switch circuit, accurate control and management of the power of each component of the computer system is achieved. The controller can send corresponding instructions to the power output module, the first switch circuit, the second switch circuit and the CPU according to the working state setting instructions input by the user, so as to control the on-off state of each part of the power supply. The output and switching of the power supply can be accurately controlled to ensure that the computer system can efficiently realize the switching of multiple working states defined by ACPI. This integrated solution reduces the complex signal interaction and timing coordination difficulty between the CPU, PCH and SIO in the traditional solution, reduces the total cost, and simplifies the power management logic.

Description

Technical Field

[0001] The present invention relates to the field of power supply design, and in particular to a power supply management device and a computer system. Background Art

[0002] ACPI (Advanced Configuration and Power Interface) is a hardware and software interface specification defined by Intel, Microsoft, and Toshiba. It aims to provide a unified, platform-independent interface for effective communication and coordination between operating systems and hardware devices to achieve efficient power management.

[0003] ACPI defines a set of standard methods and data structures for controlling and monitoring the power state, device resource allocation, and system configuration of computer systems, including power consumption states corresponding to the working states of various computer systems (such as S0, S3, S4, G2 / S5, G3, etc.). Switching between these states usually requires close coordination between the CPU (Central Processing Unit), PCH (Platform Controller Hub), and SIO (Super I / O). However, this traditional solution has a high total cost, and the signal interaction between SIO and PCH is complex, making it difficult to coordinate signal timing. Summary of the invention

[0004] The purpose of the present invention is to provide a power management device and a computer system, which can accurately control the output and switching of the power supply, ensure that the computer system can efficiently implement the switching of multiple working states defined by ACPI. This integrated solution reduces the complexity of signal interaction and timing coordination between CPU, PCH and SIO in traditional solutions, reduces the total cost, and simplifies the power management logic.

[0005] In order to solve the above technical problems, the present invention provides a power management device, which is applied to a computer system. The computer system also includes a DDR and a CPU. The power management device includes: a power output module, a controller, a first switch circuit, and a second switch circuit; the input end of the power output module is connected to the main power supply, the first output end of the power output module is connected to the first power domain of the controller, the second output end of the power output module is respectively connected to the input end of the first switch circuit and the input end of the second switch circuit, the first output end of the first switch circuit is connected to the power end of the DDR, the second output end of the first switch circuit is connected to the second power domain of the controller, and the output end of the second switch circuit is connected to the power supply end of the CPU. The source end is connected, and the output end of the controller is respectively connected to the power output module, the first switch circuit, and the second switch circuit; the power output module is used to output the first power through its own first output end when the main power is turned on, and determine whether to output the second power through its own second output end according to the power instruction of the controller; the controller is used to send the power instruction to the power output module, send the first control instruction to the first switch circuit, and send the second control instruction to the second switch circuit according to the working state setting instruction input by the user; the first switch circuit is used to adjust its own on-off state according to the first control instruction; the second switch circuit is used to adjust its own on-off state according to the second control instruction.

[0006] In one embodiment, the first switch circuit includes a two-selector selector, a first switch device and a second switch device; the first input end of the two-selector selector is connected to the first output end of the power output module, the second input end of the two-selector selector is connected to the second output end of the power output module, and the output end of the two-selector selector is connected to the power end of the DDR through the first switch device and to the second power domain of the controller through the second switch device; the controller is connected to the control end of the two-selector selector, the control end of the first switch device and the control end of the second switch device; sending a first control instruction to the first switch circuit includes: sending a gating instruction to the two-selector selector, sending a first on-off instruction to the first switch device, and sending a second on-off instruction to the second switch device; the two-selector selector is used to conduct a first path between its first input end and the output end, or conduct a second path between its second input end and the output end according to the gating instruction; the first switch device is used to adjust its on-off state according to the first on-off instruction; the second switch device is used to adjust its on-off state according to the second on-off instruction.

[0007] In one embodiment, when the working state setting instruction is an instruction corresponding to the power-on state, sending the power instruction to the power output module, sending the first control instruction to the first switch circuit, and sending the second control instruction to the second switch circuit include: sending the second power output instruction to the power output module, sending the second path turn-on instruction to the two-choice selector, sending the first turn-on instruction to the first switch device and the second switch device, and sending the second turn-on instruction to the second switch circuit; the power output module is specifically used to output the first power through its first output end when the main power is turned on, and when receiving the second power output instruction, simultaneously output the second power through its second output end; the two-choice selector is specifically used to turn on the second path when receiving the second path turn-on instruction; the first switch device is specifically used to turn on when receiving the first turn-on instruction, so that the DDR is powered on; the second switch device is specifically used to turn on when receiving the first turn-on instruction, so that the second power domain is powered on; the second switch circuit is specifically used to turn on when receiving the second turn-on instruction, so that the CPU is powered on.

[0008] In one embodiment, when the working state setting instruction is an instruction corresponding to the shutdown state, sending the power instruction to the power output module, sending the first control instruction to the first switch circuit, and sending the second control instruction to the second switch circuit include: sequentially sending the second cut-off instruction to the second switch circuit, sending the first cut-off instruction to the second switch device and the first switch device, sending the first path turn-on instruction to the two-to-one selector, and sending the second power turn-off instruction to the power output module; the power output module is specifically used to output the first power through its first output end when the main power is turned on, and stop outputting the second power through its second output end when receiving the second power turn-off instruction; the two-to-one selector is specifically used to turn on the first path when receiving the first path turn-on instruction; the first switch device is specifically used to turn off when receiving the first cut-off instruction, so as to power off the DDR; the second switch device is specifically used to turn off when receiving the first cut-off instruction, so as to power off the second power domain; the second switch circuit is specifically used to turn off when receiving the second cut-off instruction, so as to power off the CPU.

[0009] In one embodiment, when the working state setting instruction is an instruction corresponding to the sleep state, sending the power instruction to the power output module, sending the first control instruction to the first switch circuit, and sending the second control instruction to the second switch circuit include: sequentially sending the second cut-off instruction to the second switch circuit, sending the first path turn-on instruction to the two-to-one selector, continuously sending the first turn-on instruction to the first switch device and the second switch device, and sending the second power cut-off instruction to the power output module; the power output module is specifically used to output the first power through its first output end when the main power is turned on, and stop outputting the second power through its second output end when receiving the second power cut-off instruction; the two-to-one selector is specifically used to turn on the first path when receiving the first path turn-on instruction; the first switch device is specifically used to turn on when receiving the first turn-on instruction, so that the DDR is powered on; the second switch device is specifically used to turn on when receiving the first turn-on instruction, so that the second power domain is powered on; the second switch circuit is specifically used to turn off when receiving the second turn-off instruction, so that the CPU is powered off.

[0010] In one embodiment, when the working state setting instruction is an instruction corresponding to the sleep wake-up state, sending the power instruction to the power output module, sending the first control instruction to the first switch circuit, and sending the second control instruction to the second switch circuit include: sequentially sending a second turn-on instruction to the second switch circuit, sending a second power output instruction to the power output module, sending a second path turn-on instruction to the two-to-one selector, and continuously sending the first turn-on instruction to the first switch device and the second switch device; the power output module is specifically used to output the first power through its first output end when the main power is turned on, and when receiving the second power output instruction, simultaneously output the second power through its second output end; the two-to-one selector is specifically used to turn on the second path when receiving the second path turn-on instruction; the first switch device is specifically used to turn on when receiving the first turn-on instruction, so that the DDR is powered on; the second switch device is specifically used to turn on when receiving the first turn-on instruction, so that the second power domain is powered on; the second switch circuit is specifically used to turn on when receiving the second turn-on instruction, so that the CPU is powered on.

[0011] In one embodiment, it also includes: a delay circuit arranged between the power output module and the controller; the power output module is also used to send a feedback signal to the controller after outputting the second power through its own second output terminal; sending a second path conduction instruction to the two-to-one selector includes: after receiving the feedback signal, sending the second path conduction instruction to the two-to-one selector.

[0012] In one embodiment, the second switching circuit includes a voltage regulating module, the input end of the voltage regulating module is connected to the second output end of the power output module, and the output end of the voltage regulating module is connected to the power end of the CPU; sending a second control instruction to the second switching circuit includes: when the working state setting instruction is an instruction corresponding to the power-on state or the sleep-wake-up state, sending a voltage regulation instruction to the voltage regulating module; when the working state setting instruction is an instruction corresponding to the power-off state or the sleep state, sending a voltage stop regulation instruction to the voltage regulation module; the voltage regulation module is used to adjust the voltage of the second power supply to a preset voltage according to the voltage regulation instruction to power the CPU, and stop regulating the voltage of the second power supply according to the voltage stop regulation instruction to stop powering the CPU.

[0013] In one embodiment, the computer system further comprises a baseboard controller BC, and the controller is integrated into the baseboard controller BC.

[0014] In order to solve the above technical problems, the present application also provides a computer system, including DDR and CPU, and also including the power management device mentioned above.

[0015] The present invention provides a power management device and a computer system, which realizes precise control and management of the power of each component of the computer system by integrating a power output module, a controller, a first switch circuit and a second switch circuit, wherein the controller can send corresponding instructions to the power output module, the first switch circuit, the second switch circuit and the CPU according to the working state setting instructions input by the user, thereby controlling the on-off state of the power of each part, and can accurately control the output and switching of the power supply, ensuring that the computer system can efficiently realize the switching of multiple working states defined by ACPI. This integrated solution reduces the complex signal interaction and timing coordination difficulty between the CPU, PCH and SIO in the traditional solution, reduces the total cost, and simplifies the power management logic. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0017] Figure 1 A schematic diagram of a power management device provided by the present invention;

[0018] Figure 2 A schematic diagram of a power management device provided by the present invention in a power-on state;

[0019] Figure 3 A schematic diagram of a power management device provided by the present invention in a shutdown state;

[0020] Figure 4 A schematic diagram of a power management device provided by the present invention in a sleep state;

[0021] Figure 5 This is a schematic diagram of a power management device provided by the present invention in a sleep-wake-up state. DETAILED DESCRIPTION

[0022] The core of the present invention is to provide a power management device and a computer system, which can accurately control the output and switching of the power supply, and ensure that the computer system can efficiently implement the switching of multiple working states defined by ACPI. This integrated solution reduces the complexity of signal interaction and timing coordination between CPU, PCH and SIO in traditional solutions, reduces the total cost, and simplifies the power management logic.

[0023] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0024] First, several state definitions involved in this embodiment are explained:

[0025] Among them, S0--actually this is the normal working state of the computer system, all devices are fully turned on, and the power consumption is relatively large; S3--this is the familiar STR (Suspend to RAM), and the power consumption at this time does not exceed 10W; S4--also known as STD (Suspend to Disk), at this time the system main power is turned off, and the hard disk stores the data information before S4, so S4 is a more power-saving state than S3; ATX power supply also has 5VSB power supply, and the system can be awakened by USB (Universal Serial Bus) / network and other devices. G2 / S5--softOff, that is, shutdown. At this time, the ATX power supply is only powered by 5VSB. G3--ATX (Advanced Technology eXtended) power is turned off, and the system clock and a very small range of logic are powered by batteries.

[0026] In the prior art, the CPU+PCH+SIO work together to complete the ACPI function. The workflow is: 1. In the G3 state, the battery supplies power to the PCH bridge chip; 2. The user connects the ATX plug, and the ATX power supply generates 5VSB to supply power to the SIO; 3. The user presses the power button; 4. The SIO chip enables the SIO_EUP_EN signal; 5. The 5VSB power supply supplies power to the PCH bridge chip through the turned-on power switch; 6. Enable the LAN port power supply, and supply power to the SIO SYS_3VSB power supply; 7. SIO chip resets RSMRST# to PCH bridge chip; 8. SIO chip transmits power button information to PCH bridge chip; 9. PCH pulls down SLP_S4#; 10. PCH pulls down SLP_S3#; 11. SIO then pulls down PSON to turn on the ATX main power supply; 12. The PWRGD signal generated by the main power supply is aggregated and combined to generate ALL_PWRGD to notify SIO; 13. Generate H_VTTPWRGD signal; 14. Generate DRAMPWROK signal to the processor; 15. Processor power supply normal signal CORE_PWRGD; 16. CORE_PWRGD and upper PWRGD3V_350MS generate SYS_PWROK, indicating that all power supplies of the system are turned on; 17. SIO generates MINI PCIE reset; 18. PCH generates platform reset PLT_RST#; The control logic is complex.

[0027] To solve the above technical problems, Figure 1As shown, the present invention provides a power management device, which is applied to a computer system. The computer system also includes a DDR and a CPU. The power management device includes: a power output module 11, a controller 13, a first switch circuit 12, and a second switch circuit 14; the input end of the power output module 11 is connected to the main power supply, the first output end of the power output module 11 is connected to the first power domain of the controller 13, the second output end of the power output module 11 is respectively connected to the input end of the first switch circuit 12 and the input end of the second switch circuit 14, the first output end of the first switch circuit 12 is connected to the power end of the DDR, the second output end of the first switch circuit 12 is connected to the second power domain of the controller 13, the output end of the second switch circuit 14 is connected to the power end of the CPU, and the output end of the controller 13 is respectively connected to the power output module 11, the first switch circuit 12, and the second switch circuit 14.

[0028] The power output module 11 is used to output the first power through its own first output terminal when the main power is turned on, and determine whether to output the second power through its own second output terminal according to the power instruction of the controller 13.

[0029] The controller 13 is used to send a power instruction to the power output module 11 , send a first control instruction to the first switch circuit 12 , and send a second control instruction to the second switch circuit 14 according to the working state setting instruction input by the user.

[0030] The first switch circuit 12 is used to adjust its on-off state according to the first control instruction; the second switch circuit 14 is used to adjust its on-off state according to the second control instruction.

[0031] Specifically, the power management device is applied to a computer system, and includes a power output module 11, a controller 13, a first switching circuit 12 and a second switching circuit 14. By precisely controlling the output and switching of the power supply, efficient switching of various working states in the computer system is achieved.

[0032] The input end of the power output module 11 is connected to the main power supply. After the main power supply is turned on, the power output module 11 outputs the first power supply through its first output end to power the first power domain of the controller 13, so as to provide a reference power supply for the controller 13. The power output module 11 also has a second output end, which can determine whether to output the second power supply according to the power instruction sent by the controller 13. The second output end is respectively connected to the input ends of the first switch circuit 12 and the second switch circuit 14 to power the DDR / second power domain and the CPU.

[0033] The controller 13 is the core of the entire power management device and is responsible for receiving the working state setting instructions input by the user. Specifically, according to the user's instructions, the controller 13 sends a power instruction to the power output module 11 to control the power output of the second output terminal of the power output module 11. The controller 13 also sends a first control instruction and a second control instruction to the first switch circuit 12 and the second switch circuit 14 respectively to adjust the on-off state of the two switch circuits, thereby controlling the power supply of the DDR and the CPU.

[0034] The input end of the first switch circuit 12 is connected to the second output end of the power output module 11. The switch circuit has two output ends, one connected to the power end of the DDR, and the other connected to the second power domain of the controller 13. The first switch circuit 12 adjusts its on-off state according to the first control instruction sent by the controller 13, thereby controlling the power supply of the DDR and the second power domain of the controller 13.

[0035] The input end of the second switch circuit 14 is also connected to the second output end of the power output module 11, and the output end thereof is connected to the power supply end of the CPU. The second switch circuit 14 adjusts its on / off state according to the second control instruction sent by the controller 13, thereby controlling the power supply of the CPU.

[0036] The specific working process is as follows: when the main power supply is turned on, the power output module 11 outputs the first power supply through its first output terminal, firstly supplies power to the first power domain of the controller 13, and starts the controller 13. The user sends a working state setting instruction to the controller 13. After receiving the working state setting instruction, the controller 13 parses the instruction and determines the working state (such as S0, S3, S4, etc.) that the system needs to enter. According to the parsed instruction, the controller 13 sends a power instruction to the power output module 11 to control the power output of its second output terminal. If it is necessary to power the DDR, the controller 13 sends a first control instruction to the first switch circuit 12 to turn on the corresponding channel, and the second output terminal of the power output module 11 supplies power to the DDR through the first switch circuit 12. Similarly, if it is necessary to power the second power domain, the channel corresponding to the first switch circuit 12 is controlled to be turned on, so that the second output terminal of the power output module 11 supplies power to the second power domain of the controller 13 through the first switch circuit 12. If it is necessary to power the CPU, the controller 13 sends a second control instruction to the second switch circuit 14 to turn it on, and the second output terminal of the power output module 11 supplies power to the CPU through the second switch circuit 14.

[0037] In addition, Figure 1The various modules in the module are described. The reset block diagram module represents a simple circuit that can generate a reset after the module is powered on. The delay circuit block diagram module represents a simple circuit for signal delay on the board. The output signals include SLP_S3# / S4# / S5# (which can control the power switch on the board), reset signals such as PRST, PRST_CPU, and power indication signal CPU_PWROK. Through the output signal, the board power supply can be controlled and the power-on reset of the CPU can be realized.

[0038] With the cooperation of various modules, the system realizes smooth switching from one power state to another. For example, when switching from S3 (sleep state) to S0 (working state), the controller 13 will gradually turn on the power supply of DDR and CPU according to the preset instructions to ensure that the system wakes up normally and enters the working state.

[0039] In one embodiment, the computer system further includes a baseboard controller BC, and the controller 13 is integrated into the BC (Baseboard Controller). In this embodiment, in addition to the DDR, CPU and power management device, the computer system also includes a baseboard controller BC, and the controller 13 is integrated into the baseboard controller BC. The baseboard controller BC is responsible for managing and coordinating the connection and communication of various peripherals and input and output devices in the system. The integration of the controller 13 into the baseboard controller BC means that the controller 13 is closely integrated with the baseboard controller BC, and various functions and resources of the system can be managed more efficiently. The baseboard controller BC is usually also responsible for processing the storage control, USB control, Ethernet control, audio interface, SATA (Serial Advanced Technology Attachment) interface and other peripheral interfaces in the system, so that the entire computer system can realize various input and output functions and data exchange. The integration of the controller 13 inside the PCH makes the system design more compact and efficient, while helping to reduce power consumption and improve system performance. The computer system of this architecture can realize unified management and control of various peripherals through the baseboard controller BC and the integrated controller 13, thereby meeting the complexity and diversity of modern computing needs.

[0040] This integrated power management solution greatly reduces the total cost by reducing the complex signal interaction and timing coordination between the CPU, PCH and SIO in the traditional solution. It not only simplifies the power management logic and improves the reliability and efficiency of the system, but also ensures smooth switching between various power states and optimizes the overall performance of the system. This solution is particularly suitable for modern computer systems with high requirements for miniaturization and integration, and provides efficient and reliable support for implementing multiple power consumption states defined by ACPI.

[0041] In one embodiment, the first switch circuit 12 includes a two-selector selector 21, a first switch device 22, and a second switch device 23; the first input end of the two-selector selector 21 is connected to the first output end of the power output module 11, the second input end of the two-selector selector 21 is connected to the second output end of the power output module 11, and the output end of the two-selector selector 21 is connected to the power end of the DDR through the first switch device 22 and to the second power domain of the controller 13 through the second switch device 23; the controller 13 is connected to the control end of the two-selector selector 21, the control end of the first switch device 22, and the second switch device 23. The control terminal of the switch device 23 is connected; a first control instruction is sent to the first switch circuit 12, including: sending a gating instruction to the two-to-one selector 21, sending a first on-off instruction to the first switch device 22, and sending a second on-off instruction to the second switch device 23; the two-to-one selector 21 is used to conduct the first path between the first input terminal and the output terminal of itself, or to conduct the second path between the second input terminal and the output terminal of itself according to the gating instruction; the first switch device 22 is used to adjust its own on-off state according to the first on-off instruction; the second switch device 23 is used to adjust its own on-off state according to the second on-off instruction.

[0042] In this embodiment, the working principle of the first switch circuit 12 is as follows: when the system needs to adjust the power supply state of the DDR and the second power domain of the controller 13, the controller 13 sends a first control instruction to the first switch circuit 12. The controller 13 sends a selection instruction to the two-to-one selector 21 according to the current working state, instructing it to select the first input terminal or the second input terminal as the power input. If the first input terminal is selected, the two-to-one selector 21 transmits the first power supply to the output terminal. If the second input terminal is selected, the two-to-one selector 21 transmits the second power supply to the output terminal.

[0043] The controller 13 sends a first on / off instruction to the first switch device 22, instructing it to open or close the connection with the DDR power supply terminal. The controller 13 sends a second on / off instruction to the second switch device 23, instructing it to open or close the connection with the second power domain of the controller 13.

[0044] The control process is as follows: the controller 13 sends a gating instruction to the two-to-one selector 21 according to the working state currently required by the system. The two-to-one selector 21 connects the corresponding power input (the first power supply or the second power supply) to its output terminal according to the gating instruction. The power is transmitted from the output terminal of the two-to-one selector 21 to the first switch device 22 and the second switch device 23. The controller 13 sends on-off instructions to the first switch device 22 and the second switch device 23 respectively as needed. The first switch device 22 decides whether to supply power to the DDR according to the first on-off instruction of the controller 13. The second switch device 23 decides whether to supply power to the second power domain of the controller 13 according to the second on-off instruction of the controller 13.

[0045] Through this design, the system can flexibly select and switch power supplies, while accurately controlling the power supply status of the second power domain of the DDR and controller 13. Compared with the traditional power management solution, by integrating the two-to-one selector 21 and the switch device, the power management circuit is simplified, and the complex signal interaction and timing coordination difficulty between the CPU, PCH and SIO in the traditional solution are reduced. Due to the reduction of complex power management components and signal interaction design, the total cost of the system is reduced.

[0046] In one embodiment, when the working state setting instruction is an instruction corresponding to the power-on state, sending a power instruction to the power output module 11, sending a first control instruction to the first switch circuit 12, and sending a second control instruction to the second switch circuit 14 includes: sending a second power output instruction to the power output module 11, sending a second path turn-on instruction to the two-to-one selector 21, sending a first turn-on instruction to the first switch device 22 and the second switch device 23, and sending a second turn-on instruction to the second switch circuit 14; the power output module 11 is specifically used to output the first power through its own first output terminal when the main power is turned on, and when receiving the second power output instruction, simultaneously output the second power through its own second output terminal; the two-to-one selector 21 is specifically used to turn on the second path when receiving the second path turn-on instruction; the first switch device 22 is specifically used to turn on when receiving the first turn-on instruction, so that the DDR is powered on; the second switch device 23 is specifically used to turn on when receiving the first turn-on instruction, so that the second power domain is powered on; the second switch circuit 14 is specifically used to turn on when receiving the second turn-on instruction, so that the CPU is powered on.

[0047] In this embodiment, when a working state setting instruction corresponding to the power-on state is received, first, a power instruction including a second power output instruction is sent to the power output module 11. When the main power is turned on, the power output module 11 outputs the first power through its first output terminal, and decides to output the second power through its second output terminal according to the second power output instruction. Secondly, a second path conduction instruction is sent to the two-choice selector 21. The two-choice selector 21 selects to conduct the second path between its second input terminal and output terminal according to this instruction, thereby connecting the second output terminal of the power output module 11 to the second power domain of the controller 13. Next, a first conduction instruction is sent to the first switch device 22 and the second switch device 23. The first switch device 22 is turned on in response to this instruction, so that the power supply terminal of the DDR is supplied with power; the second switch device 23 is also turned on in response to this instruction, so that the second power domain of the controller 13 is powered on. Finally, a second conduction instruction is sent to the second switch circuit 14. The second switch circuit 14 is turned on in accordance with this instruction, so that the power supply terminal of the CPU is supplied with power.

[0048] For details, please refer to Figure 2 The specific process includes:

[0049] 1. When the user turns on the ATX power supply, the non-gated power supply 5VSB (first power supply) is immediately generated to supply power to the APS1 power domain (first power domain) of the basic board controller BC. 2. The reset block diagram module on the board generates RSMRST# to reset the APS1 and APS2 power domains, and the reset is released after the delay circuit. 3. When a PME event occurs (such as pressing the power button / RTC wake-up / LAN wake-up, etc.), SLP_S5 is pulled up. Pulling up SLP_S5# (the second switch device 23 is turned on) turns on the power gating of the APS2 power domain, and the APS2 power domain (the second power domain) is powered on. 4. Pulling up SLP_S4#, turning on the gating (the first switch device 22 is turned on) supplies power to the DDR. 5. Pulling up SLP_S3#, generating PSON# to turn on the VCC power output of the ATX, supplying power to the CPU and the main power domain VCC of the power management chip. 6. After VCC is turned on, the ATX outputs the POK signal, which reaches the BC_PWROK pin of the power management chip after delay processing by the external circuit. 7. After receiving BC_PWROK, the power management chip generates 5VDUAL_AUX internally to switch the APS2 power domain and DDR power supply to VCC, and the PRST# signal resets the platform. 8. After receiving the external SYS_PWROK, the basic board controller BC enters the S0 working state, and then releases the reset after a delay of PRST#. It can be seen that the ACPI module of the power management chip needs to complete the following tasks: (1) respond to PME events: press the power button / RTC wake-up / LAN wake-up / USB wake-up / GPIO wake-up; (2) control the ATX power supply; (3) control the power on and off of each device of the system; (4) generate a reset of each device.

[0050] This process ensures that when the computer system is turned on, all necessary power paths are properly turned on in the set order and conditions, thereby achieving correct power-on and operation of system components (such as DDR and CPU).

[0051] In one embodiment, when the working state setting instruction is an instruction corresponding to the shutdown state, sending a power instruction to the power output module 11, sending a first control instruction to the first switch circuit 12, and sending a second control instruction to the second switch circuit 14 includes: sending a second cut-off instruction to the second switch circuit 14 in sequence, sending a first cut-off instruction to the second switch device 23 and the first switch device 22, sending a first path turn-on instruction to the two-to-one selector 21, and sending a second power cut-off instruction to the power output module 11; the power output module 11 is specifically used to output the first power through its own first output terminal when the main power is turned on, and stop outputting the second power through its own second output terminal when receiving the second power cut-off instruction; the two-to-one selector 21 is specifically used to turn on the first path when receiving the first path turn-on instruction; the first switch device 22 is specifically used to turn off when receiving the first cut-off instruction, so as to power off the DDR; the second switch device 23 is specifically used to turn off when receiving the first cut-off instruction, so as to power off the second power domain; the second switch circuit 14 is specifically used to turn off when receiving the second cut-off instruction, so as to power off the CPU.

[0052] In this embodiment, the operating principle of the power management device in the shutdown state of the computer system is described. When the working state setting instruction corresponding to the shutdown state is received, first, a power instruction is sent to the power output module 11, including a second power supply cut-off instruction. When the main power is turned on, the power output module 11 outputs the first power through its first output terminal, and stops outputting the second power according to the second power supply cut-off instruction. Next, the second cut-off instruction is sent to the second switch circuit 14. The second switch circuit 14 is cut off according to this instruction, so that the power supply end of the CPU stops supplying power. Then, the first cut-off instruction is sent to the second switch device 23 and the first switch device 22. The second switch device 23 and the first switch device 22 are cut off in response to this instruction, so that the second power domain of the controller 13 and the power supply end of the DDR stop supplying power. Subsequently, a first path conduction instruction is sent to the two-choice selector 21. The two-choice selector 21 conducts the first path between its first input terminal and the output terminal according to this instruction, thereby connecting the first output terminal of the power output module 11 to the first power domain of the controller 13, ensuring that the necessary power paths in the system are correctly cut off according to the set logic in the shutdown state.

[0053] For details, please refer to Figure 3The specific process is as follows: 1. The user clicks the operating system to shut down, and SLP_S3 is pulled down. At the same time, PRST# is pulled down to reset. 2. SLP_S4 is pulled down to turn off the DDR power switch, and DDR is powered off. 3. SLP_S5 is pulled down. Turn off the APS2 power supply. 4. After a delay, 5VMUX / 3VSBSW switches the APS2 power domain and DDR power supply to 5VSB. 5. After a delay, PSON# is pulled up to turn off the VCC of the ATX power supply, thereby turning off the CPU and the basic board controller BC main power domain. Since VCC is turned off, BC_PWROK and SYS_PWROK are pulled down.

[0054] The entire process ensures that when the computer system is shut down, the power supply to each component is gradually cut off according to the preset sequence and conditions, thereby effectively managing the system's power consumption and power consumption, ensuring the system is shut down safely and saving energy.

[0055] In one embodiment, when the working state setting instruction is an instruction corresponding to the sleep state, sending a power instruction to the power output module 11, sending a first control instruction to the first switch circuit 12, and sending a second control instruction to the second switch circuit 14, includes: sending a second cut-off instruction to the second switch circuit 14 in sequence, sending a first path turn-on instruction to the two-to-one selector 21, continuously sending a first turn-on instruction to the first switch device 22 and the second switch device 23, and sending a second power cut-off instruction to the power output module 11; the power output module 11 is specifically used to output the first power through its own first output terminal when the main power is turned on, and stop outputting the second power through its own second output terminal when receiving the second power cut-off instruction; the two-to-one selector 21 is specifically used to turn on the first path when receiving the first path turn-on instruction; the first switch device 22 is specifically used to turn on when receiving the first turn-on instruction, so that the DDR is powered on; the second switch device 23 is specifically used to turn on when receiving the first turn-on instruction, so that the second power domain is powered on; the second switch circuit 14 is specifically used to turn off when receiving the second cut-off instruction, so that the CPU is powered off.

[0056] This embodiment describes the operating principle of the power management device in the sleep state of the computer system. When receiving the working state setting instruction corresponding to the sleep state, first, a power instruction is sent to the power output module 11, including a second power cut-off instruction. When the main power is turned on, the power output module 11 outputs the first power through its first output terminal, and stops outputting the second power according to the second power cut-off instruction. Then, a second cut-off instruction is sent to the second switch circuit 14. The second switch circuit 14 is cut off according to this instruction, so that the power supply end of the CPU stops supplying power, thereby ensuring that the CPU enters a low power consumption or stop state. Then, a first path conduction instruction is sent to the two-choice selector 21. The two-choice selector 21 conducts the first path between its first input terminal and output terminal according to this instruction, connecting the first output terminal of the power output module 11 to the first power domain of the controller 13 to maintain the necessary power path in the system. Among them, the first conduction instruction is continuously sent to the first switch device 22 and the second switch device 23. In response to this instruction, the first switch device 22 and the second switch device 23 are continuously turned on, so that the power supply end of the DDR and the second power domain of the controller 13 remain in the power supply state, so that the system can be quickly restored in the sleep state.

[0057] For details, please refer to Figure 4 The specific process is as follows: 1. The user sets the sleep mode, SLP_S3# is pulled down. At the same time, PRST# is pulled down to reset. 2. 5VMUX will be pulled high to switch the APS2 power domain and DDR power supply to 5VSB. 3. Control PSON# to pull high to turn off the VCC of the ATX power supply. 4. VCC loses power, causing BC_PWROK and SYS_PWROK to pull down.

[0058] The whole process ensures that when the computer system enters sleep mode, the power supply of the CPU is cut off to reduce power consumption, while maintaining power supply to necessary components such as DDR and controller 13 to support fast wake-up and low-power operation of the system.

[0059] In one embodiment, when the working state setting instruction is an instruction corresponding to the sleep wake-up state, a power instruction is sent to the power output module 11, a first control instruction is sent to the first switch circuit 12, and a second control instruction is sent to the second switch circuit 14, including: sequentially sending a second turn-on instruction to the second switch circuit 14, sending a second power output instruction to the power output module 11, sending a second path turn-on instruction to the two-to-one selector 21, and continuously sending the first turn-on instruction to the first switch device 22 and the second switch device 23; the power output module 11 is specifically used to output the first power through its own first output terminal when the main power is turned on, and output the second power when receiving the second power output instruction; the two-to-one selector 21 is specifically used to turn on the second path when receiving the second path turn-on instruction; the first switch device 22 is specifically used to turn on when receiving the first turn-on instruction, so that the DDR is powered on; the second switch device 23 is specifically used to turn on when receiving the first turn-on instruction, so that the second power domain is powered on; the second switch circuit 14 is specifically used to turn on when receiving the second turn-on instruction, so that the CPU is powered on.

[0060] This embodiment describes the operating principle of the power management device when the computer system wakes up from a sleep state. When a working state setting instruction corresponding to the sleep wake-up state is received, first, a power instruction is sent to the power output module 11, including a second power output instruction. When the main power is turned on, the power output module 11 outputs the first power through its first output terminal, and decides whether to output the second power according to the second power output instruction. Then, a second conduction instruction is sent to the second switch circuit 14. The second switch circuit 14 is turned on according to this instruction, so that the power supply end of the CPU is supplied with power to support the wake-up operation of the system. Then, a second path conduction instruction is sent to the two-to-one selector 21. The two-to-one selector 21 conducts the second path between its second input terminal and output terminal according to this instruction, and connects the second output terminal of the power output module 11 to the second power domain of the controller 13 to ensure that all necessary power paths of the system are connected normally after waking up. Among them, the first conduction instruction is continuously sent to the first switch device 22 and the second switch device 23. In response to the instruction, the first switch device 22 and the second switch device 23 are continuously turned on, so that the power supply end of the DDR and the second power domain of the controller 13 remain in a power supply state, so that the system returns to a normal working state.

[0061] For details, please refer to Figure 5The specific process is as follows: 1. The system receives a PME wake-up event (such as mouse shaking / keyboard pressing / power button pressing, etc.), and SLP_S3# is pulled up. 2. ATX VCC power supply is turned on through PSON#. 3. The power management chip receives BC_PWROK. 4. BC APS2 power domain and DDR power supply are switched to VCC. 5. After receiving SYS_PWROK, after a delay, PRST# is released to reset and return to S0 state. After a delay, PRST_CPU# is sent and released to reset.

[0062] The entire process ensures that when the computer system is successfully awakened from sleep mode, the CPU and other necessary components can quickly obtain power supply to quickly respond to user operations or system events while minimizing energy consumption.

[0063] In one embodiment, it also includes: a delay circuit 15 arranged between the power output module 11 and the controller 13; the power output module 11 is also used to send a feedback signal to the controller 13 after outputting the second power through its own second output terminal; sending a second path conduction instruction to the two-to-one selector 21, including: after receiving the feedback signal, sending the second path conduction instruction to the two-to-one selector 21.

[0064] In this embodiment, the power management device adds a delay circuit 15 and a feedback mechanism in the computer system to further optimize the operation of power management. First, in addition to outputting the first power through its first output terminal when the main power is turned on, the power output module 11 also has the function of outputting the second power through its second output terminal after receiving the corresponding power command. These control signals are related to the system's working state setting instructions, such as instructions corresponding to the sleep wake-up state. Secondly, a delay circuit 15 is provided between the power output module 11 and the controller 13. The function of the delay circuit 15 is to introduce a certain time delay to ensure that after the power output module 11 switches or outputs the second power, the controller 13 can properly receive and process these changes to avoid voltage mutations or other adverse effects during power switching. Then, after the power output module 11 outputs the second power through its second output terminal, it will send a feedback signal to the controller 13. This feedback signal is usually used to inform the controller 13 that the state of the second power has changed or the switching is completed, so that the controller 13 can further adjust the working state of the system or make corresponding decisions. When the controller 13 receives the feedback signal, it will send a second path conduction instruction to the two-to-one selector 21 according to the preset logical conditions. This conduction instruction informs the two-to-one selector 21 to turn on the second path between its second input terminal and output terminal, connecting the second output terminal of the power output module 11 to the second power domain of the controller 13, ensuring the stable operation of the system after switching to the second power supply.

[0065] This design achieves a smooth transition and assurance during the power switching process through the delay circuit 15 and the feedback mechanism, thereby improving the stability and reliability of the system under different working conditions.

[0066] In one embodiment, the second switching circuit 14 includes a voltage regulating module, the input end of the voltage regulating module is connected to the second output end of the power output module 11, and the output end of the voltage regulating module is connected to the power end of the CPU; a second control instruction is sent to the second switching circuit 14, including: when the working state setting instruction is an instruction corresponding to the power-on state or the sleep wake-up state, a voltage regulation instruction is sent to the voltage regulation module; when the working state setting instruction is an instruction corresponding to the power-off state or the sleep state, a voltage stop regulation instruction is sent to the voltage regulation module; the voltage regulation module is used to adjust the voltage of the second power supply to a preset voltage according to the voltage regulation instruction to power the CPU, and stop regulating the voltage of the second power supply according to the voltage stop regulation instruction to stop powering the CPU.

[0067] In this embodiment, the second switch circuit 14 is expanded to include a voltage regulating module, which is designed to effectively manage and regulate the power supply voltage required by the CPU to ensure that a stable power supply is provided under different system working conditions. First, the input end of the voltage regulating module is connected to the second output end of the power output module 11, which indicates that the voltage regulating module directly receives the second power supply from the power output module 11. Secondly, the output end of the voltage regulating module is connected to the power supply end of the CPU, which is responsible for providing the CPU with a regulated voltage. This design makes the voltage regulating module a key component to ensure the voltage required for the CPU to operate. Then, when receiving an instruction corresponding to the working state setting instruction being a power-on state or a sleep-wake-up state, the controller 13 sends a second control instruction to the second switch circuit 14, which includes a voltage regulating instruction. The voltage regulating instruction tells the voltage regulating module to adjust the voltage of the second power supply according to a preset voltage setting value to ensure that the CPU can operate in normal and wake-up states. When receiving an instruction corresponding to the working state setting instruction being a power-off state or a sleep state, the controller 13 sends another second control instruction to the second switch circuit 14, namely, a voltage stop regulating instruction. The voltage stop regulation instruction will cause the voltage regulation module to stop regulating the second power supply voltage, thereby stopping power supply to the CPU, which helps the system save energy and extend battery life when the system is turned off or in sleep mode.

[0068] In summary, the voltage regulation module manages the voltage output of the second power supply by receiving voltage regulation instructions to adapt to different system working state requirements, thereby ensuring that the CPU obtains a stable power supply. This design not only improves the power efficiency and stability of the system, but also effectively extends the service life and life of the device.

[0069] In order to solve the above technical problems, the present application also provides a computer system, including DDR and CPU, and also including the above power management device.

[0070] For other introductions to the computer system, please refer to the above embodiments, and this application will not go into details here.

[0071] It should also be noted that, in this specification, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprises", "comprising" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the statement "comprising a ..." does not exclude the presence of other identical elements in the process, method, article or device including the element.

[0072] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present invention. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A power management device, characterized in that: Applied to a computer system, the computer system further includes a memory DDR and a central processing unit CPU, and the power management device includes: A power output module, a controller, a first switch circuit, and a second switch circuit; The input end of the power output module is connected to the main power supply, the first output end of the power output module is connected to the first power domain of the controller, the second output end of the power output module is respectively connected to the input end of the first switch circuit and the input end of the second switch circuit, the first output end of the first switch circuit is connected to the power end of the DDR, the second output end of the first switch circuit is connected to the second power domain of the controller, the output end of the second switch circuit is connected to the power end of the CPU, and the output end of the controller is respectively connected to the power output module, the first switch circuit, and the second switch circuit; The power output module is used to output the first power through its own first output terminal when the main power is turned on, and determine whether to output the second power through its own second output terminal according to the power instruction of the controller; The controller is used to send the power instruction to the power output module, send a first control instruction to the first switch circuit, and send a second control instruction to the second switch circuit according to the working state setting instruction input by the user; The first switch circuit is used to adjust its on / off state according to the first control instruction; The first switch circuit includes a two-to-one selector, a first switch device and a second switch device; The first input end of the two-to-one selector is connected to the first output end of the power output module, the second input end of the two-to-one selector is connected to the second output end of the power output module, and the output end of the two-to-one selector is respectively connected to the power end of the DDR through the first switch device and to the second power domain of the controller through the second switch device; the controller is connected to the control end of the two-to-one selector, the control end of the first switch device, and the control end of the second switch device; Sending a first control instruction to the first switch circuit includes: Sending a gating instruction to the one-out-of-two selector, sending a first on-off instruction to the first switch device, and sending a second on-off instruction to the second switch device; The two-to-one selector is used to conduct a first path between its first input terminal and the output terminal, or conduct a second path between its second input terminal and the output terminal according to the gating instruction; The first switch device is used to adjust its on / off state according to the first on / off instruction; The second switch device is used to adjust its on-off state according to the second on-off instruction; The second switch circuit is used to adjust its on-off state according to the second control instruction.

2. The power management device according to claim 1, wherein: When the working state setting instruction is an instruction corresponding to the power-on state, sending the power instruction to the power output module, sending a first control instruction to the first switch circuit, and sending a second control instruction to the second switch circuit, includes: Sending a second power output instruction to the power output module, sending a second path conduction instruction to the one-out-of-two selector, sending a first conduction instruction to the first switch device and the second switch device, and sending a second conduction instruction to the second switch circuit; The power output module is specifically used to output the first power through its own first output terminal when the main power is turned on, and to output the second power through its own second output terminal when receiving the second power output instruction; The two-to-one selector is specifically configured to conduct the second path upon receiving the second path conducting instruction; The first switch device is specifically configured to be turned on when receiving the first turn-on instruction, so as to power on the DDR; the second switch device is specifically configured to be turned on when receiving the first turn-on instruction, so as to power on the second power domain; The second switch circuit is specifically configured to be turned on upon receiving the second turn-on instruction, so as to power on the CPU.

3. The power management device according to claim 1, wherein: When the working state setting instruction is an instruction corresponding to the shutdown state, sending the power instruction to the power output module, sending a first control instruction to the first switch circuit, and sending a second control instruction to the second switch circuit, includes: sequentially sending a second cut-off instruction to the second switch circuit, sending a first cut-off instruction to the second switch device and the first switch device, sending a first path conduction instruction to the one-out-of-two selector, and sending a second power supply cut-off instruction to the power supply output module; The power output module is specifically used to output the first power through its own first output terminal when the main power is turned on, and stop outputting the second power through its own second output terminal when receiving the second power cut-off instruction; The one-to-two selector is specifically configured to conduct the first path upon receiving the first path conduction instruction; The first switch device is specifically used to be turned off when receiving the first turn-off instruction, so as to power off the DDR; the second switch device is specifically used to be turned off when receiving the first turn-off instruction, so as to power off the second power domain; The second switch circuit is specifically configured to be turned off upon receiving the second turn-off instruction, so as to power off the CPU.

4. The power management device according to claim 1, wherein: When the working state setting instruction is an instruction corresponding to the sleep state, sending the power instruction to the power output module, sending a first control instruction to the first switch circuit, and sending a second control instruction to the second switch circuit, includes: Sequentially sending a second cut-off instruction to the second switch circuit, sending a first path conduction instruction to the one-out-of-two selector, continuously sending a first conduction instruction to the first switch device and the second switch device, and sending a second power supply cut-off instruction to the power supply output module; The power output module is specifically used to output the first power through its own first output terminal when the main power is turned on, and stop outputting the second power through its own second output terminal when receiving the second power cut-off instruction; The one-to-two selector is specifically configured to conduct the first path upon receiving the first path conduction instruction; The first switch device is specifically configured to be turned on when receiving the first turn-on instruction, so as to power on the DDR; the second switch device is specifically configured to be turned on when receiving the first turn-on instruction, so as to power on the second power domain; The second switch circuit is specifically configured to be turned off upon receiving the second turn-off instruction, so as to power off the CPU.

5. The power management device according to claim 1, wherein: When the working state setting instruction is an instruction corresponding to the sleep wake-up state, sending the power instruction to the power output module, sending a first control instruction to the first switch circuit, and sending a second control instruction to the second switch circuit, includes: Sequentially sending a second conduction instruction to the second switch circuit, sending a second power output instruction to the power output module, sending a second path conduction instruction to the one-out-of-two selector, and continuously sending a first conduction instruction to the first switch device and the second switch device; The power output module is specifically used to output the first power through its own first output terminal when the main power is turned on, and to output the second power through its own second output terminal when receiving the second power output instruction; The two-to-one selector is specifically configured to conduct the second path upon receiving the second path conducting instruction; The first switch device is specifically configured to be turned on when receiving the first turn-on instruction, so as to power on the DDR; the second switch device is specifically configured to be turned on when receiving the first turn-on instruction, so as to power on the second power domain; The second switch circuit is specifically configured to be turned on upon receiving the second turn-on instruction, so as to power on the CPU.

6. The power management device according to claim 2, wherein: Also includes: A delay circuit provided between the power output module and the controller; The power output module is further used to send a feedback signal to the controller after outputting the second power through its second output terminal; Sending a second path conduction instruction to the two-choice selector includes: After receiving the feedback signal, a second path conduction instruction is sent to the one-out-of-two selector.

7. The power management device according to any one of claims 1 to 6, characterized in that: The second switch circuit comprises a voltage regulating module, the input end of the voltage regulating module is connected to the second output end of the power output module, and the output end of the voltage regulating module is connected to the power end of the CPU; Sending a second control instruction to the second switch circuit includes: When the working state setting instruction is an instruction corresponding to the power-on state or the sleep-wake-up state, sending a voltage adjustment instruction to the voltage adjustment module; When the working state setting instruction is an instruction corresponding to the shutdown state or the sleep state, sending a voltage stop adjustment instruction to the voltage adjustment module; The voltage regulating module is used to adjust the voltage of the second power supply to a preset voltage according to the voltage regulating instruction to supply power to the CPU, and to stop regulating the voltage of the second power supply according to the voltage stop regulating instruction to stop supplying power to the CPU.

8. The power management device according to any one of claims 1 to 6, characterized in that: The computer system further comprises a baseboard controller BC, wherein the controller is integrated into the baseboard controller BC.

9. A computer system, characterized in that: The system comprises a DDR and a CPU, and also comprises a power management device as described in any one of claims 1 to 8.

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