Display substrate and display device

Abstract

The invention provides a display substrate and a display device. The display substrate comprises a substrate and a driving circuit. The driving circuit comprises a driving signal generating circuit, a control signal generating circuit and a control circuit; the driving signal generation circuit generates an nth-stage driving signal under the control of the first clock signal and the second clock signal; n is a positive integer; the control signal generation circuit is used for outputting a control signal according to the enable signal; and the control circuit outputs a signal to the nth-stage driving output end under the control of the control signal. According to the invention, the nth-stage driving signal or the invalid voltage signal can be accurately output to the nth-stage driving output end, so that local refreshing can be accurately carried out.

Description

[0001] This application is a divisional application of the Chinese invention application with application date of September 11, 2023 and application number 202311170623.9. Technical Field

[0002] The present invention relates to the field of display technology, and in particular to a display substrate and a display device. Background Art

[0003] In the related art, the driving circuit usually includes a driving signal generating circuit and a control circuit directly controlled by an enable signal. When the pulse width of the n-th level driving signal provided by the driving signal generating circuit is 1H (1H is a row scanning time), the control circuit directly controlled by the enable signal can be used to control the output of the n-th level driving signal or the invalid voltage signal. However, with the development of pixels, the signals for controlling pixels are diversified, and the pulse width of the n-th level driving signal will exceed 1H, resulting in the n-th level driving signal waveform crossing the change edge (rising edge or falling edge) of the enable signal, resulting in only a portion of the n-th level driving signal being output, which will cause abnormal pixel operation. Summary of the invention

[0004] The main purpose of the present invention is to provide a display substrate and a display device to solve the problem that local refresh cannot be accurately performed in related display panels.

[0005] In one aspect, an embodiment of the present invention provides a display substrate, comprising a base and a driving circuit disposed on the base;

[0006] The display substrate includes a display area and a peripheral area; the driving circuit is arranged in the peripheral area;

[0007] The driving circuit includes a driving signal generating circuit, a control signal generating circuit and a control circuit;

[0008] The drive signal generating circuit is electrically connected to the first clock signal line and the second clock signal line respectively, and is used to generate and output the n-th level drive signal through the n-th level drive signal output terminal under the control of the first clock signal provided by the first clock signal line and the second clock signal provided by the second clock signal line; n is a positive integer;

[0009] The control signal generating circuit is electrically connected to the enable signal line and the control signal terminal respectively, and is used to output a control signal to the control signal terminal according to the enable signal provided by the enable signal line;

[0010] The control circuit is electrically connected to the control signal terminal and the n-th level driving output terminal respectively, and is used to output a signal to the n-th level driving output terminal under the control of the control signal.

[0011] Optionally, the driving circuit further includes an output inverting circuit;

[0012] The output inversion circuit is electrically connected to the n-th level driving signal output terminal and the n-th level inverted signal output terminal respectively, and is used to invert the n-th level driving signal to obtain and output the n-th level inverted driving signal through the n-th level inverted signal output terminal;

[0013] The control signal generating circuit is also electrically connected to the n-1th level driving signal output terminal, the n-1th level inverted signal output terminal, the n-level driving signal output terminal and the n-level inverted signal output terminal respectively, and is used to generate a control signal according to an enable signal provided by an enable signal line under the control of the n-1th level driving signal, the n-1th level inverted signal, the n-level driving signal and the n-level inverted signal;

[0014] The n-1th level driving signal output terminal is used to provide the n-1th level driving signal, and the n-1th level inverting signal output terminal is used to provide the n-1th level inverting signal;

[0015] The control signal generating circuit is arranged on a side of the driving signal generating circuit close to the display area.

[0016] Optionally, the control circuit in the driving circuit includes a first control circuit, a second control circuit and a first energy storage circuit; the control circuit is arranged on a side of the driving signal generating circuit close to the display area;

[0017] The first control circuit is electrically connected to the control signal terminal, the n-th level drive signal output terminal, the first control voltage line, the second control voltage line and the control output terminal respectively, and is used to control the connection or disconnection between the control output terminal and the first control voltage line under the control of the control signal, control the connection or disconnection between the control output terminal and the first control voltage line under the control of the n-th level drive signal outputted by the n-th level drive signal output terminal, and control the connection or disconnection between the control output terminal and the second control voltage line under the control of the n-th level drive signal and the control signal;

[0018] The second control circuit is electrically connected to the control output terminal, the n-th level driving output terminal, the first voltage line and the second voltage line respectively, and is used to control the connection or disconnection between the n-th level driving output terminal and the first voltage line, and control the connection or disconnection between the n-th level driving output terminal and the second voltage line under the control of the potential of the control output terminal;

[0019] The first energy storage circuit is electrically connected to the control output terminal and is used to maintain the potential of the control output terminal;

[0020] The control circuit also includes a second energy storage circuit;

[0021] The second energy storage circuit is electrically connected to the control signal terminal and is used to maintain the potential of the control signal terminal;

[0022] The second energy storage circuit is arranged on a side of the second control circuit away from the display area.

[0023] Optionally, the first voltage line includes a first first voltage line and a second first voltage line sequentially arranged along a direction away from the display area, and the second voltage line includes a first second voltage line and a second second voltage line sequentially arranged along a direction away from the display area;

[0024] The orthographic projection of at least part of the active pattern of the transistor included in the second control circuit on the substrate at least partially overlaps with the orthographic projection of the first first voltage line on the substrate;

[0025] The orthographic projection of at least part of the active pattern of the transistor included in the second control circuit on the substrate at least partially overlaps with the orthographic projection of the first second voltage line on the substrate;

[0026] The orthographic projection of the first second voltage line on the substrate at least partially overlaps with the orthographic projection of the plate of the capacitor included in the first energy storage circuit on the substrate;

[0027] An orthographic projection of the enable signal line on the substrate at least partially overlaps with an orthographic projection of active patterns of at least a portion of transistors included in the control signal generating circuit on the substrate.

[0028] Optionally, the orthographic projection of the first second voltage line on the substrate at least partially overlaps with the orthographic projection of the plate of the capacitor included in the second energy storage circuit on the substrate;

[0029] An orthographic projection of the second second voltage line on the substrate at least partially overlaps with an orthographic projection of active patterns of at least a portion of transistors included in the control signal generating circuit on the substrate.

[0030] Optionally, an orthographic projection of the second first voltage line on the substrate at least partially overlaps with an orthographic projection of active patterns of at least part of transistors included in the first control circuit on the substrate;

[0031] The orthographic projection of the enabling signal line on the substrate at least partially overlaps with the orthographic projection of the plate of the capacitor included in the second energy storage circuit on the substrate;

[0032] The orthographic projection of the second second voltage line on the substrate at least partially overlaps with the orthographic projection of the plate of the capacitor included in the second energy storage circuit on the substrate;

[0033] An orthographic projection of the second second voltage line on the substrate at least partially overlaps with an orthographic projection of active patterns of at least a portion of transistors included in the control signal generating circuit on the substrate.

[0034] Optionally, an orthographic projection of the second first voltage line on the substrate at least partially overlaps with an orthographic projection of active patterns of at least part of transistors included in the first control circuit on the substrate;

[0035] The orthographic projection of the second second voltage line on the substrate at least partially overlaps with the orthographic projection of the plate of the capacitor included in the first energy storage circuit on the substrate;

[0036] The orthographic projection of the second second voltage line on the substrate at least partially overlaps with the orthographic projection of the plate of the capacitor included in the first energy storage circuit on the substrate;

[0037] The orthographic projection of the second second voltage line on the substrate at least partially overlaps with the orthographic projection of the active pattern of at least part of the transistor included in the first control circuit on the substrate;

[0038] The orthographic projection of the second first voltage line on the substrate at least partially overlaps with the orthographic projection of the active pattern of at least part of the transistor included in the first control circuit on the substrate;

[0039] An orthographic projection of the second first voltage line on the substrate at least partially overlaps with an orthographic projection of active patterns of at least a portion of transistors included in the control signal generating circuit on the substrate.

[0040] Optionally, the first first voltage line, the second first voltage line, the first second voltage line, the second second voltage line and the enable signal line all extend along a first direction;

[0041] The width of the first first voltage line along the second direction is greater than the width of the second first voltage line along the second direction;

[0042] The width of the first second voltage line along the second direction is greater than the width of the second second voltage line along the second direction;

[0043] The first direction intersects the second direction.

[0044] Optionally, the transistor included in the second control circuit is arranged on a side of the transistor included in the first control circuit close to the display area;

[0045] The control signal generating circuit includes a transistor which is arranged on a side of the second control circuit away from the display area.

[0046] Optionally, an orthographic projection of the enable signal line on the substrate at least partially overlaps with an orthographic projection of an active pattern of at least one transistor included in the output inverter circuit on the substrate.

[0047] Optionally, the second voltage line includes a third second voltage line; the third second voltage line is arranged on a side of the second second voltage line away from the display area;

[0048] An orthographic projection of the third second voltage line on the substrate at least partially overlaps with an orthographic projection of an active pattern of at least one transistor included in the output inverter circuit on the substrate.

[0049] Optionally, the orthographic projection of the second first voltage line on the substrate at least partially overlaps with the orthographic projection of the active pattern of at least one transistor included in the output inverter circuit on the substrate;

[0050] The enable signal line is arranged on a side of the second first voltage line away from the display area.

[0051] Optionally, the driving signal generating circuit includes a first node control circuit, a second node control circuit, a first output node control circuit, a second output node control circuit, a potential maintaining circuit and an output circuit;

[0052] The first node control circuit is electrically connected to the first node, the first first clock signal line, the second voltage line, and the second output node, respectively, and is used to control the connection between the first node and the second voltage line under the control of the first clock signal provided by the first first clock signal line, and to control the connection or disconnection between the first node and the first first clock signal line under the control of the potential of the second output node;

[0053] The second node control circuit is electrically connected to the first node, the first intermediate node, the first voltage line, the first second clock signal line, the second node, the input terminal and the second voltage line respectively, and is used to control the connection between the first intermediate node and the first voltage line under the control of the potential of the first node, control the connection between the first intermediate node and the first second clock signal line under the control of the potential of the second node, and control the potential of the second node according to the potential of the first intermediate node, and control the connection between the input terminal and the second node under the control of the second clock signal provided by the first second clock signal line and the second voltage signal provided by the second voltage line;

[0054] The first output node control circuit is electrically connected to the first output node, the first node, the first second clock signal line, the second intermediate node, the second output node and the first voltage line respectively, and is used to control the second intermediate node to be connected to the first second clock signal line under the control of the potential of the first node, control the potential of the second intermediate node according to the potential of the first node, control the second intermediate node to be connected to the first output node under the control of the second clock signal provided by the first second clock signal line, and control the first output node to be connected to the first voltage line under the control of the potential of the second output node;

[0055] The second output node control circuit is electrically connected to the first second clock signal line, the input terminal, the control voltage line, the first voltage line, the second node, and the second output node, respectively, and is used to control the second output node to be connected to the input terminal under the control of the second clock signal provided by the first second clock signal line, control the potential of the second output node according to the potential of the second node, and control the second output node to be connected to the first voltage line under the control of the control voltage provided by the control voltage line;

[0056] The potential maintaining circuit is electrically connected to the first output node, and is used to maintain the potential of the first output node;

[0057] The output circuit is electrically connected to the first output node, the second output node, the first voltage line, the second voltage line and the n-th level drive signal output terminal, respectively, and is used to control the connection between the n-th level drive signal output terminal and the first voltage line under the control of the potential of the first output node, and control the connection between the n-th level drive signal output terminal and the second voltage line under the control of the potential of the second output node;

[0058] The first voltage lines include a first first voltage line, a second first voltage line, and a third first voltage line sequentially arranged along a direction away from the display area, and the second voltage lines include a first second voltage line, a second second voltage line, and a third second voltage line sequentially arranged along a direction away from the display area;

[0059] The orthographic projection of the second second voltage line on the substrate at least partially overlaps with the orthographic projection of the active pattern of at least one transistor included in the output circuit on the substrate;

[0060] The orthographic projection of the second first voltage line on the substrate at least partially overlaps with the orthographic projection of the active pattern of at least one transistor included in the output circuit on the substrate;

[0061] The orthographic projection of the second first voltage line on the substrate at least partially overlaps with the orthographic projection of the plate of the capacitor included in the potential maintaining circuit on the substrate;

[0062] The orthographic projection of the third first voltage line on the substrate at least partially overlaps with the orthographic projection of the active pattern of at least one transistor included in the second output node control circuit on the substrate;

[0063] The orthographic projection of the third second voltage line on the substrate at least partially overlaps with the orthographic projection of the plate of the capacitor included in the second node control circuit on the substrate;

[0064] The orthographic projection of the third second voltage line on the substrate at least partially overlaps with the orthographic projection of the active pattern of at least one transistor included in the first node control circuit on the substrate;

[0065] An orthographic projection of the third second voltage line on the substrate at least partially overlaps with an orthographic projection of an active pattern of at least one transistor included in the second node control circuit on the substrate.

[0066] Optionally, the first first clock signal line and the first second clock signal line are arranged between the third first voltage line and the third second voltage line;

[0067] The orthographic projection of the first first clock signal line on the substrate at least partially overlaps with the orthographic projection of the plate of the capacitor included in the first output node control circuit on the substrate;

[0068] The orthographic projection of the first first clock signal line on the substrate at least partially overlaps with the orthographic projection of the active pattern of at least one transistor included in the second node control circuit on the substrate;

[0069] The orthographic projection of the first first clock signal line on the substrate at least partially overlaps with the orthographic projection of the active pattern of at least one transistor included in the first output node control circuit on the substrate;

[0070] The orthographic projection of the first second clock signal line on the substrate at least partially overlaps with the orthographic projection of the plate of the capacitor included in the first output node control circuit on the substrate;

[0071] The orthographic projection of the first second clock signal line on the substrate at least partially overlaps with the orthographic projection of the plate of the capacitor included in the second node control circuit on the substrate.

[0072] Optionally, the driving signal generating circuit includes a first node control circuit, a second node control circuit, a first output node control circuit, a second output node control circuit, a potential maintaining circuit and an output circuit;

[0073] The first node control circuit is electrically connected to the first node, the second first clock signal line, the second voltage line, and the second output node, respectively, and is used to control the connection between the first node and the second voltage line under the control of the first clock signal provided by the second first clock signal line, and to control the connection or disconnection between the first node and the second first clock signal line under the control of the potential of the second output node;

[0074] The second node control circuit is electrically connected to the first node, the first intermediate node, the first voltage line, the second second clock signal line, the second node, the input terminal and the second voltage line respectively, and is used to control the connection between the first intermediate node and the first voltage line under the control of the potential of the first node, control the connection between the first intermediate node and the second second clock signal line under the control of the potential of the second node, and control the potential of the second node according to the potential of the first intermediate node, and control the connection between the input terminal and the second node under the control of the second clock signal provided by the second second clock signal line and the second voltage signal provided by the second voltage line;

[0075] The first output node control circuit is electrically connected to the first output node, the first node, the second second clock signal line, the second intermediate node, the second output node and the first voltage line respectively, and is used to control the second intermediate node to be connected to the second second clock signal line under the control of the potential of the first node, control the potential of the second intermediate node according to the potential of the first node, control the second intermediate node to be connected to the first output node under the control of the second clock signal provided by the second second clock signal line, and control the first output node to be connected to the first voltage line under the control of the potential of the second output node;

[0076] The second output node control circuit is electrically connected to the second second clock signal line, the input terminal, the control voltage line, the first voltage line, the second node, and the second output node, respectively, and is used to control the second output node to be connected to the input terminal under the control of the second clock signal provided by the second second clock signal line, control the potential of the second output node according to the potential of the second node, and control the second output node to be connected to the first voltage line under the control of the control voltage provided by the control voltage line;

[0077] The potential maintaining circuit is electrically connected to the first output node, and is used to maintain the potential of the first output node;

[0078] The output circuit is electrically connected to the first output node, the second output node, the first voltage line, the second voltage line and the n-th level drive signal output terminal, respectively, and is used to control the connection between the n-th level drive signal output terminal and the first voltage line under the control of the potential of the first output node, and control the connection between the n-th level drive signal output terminal and the second voltage line under the control of the potential of the second output node;

[0079] The first voltage lines include a first first voltage line, a second first voltage line, and a third first voltage line sequentially arranged along a direction away from the display area, and the second voltage lines include a first second voltage line, a second second voltage line, and a third second voltage line sequentially arranged along a direction away from the display area;

[0080] The orthographic projection of the second second voltage line on the substrate at least partially overlaps with the orthographic projection of the active pattern of at least one transistor included in the output circuit on the substrate;

[0081] The orthographic projection of the second first voltage line on the substrate at least partially overlaps with the orthographic projection of the active pattern of at least one transistor included in the output circuit on the substrate;

[0082] The orthographic projection of the second first voltage line on the substrate at least partially overlaps with the orthographic projection of the plate of the capacitor included in the potential maintaining circuit on the substrate;

[0083] The orthographic projection of the third first voltage line on the substrate at least partially overlaps with the orthographic projection of the active pattern of at least one transistor included in the second output node control circuit on the substrate;

[0084] The orthographic projection of the third second voltage line on the substrate at least partially overlaps with the orthographic projection of the plate of the capacitor included in the second node control circuit on the substrate;

[0085] The orthographic projection of the third second voltage line on the substrate at least partially overlaps with the orthographic projection of the active pattern of at least one transistor included in the first node control circuit on the substrate;

[0086] An orthographic projection of the third second voltage line on the substrate at least partially overlaps with an orthographic projection of an active pattern of at least one transistor included in the second node control circuit on the substrate.

[0087] Optionally, the second first clock signal line and the second second clock signal line are arranged between the third first voltage line and the third second voltage line;

[0088] The orthographic projection of the second first clock signal line on the substrate at least partially overlaps with the orthographic projection of the plate of the capacitor included in the first output node control circuit on the substrate;

[0089] The orthographic projection of the second first clock signal line on the substrate at least partially overlaps with the orthographic projection of the active pattern of at least one transistor included in the second node control circuit on the substrate;

[0090] The orthographic projection of the second first clock signal line on the substrate at least partially overlaps with the orthographic projection of the active pattern of at least one transistor included in the first output node control circuit on the substrate;

[0091] The orthographic projection of the second second clock signal line on the substrate at least partially overlaps with the orthographic projection of the plate of the capacitor included in the first output node control circuit on the substrate;

[0092] The orthographic projection of the second second clock signal line on the substrate at least partially overlaps with the orthographic projection of the plate of the capacitor included in the second node control circuit on the substrate.

[0093] Optionally, the driving signal generating circuit includes a first node control circuit, a second node control circuit, a first output node control circuit, a second output node control circuit, a potential maintaining circuit and an output circuit;

[0094] The first node control circuit is electrically connected to the first node, the first first clock signal line, the second voltage line, and the second output node, respectively, and is used to control the connection between the first node and the second voltage line under the control of the first clock signal provided by the first first clock signal line, and to control the connection or disconnection between the first node and the first first clock signal line under the control of the potential of the second output node;

[0095] The second node control circuit is electrically connected to the first node, the first intermediate node, the first voltage line, the first second clock signal line, the second node, the input terminal and the second voltage line respectively, and is used to control the connection between the first intermediate node and the first voltage line under the control of the potential of the first node, control the connection between the first intermediate node and the first second clock signal line under the control of the potential of the second node, and control the potential of the second node according to the potential of the first intermediate node, and control the connection between the input terminal and the second node under the control of the second clock signal provided by the first second clock signal line and the second voltage signal provided by the second voltage line;

[0096] The first output node control circuit is electrically connected to the first output node, the first node, the first second clock signal line, the second intermediate node, the second output node and the first voltage line respectively, and is used to control the second intermediate node to be connected to the first second clock signal line under the control of the potential of the first node, control the potential of the second intermediate node according to the potential of the first node, control the second intermediate node to be connected to the first output node under the control of the second clock signal provided by the first second clock signal line, and control the first output node to be connected to the first voltage line under the control of the potential of the second output node;

[0097] The second output node control circuit is electrically connected to the first second clock signal line, the input terminal, the control voltage line, the first voltage line, the second node, and the second output node, respectively, and is used to control the second output node to be connected to the input terminal under the control of the second clock signal provided by the first second clock signal line, control the potential of the second output node according to the potential of the second node, and control the second output node to be connected to the first voltage line under the control of the control voltage provided by the control voltage line;

[0098] The potential maintaining circuit is electrically connected to the first output node, and is used to maintain the potential of the first output node;

[0099] The output circuit is electrically connected to the first output node, the second output node, the first voltage line, the second voltage line and the n-th level drive signal output terminal, respectively, and is used to control the connection between the n-th level drive signal output terminal and the first voltage line under the control of the potential of the first output node, and control the connection between the n-th level drive signal output terminal and the second voltage line under the control of the potential of the second output node;

[0100] The first voltage lines include a first first voltage line, a second first voltage line, a third first voltage line, and a fourth first voltage line sequentially arranged along a direction away from the display area, and the second voltage lines include a first second voltage line, a second second voltage line, a third second voltage line, and a fourth second voltage line sequentially arranged along a direction away from the display area;

[0101] The orthographic projection of the third first voltage line on the substrate at least partially overlaps with the orthographic projection of the active pattern of at least one transistor included in the output circuit on the substrate;

[0102] The orthographic projection of the third first voltage line on the substrate at least partially overlaps with the orthographic projection of the plate of the capacitor included in the potential maintaining circuit on the substrate;

[0103] The orthographic projection of the third second voltage line on the substrate at least partially overlaps with the orthographic projection of the active pattern of at least one transistor included in the output circuit on the substrate;

[0104] The orthographic projection of the fourth first voltage line on the substrate at least partially overlaps with the orthographic projection of the active pattern of at least one transistor included in the second output node control circuit on the substrate;

[0105] The orthographic projection of the fourth second voltage line on the substrate at least partially overlaps with the orthographic projection of the active pattern of at least one transistor included in the first node control circuit on the substrate;

[0106] An orthographic projection of the fourth second voltage line on the substrate at least partially overlaps with an orthographic projection of a plate of a capacitor included in the second node control circuit on the substrate.

[0107] Optionally, the display substrate further includes a first first clock signal line and a first second clock signal line disposed between the fourth first voltage line and the fourth second voltage line;

[0108] The orthographic projection of the first first clock signal line on the substrate at least partially overlaps with the orthographic projection of the plate of the capacitor included in the first output node control circuit on the substrate;

[0109] The orthographic projection of the first second clock signal line on the substrate at least partially overlaps with the orthographic projection of the plate of the capacitor included in the first output node control circuit on the substrate;

[0110] The orthographic projection of the first second clock signal line on the substrate at least partially overlaps with the orthographic projection of the plate of the capacitor included in the first output node control circuit on the substrate;

[0111] The orthographic projection of the first first clock signal line on the substrate at least partially overlaps with the orthographic projection of the active pattern of at least part of the transistor included in the second node control circuit on the substrate;

[0112] An orthographic projection of the first first clock signal line on the substrate at least partially overlaps with an orthographic projection of active patterns of at least a portion of transistors included in the first output node control circuit on the substrate.

[0113] Optionally, the driving signal generating circuit includes a first node control circuit, a second node control circuit, a first output node control circuit, a second output node control circuit, a potential maintaining circuit and an output circuit;

[0114] The first node control circuit is electrically connected to the first node, the second first clock signal line, the second voltage line, and the second output node, respectively, and is used to control the connection between the first node and the second voltage line under the control of the first clock signal provided by the second first clock signal line, and to control the connection or disconnection between the first node and the second first clock signal line under the control of the potential of the second output node;

[0115] The second node control circuit is electrically connected to the first node, the first intermediate node, the first voltage line, the second second clock signal line, the second node, the input terminal and the second voltage line respectively, and is used to control the connection between the first intermediate node and the first voltage line under the control of the potential of the first node, control the connection between the first intermediate node and the second second clock signal line under the control of the potential of the second node, and control the potential of the second node according to the potential of the first intermediate node, and control the connection between the input terminal and the second node under the control of the second clock signal provided by the second second clock signal line and the second voltage signal provided by the second voltage line;

[0116] The first output node control circuit is electrically connected to the first output node, the first node, the second second clock signal line, the second intermediate node, the second output node and the first voltage line respectively, and is used to control the second intermediate node to be connected to the second second clock signal line under the control of the potential of the first node, control the potential of the second intermediate node according to the potential of the first node, control the second intermediate node to be connected to the first output node under the control of the second clock signal provided by the second second clock signal line, and control the first output node to be connected to the first voltage line under the control of the potential of the second output node;

[0117] The second output node control circuit is electrically connected to the second second clock signal line, the input terminal, the control voltage line, the first voltage line, the second node, and the second output node, respectively, and is used to control the second output node to be connected to the input terminal under the control of the second clock signal provided by the second second clock signal line, control the potential of the second output node according to the potential of the second node, and control the second output node to be connected to the first voltage line under the control of the control voltage provided by the control voltage line;

[0118] The potential maintaining circuit is electrically connected to the first output node, and is used to maintain the potential of the first output node;

[0119] The output circuit is electrically connected to the first output node, the second output node, the first voltage line, the second voltage line and the n-th level drive signal output terminal, respectively, and is used to control the connection between the n-th level drive signal output terminal and the first voltage line under the control of the potential of the first output node, and control the connection between the n-th level drive signal output terminal and the second voltage line under the control of the potential of the second output node;

[0120] The first voltage lines include a first first voltage line, a second first voltage line, a third first voltage line, and a fourth first voltage line sequentially arranged along a direction away from the display area, and the second voltage lines include a first second voltage line, a second second voltage line, a third second voltage line, and a fourth second voltage line sequentially arranged along a direction away from the display area;

[0121] The orthographic projection of the third first voltage line on the substrate at least partially overlaps with the orthographic projection of the active pattern of at least one transistor included in the output circuit on the substrate;

[0122] The orthographic projection of the third first voltage line on the substrate at least partially overlaps with the orthographic projection of the plate of the capacitor included in the potential maintaining circuit on the substrate;

[0123] The orthographic projection of the third second voltage line on the substrate at least partially overlaps with the orthographic projection of the active pattern of at least one transistor included in the output circuit on the substrate;

[0124] The orthographic projection of the fourth first voltage line on the substrate at least partially overlaps with the orthographic projection of the active pattern of at least one transistor included in the second output node control circuit on the substrate;

[0125] The orthographic projection of the fourth second voltage line on the substrate at least partially overlaps with the orthographic projection of the active pattern of at least one transistor included in the first node control circuit on the substrate;

[0126] An orthographic projection of the fourth second voltage line on the substrate at least partially overlaps with an orthographic projection of a plate of a capacitor included in the second node control circuit on the substrate.

[0127] Optionally, the display substrate further includes a second first clock signal line and a second second clock signal line disposed between the fourth first voltage line and the fourth second voltage line;

[0128] The orthographic projection of the second first clock signal line on the substrate at least partially overlaps with the orthographic projection of the plate of the capacitor included in the first output node control circuit on the substrate;

[0129] The orthographic projection of the second second clock signal line on the substrate at least partially overlaps with the orthographic projection of the plate of the capacitor included in the first output node control circuit on the substrate;

[0130] The orthographic projection of the second second clock signal line on the substrate at least partially overlaps with the orthographic projection of the plate of the capacitor included in the first output node control circuit on the substrate;

[0131] The orthographic projection of the second first clock signal line on the substrate at least partially overlaps with the orthographic projection of the active pattern of at least part of the transistor included in the second node control circuit on the substrate;

[0132] An orthographic projection of the second first clock signal line on the substrate at least partially overlaps with an orthographic projection of active patterns of at least a portion of transistors included in the first output node control circuit on the substrate.

[0133] Optionally, the first voltage line includes a first first voltage line, the second voltage line includes a first second voltage line, a second second voltage line and a third second voltage line sequentially arranged in a direction away from the display area; the enable signal line is arranged between the second second voltage line and the third second voltage line;

[0134] The orthographic projection of the first second voltage line on the substrate at least partially overlaps with the orthographic projection of the active pattern of at least part of the transistor included in the second control circuit on the substrate;

[0135] The orthographic projection of the first first voltage line on the substrate at least partially overlaps with the orthographic projection of the active pattern of at least part of the transistor included in the second control circuit on the substrate;

[0136] The orthographic projection of the first first voltage line on the substrate at least partially overlaps with the orthographic projection of the active pattern of at least part of the transistor included in the first control circuit on the substrate;

[0137] The orthographic projection of the first first voltage line on the substrate at least partially overlaps with the orthographic projection of the plate of the capacitor included in the first energy storage circuit on the substrate;

[0138] The orthographic projection of the first second voltage line on the substrate at least partially overlaps with the orthographic projection of the plate of the capacitor included in the first energy storage circuit on the substrate;

[0139] The orthographic projection of the second second voltage line on the substrate at least partially overlaps with the orthographic projection of the active pattern of at least part of the transistor included in the first control circuit on the substrate;

[0140] The orthographic projection of the enable signal line on the substrate at least partially overlaps with the orthographic projection of the active pattern of at least part of the transistor included in the control signal generating circuit on the substrate;

[0141] An orthographic projection of the third second voltage line on the substrate at least partially overlaps with an orthographic projection of active patterns of at least a portion of transistors included in the control signal generating circuit on the substrate.

[0142] Optionally, the first voltage line includes a first first voltage line, and the second voltage line includes a first second voltage line and a second second voltage line sequentially arranged in a direction away from the display area; the enable signal line is arranged between the first second voltage line and the second second voltage line;

[0143] The orthographic projection of the first second voltage line on the substrate at least partially overlaps with the orthographic projection of the active pattern of at least part of the transistor included in the second control circuit on the substrate;

[0144] The orthographic projection of the enable signal line on the substrate at least partially overlaps with the orthographic projection of the plate of the capacitor included in the first energy storage circuit on the substrate; the orthographic projection of the second second voltage line on the substrate at least partially overlaps with the orthographic projection of the active pattern of at least part of the transistor included in the control signal generating circuit on the substrate;

[0145] The orthographic projection of the first first voltage line on the substrate at least partially overlaps with the orthographic projection of the active pattern of at least part of the transistor included in the second control circuit on the substrate;

[0146] An orthographic projection of the first first voltage line on the substrate at least partially overlaps with an orthographic projection of active patterns of at least a portion of transistors included in the first control circuit on the substrate.

[0147] Optionally, the drive signal generating circuit includes a first output node control circuit, a second output node control circuit, a third energy storage circuit and an output circuit; the drive signal generating circuit is arranged on a side of the control signal generating circuit included in the drive circuit away from the display area; the transistors in the output circuit are arranged on a side of the transistors included in the drive signal generating circuit except the transistors in the output circuit close to the display area;

[0148] The first output node control circuit is electrically connected to the third first clock signal line, the second voltage line and the second output node respectively, and is used to control the first output node to be connected to the second voltage line under the control of the first clock signal provided by the third first clock signal line, and to control the first output node to be connected to the third first clock signal line under the control of the potential of the second output node, and to maintain the potential of the first output node;

[0149] The second output node control circuit is electrically connected to the second output node, the third first clock signal line, the input terminal, the third second clock signal line, the first output node and the first voltage line respectively, and is used to control the second output node to be connected to the input terminal under the control of the first clock signal, and to control the second output node to be connected to the first voltage line under the control of the potential of the first output node and the second clock signal provided by the third second clock signal line;

[0150] The first end of the third energy storage circuit is electrically connected to the second output node, the second end of the third energy storage circuit is electrically connected to the n-th stage drive signal output terminal, and the third energy storage circuit is used to store electric energy;

[0151] The output circuit is electrically connected to the first output node, the second output node, the first voltage line, the second clock signal and the n-th level drive signal output terminal respectively, and is used to control the connection between the n-th level drive signal output terminal and the first voltage line under the control of the potential of the first output node, and control the connection between the n-th level drive signal output terminal and the third second clock signal line under the control of the potential of the second output node;

[0152] The first voltage lines include a first first voltage line and a second first voltage line sequentially arranged along a direction away from the display area, and the second voltage lines include a first second voltage line, a second second voltage line, a third second voltage line and a fourth second voltage line sequentially arranged along a direction away from the display area;

[0153] The orthographic projection of the plate of the capacitor included in the third energy storage circuit on the substrate is arranged between the orthographic projection of the third second voltage line on the substrate and the orthographic projection of the second first voltage line on the substrate;

[0154] The orthographic projection of the second first voltage line on the substrate at least partially overlaps with the orthographic projection of the plate of the capacitor included in the first output node control circuit on the substrate;

[0155] The orthographic projection of the second first voltage line on the substrate at least partially overlaps with the orthographic projection of the active pattern of at least part of the transistor included in the output circuit on the substrate;

[0156] An orthographic projection of the fourth second voltage line on the substrate at least partially overlaps with an orthographic projection of active patterns of at least a portion of transistors included in the first output node control circuit on the substrate.

[0157] Optionally, the drive signal generating circuit includes a first output node control circuit, a second output node control circuit, a third energy storage circuit and an output circuit; the drive signal generating circuit is arranged on a side of the control signal generating circuit included in the drive circuit away from the display area; the transistors in the output circuit are arranged on a side of the transistors included in the drive signal generating circuit except the transistors in the output circuit close to the display area;

[0158] The first output node control circuit is electrically connected to the third first clock signal line, the second voltage line and the second output node respectively, and is used to control the first output node to be connected to the second voltage line under the control of the first clock signal provided by the third first clock signal line, and to control the first output node to be connected to the third first clock signal line under the control of the potential of the second output node, and to maintain the potential of the first output node;

[0159] The second output node control circuit is electrically connected to the second output node, the third first clock signal line, the input terminal, the third second clock signal line, the first output node and the first voltage line respectively, and is used to control the second output node to be connected to the input terminal under the control of the first clock signal, and to control the second output node to be connected to the first voltage line under the control of the potential of the first output node and the second clock signal provided by the third second clock signal line;

[0160] The first end of the third energy storage circuit is electrically connected to the second output node, the second end of the third energy storage circuit is electrically connected to the n-th stage drive signal output terminal, and the third energy storage circuit is used to store electric energy;

[0161] The output circuit is electrically connected to the first output node, the second output node, the first voltage line, the second clock signal and the n-th level drive signal output terminal respectively, and is used to control the connection between the n-th level drive signal output terminal and the first voltage line under the control of the potential of the first output node, and control the connection between the n-th level drive signal output terminal and the third second clock signal line under the control of the potential of the second output node;

[0162] The first voltage lines include a first first voltage line and a second first voltage line sequentially arranged along a direction away from the display area, and the second voltage lines include a first second voltage line, a second second voltage line, a third second voltage line and a fourth second voltage line sequentially arranged along a direction away from the display area;

[0163] The orthographic projection of the third second voltage line on the substrate at least partially overlaps with the orthographic projection of the plate of the capacitor included in the third energy storage circuit on the substrate;

[0164] The orthographic projection of the second first voltage line on the substrate at least partially overlaps with the orthographic projection of the plate of the capacitor included in the first output node control circuit on the substrate;

[0165] The orthographic projection of the second first voltage line on the substrate at least partially overlaps with the orthographic projection of the active pattern of at least part of the transistor included in the output circuit on the substrate;

[0166] An orthographic projection of the fourth second voltage line on the substrate at least partially overlaps with an orthographic projection of active patterns of at least a portion of transistors included in the first output node control circuit on the substrate.

[0167] Optionally, the third first clock signal line and the third second clock signal line are arranged between the second first voltage line and the fourth second voltage line;

[0168] The orthographic projection of the third first clock signal line on the substrate at least partially overlaps with the orthographic projection of the active pattern of at least part of the transistor included in the second output node control circuit on the substrate;

[0169] An orthographic projection of the third second clock signal line on the substrate at least partially overlaps with an orthographic projection of active patterns of at least a portion of transistors included in the second output node control circuit on the substrate.

[0170] Optionally, the active pattern of at least part of the transistors included in the second control circuit includes at least two active pattern parts that are independent of each other.

[0171] In a second aspect, an embodiment of the present invention provides a display device, comprising the above-mentioned display substrate.

[0172] The present invention can accurately output the n-th level driving signal or the invalid voltage signal to the n-th level driving output terminal, so as to accurately perform local refresh. BRIEF DESCRIPTION OF THE DRAWINGS

[0173] Figure 1 is a structural diagram of a driving circuit according to an embodiment of the present invention;

[0174] Figure 2 is a circuit diagram of a related pixel circuit;

[0175] Figure 3 is a structural diagram of a driving circuit according to at least one embodiment of the present invention;

[0176] Figure 4 is a structural diagram of a driving circuit according to at least one embodiment of the present invention;

[0177] Figure 5 is a structural diagram of a driving circuit according to at least one embodiment of the present invention;

[0178] Figure 6 is a structural diagram of a driving circuit according to at least one embodiment of the present invention;

[0179] Figure 7 is a structural diagram of a driving circuit according to at least one embodiment of the present invention;

[0180] Figure 8 is a structural diagram of a driving circuit according to at least one embodiment of the present invention;

[0181] Fig. 9 is a structural diagram of a driving circuit according to at least one embodiment of the present invention;

[0182] Fig.10 is a structural diagram of a driving circuit according to at least one embodiment of the present invention;

[0183] Fig.11 is a structural diagram of a driving circuit according to at least one embodiment of the present invention;

[0184] Fig.12 is a structural diagram of a driving circuit according to at least one embodiment of the present invention;

[0185] Fig.13 is a structural diagram of a driving circuit according to at least one embodiment of the present invention;

[0186] Fig.14 is a circuit diagram of a driving circuit according to at least one embodiment of the present invention;

[0187] Fig.15 yes Fig.14 FIG. 1 is a timing diagram showing the operation of a driving signal generating circuit in at least one embodiment of the driving circuit shown.

[0188] Fig.16 is a working timing diagram of at least one embodiment of the n-1th stage driving circuit and at least one embodiment of the nth stage driving circuit;

[0189] Fig.17 is a circuit diagram of a driving circuit according to at least one embodiment of the present invention;

[0190] Fig.18 yes Fig.17 An operation timing diagram of a driving signal generating circuit in at least one embodiment of the driving circuit shown;

[0191] Fig.19 is a working timing diagram of at least one embodiment of the n-1th stage driving circuit and at least one embodiment of the nth stage driving circuit;

[0192] Fig. 20 is a circuit diagram of a driving circuit according to at least one embodiment of the present invention;

[0193] Fig.21 yes Fig. 20 An operation timing diagram of a driving signal generating circuit in at least one embodiment of the driving circuit shown;

[0194] Fig. 22 is a working timing diagram of at least one embodiment of the n-1th stage driving circuit and at least one embodiment of the nth stage driving circuit;

[0195] Fig.23 is a structural diagram of a display substrate according to at least one embodiment of the present invention;

[0196] Fig.24A , Fig. 24B and Fig.24C yes Fig.14 A first layout diagram of at least one embodiment of the driving circuit shown;

[0197] Fig.25 yes Fig.24A A layout diagram of a first semiconductor layer in;

[0198] Fig.26 yes Fig.24A A layout diagram of the first gate metal layer in FIG.

[0199] Fig. 27 yes Fig.24A A layout diagram of a second gate metal layer in FIG.

[0200] Fig.28 yes Fig.24AA layout diagram of the first source and drain metal layer in FIG.

[0201] Fig.29 yes Fig.24A A layout diagram of a second source / drain metal layer in FIG.

[0202] Fig.30 yes Fig.24A A layout diagram of the third source / drain metal layer in FIG.

[0203] Fig.31A yes Fig.24A An overlay diagram of a first semiconductor layer and a first gate metal layer in FIG.

[0204] Fig.31B yes Fig.24A An overlay diagram of a first gate metal layer and a second gate metal layer in FIG.

[0205] Fig. 31C yes Fig.24A An overlay diagram of the second gate metal layer and the first source and drain metal layer;

[0206] Fig.31D yes Fig.24A An overlay diagram of a first source-drain metal layer and a second source-drain metal layer;

[0207] Fig.31E yes Fig.24A An overlay diagram of the second source-drain metal layer and the third source-drain metal layer;

[0208] Fig.32A , Fig.32B and Fig.32C yes Fig.14 A second layout diagram of at least one embodiment of the driving circuit shown;

[0209] Fig.33 yes Fig.32A A layout diagram of a first semiconductor layer in;

[0210] Fig.34 yes Fig.32A A layout diagram of the first gate metal layer in FIG.

[0211] Fig.35 yes Fig.32A A layout diagram of a second gate metal layer in FIG.

[0212] Fig.36 yes Fig.32A A layout diagram of a second semiconductor layer in;

[0213] Fig.37 yes Fig.32A A layout diagram of the third gate metal layer in FIG.

[0214] Fig.38 yes Fig.32AA layout diagram of the first source and drain metal layer in FIG.

[0215] Fig.39 yes Fig.32A A layout diagram of a second source / drain metal layer in FIG.

[0216] Fig.40 yes Fig.32A A layout diagram of the third source / drain metal layer in FIG.

[0217] Fig.41A yes Fig.32A A schematic diagram of the superposition of the first semiconductor layer and the first gate metal layer;

[0218] Fig.41B yes Fig.32A A schematic diagram of the superposition of the first gate metal layer and the second gate metal layer;

[0219] Fig.41C yes Fig.32A A schematic diagram of the superposition of the second gate metal layer and the second semiconductor layer;

[0220] Fig.41D yes Fig.32A A schematic diagram of the superposition of the third gate metal layer and the second semiconductor layer;

[0221] Fig.41E yes Fig.32A A schematic diagram of the superposition of the third gate metal layer and the first source and drain metal layer;

[0222] Fig.41F yes Fig.32A A schematic diagram of the superposition of the first source-drain metal layer and the second source-drain metal layer;

[0223] Figure 41G yes Fig.32A A schematic diagram of the superposition of the second source-drain metal layer and the third source-drain metal layer;

[0224] Fig.42A , Fig.42B and Fig.42C yes Fig.17 A first layout diagram of at least one embodiment of the driving circuit shown;

[0225] Fig.43 yes Fig.42A A layout diagram of a first semiconductor layer in;

[0226] Fig.44 yes Fig.42A A layout diagram of the first gate metal layer in FIG.

[0227] Fig.45 yes Fig.42A A layout diagram of a second gate metal layer in FIG.

[0228] Fig.46 yes Fig.42A A layout diagram of the first source and drain metal layer in FIG.

[0229] Fig.47 yes Fig.42A A layout diagram of a second source / drain metal layer in FIG.

[0230] Fig.48 yes Fig.42A A layout diagram of the third source / drain metal layer in FIG.

[0231] Fig.49A yes Fig.42A An overlay diagram of a first semiconductor layer and a first gate metal layer in FIG.

[0232] Fig.49B yes Fig.42A An overlay diagram of a first gate metal layer and a second gate metal layer in FIG.

[0233] Fig.49C yes Fig.42A An overlay diagram of the second gate metal layer and the first source and drain metal layer;

[0234] Fig.49D yes Fig.42A An overlay diagram of a first source-drain metal layer and a second source-drain metal layer;

[0235] Fig.49E yes Fig.42A An overlay diagram of the second source-drain metal layer and the third source-drain metal layer;

[0236] Fig.50A , Fig.50B and Fig.50C yes Fig.17 A second layout diagram of at least one embodiment of the driving circuit shown;

[0237] Fig.51 yes Fig.50A A layout diagram of a first semiconductor layer in;

[0238] Fig.52 yes Fig.50A A layout diagram of the first gate metal layer in FIG.

[0239] Fig.53 yes Fig.50A A layout diagram of a second gate metal layer in FIG.

[0240] Fig.54 yes Fig.50A A layout diagram of a second semiconductor layer in;

[0241] Fig.55 yes Fig.50A A layout diagram of the third gate metal layer in FIG.

[0242] Fig.56 yes Fig.50A A layout diagram of the first source and drain metal layer in FIG.

[0243] Fig.57 yes Fig.50A A layout diagram of a second source / drain metal layer in FIG.

[0244] Fig.58 yes Fig.50A A layout diagram of the third source / drain metal layer in FIG.

[0245] Fig.59A yes Fig.50A A schematic diagram of the superposition of the first semiconductor layer and the first gate metal layer;

[0246] Fig.59B yes Fig.50A A schematic diagram of the superposition of the first gate metal layer and the second gate metal layer;

[0247] Fig.59C yes Fig.50A A schematic diagram of the superposition of the second gate metal layer and the second semiconductor layer;

[0248] Fig.59D yes Fig.50A A schematic diagram of the superposition of the third gate metal layer and the second semiconductor layer;

[0249] Fig.59E yes Fig.50A A schematic diagram of the superposition of the third gate metal layer and the first source and drain metal layer;

[0250] Fig.59F yes Fig.50A A schematic diagram of the superposition of the first source-drain metal layer and the second source-drain metal layer;

[0251] Figure 59G yes Fig.50A A schematic diagram of the superposition of the second source-drain metal layer and the third source-drain metal layer;

[0252] Fig.60A , Fig.60B and Fig.60C yes Fig. 20 A first layout diagram of at least one embodiment of the driving circuit shown;

[0253] Fig.61 yes Fig.60A A layout diagram of a first semiconductor layer in;

[0254] Fig.62 yes Fig.60A A layout diagram of the first gate metal layer in FIG.

[0255] Fig.63 yes Fig.60AA layout diagram of a second gate metal layer in FIG.

[0256] Fig.64 yes Fig.60A A layout diagram of the first source and drain metal layer in FIG.

[0257] Fig.65 yes Fig.60A A layout diagram of a second source / drain metal layer in FIG.

[0258] Fig.66A yes Fig.60A An overlay diagram of a first semiconductor layer and a first gate metal layer in FIG.

[0259] Fig.66B yes Fig.60A An overlay diagram of a first gate metal layer and a second gate metal layer in FIG.

[0260] Fig.66C yes Fig.60A An overlay diagram of the second gate metal layer and the first source and drain metal layer;

[0261] Fig.66D yes Fig.60A An overlay diagram of a first source-drain metal layer and a second source-drain metal layer;

[0262] Fig.67A , Fig.67B and Fig.67C Yes Fig. 20 A second layout diagram of a display substrate of at least one embodiment of the driving circuit shown;

[0263] Fig.68 yes Fig.67A A layout diagram of a first semiconductor layer in;

[0264] Fig.69 yes Fig.67A A layout diagram of the first gate metal layer in FIG.

[0265] Fig.70 yes Fig.67A A layout diagram of a second gate metal layer in FIG.

[0266] Fig.71 yes Fig.67A A layout diagram of a second semiconductor layer in;

[0267] Fig.72 yes Fig.67A A layout diagram of the third gate metal layer in FIG.

[0268] Fig.73 yes Fig.67A A layout diagram of the first source and drain metal layer in FIG.

[0269] Fig.74 yes Fig.67AA layout diagram of a second source / drain metal layer in FIG.

[0270] Fig.75A yes Fig.67A A layout diagram of a first semiconductor layer and a first gate metal layer in the embodiment of the present invention;

[0271] Fig.75B yes Fig.67A A layout diagram of a first gate metal layer and a second gate metal layer in the embodiment of the present invention;

[0272] Fig.75C yes Fig.67A A layout diagram of a second gate metal layer and a second semiconductor layer in the embodiment of the present invention;

[0273] Fig.75D yes Fig.67A A layout diagram of a third gate metal layer and a second semiconductor layer in the embodiment of the present invention;

[0274] Fig.75E yes Fig.67A A layout diagram of the third gate metal layer and the first source and drain metal layer in FIG.

[0275] Fig.75F yes Fig.67A Layout diagram of the first source-drain metal layer and the second source-drain metal layer. DETAILED DESCRIPTION

[0276] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0277] The transistors used in all embodiments of the present invention may be thin film transistors or field effect transistors or other devices with the same characteristics. In the embodiments of the present invention, to distinguish the two electrodes of the transistor except the gate, one electrode is called the first electrode and the other electrode is called the second electrode.

[0278] In actual operation, when the transistor is a thin film transistor or a field effect transistor, the first electrode may be a drain electrode, and the second electrode may be a source electrode; or, the first electrode may be a source electrode, and the second electrode may be a drain electrode.

[0279] like Figure 1 As shown, the driving circuit according to the embodiment of the present invention includes a driving signal generating circuit 11, a control signal generating circuit 12 and a control circuit 13;

[0280] The drive signal generating circuit 11 is electrically connected to the first clock signal line CK and the second clock signal line CB respectively, and is used to generate and output the n-level drive signal through the n-level drive signal output terminal OTn under the control of the first clock signal provided by the first clock signal line CK and the second clock signal provided by the second clock signal line CB; n is a positive integer;

[0281] The control signal generating circuit 12 is electrically connected to the enable signal line EN and the control signal terminal CS respectively, and is used to output a control signal to the control signal terminal CS according to the enable signal provided by the enable signal line EN;

[0282] The control circuit 13 is electrically connected to the control signal terminal CS and the n-th stage driving output terminal DTn, respectively, and is used to output a signal to the n-th stage driving output terminal DTn under the control of the control signal.

[0283] When the driving circuit described in the embodiment of the present invention is working, the driving signal generating circuit 11 outputs the nth level driving signal, the control signal generating circuit 12 generates a control signal according to the enable signal, and the control circuit 13 controls the output of the nth level driving signal or the invalid voltage signal to the nth driving output terminal DTn under the control of the control signal.

[0284] In the related art, the driving circuit usually includes a driving signal generating circuit and a control circuit directly controlled by an enable signal. When the pulse width of the n-th level driving signal provided by the driving signal generating circuit is 1H (1H is a row scanning time), the control circuit directly controlled by the enable signal can be used to control the output of the n-th level driving signal or the invalid voltage signal. However, with the development of pixels, the signals for controlling pixels are diversified, and the pulse width of the n-th level driving signal will exceed 1H, resulting in the n-th level driving signal waveform crossing the change edge (rising edge or falling edge) of the enable signal, resulting in only a portion of the n-th level driving signal being output, which will cause abnormal pixel operation.

[0285] Based on this, the driving circuit described in the embodiment of the present invention is additionally provided with a control signal generating circuit 12, which generates a control signal according to the enable signal, and controls the output of the n-level driving signal or the invalid voltage signal to the n-level driving output terminal DTn through the control signal. In at least one embodiment of the present invention, the control signal generating circuit can generate the control signal according to the enable signal under the control of the n-1-level driving signal, the n-1-level inverted driving signal (the n-1-level inverted driving signal can be inverted with the n-1-level driving signal), the n-level driving signal and the n-level inverted driving signal (the n-level inverted driving signal can be inverted with the n-level driving signal) provided at the n-1-level driving signal output terminal, and the control circuit 13 outputs the n-level driving signal or the invalid voltage signal to the n-level driving output terminal DTn under the control of the control signal, so that even when the pulse width of the n-level driving signal is greater than 1H, the n-level driving signal or the invalid voltage signal can be accurately output to the n-level driving output terminal DTn, so that local refresh can be accurately performed.

[0286] In at least one embodiment of the present invention, the control signal generating circuit is also electrically connected to the n-1th level drive signal output terminal, the n-1th level inverted signal output terminal, the nth level drive signal output terminal and the nth level inverted signal output terminal, respectively, and is used to control the connection or disconnection between the enable signal line and the control signal terminal under the control of the n-1th level drive signal, the n-1th level inverted drive signal, the nth level drive signal and the nth level inverted drive signal.

[0287] like Figure 2 As shown, at least one embodiment of the related pixel circuit includes a first display control transistor M1, a second display control transistor M2, a driving transistor M3, a fourth display control transistor M4, a fifth display control transistor M5, a sixth display control transistor M6, a seventh display control transistor M7, an eighth display control transistor M8, a storage capacitor Cst and an organic light emitting diode O1;

[0288] The gate of M1 is electrically connected to the first reset terminal PR, the source of M1 is electrically connected to the first starting voltage terminal I1, the second electrode of M1 is electrically connected to the drain of M3, and the first starting voltage terminal I1 is used to provide a first starting voltage Vinit1;

[0289] The gate of M2 is electrically connected to the first scanning terminal NT, the source of M2 is electrically connected to the gate of M3, and the drain of M2 is electrically connected to the drain of M3;

[0290] The gate of M4 is electrically connected to the second scanning terminal PT, the source of M4 is electrically connected to the data line DL, and the drain of M4 is electrically connected to the source of M3;

[0291] The gate of M5 is electrically connected to the light emitting control terminal E1, the source of M5 is electrically connected to the high level terminal VDD, and the drain of M5 is electrically connected to the source of M3;

[0292] The gate of M6 is electrically connected to the light emitting control terminal E1, the source of M6 is electrically connected to the drain of M3, the drain of M6 is electrically connected to the anode of O1; the cathode of O1 is electrically connected to the low level terminal VSS;

[0293] The gate of M7 is electrically connected to the second reset terminal HR, the source of M7 is electrically connected to the second initial voltage terminal I2, and the drain of M7 is electrically connected to the anode of O1;

[0294] The gate of M8 is electrically connected to the second reset terminal HR, the source of M8 is electrically connected to the third initial voltage terminal I3, and the drain of M8 is electrically connected to the source of M3;

[0295] The first electrode plate of Cst is electrically connected to the gate of M3, and the second electrode plate of Cst is electrically connected to the high level terminal VDD;

[0296] M1, M3, M4, M5, M6, M7 and M8 are all p-type transistors, and M2 is an n-type transistor.

[0297] In at least one embodiment of the present invention, the n-th stage driving output terminal DTn may be an n-th stage first scanning terminal, an n-th stage second scanning terminal or an n-th stage first reset terminal, but is not limited thereto.

[0298] The driving circuit described in at least one embodiment of the present invention further includes an output inverting circuit;

[0299] The output inversion circuit is electrically connected to the n-th level driving signal output terminal and the n-th level inverted signal output terminal respectively, and is used to invert the n-th level driving signal to obtain and output the n-th level inverted driving signal through the n-th level inverted signal output terminal.

[0300] like Figure 3 As shown, in Figure 1 Based on the embodiment of the driving circuit shown, the driving circuit according to at least one embodiment of the present invention further includes an output inverting circuit 31;

[0301] The output inversion circuit 31 is electrically connected to the n-th level inversion signal output terminal FOn, and is used to invert the n-th level driving signal to obtain and output the n-th level inversion driving signal through the n-th level inversion signal output terminal FOn.

[0302] In at least one embodiment of the present invention, the control circuit includes a first control circuit, a second control circuit and a first energy storage circuit;

[0303] The first control circuit is electrically connected to the control signal terminal, the n-th level drive signal output terminal, the first control voltage line, the second control voltage line and the control output terminal respectively, and is used to control the connection or disconnection between the control output terminal and the first control voltage line under the control of the control signal, control the connection or disconnection between the control output terminal and the first control voltage line under the control of the n-th level drive signal outputted by the n-th level drive signal output terminal, and control the connection or disconnection between the control output terminal and the second control voltage line under the control of the n-th level drive signal and the control signal;

[0304] The second control circuit is electrically connected to the control output terminal, the n-th level driving output terminal, the first voltage line and the second voltage line respectively, and is used to control the connection or disconnection between the n-th level driving output terminal and the first voltage line, and control the connection or disconnection between the n-th level driving output terminal and the second voltage line under the control of the potential of the control output terminal;

[0305] The first energy storage circuit is electrically connected to the control output terminal and is used to maintain the potential of the control output terminal.

[0306] Optionally, the first control voltage line is the first voltage line, and the second control voltage line is the second voltage line; or, the first control voltage line is the second voltage line, and the second control voltage line is the first voltage line.

[0307] like Figure 4 As shown, in Figure 3 Based on at least one embodiment of the driving circuit shown, the control circuit includes a first control circuit 41, a second control circuit 42 and a first energy storage circuit 44;

[0308] The first control circuit 41 is electrically connected to the control signal terminal CS, the n-th drive signal output terminal OTn, the first voltage line V1, the second voltage line V2 and the control output terminal CO, respectively, and is used to control the control output terminal CO to be connected to the first voltage line V1 under the control of the control signal, to control the control output terminal CO to be connected or disconnected to the first voltage line V1 under the control of the n-th level drive signal, and to control the control output terminal CO to be connected or disconnected to the second voltage line V2 under the control of the n-th level drive signal and the control signal;

[0309] The second control circuit 42 is electrically connected to the control output terminal CO, the n-th level driving output terminal DTn, the first voltage line V1 and the second voltage line V2 respectively, and is used to control the connection or disconnection between the n-th level driving output terminal DTn and the first voltage line V1, and control the connection or disconnection between the n-th level driving output terminal DTn and the second voltage line V2 under the control of the potential of the control output terminal CO;

[0310] The first energy storage circuit 44 is electrically connected to the control output terminal CO, and is used to maintain the potential of the control output terminal CO.

[0311] Optionally, the first voltage line may be a high voltage line, and the second voltage line may be a low voltage line, but is not limited thereto.

[0312] like Figure 5 As shown, in Figure 3 Based on at least one embodiment of the driving circuit shown, the control circuit includes a first control circuit 41, a second control circuit 42 and a first energy storage circuit 44;

[0313] The first control circuit 41 is electrically connected to the control signal terminal CS, the n-th drive signal output terminal OTn, the first voltage line V1, the second voltage line V2 and the control output terminal CO, respectively, and is used to control the connection between the control output terminal CO and the second voltage line V2 under the control of the control signal, control the connection or disconnection between the control output terminal CO and the second voltage line V2 under the control of the n-th level drive signal, and control the connection or disconnection between the control output terminal CO and the first voltage line V1 under the control of the n-th level drive signal and the control signal;

[0314] The second control circuit 42 is electrically connected to the control output terminal CO, the n-th level driving output terminal DTn, the first voltage line V1 and the second voltage line V2 respectively, and is used to control the connection or disconnection between the n-th level driving output terminal DTn and the first voltage line V1, and control the connection or disconnection between the n-th level driving output terminal DTn and the second voltage line V2 under the control of the potential of the control output terminal CO;

[0315] The first energy storage circuit 44 is electrically connected to the control output terminal CO, and is used to maintain the potential of the control output terminal CO.

[0316] Optionally, the control circuit further includes a second energy storage circuit;

[0317] The second energy storage circuit is electrically connected to the control signal terminal and is used to maintain the potential of the control signal terminal.

[0318] like Figure 6 As shown, in Figure 4 Based on at least one embodiment of the driving circuit shown, the control circuit further includes a second energy storage circuit 45;

[0319] The second energy storage circuit 45 is electrically connected to the control signal terminal CS, and is used to maintain the potential of the control signal terminal CS.

[0320] like Figure 7 As shown, in Figure 5 Based on at least one embodiment of the driving circuit shown, the control circuit further includes a second energy storage circuit 45;

[0321] The second energy storage circuit 45 is electrically connected to the control signal terminal CS, and is used to maintain the potential of the control signal terminal CS.

[0322] In at least one embodiment of the present invention, the control signal generating circuit is also electrically connected to the n-1th level drive signal output terminal, the n-1th level inverted signal output terminal, the nth level drive signal output terminal and the nth level inverted signal output terminal, respectively, and is used to control the connection or disconnection between the enable signal line and the control signal terminal under the control of the n-1th level drive signal, the n-1th level inverted drive signal, the nth level drive signal and the nth level inverted drive signal.

[0323] like Figure 8 As shown, in Figure 6 On the basis of at least one embodiment of the driving circuit shown, the control signal generating circuit 12 is also electrically connected to the n-1th level driving signal output terminal OTn-1, the n-1th level inverted signal output terminal FTn-1, the n-level driving signal output terminal OTn and the n-level inverted signal output terminal FTn, respectively, and is used to control the connection or disconnection between the enable signal line EN and the control signal terminal CS under the control of the n-1th level driving signal, the n-1th level inverted driving signal, the n-level driving signal and the n-level inverted driving signal.

[0324] like Fig. 9 As shown, in Figure 7 On the basis of at least one embodiment of the driving circuit shown, the control signal generating circuit 12 is also electrically connected to the n-1th level driving signal output terminal OTn-1, the n-1th level inverted signal output terminal FTn-1, the n-level driving signal output terminal OTn and the n-level inverted signal output terminal FTn, respectively, and is used to control the connection or disconnection between the enable signal line EN and the control signal terminal CS under the control of the n-1th level driving signal, the n-1th level inverted driving signal, the n-level driving signal and the n-level inverted driving signal.

[0325] like Fig.10 As shown, in Figure 1Based on at least one embodiment of the driving circuit shown, the control circuit includes a first control circuit 41, a second control circuit 42 and a first energy storage circuit 44;

[0326] The first control circuit 41 is electrically connected to the control signal terminal CS, the n-th drive signal output terminal OTn, the first voltage line V1, the second voltage line V2 and the control output terminal CO, respectively, and is used to control the connection between the control output terminal CO and the second voltage line V2 under the control of the control signal, control the connection or disconnection between the control output terminal CO and the second voltage line V2 under the control of the n-th level drive signal, and control the connection or disconnection between the control output terminal CO and the first voltage line V1 under the control of the n-th level drive signal and the control signal;

[0327] The second control circuit 42 is electrically connected to the control output terminal CO, the n-th level driving output terminal DTn, the first voltage line V1 and the second voltage line V2 respectively, and is used to control the connection or disconnection between the n-th level driving output terminal DTn and the first voltage line V1, and control the connection or disconnection between the n-th level driving output terminal DTn and the second voltage line V2 under the control of the potential of the control output terminal CO;

[0328] The first energy storage circuit 44 is electrically connected to the control output terminal CO, and is used to maintain the potential of the control output terminal CO.

[0329] In at least one embodiment of the present invention, the control signal generating circuit is used to invert the enable signal to generate an inverted enable signal, and output the inverted enable signal through the control signal terminal.

[0330] In a specific implementation, the control signal generating circuit may invert the enable signal to generate an inverted enable signal.

[0331] Optionally, the first control circuit includes a first control transistor, a second control transistor, a third control transistor and a fourth control transistor; the second control circuit includes a fifth control transistor and a sixth control transistor; the first energy storage circuit includes a first capacitor;

[0332] The gate of the first control transistor is electrically connected to the nth stage driving signal output terminal, the first electrode of the first control transistor is electrically connected to the first control voltage line, and the second electrode of the first control transistor is electrically connected to the control output terminal;

[0333] The gate of the second control transistor is electrically connected to the control signal terminal, the first electrode of the second control transistor is electrically connected to the second electrode of the fourth control transistor, and the second electrode of the second control transistor is electrically connected to the second control voltage line;

[0334] The gate of the third control transistor is electrically connected to the control signal terminal, the first electrode of the third control transistor is electrically connected to the first control voltage line, and the second electrode of the third control transistor is electrically connected to the control output terminal;

[0335] The gate of the fourth control transistor is electrically connected to the n-th stage drive signal output terminal, and the first electrode of the fourth control transistor is electrically connected to the control output terminal;

[0336] The gate of the fifth control transistor is electrically connected to the control output terminal, the first electrode of the fifth control transistor is electrically connected to the first voltage line, and the second electrode of the fifth control transistor is electrically connected to the nth driving output terminal;

[0337] The gate of the sixth control transistor is electrically connected to the control output terminal, the first electrode of the sixth control transistor is electrically connected to the nth driving output terminal, and the second electrode of the sixth control transistor is electrically connected to the second voltage line;

[0338] A first end of the first capacitor is electrically connected to the control output end, and a second end of the first capacitor is electrically connected to the second voltage line.

[0339] Optionally, the first control circuit includes a first control transistor, a second control transistor, a third control transistor and a fourth control transistor; the second control circuit includes a fifth control transistor and a sixth control transistor; the first energy storage circuit includes a first capacitor; the first control voltage line is a second voltage line, and the second control voltage line is a first voltage line;

[0340] The gate of the first control transistor is electrically connected to the control signal terminal, the first electrode of the first control transistor is electrically connected to the second electrode of the third control transistor, and the second electrode of the first control transistor is electrically connected to the control output terminal;

[0341] The gate of the second control transistor is electrically connected to the control signal terminal, the first electrode of the second control transistor is electrically connected to the control output terminal, and the second electrode of the second control transistor is electrically connected to the second voltage line;

[0342] The gate of the third control transistor is electrically connected to the nth stage drive signal output terminal, and the first electrode of the third control transistor is electrically connected to the first voltage line;

[0343] The gate of the fourth control transistor is electrically connected to the n-th stage drive signal output terminal, the first electrode of the fourth control transistor is electrically connected to the control output terminal, and the second electrode of the fourth control transistor is electrically connected to the second voltage line;

[0344] The gate of the fifth control transistor is electrically connected to the control output terminal, the first electrode of the fifth control transistor is electrically connected to the first voltage line, and the second electrode of the fifth control transistor is electrically connected to the nth driving output terminal;

[0345] The gate of the sixth control transistor is electrically connected to the control output terminal, the first electrode of the sixth control transistor is electrically connected to the nth driving output terminal, and the second electrode of the sixth control transistor is electrically connected to the second voltage line;

[0346] A first end of the first capacitor is electrically connected to the control output end, and a second end of the first capacitor is electrically connected to the second voltage line.

[0347] Optionally, the second energy storage circuit includes a second capacitor;

[0348] A first end of the second capacitor is electrically connected to the control signal end, and a second end of the second capacitor is electrically connected to the second voltage line.

[0349] Optionally, the control signal generating circuit includes a seventh control transistor, an eighth control transistor, a ninth control transistor and a tenth control transistor;

[0350] The gate of the seventh control transistor is electrically connected to the n-1th stage driving signal output terminal, the first electrode of the seventh control transistor is electrically connected to the enable signal line, and the second electrode of the seventh control transistor is electrically connected to the first electrode of the tenth control transistor;

[0351] The gate of the eighth control transistor is electrically connected to the n-1th stage inverting signal output terminal, the first electrode of the eighth control transistor is electrically connected to the enable signal line, and the second electrode of the eighth control transistor is electrically connected to the first electrode of the ninth control transistor;

[0352] The gate of the ninth control transistor is electrically connected to the nth stage drive signal output terminal, the first electrode of the ninth control transistor is electrically connected to the first electrode of the tenth control transistor, and the second electrode of the ninth control transistor is electrically connected to the control signal terminal;

[0353] The gate of the tenth control transistor is electrically connected to the nth stage inverting signal output terminal, and the second electrode of the tenth control transistor is electrically connected to the control signal terminal;

[0354] The seventh control transistor and the tenth control transistor are both n-type transistors, and the eighth control transistor and the ninth control transistor are both p-type transistors; or,

[0355] The seventh control transistor and the tenth control transistor are both p-type transistors, and the eighth control transistor and the ninth control transistor are both n-type transistors.

[0356] Optionally, the control signal generating circuit includes a seventh control transistor and an eighth control transistor;

[0357] The gate of the seventh control transistor is electrically connected to the enable signal line, the first electrode of the seventh control transistor is electrically connected to the first voltage line, and the second electrode of the seventh control transistor is electrically connected to the control signal terminal;

[0358] The gate of the eighth control transistor is electrically connected to the enable signal line, the first electrode of the eighth control transistor is electrically connected to the control signal terminal, and the second electrode of the eighth control transistor is electrically connected to the second voltage line;

[0359] The seventh control transistor is a p-type transistor, and the eighth control transistor is an n-type transistor; or, the seventh control transistor is an n-type transistor, and the eighth control transistor is a p-type transistor.

[0360] Optionally, the output inverting circuit includes an eleventh control transistor and a twelfth control transistor;

[0361] The gate of the eleventh control transistor is electrically connected to the n-th stage driving signal output terminal, the first electrode of the eleventh control transistor is electrically connected to the n-th stage inverting signal output terminal, and the second electrode of the eleventh control transistor is electrically connected to the second voltage line;

[0362] The gate of the twelfth control transistor is electrically connected to the n-th stage driving signal output terminal, the first electrode of the twelfth control transistor is electrically connected to the first voltage line, and the second electrode of the twelfth control transistor is electrically connected to the n-th stage inverting signal output terminal.

[0363] In at least one embodiment of the present invention, the drive signal generating circuit includes a first node control circuit, a second node control circuit, a first output node control circuit, a second output node control circuit, a potential maintaining circuit and an output circuit; the first clock signal line includes a first first clock signal line, and the second clock signal line includes a first second clock signal line;

[0364] The first node control circuit is electrically connected to the first node, the first first clock signal line, the second voltage line, and the second output node, respectively, and is used to control the connection between the first node and the second voltage line under the control of the first clock signal provided by the first first clock signal line, and to control the connection or disconnection between the first node and the first first clock signal line under the control of the potential of the second output node;

[0365] The second node control circuit is electrically connected to the first node, the first intermediate node, the first voltage line, the first second clock signal line, the second node, the input terminal and the second voltage line respectively, and is used to control the connection between the first intermediate node and the first voltage line under the control of the potential of the first node, control the connection between the first intermediate node and the first second clock signal line under the control of the potential of the second node, and control the potential of the second node according to the potential of the first intermediate node, and control the connection between the input terminal and the second node under the control of the second clock signal provided by the first second clock signal line and the second voltage signal provided by the second voltage line;

[0366] The first output node control circuit is electrically connected to the first output node, the first node, the first second clock signal line, the second intermediate node, the second output node and the first voltage line respectively, and is used to control the second intermediate node to be connected to the first second clock signal line under the control of the potential of the first node, control the potential of the second intermediate node according to the potential of the first node, control the second intermediate node to be connected to the first output node under the control of the second clock signal provided by the first second clock signal line, and control the first output node to be connected to the first voltage line under the control of the potential of the second output node;

[0367] The second output node control circuit is electrically connected to the first second clock signal line, the input terminal, the control voltage line, the first voltage line, the second node, and the second output node, respectively, and is used to control the second output node to be connected to the input terminal under the control of the second clock signal provided by the first second clock signal line, control the potential of the second output node according to the potential of the second node, and control the second output node to be connected to the first voltage line under the control of the control voltage provided by the control voltage line;

[0368] The potential maintaining circuit is electrically connected to the first output node, and is used to maintain the potential of the first output node;

[0369] The output circuit is electrically connected to the first output node, the second output node, the first voltage line, the second voltage line and the n-th level drive signal output terminal, respectively, and is used to control the connection between the n-th level drive signal output terminal and the first voltage line under the control of the potential of the first output node, and to control the connection between the n-th level drive signal output terminal and the second voltage line under the control of the potential of the second output node.

[0370] like Fig.11 As shown, in Figure 8Based on at least one embodiment of the driving circuit shown in FIG. 1 , the driving signal generating circuit includes a first node control circuit 91, a second node control circuit 92, a first output node control circuit 93, a second output node control circuit 94, a potential maintaining circuit 95 and an output circuit 96; the first clock signal line includes a first first clock signal line CK1, and the second clock signal line includes a first second clock signal line CB1;

[0371] The first node control circuit 91 is electrically connected to the first node N1, the first first clock signal line CK1, the second voltage line V2 and the second output node NJ2 respectively, and is used to control the connection between the first node N1 and the second voltage line V2 under the control of the first clock signal provided by the first first clock signal line CK1, and to control the connection or disconnection between the first node N1 and the first first clock signal line CK1 under the control of the potential of the second output node NJ2;

[0372] The second node control circuit 92 is electrically connected to the first node N1, the first intermediate node NZ1, the first voltage line V1, the first second clock signal line CB1, the second node N2, the input terminal I0 and the second voltage line V2, respectively, and is used to control the connection between the first intermediate node NZ1 and the first voltage line V1 under the control of the potential of the first node N1, control the connection between the first intermediate node NZ1 and the first second clock signal line CB1 under the control of the potential of the second node N2, and control the potential of the second node N2 according to the potential of the second intermediate node NZ2, and control the connection between the input terminal I0 and the second node N2 under the control of the second clock signal provided by the first second clock signal line CB1 and the second voltage signal provided by the second voltage line V2;

[0373] The first output node control circuit 93 is electrically connected to the first output node NJ1, the first node N1, the first second clock signal line CB1, the second intermediate node NZ2, the second output node NJ2 and the first voltage line V1, respectively, and is used to control the second intermediate node NZ2 to be connected to the first second clock signal line CB1 under the control of the potential of the first node N1, control the potential of the second intermediate node NZ2 according to the potential of the first node N1, control the second intermediate node NZ2 to be connected to the first output node NJ1 under the control of the second clock signal provided by the first second clock signal line CB1, and control the first output node NJ1 to be connected to the first voltage line V1 under the control of the potential of the second output node NJ2;

[0374] The second output node control circuit 94 is electrically connected to the first second clock signal line CB1, the input terminal I0, the control voltage line VEL, the first voltage line V1, the second node N2 and the second output node NJ2, respectively, and is used to control the second output node NJ2 to be connected to the input terminal I0 under the control of the second clock signal provided by the first second clock signal line CB1, control the potential of the second output node NJ2 according to the potential of the second node N2, and control the second output node NJ2 to be connected to the first voltage line V1 under the control of the control voltage provided by the control voltage line VEL;

[0375] The potential maintaining circuit 95 is electrically connected to the first output node NJ1 and is used to maintain the potential of the first output node NJ1;

[0376] The output circuit 96 is electrically connected to the first output node NJ1, the second output node NJ2, the first voltage line V1, the second voltage line V2 and the n-th level drive signal output terminal OTn, respectively, and is used to control the connection between the n-th level drive signal output terminal OTn and the first voltage line V1 under the control of the potential of the first output node NJ1, and to control the connection between the n-th level drive signal output terminal OTn and the second voltage line V2 under the control of the potential of the second output node NJ2.

[0377] In at least one embodiment of the present invention, the drive signal generating circuit includes a first node control circuit, a second node control circuit, a first output node control circuit, a second output node control circuit, a potential maintaining circuit and an output circuit; the first clock signal line includes a second first clock signal line, and the second clock signal line includes a second second clock signal line;

[0378] The first node control circuit is electrically connected to the first node, the second first clock signal line, the second voltage line, and the second output node, respectively, and is used to control the connection between the first node and the second voltage line under the control of the first clock signal provided by the second first clock signal line, and to control the connection or disconnection between the first node and the second first clock signal line under the control of the potential of the second output node;

[0379] The second node control circuit is electrically connected to the first node, the first intermediate node, the first voltage line, the second second clock signal line, the second node, the input terminal and the second voltage line respectively, and is used to control the connection between the first intermediate node and the first voltage line under the control of the potential of the first node, control the connection between the first intermediate node and the second second clock signal line under the control of the potential of the second node, and control the potential of the second node according to the potential of the first intermediate node, and control the connection between the input terminal and the second node under the control of the second clock signal provided by the second second clock signal line and the second voltage signal provided by the second voltage line;

[0380] The first output node control circuit is electrically connected to the first output node, the first node, the second second clock signal line, the second intermediate node, the second output node and the first voltage line respectively, and is used to control the second intermediate node to be connected to the second second clock signal line under the control of the potential of the first node, control the potential of the second intermediate node according to the potential of the first node, control the second intermediate node to be connected to the first output node under the control of the second clock signal provided by the second second clock signal line, and control the first output node to be connected to the first voltage line under the control of the potential of the second output node;

[0381] The second output node control circuit is electrically connected to the second second clock signal line, the input terminal, the control voltage line, the first voltage line, the second node, and the second output node, respectively, and is used to control the second output node to be connected to the input terminal under the control of the second clock signal provided by the second second clock signal line, control the potential of the second output node according to the potential of the second node, and control the second output node to be connected to the first voltage line under the control of the control voltage provided by the control voltage line;

[0382] The potential maintaining circuit is electrically connected to the first output node, and is used to maintain the potential of the first output node;

[0383] The output circuit is electrically connected to the first output node, the second output node, the first voltage line, the second voltage line and the n-th level drive signal output terminal, respectively, and is used to control the connection between the n-th level drive signal output terminal and the first voltage line under the control of the potential of the first output node, and to control the connection between the n-th level drive signal output terminal and the second voltage line under the control of the potential of the second output node.

[0384] like Fig.12 As shown, in Fig. 9Based on at least one embodiment of the driving circuit shown, the driving signal generating circuit includes a first node control circuit 91, a second node control circuit 92, a first output node control circuit 93, a second output node control circuit 94, a potential maintaining circuit 95 and an output circuit 96;

[0385] The first node control circuit 91 is electrically connected to the first node N1, the second first clock signal line CK2, the second voltage line V2 and the second output node NJ2 respectively, and is used to control the connection between the first node N1 and the second voltage line V2 under the control of the first clock signal provided by the second first clock signal line CK2, and to control the connection or disconnection between the first node N1 and the second first clock signal line CK2 under the control of the potential of the second output node NJ2;

[0386] The second node control circuit 92 is electrically connected to the first node N1, the first intermediate node NZ1, the first voltage line V1, the second second clock signal line CB2, the second node N2, the input terminal I0 and the second voltage line V2, respectively, and is used to control the connection between the first intermediate node NZ1 and the first voltage line V1 under the control of the potential of the first node N1, control the connection between the first intermediate node NZ1 and the second second clock signal line CB2 under the control of the potential of the second node N2, and control the potential of the second node N2 according to the potential of the second intermediate node NZ2, and control the connection between the input terminal and the second node N2 under the control of the second clock signal provided by the second second clock signal line CB2 and the second voltage signal provided by the second voltage line V2;

[0387] The first output node control circuit 93 is electrically connected to the first output node NJ1, the first node N1, the second second clock signal line CB2, the second intermediate node NZ2, the second output node NJ2 and the first voltage line V1, respectively, and is used to control the second intermediate node NZ2 to be connected to the second second clock signal line CB2 under the control of the potential of the first node N1, control the potential of the second intermediate node NZ2 according to the potential of the first node N1, control the second intermediate node NZ2 to be connected to the first output node NJ1 under the control of the second clock signal provided by the second second clock signal line CB2, and control the first output node NJ1 to be connected to the first voltage line V1 under the control of the potential of the second output node NJ2;

[0388] The second output node control circuit 94 is electrically connected to the second second clock signal line CB2, the input terminal I0, the control voltage line VEL, the first voltage line V1, the second node N2 and the second output node NJ2, respectively, and is used to control the second output node NJ2 to be connected to the input terminal I0 under the control of the second clock signal provided by the second second clock signal line CB2, control the potential of the second output node NJ2 according to the potential of the second node N2, and control the second output node NJ2 to be connected to the first voltage line V1 under the control of the control voltage provided by the control voltage line VEL;

[0389] The potential maintaining circuit 95 is electrically connected to the first output node NJ1 and is used to maintain the potential of the first output node NJ1;

[0390] The output circuit 96 is electrically connected to the first output node NJ1, the second output node NJ2, the first voltage line V1, the second voltage line V2 and the n-th level drive signal output terminal OTn, respectively, and is used to control the connection between the n-th level drive signal output terminal OTn and the first voltage line V1 under the control of the potential of the first output node NJ1, and to control the connection between the n-th level drive signal output terminal OTn and the second voltage line V2 under the control of the potential of the second output node NJ2.

[0391] Optionally, the first node control circuit includes a first transistor, a second transistor and a third transistor; the second output node control circuit includes a fourth transistor, a fifth transistor, a sixth transistor and a seventh transistor;

[0392] The gate of the first transistor is electrically connected to the first first clock signal line, the first electrode of the first transistor is electrically connected to the second voltage line, and the second electrode of the first transistor is electrically connected to the first electrode of the third transistor;

[0393] The gate of the second transistor is electrically connected to the second electrode of the fourth transistor, the first electrode of the second transistor is electrically connected to the first first clock signal line, and the second electrode of the second transistor is electrically connected to the first electrode of the third transistor;

[0394] The gate of the third transistor is electrically connected to the second voltage line, and the second electrode of the third transistor is electrically connected to the first node;

[0395] The gate of the fourth transistor is electrically connected to the first first clock signal line, and the first electrode of the fourth transistor is electrically connected to the input terminal;

[0396] The gate of the fifth transistor is electrically connected to the second voltage line, the first electrode of the fifth transistor is electrically connected to the second electrode of the fourth transistor, and the second electrode of the fifth transistor is electrically connected to the second output node;

[0397] The gate of the sixth transistor and the first electrode of the sixth transistor are both electrically connected to the second node, and the second electrode of the sixth transistor is electrically connected to the second output node;

[0398] The gate of the seventh transistor is electrically connected to the control voltage line, the first electrode of the seventh transistor is electrically connected to the first voltage line, and the second electrode of the seventh transistor is electrically connected to the first electrode of the fifth transistor;

[0399] The second node control circuit includes an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor and a third capacitor;

[0400] The gate of the eighth transistor is electrically connected to the second node, the first electrode of the eighth transistor is electrically connected to the first second clock signal line, and the second electrode of the eighth transistor is electrically connected to the first intermediate node;

[0401] The gate of the ninth transistor is electrically connected to the second electrode of the first transistor, the first electrode of the ninth transistor is electrically connected to the first voltage line, and the second electrode of the ninth transistor is electrically connected to the first intermediate node;

[0402] The gate of the tenth transistor is electrically connected to the first first clock signal line, the first electrode of the tenth transistor is electrically connected to the input terminal, and the second electrode of the tenth transistor is electrically connected to the first electrode of the eleventh transistor;

[0403] The gate of the eleventh transistor is electrically connected to the second voltage line, and the second electrode of the eleventh transistor is electrically connected to the second node;

[0404] The first electrode plate of the third capacitor is electrically connected to the second node, and the second electrode plate of the third capacitor is electrically connected to the first intermediate node;

[0405] The first output node control circuit includes a twelfth transistor, a thirteenth transistor, a fourteenth transistor and a fourth capacitor;

[0406] The gate of the twelfth transistor is electrically connected to the first node, the first electrode of the twelfth transistor is electrically connected to the first second clock signal line, and the second electrode of the twelfth transistor is electrically connected to the second intermediate node;

[0407] The gate of the thirteenth transistor is electrically connected to the first second clock signal line, the first electrode of the thirteenth transistor is electrically connected to the second intermediate node, and the second electrode of the thirteenth transistor is electrically connected to the first output node;

[0408] The gate of the fourteenth transistor is electrically connected to the first electrode of the fifth transistor, the first electrode of the fourteenth transistor is electrically connected to the first voltage line, and the second electrode of the fourteenth transistor is electrically connected to the first output node;

[0409] The first electrode plate of the fourth capacitor is electrically connected to the first node, and the second electrode plate of the fourth capacitor is electrically connected to the second intermediate node;

[0410] The potential maintaining circuit includes a fifth capacitor;

[0411] The first plate of the fifth capacitor is electrically connected to the first output node, and the second plate of the fifth capacitor is electrically connected to the first voltage line;

[0412] The output circuit includes a fifteenth transistor and a sixteenth transistor;

[0413] The gate of the fifteenth transistor is electrically connected to the first output node, the first electrode of the fifteenth transistor is electrically connected to the first voltage line, and the second electrode of the fifteenth transistor is electrically connected to the n-th stage driving signal output terminal;

[0414] A gate of the sixteenth transistor is electrically connected to the second output node, a first electrode of the sixteenth transistor is electrically connected to the nth stage driving signal output terminal, and a second electrode of the sixteenth transistor is electrically connected to the second voltage line.

[0415] Optionally, the first node control circuit includes a first transistor, a second transistor and a third transistor; the second output node control circuit includes a fourth transistor, a fifth transistor, a sixth transistor and a seventh transistor;

[0416] The gate of the first transistor is electrically connected to the second first clock signal line, the first electrode of the first transistor is electrically connected to the second voltage line, and the second electrode of the first transistor is electrically connected to the first electrode of the third transistor;

[0417] The gate of the second transistor is electrically connected to the second electrode of the fourth transistor, the first electrode of the second transistor is electrically connected to the second first clock signal line, and the second electrode of the second transistor is electrically connected to the first electrode of the third transistor;

[0418] The gate of the third transistor is electrically connected to the second voltage line, and the second electrode of the third transistor is electrically connected to the first node;

[0419] The gate of the fourth transistor is electrically connected to the second first clock signal line, and the first electrode of the fourth transistor is electrically connected to the input terminal;

[0420] The gate of the fifth transistor is electrically connected to the second voltage line, the first electrode of the fifth transistor is electrically connected to the second electrode of the fourth transistor, and the second electrode of the fifth transistor is electrically connected to the second output node;

[0421] The gate of the sixth transistor and the first electrode of the sixth transistor are both electrically connected to the second node, and the second electrode of the sixth transistor is electrically connected to the second output node;

[0422] The gate of the seventh transistor is electrically connected to the control voltage line, the first electrode of the seventh transistor is electrically connected to the first voltage line, and the second electrode of the seventh transistor is electrically connected to the first electrode of the fifth transistor;

[0423] The second node control circuit includes an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor and a third capacitor;

[0424] The gate of the eighth transistor is electrically connected to the second node, the first electrode of the eighth transistor is electrically connected to the second second clock signal line, and the second electrode of the eighth transistor is electrically connected to the first intermediate node;

[0425] The gate of the ninth transistor is electrically connected to the second electrode of the first transistor, the first electrode of the ninth transistor is electrically connected to the first voltage line, and the second electrode of the ninth transistor is electrically connected to the first intermediate node;

[0426] The gate of the tenth transistor is electrically connected to the second first clock signal line, the first electrode of the tenth transistor is electrically connected to the input terminal, and the second electrode of the tenth transistor is electrically connected to the first electrode of the eleventh transistor;

[0427] The gate of the eleventh transistor is electrically connected to the second voltage line, and the second electrode of the eleventh transistor is electrically connected to the second node;

[0428] The first electrode plate of the third capacitor is electrically connected to the second node, and the second electrode plate of the third capacitor is electrically connected to the first intermediate node;

[0429] The first output node control circuit includes a twelfth transistor, a thirteenth transistor, a fourteenth transistor and a fourth capacitor;

[0430] The gate of the twelfth transistor is electrically connected to the first node, the first electrode of the twelfth transistor is electrically connected to the second second clock signal line, and the second electrode of the twelfth transistor is electrically connected to the second intermediate node;

[0431] The gate of the thirteenth transistor is electrically connected to the second second clock signal line, the first electrode of the thirteenth transistor is electrically connected to the second intermediate node, and the second electrode of the thirteenth transistor is electrically connected to the first output node;

[0432] The gate of the fourteenth transistor is electrically connected to the first electrode of the fifth transistor, the first electrode of the fourteenth transistor is electrically connected to the first voltage line, and the second electrode of the fourteenth transistor is electrically connected to the first output node;

[0433] The first electrode plate of the fourth capacitor is electrically connected to the first node, and the second electrode plate of the fourth capacitor is electrically connected to the second intermediate node;

[0434] The potential maintaining circuit includes a fifth capacitor;

[0435] The first plate of the fifth capacitor is electrically connected to the first output node, and the second plate of the fifth capacitor is electrically connected to the first voltage line;

[0436] The output circuit includes a fifteenth transistor and a sixteenth transistor;

[0437] The gate of the fifteenth transistor is electrically connected to the first output node, the first electrode of the fifteenth transistor is electrically connected to the first voltage line, and the second electrode of the fifteenth transistor is electrically connected to the n-th stage driving signal output terminal;

[0438] A gate of the sixteenth transistor is electrically connected to the second output node, a first electrode of the sixteenth transistor is electrically connected to the nth stage driving signal output terminal, and a second electrode of the sixteenth transistor is electrically connected to the second voltage line.

[0439] In at least one embodiment of the present invention, the drive signal generating circuit includes a first output node control circuit, a second output node control circuit, a third energy storage circuit and an output circuit; the first clock signal line includes a third first clock signal line, and the second clock signal line includes a third second clock signal line;

[0440] The first output node control circuit is electrically connected to the third first clock signal line, the second voltage line and the second output node respectively, and is used to control the first output node to be connected to the second voltage line under the control of the first clock signal provided by the third first clock signal line, and to control the first output node to be connected to the third first clock signal line under the control of the potential of the second output node, and to maintain the potential of the first output node;

[0441] The second output node control circuit is electrically connected to the second output node, the third first clock signal line, the input terminal, the third second clock signal line, the first output node and the first voltage line respectively, and is used to control the second output node to be connected to the input terminal under the control of the first clock signal, and to control the second output node to be connected to the first voltage line under the control of the potential of the first output node and the second clock signal provided by the third second clock signal line;

[0442] The first end of the third energy storage circuit is electrically connected to the second output node, the second end of the third energy storage circuit is electrically connected to the n-th stage drive signal output terminal, and the third energy storage circuit is used to store electric energy;

[0443] The output circuit is electrically connected to the first output node, the second output node, the first voltage line, the second clock signal and the n-th level drive signal output terminal, respectively, and is used to control the connection between the n-th level drive signal output terminal and the first voltage line under the control of the potential of the first output node, and to control the connection between the n-th level drive signal output terminal and the third second clock signal line under the control of the potential of the second output node.

[0444] like Fig.13 As shown, in Fig.10 Based on at least one embodiment of the driving circuit shown in FIG. 1 , the driving signal generating circuit includes a first output node control circuit 93, a second output node control circuit 94, a third energy storage circuit 90 and an output circuit 96; the first clock signal line includes a third first clock signal line CK3, and the second clock signal line includes a third second clock signal line CB3;

[0445] The first output node control circuit 93 is electrically connected to the third first clock signal line CK3, the second voltage line V2, the first output node NJ1 and the second output node NJ2 respectively, and is used to control the connection between the first output node NJ1 and the second voltage line V2 under the control of the first clock signal provided by the third first clock signal line CK3, and to control the connection between the first output node NJ1 and the first clock signal line CK under the control of the potential of the second output node NJ2, and to maintain the potential of the first output node NJ1;

[0446] The second output node control circuit 94 is electrically connected to the second output node NJ2, the third first clock signal line CK3, the input terminal I0, the third second clock signal line CB3, the first output node NJ1 and the first voltage line V1, respectively, and is used to control the second output node NJ2 to be connected to the input terminal I0 under the control of the first clock signal, and to control the second output node NJ2 to be connected to the first voltage line V1 under the control of the potential of the first output node NJ1 and the second clock signal provided by the third second clock signal line CB3;

[0447] A first end of the third energy storage circuit 90 is electrically connected to the second output node NJ2, a second end of the third energy storage circuit 90 is electrically connected to the n-th stage drive signal output terminal OTn, and the third energy storage circuit 90 is used to store electric energy;

[0448] The output circuit 96 is electrically connected to the first output node NJ1, the second output node NJ2, the first voltage line V1, the second clock signal CB and the n-th level drive signal output terminal OTn, respectively, and is used to control the connection between the n-th level drive signal output terminal OTn and the first voltage line V1 under the control of the potential of the first output node NJ1, and to control the connection between the n-th level drive signal output terminal OTn and the third second clock signal line CB3 under the control of the potential of the second output node NJ2.

[0449] Optionally, the first output node control circuit includes a seventeenth transistor, an eighteenth transistor and a sixth capacitor;

[0450] The gate of the seventeenth transistor is electrically connected to the third first clock signal line, the first electrode of the seventeenth transistor is electrically connected to the second voltage line, and the second electrode of the seventeenth transistor is electrically connected to the first output node;

[0451] A gate of the eighteenth transistor is electrically connected to the second output node, a first electrode of the eighteenth transistor is electrically connected to the third first clock signal line, and a second electrode of the eighteenth transistor is electrically connected to the first output node;

[0452] The first plate of the sixth capacitor is electrically connected to the first output node, and the second plate of the sixth capacitor is electrically connected to the first voltage line;

[0453] The second output node control circuit includes a nineteenth transistor, a twentieth transistor, and a twenty-first transistor; the third energy storage circuit includes a seventh capacitor;

[0454] The gate of the nineteenth transistor is electrically connected to the third first clock signal line, the first electrode of the nineteenth transistor is electrically connected to the input terminal, and the second electrode of the nineteenth transistor is electrically connected to the second output node;

[0455] A gate of the 20th transistor is electrically connected to the first output node, a first electrode of the 20th transistor is electrically connected to the first voltage line, and a second electrode of the 20th transistor is electrically connected to a first electrode of the 21st transistor;

[0456] A gate of the twenty-first transistor is electrically connected to the third second clock signal line, and a second electrode of the twenty-first transistor is electrically connected to the second output node;

[0457] The first electrode plate of the seventh capacitor is electrically connected to the second output node, and the second electrode plate of the seventh capacitor is electrically connected to the n-th level driving signal output terminal;

[0458] The output circuit includes a twenty-second transistor and a twenty-third transistor;

[0459] A gate of the 22nd transistor is electrically connected to the first output node, a first electrode of the 22nd transistor is electrically connected to the first voltage line, and a second electrode of the 22nd transistor is electrically connected to the nth stage driving signal output terminal;

[0460] a gate of the twenty-third transistor is electrically connected to the second output node, a first electrode of the twenty-third transistor is electrically connected to the n-th stage driving signal output terminal, and a second electrode of the twenty-third transistor is electrically connected to the third second clock signal line;

[0461] The driving circuit further includes a twenty-fourth transistor;

[0462] The second electrode of the 21st transistor is electrically connected to the second output node through the 24th transistor; the gate of the 24th transistor is electrically connected to the second voltage line, the first electrode of the 24th transistor is electrically connected to the second electrode of the 21st transistor, and the second electrode of the 24th transistor is electrically connected to the second output node.

[0463] like Fig.14 As shown, in Fig.11 Based on at least one embodiment of the driving circuit shown, the n-th stage driving output terminal is the n-th stage first scanning terminal NTn;

[0464] The first control circuit includes a first control transistor CT1, a second control transistor CT2, a third control transistor CT3 and a fourth control transistor CT4; the second control circuit includes a fifth control transistor CT5 and a sixth control transistor CT6; the first energy storage circuit includes a first capacitor CC1;

[0465] The gate of the first control transistor CT1 is electrically connected to the n-th stage drive signal output terminal OTn, the source of the first control transistor CT1 is electrically connected to the high voltage line VGH, and the drain of the first control transistor CT1 is electrically connected to the control output terminal CO;

[0466] The gate of the second control transistor CT2 is electrically connected to the control signal terminal CS, the source of the second control transistor CT2 is electrically connected to the drain of the fourth control transistor CT4, and the drain of the second control transistor CT2 is electrically connected to the low voltage line VGL;

[0467] The gate of the third control transistor CT3 is electrically connected to the control signal terminal CS, the source of the third control transistor CT3 is electrically connected to the high voltage line VGH, and the drain of the third control transistor CT3 is electrically connected to the control output terminal CO;

[0468] The gate of the fourth control transistor CT4 is electrically connected to the n-th stage drive signal output terminal OTn, and the source of the fourth control transistor CT4 is electrically connected to the control output terminal CO;

[0469] The gate of the fifth control transistor CT5 is electrically connected to the control output terminal CO, the source of the fifth control transistor CT5 is electrically connected to the high voltage line VGH, and the drain of the fifth control transistor CT5 is electrically connected to the n-th stage first scanning terminal NTn;

[0470] The gate of the sixth control transistor CT6 is electrically connected to the control output terminal CO, the source of the sixth control transistor CT6 is electrically connected to the n-th stage first scanning terminal NTn, and the drain of the sixth control transistor CT6 is electrically connected to the low voltage line VGL;

[0471] A first end of the first capacitor CC1 is electrically connected to the control output terminal CO, and a second end of the first capacitor CC1 is electrically connected to the low voltage line VGL;

[0472] The second energy storage circuit includes a second capacitor CC2;

[0473] A first end of the second capacitor CC2 is electrically connected to the control signal terminal CS, and a second end of the second capacitor CC2 is electrically connected to the low voltage line VGL;

[0474] The control signal generating circuit includes a seventh control transistor CT7, an eighth control transistor CT8, a ninth control transistor CT9 and a tenth control transistor CT10;

[0475] The gate of the seventh control transistor CT7 is electrically connected to the n-1th stage drive signal output terminal OTn-1, the source of the seventh control transistor CT7 is electrically connected to the enable signal line EN, and the drain of the seventh control transistor CT7 is electrically connected to the source of the tenth control transistor CT10;

[0476] The gate of the eighth control transistor CT8 is electrically connected to the n-1th stage inverting signal output terminal FTn-1, the source of the eighth control transistor CT8 is electrically connected to the enable signal line EN, and the drain of the eighth control transistor CT8 is electrically connected to the source of the ninth control transistor CT9;

[0477] The gate of the ninth control transistor CT9 is electrically connected to the n-th stage drive signal output terminal OTn, the source of the ninth control transistor CT9 is electrically connected to the source of the tenth control transistor CT10, and the drain of the ninth control transistor CT9 is electrically connected to the control signal terminal CS;

[0478] The gate of the tenth control transistor CT10 is electrically connected to the n-th stage inverting signal output terminal FTn, and the drain of the tenth control transistor CT10 is electrically connected to the control signal terminal CS;

[0479] The output inverting circuit includes an eleventh control transistor CT11 and a twelfth control transistor CT12;

[0480] The gate of the eleventh control transistor CT11 is electrically connected to the n-th stage driving signal output terminal OTn, the source of the eleventh control transistor CT11 is electrically connected to the n-th stage inverting signal output terminal FTn, and the drain of the eleventh control transistor CT11 is electrically connected to the low voltage line VGL;

[0481] The gate of the twelfth control transistor CT12 is electrically connected to the n-th stage drive signal output terminal OTn, the source of the twelfth control transistor CT12 is electrically connected to the high voltage line VGH, and the drain of the twelfth control transistor CT12 is electrically connected to the n-th stage inverting signal output terminal FTn;

[0482] The first node control circuit includes a first transistor T1, a second transistor T2 and a third transistor T3; the second output node control circuit includes a fourth transistor T4, a fifth transistor T5, a sixth transistor T6 and a seventh transistor T7;

[0483] The gate of the first transistor T1 is electrically connected to the first first clock signal line CK1, the source of the first transistor T1 is electrically connected to the low voltage line VGL, and the drain of the first transistor T1 is electrically connected to the source of the third transistor T3;

[0484] The gate of the second transistor T2 is electrically connected to the drain of the fourth transistor T4, the source of the second transistor T2 is electrically connected to the first first clock signal line CK1, and the drain of the second transistor T2 is electrically connected to the source of the third transistor T3;

[0485] A gate of the third transistor T3 is electrically connected to the low voltage line VGL, and a drain of the third transistor T3 is electrically connected to the first node N1;

[0486] The gate of the fourth transistor T4 is electrically connected to the first first clock signal line CK1, and the source of the fourth transistor T4 is electrically connected to the input terminal I0;

[0487] The gate of the fifth transistor T5 is electrically connected to the low voltage line VGL, the source of the fifth transistor T5 is electrically connected to the drain of the fourth transistor T4, and the drain of the fifth transistor T5 is electrically connected to the second output node NJ2;

[0488] The gate of the sixth transistor T6 and the source of the sixth transistor T6 are both electrically connected to the second node N2, and the drain of the sixth transistor T6 is electrically connected to the second output node NJ2;

[0489] The gate of the seventh transistor T7 is electrically connected to the control voltage line VEL, the source of the seventh transistor T7 is electrically connected to the high voltage line VGH, and the drain of the seventh transistor T7 is electrically connected to the source of the fifth transistor T5;

[0490] The second node control circuit includes an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, an eleventh transistor T11 and a third capacitor C3;

[0491] The gate of the eighth transistor T8 is electrically connected to the second node N2, the source of the eighth transistor T8 is electrically connected to the first second clock signal line CB1, and the drain of the eighth transistor T8 is electrically connected to the first intermediate node NZ1;

[0492] The gate of the ninth transistor T9 is electrically connected to the drain of the first transistor T1, the source of the ninth transistor T9 is electrically connected to the high voltage line VGH, and the drain of the ninth transistor T9 is electrically connected to the first intermediate node NZ1;

[0493] The gate of the tenth transistor T10 is electrically connected to the first first clock signal line CK1, the source of the tenth transistor T10 is electrically connected to the input terminal I0, and the drain of the tenth transistor T10 is electrically connected to the source of the eleventh transistor T11;

[0494] A gate of the eleventh transistor T11 is electrically connected to the low voltage line VGL, and a drain of the eleventh transistor T11 is electrically connected to the second node N2;

[0495] The first plate of the third capacitor C3 is electrically connected to the second node N2, and the second plate of the third capacitor C3 is electrically connected to the first intermediate node NZ1;

[0496] The first output node control circuit includes a twelfth transistor T12, a thirteenth transistor T13, a fourteenth transistor T14 and a fourth capacitor C4;

[0497] The gate of the twelfth transistor T12 is electrically connected to the first node N1, the source of the twelfth transistor T12 is electrically connected to the first second clock signal line CB1, and the drain of the twelfth transistor T12 is electrically connected to the second intermediate node NZ2;

[0498] The gate of the thirteenth transistor T13 is electrically connected to the first second clock signal line CB1, the source of the thirteenth transistor T13 is electrically connected to the second intermediate node NZ2, and the drain of the thirteenth transistor T13 is electrically connected to the first output node NJ1;

[0499] The gate of the fourteenth transistor T14 is electrically connected to the source of the fifth transistor T5, the source of the fourteenth transistor T14 is electrically connected to the high voltage line VGH, and the drain of the fourteenth transistor T14 is electrically connected to the first output node NJ1;

[0500] The first plate of the fourth capacitor C4 is electrically connected to the first node N1, and the second plate of the fourth capacitor C4 is electrically connected to the second intermediate node NZ2;

[0501] The potential maintaining circuit includes a fifth capacitor C5;

[0502] The first plate of the fifth capacitor C5 is electrically connected to the first output node NJ1, and the second plate of the fifth capacitor C5 is electrically connected to the high voltage line VGH;

[0503] The output circuit includes a fifteenth transistor T15 and a sixteenth transistor T16;

[0504] The gate of the fifteenth transistor T15 is electrically connected to the first output node NJ1, the source of the fifteenth transistor T15 is electrically connected to the high voltage line VGH, and the drain of the fifteenth transistor T15 is electrically connected to the n-th stage driving signal output terminal OTn;

[0505] The gate of the sixteenth transistor T16 is electrically connected to the second output node NJ2, the source of the sixteenth transistor T16 is electrically connected to the n-th stage driving signal output terminal OTn, and the drain of the sixteenth transistor T16 is electrically connected to the low voltage line VGL.

[0506] exist Fig.14 In at least one embodiment of the driving circuit shown, T1-T16 can be p-type transistors, CT11 is an n-type transistor, CT12 is a p-type transistor, CT7 is an n-type transistor, CT8 is a p-type transistor, CT10 is an n-type transistor, CT9 is a p-type transistor, CT1 is a p-type transistor, CT2 is an n-type transistor, CT3 is a p-type transistor, CT4 is an n-type transistor, CT5 is a p-type transistor, and CT6 is an n-type transistor.

[0507] exist Fig.14 In at least one embodiment of the driving circuit shown, the driving signal generating circuit is a 16T3C circuit. In actual operation, the driving signal generating circuit may also adopt a circuit with other structures for generating an n-th level driving signal.

[0508] exist Fig.14 In at least one embodiment of the driving circuit shown, T3 and T5 may not be provided.

[0509] Fig.15 yes Fig.14 FIG. 1 is a timing diagram showing the operation of a driving signal generating circuit in at least one embodiment of the driving circuit shown.

[0510] Fig.14 When at least one embodiment of the driving circuit shown is in operation, when the display device including the driving circuit just starts to operate, VEL provides a low voltage signal and T7 is turned on to control the connection between the gate of T14 and VGH, so that T14 is turned off; thereafter, when the driving circuit is operating, VEL always provides a high voltage signal, so that T7 is turned off.

[0511] Fig.16 is a working timing diagram of at least one embodiment of the n-1th stage driving circuit and at least one embodiment of the nth stage driving circuit; the structure of the nth stage driving circuit is as follows Fig.14 As shown;

[0512] The structure of the n-1th stage driving circuit is Fig.14 The structure of the n-th level driving circuit is the same as that of the n-1-th level driving circuit. Fig.14 The differences in the nth level drive circuit shown include:

[0513] The drain of T15 is electrically connected to the n-1th stage driving signal output terminal OTn-1, and the drain of CT12 is electrically connected to the n-1th stage inverting signal output terminal FTn-1;

[0514] The gate of CT9 is electrically connected to the n-2th level drive signal output terminal OTn-2, the gate of CT8 is electrically connected to the n-2th level inverting signal output terminal FTn-2, the gate of CT10 is electrically connected to the n-1th level inverting signal output terminal FTn-1, the gate of CT7, the gate of CT3 and the gate of CT4 are electrically connected to the n-1th level drive signal output terminal OTn-1, and the drain of CT5 is electrically connected to the n-1th level first scanning terminal NTn-1.

[0515] like Fig.16 As shown, when at least one embodiment of the n-1th stage driving circuit and at least one embodiment of the nth stage driving circuit are working,

[0516] In the first stage t1, EN outputs a high voltage signal, OTn-2 provides a high voltage signal, FTn-2 provides a low voltage signal, OTn-1 provides a low voltage signal, FTn-1 provides a high voltage signal, OTn provides a low voltage signal, and FTn provides a high voltage signal;

[0517] In the n-1th level driving circuit, CT7 and CT8 are turned on, CT9 and CT10 are turned on, EN is connected to CS, and the potential of CS is high voltage; OTn-1 provides a low voltage signal, CT1 is turned on, CO outputs a high voltage signal, CT4 is turned off, CT6 is turned on, CT5 is turned off, and NTn-1 outputs a low voltage signal;

[0518] In the nth stage driving circuit, CT7 and CT8 are turned off, EN is disconnected from CS; OTn provides a low voltage signal, CT1 is turned on, CO outputs a high voltage signal, CT6 is turned on, and NTn outputs a low voltage signal;

[0519] In the second stage t2, EN provides a high voltage signal, OTn-2 provides a high voltage signal, FTn-2 provides a low voltage signal, OTn-1 provides a high voltage signal, FTn-1 provides a low voltage signal, OTn provides a low voltage signal, and FTn provides a high voltage signal;

[0520] In the n-1th level driving circuit, CT7 and CT8 are turned on, CT9 and CT10 are turned off, EN is disconnected from CS, and the potential of CS is maintained at a high voltage; CT3 is turned off, OTn-1 provides a high voltage signal, CT4 is turned on, CT2 is turned on, CO outputs a low voltage signal, CT5 is turned on, and NTn-1 provides a high voltage signal;

[0521] In the nth level driving circuit, CT7 and CT8 are turned on, CT9 and CT10 are turned on, EN is connected to CS, the potential of CS is a high voltage signal, CT3 is turned off, OTn outputs a low voltage signal, CT1 is turned on, CO outputs a high voltage signal, CT6 is turned on, and NTn provides a low voltage signal;

[0522] In the third stage t3, EN provides a low voltage signal, OTn-2 provides a low voltage signal, FTn-2 provides a high voltage signal, OTn-1 provides a high voltage signal, FTn-1 provides a low voltage signal, OTn provides a high voltage signal, and FTn provides a low voltage signal;

[0523] In the n-1th level driving circuit, CT7 and CT8 are turned off, EN is disconnected from CS, CC2 maintains the potential of CS at a high voltage; OTn-1 provides a high voltage signal, CT2 and CT4 are turned on, CO outputs a low voltage signal, CT5 is turned on, and NTn-1 provides a high voltage signal;

[0524] In the nth level driving circuit, CT9 and CT10 are turned off, EN is disconnected from CS, the potential of CS is high voltage, OTn provides a high voltage signal, CT2 and CT4 are both turned on, CO outputs a high voltage signal, CT6 is turned on, and NTn provides a low voltage signal;

[0525] In the fourth stage t4, EN provides a low voltage signal, OTn-2 provides a low voltage signal, FTn-2 provides a high voltage signal, OTn-1 provides a low voltage signal, FTn-1 provides a high voltage signal, OTn provides a high voltage signal, and FTn provides a low voltage signal;

[0526] In the n-1th level driving circuit, CT7 and CT8 are turned off, EN is disconnected from CS, and CC2 maintains the potential of CS at a low voltage; OTn-1 provides a low voltage signal, CT1 is turned on, CO outputs a high voltage signal, CT6 is turned on, and NTn-1 provides a low voltage signal;

[0527] In the nth stage driving circuit, CT7 and CT8 are turned off, EN is disconnected from CS, the potential of CS is high voltage, OTn provides a high voltage signal, CT2 and CT4 are both turned on, CO outputs a high voltage signal, CT6 is turned on, and NTn provides a low voltage signal;

[0528] In the fifth stage t5, EN provides a low voltage signal, OTn-2 provides a low voltage signal, FTn-2 provides a high voltage signal, OTn-1 provides a low voltage signal, FTn-1 provides a high voltage signal, OTn provides a low voltage signal, and FTn provides a high voltage signal;

[0529] In the n-1th level driving circuit, CT7 and CT8 are turned off, EN is disconnected from CS, CC2 maintains the potential of CS at a low voltage; CT3 is turned on, CO outputs a high voltage signal, CT6 is turned on, and NTn-1 provides a low voltage signal;

[0530] In the nth stage driving circuit, CT7 and CT8 are turned off, EN is disconnected from CS, the potential of CS is high voltage, OTn provides a low voltage signal, CT1 is turned on, CO outputs a high voltage signal, CT6 is turned on, and NTn provides a low voltage signal.

[0531] like Fig.16 As shown, NTn provides an invalid voltage signal, and NTn-1 provides a valid first scanning signal of the n-1th level, which can control the transistor whose gate is electrically connected to NTn in the pixel circuit of the n-th row to be turned off so as not to perform scanning; when the potential of the first scanning signal of the n-1th level is a valid voltage, the transistor whose gate is electrically connected to NTn-1 in the pixel circuit of the n-1th row is controlled to be turned on so as to perform normal scanning; so as to achieve the purpose of partial refresh;

[0532] Since the transistor in the pixel circuit electrically connected to NTn is an n-type transistor, the invalid voltage signal provided by NTn is a low voltage signal.

[0533] like Fig.17 As shown, in Fig.12 Based on at least one embodiment of the driving circuit shown, the n-th stage driving output terminal is the n-th stage first reset terminal PRn;

[0534] The first control circuit includes a first control transistor CT1, a second control transistor CT2, a third control transistor CT3 and a fourth control transistor CT4; the second control circuit includes a fifth control transistor CT5 and a sixth control transistor CT6; the first energy storage circuit includes a first capacitor CC1; the first control voltage line is a second voltage line, and the second control voltage line is a first voltage line;

[0535] The gate of the first control transistor CT1 is electrically connected to the control signal terminal CS, the source of the first control transistor CT1 is electrically connected to the drain of the third control transistor CT3, and the drain of the first control transistor CT1 is electrically connected to the control output terminal CO;

[0536] The gate of the second control transistor CT2 is electrically connected to the control signal terminal CS, the source of the second control transistor CT2 is electrically connected to the control output terminal CO, and the drain of the second control transistor CT2 is electrically connected to the low voltage line VGL;

[0537] The gate of the third control transistor CT3 is electrically connected to the n-th stage drive signal output terminal OTn, and the source of the third control transistor CT3 is electrically connected to the high voltage line VGH;

[0538] The gate of the fourth control transistor CT4 is electrically connected to the n-th stage drive signal output terminal OTn, the source of the fourth control transistor CT4 is electrically connected to the control output terminal CO, and the drain of the fourth control transistor CT4 is electrically connected to the low voltage line VGL;

[0539] The gate of the fifth control transistor CT5 is electrically connected to the control output terminal CO, the source of the fifth control transistor CT5 is electrically connected to the high voltage line VGH, and the drain of the fifth control transistor CT5 is electrically connected to the n-th stage first reset terminal PRn;

[0540] The gate of the sixth control transistor CT6 is electrically connected to the control output terminal CO, the source of the sixth control transistor CT6 is electrically connected to the n-th stage first reset terminal PRn, and the drain of the sixth control transistor CT6 is electrically connected to the low voltage line VGL;

[0541] A first end of the first capacitor CC1 is electrically connected to the control output terminal CO, and a second end of the first capacitor CC1 is electrically connected to the low voltage line VGL;

[0542] The second energy storage circuit includes a second capacitor CC2;

[0543] A first end of the second capacitor CC2 is electrically connected to the control signal terminal CS, and a second end of the second capacitor CC2 is electrically connected to the low voltage line VGL;

[0544] The control signal generating circuit includes a seventh control transistor CT7, an eighth control transistor CT8, a ninth control transistor CT9 and a tenth control transistor CT10;

[0545] The gate of the seventh control transistor CT7 is electrically connected to the n-1th stage drive signal output terminal OTn-1, the source of the seventh control transistor CT7 is electrically connected to the enable signal line EN, and the drain of the seventh control transistor CT7 is electrically connected to the source of the tenth control transistor CT10;

[0546] The gate of the eighth control transistor CT8 is electrically connected to the n-1th stage inverting signal output terminal FTn-1, the source of the eighth control transistor CT8 is electrically connected to the enable signal line EN, and the drain of the eighth control transistor CT8 is electrically connected to the source of the ninth control transistor CT9;

[0547] The gate of the ninth control transistor CT9 is electrically connected to the n-th stage drive signal output terminal OTn, the source of the ninth control transistor CT9 is electrically connected to the source of the tenth control transistor CT10, and the drain of the ninth control transistor CT9 is electrically connected to the control signal terminal CS;

[0548] The gate of the tenth control transistor CT10 is electrically connected to the n-th stage inverting signal output terminal FTn, and the drain of the tenth control transistor CT10 is electrically connected to the control signal terminal CS;

[0549] The output inverting circuit includes an eleventh control transistor CT11 and a twelfth control transistor CT12;

[0550] The gate of the eleventh control transistor CT11 is electrically connected to the n-th stage driving signal output terminal OTn, the source of the eleventh control transistor CT11 is electrically connected to the n-th stage inverting signal output terminal FTn, and the drain of the eleventh control transistor CT11 is electrically connected to the low voltage line VGL;

[0551] The gate of the twelfth control transistor CT12 is electrically connected to the n-th stage drive signal output terminal OTn, the source of the twelfth control transistor CT12 is electrically connected to the high voltage line VGH, and the drain of the twelfth control transistor CT12 is electrically connected to the n-th stage inverting signal output terminal FTn;

[0552] The first node control circuit includes a first transistor T1, a second transistor T2 and a third transistor T3; the second output node control circuit includes a fourth transistor T4, a fifth transistor T5, a sixth transistor T6 and a seventh transistor T7;

[0553] The gate of the first transistor T1 is electrically connected to the second first clock signal line CK2, the source of the first transistor T1 is electrically connected to the low voltage line VGL, and the drain of the first transistor T1 is electrically connected to the source of the third transistor T3;

[0554] The gate of the second transistor T2 is electrically connected to the drain of the fourth transistor T4, the source of the second transistor T2 is electrically connected to the second first clock signal line CK2, and the drain of the second transistor T2 is electrically connected to the source of the third transistor T3;

[0555] A gate of the third transistor T3 is electrically connected to the low voltage line VGL, and a drain of the third transistor T3 is electrically connected to the first node N1;

[0556] The gate of the fourth transistor T4 is electrically connected to the second first clock signal line CK2, and the source of the fourth transistor T4 is electrically connected to the input terminal I0;

[0557] The gate of the fifth transistor T5 is electrically connected to the low voltage line VGL, the source of the fifth transistor T5 is electrically connected to the drain of the fourth transistor T4, and the drain of the fifth transistor T5 is electrically connected to the second output node NJ2;

[0558] The gate of the sixth transistor T6 and the source of the sixth transistor T6 are both electrically connected to the second node N2, and the drain of the sixth transistor T6 is electrically connected to the second output node NJ2;

[0559] The gate of the seventh transistor T7 is electrically connected to the control voltage line VEL, the source of the seventh transistor T7 is electrically connected to the high voltage line VGH, and the drain of the seventh transistor T7 is electrically connected to the source of the fifth transistor T5;

[0560] The second node control circuit includes an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, an eleventh transistor T11 and a third capacitor C3;

[0561] The gate of the eighth transistor T8 is electrically connected to the second node N2, the source of the eighth transistor T8 is electrically connected to the second second clock signal line CB2, and the drain of the eighth transistor T8 is electrically connected to the first intermediate node NZ1;

[0562] The gate of the ninth transistor T9 is electrically connected to the drain of the first transistor T1, the source of the ninth transistor T9 is electrically connected to the high voltage line VGH, and the drain of the ninth transistor T9 is electrically connected to the first intermediate node NZ1;

[0563] The gate of the tenth transistor T10 is electrically connected to the second first clock signal line CK2, the source of the tenth transistor T10 is electrically connected to the input terminal I0, and the drain of the tenth transistor T10 is electrically connected to the source of the eleventh transistor T11;

[0564] A gate of the eleventh transistor T11 is electrically connected to the low voltage line VGL, and a drain of the eleventh transistor T11 is electrically connected to the second node N2;

[0565] The first plate of the third capacitor C3 is electrically connected to the second node N2, and the second plate of the third capacitor C3 is electrically connected to the first intermediate node NZ1;

[0566] The first output node control circuit includes a twelfth transistor T12, a thirteenth transistor T13, a fourteenth transistor T14 and a fourth capacitor C4;

[0567] The gate of the twelfth transistor T12 is electrically connected to the first node N1, the source of the twelfth transistor T12 is electrically connected to the second second clock signal line CB2, and the drain of the twelfth transistor T12 is electrically connected to the second intermediate node NZ2;

[0568] The gate of the thirteenth transistor T13 is electrically connected to the second second clock signal line CB2, the source of the thirteenth transistor T13 is electrically connected to the second intermediate node NZ2, and the drain of the thirteenth transistor T13 is electrically connected to the first output node NJ1;

[0569] The gate of the fourteenth transistor T14 is electrically connected to the source of the fifth transistor T5, the source of the fourteenth transistor T14 is electrically connected to the high voltage line VGH, and the drain of the fourteenth transistor T14 is electrically connected to the first output node NJ1;

[0570] The first plate of the fourth capacitor C4 is electrically connected to the first node N1, and the second plate of the fourth capacitor C4 is electrically connected to the second intermediate node NZ2;

[0571] The potential maintaining circuit includes a fifth capacitor C5;

[0572] The first plate of the fifth capacitor C5 is electrically connected to the first output node NJ1, and the second plate of the fifth capacitor C5 is electrically connected to the high voltage line VGH;

[0573] The output circuit includes a fifteenth transistor T15 and a sixteenth transistor T16;

[0574] The gate of the fifteenth transistor T15 is electrically connected to the first output node NJ1, the source of the fifteenth transistor T15 is electrically connected to the high voltage line VGH, and the drain of the fifteenth transistor T15 is electrically connected to the n-th stage driving signal output terminal OTn;

[0575] The gate of the sixteenth transistor T16 is electrically connected to the second output node NJ2, the source of the sixteenth transistor T16 is electrically connected to the n-th stage driving signal output terminal OTn, and the drain of the sixteenth transistor T16 is electrically connected to the low voltage line VGL.

[0576] exist Fig.17In at least one embodiment of the driving circuit shown, T1-T16 are all p-type transistors, CT1, CT3, CT5, CT8, CT9 and CT12 are p-type transistors, and CT2, CT4, CT6, CT7, CT10 and CT11 are n-type transistors.

[0577] exist Fig.17 In at least one embodiment of the driving circuit shown, the driving signal generating circuit is a 16T2C circuit. In actual operation, the driving signal generating circuit may also adopt a circuit with other structures for generating an n-th level driving signal.

[0578] Fig.18 yes Fig.17 FIG. 1 is a timing diagram showing the operation of a driving signal generating circuit in at least one embodiment of the driving circuit shown.

[0579] Fig.19 is a working timing diagram of at least one embodiment of the n-1th stage driving circuit and at least one embodiment of the nth stage driving circuit; the structure of the nth stage driving circuit is as follows Fig.17 As shown;

[0580] The structure of the n-1th stage driving circuit is Fig.17 The structure of the n-th level driving circuit is the same as that of the n-1-th level driving circuit. Fig.17 The differences in the nth level drive circuit shown include:

[0581] The drain of T15 is electrically connected to the n-1th stage driving signal output terminal OTn-1, and the drain of CT12 is electrically connected to the n-1th stage inverting signal output terminal FTn-1;

[0582] The gate of CT7 is electrically connected to the n-1th level drive signal output terminal OTn-1, the gate of CT8 is electrically connected to the n-1th level inverting signal output terminal FTn-1, the gate of CT10 is electrically connected to the n-2th level inverting signal output terminal FTn-2, the gate of CT9 is electrically connected to the n-2th level drive signal output terminal OTn-2, the drain of CT5 is electrically connected to the n-1th level first reset terminal PRn-1, and the gates of CT3 and CT4 are electrically connected to the n-1th level drive signal output terminal OTn-1.

[0583] like Fig.19 As shown, when at least one embodiment of the n-1th stage driving circuit and at least one embodiment of the nth stage driving circuit are working,

[0584] In the first stage t1, EN outputs a low voltage signal, OTn-2 provides a low voltage signal, FTn-2 provides a high voltage signal, OTn-1 provides a high voltage signal, FTn-1 provides a low voltage signal, OTn provides a high voltage signal, and FTn provides a low voltage signal;

[0585] In the n-1th level driving circuit, CT7 and CT8 are turned on, CT9 and CT10 are turned on, EN is connected to CS, the potential of CS is low voltage, CT1 is turned on, OTn-1 provides a high voltage signal, CT4 is turned on, CO outputs a low voltage signal, CT5 is turned on, and PRn-1 provides a high voltage signal;

[0586] In the nth stage driving circuit, CT7 and CT8 are turned on, CT9 and CT10 are turned off, and EN is disconnected from CS;

[0587] In the second stage t2, EN outputs a low voltage signal, OTn-2 provides a low voltage signal, FTn-2 provides a high voltage signal, OTn-1 provides a low voltage signal, FTn-1 provides a high voltage signal, OTn provides a high voltage signal, and FTn provides a low voltage signal;

[0588] In the n-1th level driving circuit, CT7 and CT8 are turned off, EN is disconnected from CS, the potential of CS is maintained at a low voltage, OTn-1 provides a low voltage signal, CT1 and CT3 are turned on, CO outputs a high voltage signal, CT6 is turned on, and PRn-1 provides a low voltage signal;

[0589] In the nth level driving circuit, CT7 and CT8 are turned on, CT9 and CT10 are turned on, EN is connected to CS, and the potential of CS is low voltage; OTn provides a high voltage signal, CT4 is turned on, CO outputs a low voltage signal, CT5 is turned on, and PRn provides a high voltage signal;

[0590] In the third stage t3, EN provides a high voltage signal, OTn-2 provides a high voltage signal, FTn-2 provides a low voltage signal, OTn-1 provides a low voltage signal, FTn-1 provides a high voltage signal, OTn provides a low voltage signal, and FTn provides a high voltage signal;

[0591] In the n-1th level driving circuit, CT7 and CT8 are turned off, EN is disconnected from CS, the potential of CS is maintained at a low voltage, OTn-1 provides a low voltage signal, CT1 and CT3 are turned on, CO outputs a high voltage signal, CT6 is turned on, and PRn-1 provides a low voltage signal;

[0592] In the nth level driving circuit, CT7 and CT8 are turned off, EN is disconnected from CS, and the potential of CS is maintained at a low voltage; OTn provides a low voltage signal, CT1 and CT2 are turned on, CO outputs a high voltage signal, CT6 is turned on, and PRn provides a low voltage signal;

[0593] In the fourth stage t4, EN provides a high voltage signal, OTn-2 provides a high voltage signal, FTn-2 provides a low voltage signal, OTn-1 provides a high voltage signal, FTn-1 provides a low voltage signal, OTn provides a low voltage signal, and FTn provides a high voltage signal;

[0594] In the n-1th level driving circuit, CT7 and CT8 are turned on, CT9 and CT10 are turned off, EN is disconnected from CS, the potential of CS is maintained at a low voltage, OTn-1 provides a high voltage signal, CT4 is turned on, CO outputs a low voltage signal, CT5 is turned on, and PRn-1 provides a high voltage signal;

[0595] In the nth level driving circuit, CT7 and CT8 are turned off, EN is disconnected from CS, and the potential of CS is maintained at a low voltage; OTn provides a low voltage signal, CT1 and CT2 are turned on, CO outputs a high voltage signal, CT6 is turned on, and PRn provides a low voltage signal;

[0596] In the fifth stage t5, EN provides a high voltage signal, OTn-2 provides a high voltage signal, FTn-2 provides a low voltage signal, OTn-1 provides a high voltage signal, FTn-1 provides a low voltage signal, OTn provides a high voltage signal, and FTn provides a low voltage signal;

[0597] In the n-1th level driving circuit, CT9 and CT10 are turned on, CT11 and CT12 are turned off, EN is disconnected from CS, the potential of CS is maintained at a low voltage, CT1 is turned on, CO1 outputs a high voltage signal, CT4 is turned on, CS is connected to VGL, OTn-1 provides a high voltage signal, CT6 is turned on, CO2 outputs a low voltage signal, CT7 is turned on, and PRn-1 provides a high voltage signal;

[0598] In the nth level driving circuit, CT9 and CT10 are turned on, CT11 and CT12 are turned off, EN is disconnected from CS, and the potential of CS is maintained at a low voltage; OTn provides a high voltage signal, CT4 is turned on, CO outputs a low voltage signal, CT5 is turned on, and PRn provides a high voltage signal.

[0599] like Fig.19 As shown, PRn provides an invalid voltage signal, and PRn-1 provides a valid first reset signal of the n-1th level, which can control the transistor whose gate is electrically connected to PRn in the pixel circuit of the nth row to be turned off so as not to perform a reset; when the potential of the first reset signal of the n-1th level is a valid voltage, the transistor whose gate is electrically connected to PRn-1 in the pixel circuit of the n-1th row is controlled to be turned on so as to perform a normal reset;

[0600] Since the transistor in the pixel circuit electrically connected to PRn is a p-type transistor, the invalid voltage signal provided by PRn is a high voltage signal.

[0601] like Fig. 20 As shown, in Fig.13 Based on at least one embodiment of the driving circuit shown, the n-th level driving output terminal is the n-th level second scanning terminal PTn;

[0602] The first control circuit includes a first control transistor CT1, a second control transistor CT2, a third control transistor CT3 and a fourth control transistor CT4; the second control circuit includes a fifth control transistor CT5 and a sixth control transistor CT6; the first energy storage circuit includes a first capacitor CC1;

[0603] The gate of the first control transistor CT1 is electrically connected to the control signal terminal CS, the source of the first control transistor CT1 is electrically connected to the drain of the third control transistor CT3, and the drain of the first control transistor CT1 is electrically connected to the control output terminal CO;

[0604] The gate of the second control transistor CT2 is electrically connected to the control signal terminal CS, the source of the second control transistor CT2 is electrically connected to the control output terminal CO, and the drain of the second control transistor CT2 is electrically connected to the low voltage line VGL;

[0605] The gate of the third control transistor CT3 is electrically connected to the n-th stage drive signal output terminal OTn, and the source of the third control transistor CT3 is electrically connected to the high voltage line VGH;

[0606] The gate of the fourth control transistor CT4 is electrically connected to the n-th stage drive signal output terminal OTn, the source of the fourth control transistor CT4 is electrically connected to the control output terminal CO, and the drain of the fourth control transistor CT4 is electrically connected to the low voltage line VGL;

[0607] The gate of the fifth control transistor CT5 is electrically connected to the control output terminal CO, the source of the fifth control transistor CT5 is electrically connected to the high voltage line VGH, and the drain of the fifth control transistor CT5 is electrically connected to the n-th stage second scanning terminal PTn;

[0608] The gate of the sixth control transistor CT6 is electrically connected to the control output terminal CO, the source of the sixth control transistor CT6 is electrically connected to the n-th stage second scanning terminal PTn, and the drain of the sixth control transistor CT6 is electrically connected to the low voltage line VGL;

[0609] A first end of the first capacitor CC1 is electrically connected to the control output terminal CO, and a second end of the first capacitor CC1 is electrically connected to the low voltage line VGL;

[0610] The control signal generating circuit includes a seventh control transistor CT7 and an eighth control transistor CT8;

[0611] The gate of the seventh control transistor CT7 is electrically connected to the enable signal line EN, the source of the seventh control transistor CT7 is electrically connected to the high voltage line VGH, and the drain of the seventh control transistor CT7 is electrically connected to the control signal terminal CS;

[0612] The gate of the eighth control transistor CT8 is electrically connected to the enable signal line EN, the source of the eighth control transistor CT8 is electrically connected to the control signal terminal CS, and the drain of the eighth control transistor CT8 is electrically connected to the low voltage line VGL;

[0613] CT1, CT3 and CT5 are p-type transistors, CT2, CT4 and CT6 are n-type transistors; CT7 is a p-type transistor, and CT8 is an n-type transistor;

[0614] The first output node control circuit includes a seventeenth transistor T17, an eighteenth transistor T18 and a sixth capacitor C6;

[0615] The gate of the seventeenth transistor T17 is electrically connected to the third first clock signal line CK3, the source of the seventeenth transistor T17 is electrically connected to the low voltage line VGL, and the drain of the seventeenth transistor T17 is electrically connected to the first output node NJ1;

[0616] The gate of the eighteenth transistor T18 is electrically connected to the second output node NJ2, the source of the eighteenth transistor T18 is electrically connected to the third first clock signal line CK3, and the drain of the eighteenth transistor T18 is electrically connected to the first output node NJ1;

[0617] The first plate of the sixth capacitor C6 is electrically connected to the first output node NJ1, and the second plate of the sixth capacitor C6 is electrically connected to the high voltage line VGH;

[0618] The second output node control circuit includes a nineteenth transistor T19, a twentieth transistor T20 and a twenty-first transistor T21; the third energy storage circuit includes a seventh capacitor C7;

[0619] The gate of the nineteenth transistor T19 is electrically connected to the third first clock signal line CK3, the source of the nineteenth transistor T19 is electrically connected to the input terminal I0, and the drain of the nineteenth transistor T19 is electrically connected to the second output node NJ2;

[0620] A gate of the 20th transistor T20 is electrically connected to the first output node NJ1, a source of the 20th transistor T20 is electrically connected to the high voltage line VGH, and a drain of the 20th transistor T20 is electrically connected to a source of the 21st transistor T21;

[0621] A gate of the twenty-first transistor T21 is electrically connected to the third second clock signal line CB3, and a second electrode of the twenty-first transistor T21 is electrically connected to the second output node NJ2;

[0622] The first plate of the seventh capacitor C7 is electrically connected to the second output node NJ2, and the second plate of the seventh capacitor C7 is electrically connected to the n-th stage drive signal output terminal OTn;

[0623] The output circuit includes a twenty-second transistor T22 and a twenty-third transistor T23;

[0624] The gate of the 22nd transistor T22 is electrically connected to the first output node NJ1, the source of the 22nd transistor T22 is electrically connected to the high voltage line VGH, and the drain of the 22nd transistor T22 is electrically connected to the n-th stage driving signal output terminal OTn;

[0625] The gate of the twenty-third transistor T23 is electrically connected to the second output node NJ2, the source of the twenty-third transistor T23 is electrically connected to the n-th stage driving signal output terminal OTn, and the drain of the twenty-third transistor T23 is electrically connected to the third second clock signal line CB3;

[0626] The driving circuit further includes a twenty-fourth transistor T24;

[0627] The drain of the twenty-first transistor T21 is electrically connected to the second output node NJ2 through the twenty-fourth transistor T24;

[0628] A gate of the 24th transistor T24 is electrically connected to the low voltage line VGL, a source of the 24th transistor T24 is electrically connected to the drain of the 21st transistor T21 , and a drain of the 24th transistor T24 is electrically connected to the second output node NJ2 .

[0629] exist Fig. 20 In at least one embodiment of the driving circuit shown, T17 - T24 are p-type transistors, but the present invention is not limited thereto.

[0630] exist Fig. 20 In at least one embodiment of the driving circuit shown, T24 may not be provided.

[0631] exist Fig. 20In at least one embodiment of the driving circuit shown, the driving signal generating circuit is an 8T2C circuit. In actual operation, the driving signal generating circuit may also adopt a circuit with other structures for generating an n-th level driving signal.

[0632] Fig.21 yes Fig. 20 FIG. 1 is a timing diagram showing the operation of a driving signal generating circuit in at least one embodiment of the driving circuit shown.

[0633] Fig. 22 is a working timing diagram of at least one embodiment of the n-1th stage driving circuit and at least one embodiment of the nth stage driving circuit; the structure of the nth stage driving circuit is as follows Fig. 20 As shown;

[0634] The structure of the n-1th stage driving circuit is Fig. 20 The structure of the n-th level driving circuit is the same as that of the n-1-th level driving circuit. Fig. 20 The differences in the nth level drive circuit shown include:

[0635] The drain of T22 is electrically connected to the n-1th stage driving signal output terminal OTn-1;

[0636] The gate of CT5 and the gate of CT6 are both electrically connected to the n-1th stage driving signal output terminal OTn-1, and the drain of CT5 is electrically connected to the n-1th stage second scanning terminal PTn-1.

[0637] like Fig. 22 As shown, when at least one embodiment of the n-1th stage driving circuit and at least one embodiment of the nth stage driving circuit are working,

[0638] In the first stage t1, EN provides a high voltage signal, OTn-1 provides a high voltage signal, and OTn provides a high voltage signal;

[0639] In the n-1th level driving circuit, CT8 is turned on, CS is connected to VGL, the potential of CS is low voltage, CT1 is turned on; OTn-1 provides a high voltage signal, CT4 is turned on, CO outputs a low voltage signal, CT5 is turned on, and PTn-1 provides a high voltage signal;

[0640] In the nth level driving circuit, CT8 is turned on, CS is connected to VGL, the potential of CS is low voltage, CT1 is turned on; OTn provides a high voltage signal, CT4 is turned on, CO outputs a low voltage signal, CT5 is turned on, and PTn provides a high voltage signal;

[0641] In the second phase t2, EN provides a high voltage signal, OTn-1 provides a low voltage signal, and OTn provides a high voltage signal;

[0642] In the n-1th level driving circuit, CT8 is turned on, CS is connected to VGL, the potential of CS is low voltage, CT1 is turned on, CO outputs a high voltage signal, OTn-1 provides a low voltage signal, CT3 is turned on, CO outputs a high voltage signal, CT6 is turned on, and PTn-1 outputs a low voltage signal;

[0643] In the nth level driving circuit, CT8 is turned on, CS is connected to VGL, the potential of CS is low voltage, CT1 is turned on; OTn provides a high voltage signal, CT4 is turned on, CO outputs a low voltage signal, CT5 is turned on, and PTn provides a high voltage signal;

[0644] In the third stage t3, EN provides a low voltage signal, OTn-1 provides a high voltage signal, and OTn provides a low voltage signal;

[0645] In the n-1th level driving circuit, CT7 is turned on, CS is connected to VGH, the potential of CS is high voltage, CT2 is turned on, CT5 is turned on, OTn-1 provides a high voltage signal, CT4 is turned on, CO outputs a low voltage signal, CT5 is turned on, and PTn-1 outputs a high voltage signal;

[0646] In the nth stage driving circuit, CT7 is turned on, CS is connected to VGH, the potential of CS is high voltage, CT2 is turned on, CO outputs a low voltage signal, CT5 is turned on, and PTn provides a high voltage signal;

[0647] In the fourth stage t4, EN provides a low voltage signal, OTn-1 provides a high voltage signal, and OTn provides a high voltage signal;

[0648] In the n-1th level driving circuit, CT7 is turned on, CS is connected to VGH, the potential of CS is high voltage, CT2 is turned on, CO outputs a low voltage signal, CT1 is turned on, OTn-1 provides a high voltage signal, CT4 is turned on, CT5 is turned on, and PTn-1 outputs a high voltage signal;

[0649] In the nth level driving circuit, CT7 is turned on, CS is connected to VGH, the potential of CS is high voltage, CT2 is turned on, CO71 outputs a low voltage signal, CT1 is turned on, OTn provides a high voltage signal, CT4 is turned on, CT5 is turned on, and PTn provides a high voltage signal.

[0650] like Fig. 22 As shown, PTn provides an invalid voltage signal, and PTn-1 provides a valid second scanning signal of the n-1th level, which can control the transistor whose gate is electrically connected to PTn in the pixel circuit of the n-th row to be turned off so as not to perform scanning; when the potential of the second scanning signal of the n-1th level is a valid voltage, the transistor whose gate is electrically connected to PTn-1 in the pixel circuit of the n-1th row is controlled to be turned on so as to perform normal scanning;

[0651] Since the transistor in the pixel circuit electrically connected to PTn is a p-type transistor, the invalid voltage signal provided by PTn is a high voltage signal.

[0652] In an embodiment of the present invention, the display substrate comprises a base and the above-mentioned driving circuit disposed on the base;

[0653] The display substrate includes a display area and a peripheral area; the driving circuit is arranged in the peripheral area.

[0654] like Fig.23 As shown, the display substrate P0 includes a display area A0 and a peripheral area AZ;

[0655] The driving circuit is arranged in the peripheral area AZ;

[0656] A plurality of rows and columns of pixel circuits are arranged in the display area A0.

[0657] In a specific implementation, the driving circuit may be arranged on the left side and / or the right side of the display area A01.

[0658] In at least one embodiment of the present invention, the driving circuit further includes an output inverting circuit;

[0659] The output inversion circuit is electrically connected to the n-th level driving signal output terminal and the n-th level inverted signal output terminal respectively, and is used to invert the n-th level driving signal to obtain and output the n-th level inverted driving signal through the n-th level inverted signal output terminal;

[0660] The control signal generating circuit is also electrically connected to the n-1th level driving signal output terminal, the n-1th level inverted signal output terminal, the n-level driving signal output terminal and the n-level inverted signal output terminal respectively, and is used to generate a control signal according to an enable signal provided by an enable signal line under the control of the n-1th level driving signal, the n-1th level inverted signal, the n-level driving signal and the n-level inverted signal;

[0661] The n-1th level driving signal output terminal is used to provide the n-1th level driving signal, and the n-1th level inverting signal output terminal is used to provide the n-1th level inverting signal;

[0662] The control signal generating circuit is arranged on a side of the driving signal generating circuit close to the display area.

[0663] Optionally, the control circuit in the driving circuit includes a first control circuit, a second control circuit and a first energy storage circuit; the control circuit is arranged on a side of the driving signal generating circuit close to the display area;

[0664] The first control circuit is electrically connected to the control signal terminal, the n-th drive signal output terminal, the first control voltage line, the second control voltage line and the control output terminal respectively, and is used to control the control output terminal to be connected to the first control voltage line under the control of the control signal, to control the control output terminal to be connected or disconnected from the first control voltage line under the control of the n-th level drive signal, and to control the control output terminal to be connected or disconnected from the second control voltage line under the control of the n-th level drive signal and the control signal;

[0665] The second control circuit is electrically connected to the control output terminal, the n-th level driving output terminal, the first voltage line and the second voltage line respectively, and is used to control the connection or disconnection between the n-th level driving output terminal and the first voltage line, and control the connection or disconnection between the n-th level driving output terminal and the second voltage line under the control of the potential of the control output terminal;

[0666] The first energy storage circuit is electrically connected to the control output terminal and is used to maintain the potential of the control output terminal;

[0667] The first control voltage line is the first voltage line, and the second control voltage line is the second voltage line; or, the first control voltage line is the second voltage line, and the second control voltage line is the first voltage line.

[0668] In at least one embodiment of the present invention, the control circuit further includes a second energy storage circuit;

[0669] The second energy storage circuit is electrically connected to the control signal terminal and is used to maintain the potential of the control signal terminal;

[0670] The second energy storage circuit is arranged on a side of the second control circuit away from the display area.

[0671] Optionally, the drive signal generating circuit includes a first node control circuit, a second node control circuit, a first output node control circuit, a second output node control circuit, a potential maintaining circuit and an output circuit; the drive signal generating circuit is arranged in the

[0672] The first node control circuit is electrically connected to the first node, the first first clock signal line, the second voltage line, and the second output node, respectively, and is used to control the connection between the first node and the second voltage line under the control of the first clock signal provided by the first first clock signal line, and to control the connection or disconnection between the first node and the first first clock signal line under the control of the potential of the second output node;

[0673] The second node control circuit is electrically connected to the first node, the first intermediate node, the first voltage line, the first second clock signal line, the second node, the input terminal and the second voltage line respectively, and is used to control the connection between the first intermediate node and the first voltage line under the control of the potential of the first node, control the connection between the first intermediate node and the first second clock signal line under the control of the potential of the second node, and control the potential of the second node according to the potential of the first intermediate node, and control the connection between the input terminal and the second node under the control of the second clock signal provided by the first second clock signal line and the second voltage signal provided by the second voltage line;

[0674] The first output node control circuit is electrically connected to the first output node, the first node, the first second clock signal line, the second intermediate node, the second output node and the first voltage line respectively, and is used to control the second intermediate node to be connected to the first second clock signal line under the control of the potential of the first node, control the potential of the second intermediate node according to the potential of the first node, control the second intermediate node to be connected to the first output node under the control of the second clock signal provided by the first second clock signal line, and control the first output node to be connected to the first voltage line under the control of the potential of the second output node;

[0675] The second output node control circuit is electrically connected to the first second clock signal line, the input terminal, the control voltage line, the first voltage line, the second node, and the second output node, respectively, and is used to control the second output node to be connected to the input terminal under the control of the second clock signal provided by the first second clock signal line, control the potential of the second output node according to the potential of the second node, and control the second output node to be connected to the first voltage line under the control of the control voltage provided by the control voltage line;

[0676] The potential maintaining circuit is electrically connected to the first output node, and is used to maintain the potential of the first output node;

[0677] The output circuit is electrically connected to the first output node, the second output node, the first voltage line, the second voltage line and the n-th level drive signal output terminal, respectively, and is used to control the connection between the n-th level drive signal output terminal and the first voltage line under the control of the potential of the first output node, and to control the connection between the n-th level drive signal output terminal and the second voltage line under the control of the potential of the second output node.

[0678] Optionally, the driving signal generating circuit includes a first node control circuit, a second node control circuit, a first output node control circuit, a second output node control circuit, a potential maintaining circuit and an output circuit;

[0679] The first node control circuit is electrically connected to the first node, the second first clock signal line, the second voltage line, and the second output node, respectively, and is used to control the connection between the first node and the second voltage line under the control of the first clock signal provided by the second first clock signal line, and to control the connection or disconnection between the first node and the second first clock signal line under the control of the potential of the second output node;

[0680] The second node control circuit is electrically connected to the first node, the first intermediate node, the first voltage line, the second second clock signal line, the second node, the input terminal and the second voltage line respectively, and is used to control the connection between the first intermediate node and the first voltage line under the control of the potential of the first node, control the connection between the first intermediate node and the second second clock signal line under the control of the potential of the second node, and control the potential of the second node according to the potential of the first intermediate node, and control the connection between the input terminal and the second node under the control of the second clock signal provided by the second second clock signal line and the second voltage signal provided by the second voltage line;

[0681] The first output node control circuit is electrically connected to the first output node, the first node, the second second clock signal line, the second intermediate node, the second output node and the first voltage line respectively, and is used to control the second intermediate node to be connected to the second second clock signal line under the control of the potential of the first node, control the potential of the second intermediate node according to the potential of the first node, control the second intermediate node to be connected to the first output node under the control of the second clock signal provided by the second second clock signal line, and control the first output node to be connected to the first voltage line under the control of the potential of the second output node;

[0682] The second output node control circuit is electrically connected to the second second clock signal line, the input terminal, the control voltage line, the first voltage line, the second node, and the second output node, respectively, and is used to control the second output node to be connected to the input terminal under the control of the second clock signal provided by the second second clock signal line, control the potential of the second output node according to the potential of the second node, and control the second output node to be connected to the first voltage line under the control of the control voltage provided by the control voltage line;

[0683] The potential maintaining circuit is electrically connected to the first output node, and is used to maintain the potential of the first output node;

[0684] The output circuit is electrically connected to the first output node, the second output node, the first voltage line, the second voltage line and the n-th level drive signal output terminal, respectively, and is used to control the connection between the n-th level drive signal output terminal and the first voltage line under the control of the potential of the first output node, and to control the connection between the n-th level drive signal output terminal and the second voltage line under the control of the potential of the second output node.

[0685] In at least one embodiment of the present invention, the drive signal generating circuit includes a first output node control circuit, a second output node control circuit, a third energy storage circuit and an output circuit; the drive signal generating circuit is arranged on a side of the control signal generating circuit included in the drive circuit away from the display area; the transistors in the output circuit are arranged on a side of the transistors included in the drive signal generating circuit except the transistors in the output circuit close to the display area;

[0686] The first output node control circuit is electrically connected to the third first clock signal line, the second voltage line and the second output node respectively, and is used to control the first output node to be connected to the second voltage line under the control of the first clock signal provided by the third first clock signal line, and to control the first output node to be connected to the third first clock signal line under the control of the potential of the second output node, and to maintain the potential of the first output node;

[0687] The second output node control circuit is electrically connected to the second output node, the third first clock signal line, the input terminal, the third second clock signal line, the first output node and the first voltage line respectively, and is used to control the second output node to be connected to the input terminal under the control of the first clock signal, and to control the second output node to be connected to the first voltage line under the control of the potential of the first output node and the second clock signal provided by the third second clock signal line;

[0688] The first end of the third energy storage circuit is electrically connected to the second output node, the second end of the third energy storage circuit is electrically connected to the n-th stage drive signal output terminal, and the third energy storage circuit is used to store electric energy;

[0689] The output circuit is electrically connected to the first output node, the second output node, the first voltage line, the second clock signal and the n-th level drive signal output terminal, respectively, and is used to control the connection between the n-th level drive signal output terminal and the first voltage line under the control of the potential of the first output node, and to control the connection between the n-th level drive signal output terminal and the third second clock signal line under the control of the potential of the second output node.

[0690] Fig.24A , Fig. 24B and Fig.24C yes Fig.14 A first layout diagram of at least one embodiment of a driving circuit is shown.

[0691] Fig.25 yes Fig.24A Layout diagram of the first semiconductor layer in FIG. Fig.26 yes Fig.24A The layout diagram of the first gate metal layer in Fig. 27 yes Fig.24A The layout diagram of the second gate metal layer in Fig.28 yes Fig.24A Layout diagram of the first source and drain metal layer in, Fig.29 yes Fig.24A Layout diagram of the second source and drain metal layer in FIG. Fig.30 yes Fig.24A Layout diagram of the third source and drain metal layer in .

[0692] Fig.31A yes Fig.24A The superposition diagram of the first semiconductor layer and the first gate metal layer in FIG. Fig.31B yes Fig.24A The superposition diagram of the first gate metal layer and the second gate metal layer in FIG. Fig. 31C yes Fig.24A The superposition diagram of the second gate metal layer and the first source and drain metal layer in FIG. Fig.31D yes Fig.24A An overlay diagram of the first source-drain metal layer and the second source-drain metal layer in FIG. Fig.31E yes Fig.24A An overlay diagram of the second source-drain metal layer and the third source-drain metal layer in FIG.

[0693] exist Fig.25, AT1 is an active pattern of CT1, AT2 is an active pattern of CT2, AT3 is an active pattern of CT3, AT4 is an active pattern of CT4, AT5 is an active pattern of CT5, AT6 is an active pattern of CT6, AT7 is an active pattern of CT7, AT8 is an active pattern of CT8, AT9 is an active pattern of CT9, AT10 is an active pattern of CT10, AT11 is an active pattern of CT11, and AT12 is an active pattern of CT12;

[0694] A1 is the active pattern of T1, A2 is the active pattern of T2, A3 is the active pattern of T3, A4 is the active pattern of T4, A5 is the active pattern of T5, A6 is the active pattern of T6, A7 is the active pattern of T7, A8 is the active pattern of T8, A9 is the active pattern of T9, A10 is the active pattern of T10, A11 is the active pattern of T11, A12 is the active pattern of T12, A13 is the active pattern of T13, A14 is the active pattern of T14, A15 is the active pattern of T15, and A16 is the active pattern of T16.

[0695] exist Fig.26 , the first electrode plate labeled CC11 is CC1, the first electrode plate labeled CC21 is CC2, the first electrode plate labeled C31 is C3, the first electrode plate labeled C41 is C4, and the first electrode plate labeled C51 is C5.

[0696] exist Fig. 27 , the second electrode plate labeled CC12 is CC1, the second electrode plate labeled CC22 is CC2, the second electrode plate labeled C32 is C3, the second electrode plate labeled C42 is C4, and the second electrode plate labeled C52 is C5.

[0697] exist Fig.24A In at least one embodiment of the display substrate shown, the first semiconductor layer, the first gate metal layer, the second gate metal layer, the first source-drain metal layer, the second source-drain metal layer and the third source-drain metal layer are arranged in sequence in a direction away from the substrate.

[0698] Fig.24A At least one embodiment of the display substrate shown is a driving circuit manufactured using a CMOS (Complementary Metal Oxide Semiconductor) process.

[0699] In at least one embodiment of the present invention, the first semiconductor layer may be made of polysilicon, and the second semiconductor layer may be made of IGZO (indium gallium zinc oxide), but the present invention is not limited thereto.

[0700] In at least one embodiment of the present invention, the control signal generating circuit and the control circuit are arranged on a side of the driving signal generating circuit close to the display area, so that the control circuit provides a corresponding driving signal to a pixel circuit arranged in the display area.

[0701] In at least one embodiment of the present invention, the first voltage line includes a first first voltage line and a second first voltage line sequentially arranged along a direction away from the display area, and the second voltage line includes a first second voltage line and a second second voltage line sequentially arranged along a direction away from the display area;

[0702] The orthographic projection of at least part of the active pattern of the transistor included in the second control circuit on the substrate at least partially overlaps with the orthographic projection of the first first voltage line on the substrate;

[0703] The orthographic projection of at least part of the active pattern of the transistor included in the second control circuit on the substrate at least partially overlaps with the orthographic projection of the first second voltage line on the substrate;

[0704] The orthographic projection of the first second voltage line on the substrate at least partially overlaps with the orthographic projection of the plate of the capacitor included in the first energy storage circuit on the substrate;

[0705] An orthographic projection of the enable signal line on the substrate at least partially overlaps with an orthographic projection of active patterns of at least a portion of transistors included in the control signal generating circuit on the substrate.

[0706] In at least one embodiment of the present invention, the orthographic projection of each signal line on the substrate at least partially overlaps with the orthographic projection of the active pattern of the corresponding transistor on the substrate, and the signal line and the electrode plate of the corresponding capacitor are arranged to at least partially overlap with the orthographic projection on the substrate, so as to reduce the lateral space occupied by the driving circuit, thereby facilitating the realization of a narrow frame.

[0707] Optionally, the first voltage line may be a high voltage line, and the second voltage line may be a low voltage line.

[0708] like Figure 24A-Figure 30 As shown, the high voltage line includes a first first voltage line V11 and a second first voltage line V21, and the second voltage line includes a first second voltage line V12 and a second second voltage line V22;

[0709] V11 and V21 are arranged in sequence along a side away from the display area, and V12 and V22 are arranged in sequence along a side away from the display area;

[0710] exist Figure 24A-Figure 30 Among them, the one labeled NTn is the first scanning end of the nth level;

[0711] like Figure 24A-Figure 30 As shown, the orthographic projection of the active pattern AT6 of CT6 on the substrate at least partially overlaps with the orthographic projection of V11 on the substrate; the orthographic projection of the active pattern AT5 of CT5 on the substrate at least partially overlaps with the orthographic projection of V11 on the substrate;

[0712] The orthographic projection of the active pattern AT6 of CT6 on the substrate at least partially overlaps with the orthographic projection of V12 on the substrate; the orthographic projection of the active pattern AT5 of CT5 on the substrate at least partially overlaps with the orthographic projection of V12 on the substrate;

[0713] The orthographic projection of the active pattern AT4 of CT4 on the substrate at least partially overlaps with the orthographic projection of V12 on the substrate; the orthographic projection of the active pattern AT2 of CT2 on the substrate at least partially overlaps with the orthographic projection of V12 on the substrate;

[0714] The orthographic projection of the first electrode plate CC11 of CC1 on the substrate at least partially overlaps with the orthographic projection of V12 on the substrate; the orthographic projection of the second electrode plate CC12 of CC1 on the substrate at least partially overlaps with the orthographic projection of V12 on the substrate;

[0715] The orthographic projection of the first electrode plate CC21 of CC2 on the substrate at least partially overlaps with the orthographic projection of V12 on the substrate; the orthographic projection of the second electrode plate CC22 of CC2 on the substrate at least partially overlaps with the orthographic projection of V12 on the substrate;

[0716] The orthographic projection of the enable signal line EN on the substrate at least partially overlaps with the orthographic projection of the active pattern of CT8 on the substrate.

[0717] In at least one embodiment of the present invention, the orthographic projection of the first second voltage line on the substrate at least partially overlaps with the orthographic projection of the plate of the capacitor included in the second energy storage circuit on the substrate;

[0718] An orthographic projection of the second second voltage line on the substrate at least partially overlaps with an orthographic projection of active patterns of at least a portion of transistors included in the control signal generating circuit on the substrate.

[0719] like Figure 24A-Figure 30 As shown, the orthographic projection of V22 on the substrate at least partially overlaps with the orthographic projection of the active pattern AT7 of CT7 on the substrate.

[0720] In at least one embodiment of the present invention, an orthographic projection of the enable signal line on the substrate at least partially overlaps with an orthographic projection of an active pattern of at least one transistor included in the output inverter circuit on the substrate.

[0721] like Figure 24A-Figure 30 As shown, the orthographic projection of the enable signal line EN on the substrate at least partially overlaps with the orthographic projection of the active pattern of CT12 on the substrate; the orthographic projection of the enable signal line EN on the substrate at least partially overlaps with the orthographic projection of the active pattern of CT11 on the substrate.

[0722] Optionally, the first first voltage line, the second first voltage line, the first second voltage line, the second second voltage line and the enable signal line all extend along a first direction;

[0723] The width of the first first voltage line along the second direction is greater than the width of the second first voltage line along the second direction;

[0724] The width of the first second voltage line along the second direction is greater than the width of the second second voltage line along the second direction;

[0725] The first direction intersects the second direction.

[0726] In at least one embodiment of the present invention, the first voltage line may include at least two voltage lines electrically connected to each other, and the width of at least one voltage line of the at least two voltage lines electrically connected to each other included in the first voltage line may be set to be larger along the second direction to reduce the resistance of the first voltage line;

[0727] The second voltage line may include at least two voltage lines electrically connected to each other, and the width of at least one voltage line of the at least two voltage lines electrically connected to each other included in the second voltage line may be set to be larger along the second direction to reduce the resistance of the second voltage line.

[0728] Optionally, the first direction may be a vertical direction, and the second direction may be a horizontal direction.

[0729] like Figure 24A-Figure 30 As shown, V11, V21, V12, V22 and EN all extend in the vertical direction.

[0730] The width of V11 along the horizontal direction is greater than the width of V21 along the horizontal direction.

[0731] The width of V12 along the horizontal direction is greater than the width of V22 along the horizontal direction.

[0732] In at least one embodiment of the present invention, CT5 and CT6 are transistors electrically connected to the n-th level driving output terminal, and the orthographic projection of the active pattern AT5 of CT5 on the substrate at least partially overlaps with the orthographic projection of V11 on the substrate; the orthographic projection of the active pattern AT6 of CT6 on the substrate at least partially overlaps with the orthographic projection of V11 on the substrate; the orthographic projection of the active pattern AT5 of CT5 on the substrate at least partially overlaps with the orthographic projection of V12 on the substrate; the orthographic projection of the active pattern AT6 of CT6 on the substrate at least partially overlaps with the orthographic projection of V12 on the substrate; the width of V11 along the horizontal direction is set to be larger, and the width of V12 along the horizontal direction is set to be larger, so as to reduce the resistance of V11 and the resistance of V12, and reduce the IR Drop (IR voltage drop, IR voltage drop is the voltage drop caused by current and resistance) of the high voltage line and the IR Drop of the low voltage line.

[0733] In at least one embodiment of the present invention, the transistor included in the second control circuit is arranged on a side of the transistor included in the first control circuit close to the display area;

[0734] The control signal generating circuit includes a transistor which is arranged on a side of the second control circuit away from the display area.

[0735] like Figure 24A-Figure 30 As shown, the fifth control transistor CT5 and the sixth control transistor CT6 included in the second control circuit are arranged on a side close to the display area of ​​the first control transistor CT1, the second control transistor CT2, the third control transistor CT3 and the fourth control transistor CT4 included in the first control circuit;

[0736] The seventh control transistor CT7 , the eighth control transistor CT8 , the ninth control transistor CT9 and the tenth control transistor CT10 included in the control signal generating circuit are arranged on a side away from the display area of ​​the fifth control transistor CT5 and the sixth control transistor CT6 included in the second control circuit.

[0737] In at least one embodiment of the present invention, the first voltage line includes a first first voltage line, a second first voltage line, and a third first voltage line sequentially arranged along a direction away from the display area, and the second voltage line includes a first second voltage line, a second second voltage line, and a third second voltage line sequentially arranged along a direction away from the display area;

[0738] The orthographic projection of the second second voltage line on the substrate at least partially overlaps with the orthographic projection of the active pattern of at least one transistor included in the output circuit on the substrate;

[0739] The orthographic projection of the second first voltage line on the substrate at least partially overlaps with the orthographic projection of the active pattern of at least one transistor included in the output circuit on the substrate;

[0740] The orthographic projection of the second first voltage line on the substrate at least partially overlaps with the orthographic projection of the plate of the capacitor included in the potential maintaining circuit on the substrate;

[0741] The orthographic projection of the third first voltage line on the substrate at least partially overlaps with the orthographic projection of the active pattern of at least one transistor included in the second output node control circuit on the substrate;

[0742] The orthographic projection of the third second voltage line on the substrate at least partially overlaps with the orthographic projection of the plate of the capacitor included in the second node control circuit on the substrate;

[0743] The orthographic projection of the third second voltage line on the substrate at least partially overlaps with the orthographic projection of the active pattern of at least one transistor included in the first node control circuit on the substrate;

[0744] An orthographic projection of the third second voltage line on the substrate at least partially overlaps with an orthographic projection of an active pattern of at least one transistor included in the second node control circuit on the substrate.

[0745] In at least one embodiment of the present invention, each signal line and the active pattern of the corresponding transistor are arranged so that their orthographic projections on the substrate at least partially overlap, so as to facilitate the realization of a narrow frame.

[0746] like Figure 24A-Figure 30 As shown, the first voltage lines include a first first voltage line V11, a second first voltage line V21 and a third first voltage line V31 which are sequentially arranged in a direction away from the display area;

[0747] The second voltage lines include a first second voltage line V12, a second second voltage line V22 and a third second voltage line V32 which are sequentially arranged in a direction away from the display area;

[0748] The orthographic projection of V22 on the substrate at least partially overlaps with the orthographic projection of the active pattern A15 of T15 on the substrate, and the orthographic projection of V22 on the substrate at least partially overlaps with the orthographic projection of the active pattern A16 of T16 on the substrate;

[0749] The orthographic projection of V22 on the substrate at least partially overlaps with the orthographic projection of the active pattern A15 of T15 on the substrate, and the orthographic projection of V22 on the substrate at least partially overlaps with the orthographic projection of the active pattern A16 of T16 on the substrate;

[0750] The orthographic projection of V21 on the substrate at least partially overlaps with the orthographic projection of the first electrode plate C51 of C5 on the substrate; the orthographic projection of V21 on the substrate at least partially overlaps with the orthographic projection of the second electrode plate C52 of C5 on the substrate;

[0751] The orthographic projection of V31 on the substrate at least partially overlaps with the orthographic projection of the active pattern A5 of T5 on the substrate; the orthographic projection of V31 on the substrate at least partially overlaps with the orthographic projection of the active pattern A6 of T6 on the substrate; the orthographic projection of V31 on the substrate at least partially overlaps with the orthographic projection of the active pattern A7 of T7 on the substrate;

[0752] The orthographic projection of V32 on the substrate at least partially overlaps with the orthographic projection of the active pattern A4 of T4 on the substrate; the orthographic projection of V32 on the substrate at least partially overlaps with the orthographic projection of the active pattern A1 of T1 on the substrate; the orthographic projection of V32 on the substrate at least partially overlaps with the orthographic projection of the active pattern A8 of T8 on the substrate;

[0753] The orthographic projection of V32 on the substrate at least partially overlaps with the orthographic projection of the first electrode plate C31 of C3 on the substrate; the orthographic projection of V32 on the substrate at least partially overlaps with the orthographic projection of the second electrode plate C32 of C3 on the substrate.

[0754] In at least one embodiment of the present invention, the first first clock signal line and the second clock signal line are arranged between the third first voltage line and the third second voltage line;

[0755] The orthographic projection of the first first clock signal line on the substrate at least partially overlaps with the orthographic projection of the plate of the capacitor included in the first output node control circuit on the substrate;

[0756] The orthographic projection of the first first clock signal line on the substrate at least partially overlaps with the orthographic projection of the active pattern of at least one transistor included in the second node control circuit on the substrate;

[0757] The orthographic projection of the first first clock signal line on the substrate at least partially overlaps with the orthographic projection of the active pattern of at least one transistor included in the first output node control circuit on the substrate;

[0758] The orthographic projection of the first second clock signal line on the substrate at least partially overlaps with the orthographic projection of the plate of the capacitor included in the first output node control circuit on the substrate;

[0759] The orthographic projection of the first second clock signal line on the substrate at least partially overlaps with the orthographic projection of the plate of the capacitor included in the second node control circuit on the substrate.

[0760] like Figure 24A-Figure 30 As shown, the first first clock signal line CK1 and the first second clock signal line CB1 are arranged between the third first voltage line V31 and the third second voltage line V32;

[0761] The orthographic projection of CK1 on the substrate at least partially overlaps with the orthographic projection of the first electrode plate C41 of C4 on the substrate; the orthographic projection of CK1 on the substrate at least partially overlaps with the orthographic projection of the second electrode plate C42 of C4 on the substrate;

[0762] The orthographic projection of CK1 on the substrate at least partially overlaps with the orthographic projection of the active pattern A9 of T9 on the substrate; the orthographic projection of CK1 on the substrate at least partially overlaps with the orthographic projection of the active pattern A12 of T12 on the substrate;

[0763] The orthographic projection of CB1 on the substrate at least partially overlaps with the orthographic projection of the active pattern A9 of T9 on the substrate;

[0764] The orthographic projection of CB1 on the substrate at least partially overlaps with the orthographic projection of the first electrode plate C31 of C3 on the substrate; the orthographic projection of CB1 on the substrate at least partially overlaps with the orthographic projection of the second electrode plate C32 of C3 on the substrate;

[0765] The orthographic projection of CB1 on the substrate at least partially overlaps with the orthographic projection of the first electrode plate C31 of C3 on the substrate; the orthographic projection of CB1 on the substrate at least partially overlaps with the orthographic projection of the second electrode plate C32 of C3 on the substrate;

[0766] The orthographic projection of CB1 on the substrate at least partially overlaps with the orthographic projection of the first electrode plate C41 of C4 on the substrate; the orthographic projection of CB1 on the substrate at least partially overlaps with the orthographic projection of the second electrode plate C42 of C4 on the substrate.

[0767] Optionally, the active graphics of at least some transistors included in the second control circuit include at least two independent active graphic parts, and the at least two independent active graphic parts are spaced a certain distance apart to facilitate heat dissipation, so as to improve the performance of the transistor while ensuring the area of ​​the active graphics.

[0768] Fig.32A , Fig.32B and Fig.32C yes Fig.14 A second layout diagram of at least one embodiment of a driving circuit is shown.

[0769] Fig.33 yes Fig.32A Layout diagram of the first semiconductor layer in FIG. Fig.34 yes Fig.32A The layout diagram of the first gate metal layer in Fig.35 yes Fig.32AThe layout diagram of the second gate metal layer in Fig.36 yes Fig.32A A layout diagram of the second semiconductor layer in FIG. Fig.37 yes Fig.32A The layout diagram of the third gate metal layer in Fig.38 yes Fig.32A Layout diagram of the first source and drain metal layer in, Fig.39 yes Fig.32A Layout diagram of the second source and drain metal layer in FIG. Fig.40 yes Fig.32A Layout diagram of the third source and drain metal layer in .

[0770] Fig.41A yes Fig.32A A schematic diagram of the superposition of the first semiconductor layer and the first gate metal layer; Fig.41B yes Fig.32A A schematic diagram of the superposition of the first gate metal layer and the second gate metal layer;

[0771] Fig.41C yes Fig.32A A schematic diagram of the superposition of the second gate metal layer and the second semiconductor layer; Fig.41D yes Fig.32A A schematic diagram of the superposition of the third gate metal layer and the second semiconductor layer; Fig.41E yes Fig.32A A schematic diagram of the superposition of the third gate metal layer and the first source and drain metal layer; Fig.41F yes Fig.32A A schematic diagram of the superposition of the first source-drain metal layer and the second source-drain metal layer; Figure 41G yes Fig.32A Schematic diagram of the superposition of the second source-drain metal layer and the third source-drain metal layer.

[0772] exist Fig.32A In at least one embodiment of the display substrate shown, the first semiconductor layer, the first gate metal layer, the second gate metal layer, the second semiconductor layer, the third gate metal layer, the first source-drain metal layer, the second source-drain metal layer and the third source-drain metal layer are arranged in sequence along a direction away from the substrate.

[0773] Fig.32A At least one embodiment of the display substrate shown is a driving circuit manufactured using an LTPO (low temperature polycrystalline oxide) process.

[0774] In at least one embodiment of the present invention, the first semiconductor layer may be made of polysilicon, and the second semiconductor layer may be made of IGZO (indium gallium zinc oxide), but the present invention is not limited thereto.

[0775] exist Fig.33 , Fig.36, AT1 is an active pattern of CT1, AT2 is an active pattern of CT2, AT3 is an active pattern of CT3, AT4 is an active pattern of CT4, AT5 is an active pattern of CT5, AT6 is an active pattern of CT6, AT7 is an active pattern of CT7, AT8 is an active pattern of CT8, AT9 is an active pattern of CT9, AT10 is an active pattern of CT10, AT11 is an active pattern of CT11, and AT12 is an active pattern of CT12;

[0776] A1 is the active pattern of T1, A2 is the active pattern of T2, A3 is the active pattern of T3, A4 is the active pattern of T4, A5 is the active pattern of T5, A6 is the active pattern of T6, A7 is the active pattern of T7, A8 is the active pattern of T8, A9 is the active pattern of T9, A10 is the active pattern of T10, A11 is the active pattern of T11, A12 is the active pattern of T12, A13 is the active pattern of T13, A14 is the active pattern of T14, A15 is the active pattern of T15, and A16 is the active pattern of T16.

[0777] exist Fig.34 , the first electrode plate labeled CC11 is CC1, the first electrode plate labeled CC21 is CC2, the first electrode plate labeled C31 is C3, the first electrode plate labeled C41 is C4, and the first electrode plate labeled C51 is C5.

[0778] exist Fig.35 , the second electrode plate labeled CC12 is CC1, the second electrode plate labeled CC22 is CC2, the second electrode plate labeled C32 is C3, the second electrode plate labeled C42 is C4, and the second electrode plate labeled C52 is C5.

[0779] exist Fig.37 In the figure, the gate electrode labeled GT61 includes a gate electrode pattern of CT61.

[0780] like Fig.36 As shown, the active pattern of CT5 includes two independent active pattern parts, and the active pattern of CT6 includes two independent active pattern parts;

[0781] The two independent active pattern portions are spaced a certain distance apart to facilitate heat dissipation, so as to improve the performance of the transistor while ensuring the area of ​​the active pattern.

[0782] Figure 32- Fig.40 As shown, the first first voltage line V11, the first second voltage line V12, the second second voltage line V22, the second first voltage line V21, the third first voltage line V31 and the third second voltage line V32 are sequentially arranged in a direction away from the display area;

[0783] V11, V12, V22, V21, V31 and V32 all extend in the vertical direction;

[0784] EN, VEL, CK1 and CB1 all extend in the vertical direction;

[0785] V11, V12, EN, V22, V21, VEL, V31, CK1, CB1 and V32 are arranged in sequence in a direction away from the display area;

[0786] The orthographic projection of V11 on the substrate at least partially overlaps with the orthographic projection of the active pattern AT5 of CT5 on the substrate, and the orthographic projection of V11 on the substrate at least partially overlaps with the orthographic projection of the active pattern AT6 of CT6 on the substrate;

[0787] The orthographic projection of V12 on the substrate at least partially overlaps with the orthographic projection of the active pattern AT5 of CT5 on the substrate, and the orthographic projection of V12 on the substrate at least partially overlaps with the orthographic projection of the active pattern AT6 of CT6 on the substrate;

[0788] The orthographic projection of EN on the substrate at least partially overlaps with the orthographic projection of the active pattern AT8 of CT8 on the substrate; the orthographic projection of EN on the substrate at least partially overlaps with the orthographic projection of the active pattern AT12 of CT12 on the substrate; the orthographic projection of EN on the substrate at least partially overlaps with the orthographic projection of the active pattern AT11 of CT11 on the substrate;

[0789] The orthographic projection of V22 on the substrate at least partially overlaps with the orthographic projection of the active pattern AT7 of CT7 on the substrate;

[0790] The orthographic projection of V22 on the substrate at least partially overlaps with the orthographic projection of the active pattern AT15 of T15 on the substrate; the orthographic projection of V22 on the substrate at least partially overlaps with the orthographic projection of the active pattern AT16 of T16 on the substrate;

[0791] The orthographic projection of V21 on the substrate at least partially overlaps with the orthographic projection of the active pattern AT15 of T15 on the substrate; the orthographic projection of V21 on the substrate at least partially overlaps with the orthographic projection of the active pattern AT16 of T16 on the substrate;

[0792] The orthographic projection of V21 on the substrate at least partially overlaps with the orthographic projection of the first electrode plate C51 of C5 on the substrate; the orthographic projection of V21 on the substrate at least partially overlaps with the orthographic projection of the second electrode plate C52 of C5 on the substrate; the orthographic projection of V31 on the substrate at least partially overlaps with the orthographic projection of the active pattern A5 of T5 on the substrate; the orthographic projection of V31 on the substrate at least partially overlaps with the orthographic projection of the active pattern A6 of T6 on the substrate; the orthographic projection of V31 on the substrate at least partially overlaps with the orthographic projection of the active pattern A7 of T7 on the substrate;

[0793] The orthographic projection of CK1 on the substrate at least partially overlaps with the orthographic projection of the active pattern A9 of T9 on the substrate; the orthographic projection of CK1 on the substrate at least partially overlaps with the orthographic projection of the active pattern A12 of T12 on the substrate;

[0794] The orthographic projection of CK1 on the substrate at least partially overlaps with the orthographic projection of the first electrode plate C41 of C4 on the substrate; the orthographic projection of CK1 on the substrate at least partially overlaps with the orthographic projection of the second electrode plate C42 of C4 on the substrate;

[0795] The orthographic projection of CB1 on the substrate at least partially overlaps with the orthographic projection of the first electrode plate C41 of C4 on the substrate; the orthographic projection of CB1 on the substrate at least partially overlaps with the orthographic projection of the second electrode plate C42 of C4 on the substrate;

[0796] The orthographic projection of CB1 on the substrate at least partially overlaps with the orthographic projection of the first electrode plate C31 of C3 on the substrate; the orthographic projection of CB1 on the substrate at least partially overlaps with the orthographic projection of the second electrode plate C32 of C3 on the substrate;

[0797] The orthographic projection of V32 on the substrate at least partially overlaps with the orthographic projection of the first electrode plate C31 of C3 on the substrate; the orthographic projection of V32 on the substrate at least partially overlaps with the orthographic projection of the second electrode plate C32 of C3 on the substrate;

[0798] The orthographic projection of V32 on the substrate at least partially overlaps with the orthographic projection of the active graphic A4 of T4 on the substrate; the orthographic projection of V32 on the substrate at least partially overlaps with the orthographic projection of the active graphic A1 of T1 on the substrate; the orthographic projection of V32 on the substrate at least partially overlaps with the orthographic projection of the active graphic A8 of T8 on the substrate.

[0799] In at least one embodiment of the present invention, the first voltage line includes a first first voltage line, a second first voltage line, a third first voltage line, and a fourth first voltage line sequentially arranged along a direction away from the display area, and the second voltage line includes a first second voltage line, a second second voltage line, a third second voltage line, and a fourth second voltage line sequentially arranged along a direction away from the display area;

[0800] The orthographic projection of the third first voltage line on the substrate at least partially overlaps with the orthographic projection of the active pattern of at least one transistor included in the output circuit on the substrate;

[0801] The orthographic projection of the third first voltage line on the substrate at least partially overlaps with the orthographic projection of the plate of the capacitor included in the potential maintaining circuit on the substrate;

[0802] The orthographic projection of the third second voltage line on the substrate at least partially overlaps with the orthographic projection of the active pattern of at least one transistor included in the output circuit on the substrate;

[0803] The orthographic projection of the fourth first voltage line on the substrate at least partially overlaps with the orthographic projection of the active pattern of at least one transistor included in the second output node control circuit on the substrate;

[0804] The orthographic projection of the fourth second voltage line on the substrate at least partially overlaps with the orthographic projection of the active pattern of at least one transistor included in the first node control circuit on the substrate;

[0805] An orthographic projection of the fourth second voltage line on the substrate at least partially overlaps with an orthographic projection of a plate of a capacitor included in the second node control circuit on the substrate.

[0806] In at least one embodiment of the present invention, the orthographic projection of each signal line on the substrate at least partially overlaps with the orthographic projection of the active pattern of the corresponding transistor on the substrate, and the signal line and the electrode plate of the corresponding capacitor are arranged to at least partially overlap with the orthographic projection on the substrate, so as to reduce the lateral space occupied by the driving circuit, thereby facilitating the realization of a narrow frame.

[0807] In at least one embodiment of the present invention, the display substrate further includes a second first clock signal line and a second second clock signal line disposed between the fourth first voltage line and the fourth second voltage line;

[0808] The orthographic projection of the second first clock signal line on the substrate at least partially overlaps with the orthographic projection of the plate of the capacitor included in the first output node control circuit on the substrate;

[0809] The orthographic projection of the second second clock signal line on the substrate at least partially overlaps with the orthographic projection of the plate of the capacitor included in the first output node control circuit on the substrate;

[0810] The orthographic projection of the second second clock signal line on the substrate at least partially overlaps with the orthographic projection of the plate of the capacitor included in the first output node control circuit on the substrate;

[0811] The orthographic projection of the second first clock signal line on the substrate at least partially overlaps with the orthographic projection of the active pattern of at least part of the transistor included in the second node control circuit on the substrate;

[0812] An orthographic projection of the second first clock signal line on the substrate at least partially overlaps with an orthographic projection of active patterns of at least a portion of transistors included in the first output node control circuit on the substrate.

[0813] In at least one embodiment of the present invention, the second first clock signal line and the second second clock signal line are arranged between the second first voltage line and the fourth second voltage line;

[0814] The orthographic projection of the second first clock signal line on the substrate at least partially overlaps with the orthographic projection of the active pattern of at least part of the transistors included in the second output node control circuit on the substrate;

[0815] An orthographic projection of the second second clock signal line on the substrate at least partially overlaps with an orthographic projection of active patterns of at least a portion of transistors included in the second output node control circuit on the substrate.

[0816] In at least one embodiment of the present invention, the orthographic projection of the second first voltage line on the substrate at least partially overlaps with the orthographic projection of at least part of the active pattern of the transistor included in the first control circuit on the substrate;

[0817] The orthographic projection of the enabling signal line on the substrate at least partially overlaps with the orthographic projection of the plate of the capacitor included in the second energy storage circuit on the substrate;

[0818] The orthographic projection of the second second voltage line on the substrate at least partially overlaps with the orthographic projection of the plate of the capacitor included in the second energy storage circuit on the substrate;

[0819] An orthographic projection of the second second voltage line on the substrate at least partially overlaps with an orthographic projection of active patterns of at least a portion of transistors included in the control signal generating circuit on the substrate.

[0820] Fig.42A , Fig.42B and Fig.42C yes Fig.17 A first layout diagram of at least one embodiment of a driving circuit is shown.

[0821] Fig.43 yes Fig.42A Layout diagram of the first semiconductor layer in FIG. Fig.44 yes Fig.42A The layout diagram of the first gate metal layer in Fig.45 yes Fig.42A The layout diagram of the second gate metal layer in Fig.46 yes Fig.42A Layout diagram of the first source and drain metal layer in, Fig.47 yes Fig.42A Layout diagram of the second source and drain metal layer in FIG. Fig.48 yes Fig.42A Layout diagram of the third source and drain metal layer in .

[0822] Fig.49A yes Fig.42A The superposition diagram of the first semiconductor layer and the first gate metal layer in FIG. Fig.49B yes Fig.42A The superposition diagram of the first gate metal layer and the second gate metal layer in FIG. Fig.49C yes Fig.42A The superposition diagram of the second gate metal layer and the first source and drain metal layer in FIG. Fig.49D yes Fig.42A An overlay diagram of the first source-drain metal layer and the second source-drain metal layer in FIG. Fig.49E yes Fig.42A An overlay diagram of the second source-drain metal layer and the third source-drain metal layer in FIG.

[0823] exist Fig.42A In at least one embodiment of the display substrate shown, the first semiconductor layer, the first gate metal layer, the second gate metal layer, the first source-drain metal layer, the second source-drain metal layer and the third source-drain metal layer are arranged in sequence in a direction away from the substrate.

[0824] Fig.42A At least one embodiment of the display substrate shown is a display substrate manufactured using a CMOS process.

[0825] exist Fig.43 , AT1 is an active pattern of CT1, AT2 is an active pattern of CT2, AT3 is an active pattern of CT3, AT4 is an active pattern of CT4, AT5 is an active pattern of CT5, AT6 is an active pattern of CT6, AT7 is an active pattern of CT7, AT8 is an active pattern of CT8, AT9 is an active pattern of CT9, AT10 is an active pattern of CT10, AT11 is an active pattern of CT11, and AT12 is an active pattern of CT12;

[0826] A1 is the active pattern of T1, A2 is the active pattern of T2, A3 is the active pattern of T3, A4 is the active pattern of T4, A5 is the active pattern of T5, A6 is the active pattern of T6, A7 is the active pattern of T7, A8 is the active pattern of T8, A9 is the active pattern of T9, A10 is the active pattern of T10, A11 is the active pattern of T11, A12 is the active pattern of T12, A13 is the active pattern of T13, A14 is the active pattern of T14, A15 is the active pattern of T15, and A16 is the active pattern of T16.

[0827] exist Fig.44 , the first electrode plate labeled CC11 is CC1, the first electrode plate labeled CC21 is CC2, the first electrode plate labeled C31 is C3, the first electrode plate labeled C41 is C4, and the first electrode plate labeled C51 is C5.

[0828] exist Fig.45 , the second electrode plate labeled CC12 is CC1, the second electrode plate labeled CC22 is CC2, the second electrode plate labeled C32 is C3, the second electrode plate labeled C42 is C4, and the second electrode plate labeled C52 is C5.

[0829] like Figures 42A-48 As shown, the first voltage line includes a first first voltage line V11, a second first voltage line V21, a third first voltage line V31 and a fourth first voltage line V41 arranged in sequence along a direction away from the display area; the second voltage line includes a first second voltage line V12, a second second voltage line V22, a third second voltage line V32 and a fourth second voltage line V42 arranged in sequence along a direction away from the display area;

[0830] The orthographic projection of V11 on the substrate at least partially overlaps with the orthographic projection of the active pattern AT5 of CT5 on the substrate; the orthographic projection of V11 on the substrate at least partially overlaps with the orthographic projection of the active pattern AT6 of CT6 on the substrate;

[0831] The orthographic projection of V12 on the substrate at least partially overlaps with the orthographic projection of the active pattern AT5 of CT5 on the substrate; the orthographic projection of V12 on the substrate at least partially overlaps with the orthographic projection of the active pattern AT6 of CT6 on the substrate;

[0832] The orthographic projection of V12 on the substrate at least partially overlaps with the orthographic projection of the first electrode plate CC11 of CC1 on the substrate; the orthographic projection of V12 on the substrate at least partially overlaps with the orthographic projection of the second electrode plate CC12 of CC1 on the substrate;

[0833] The orthographic projection of V21 on the substrate at least partially overlaps with the orthographic projection of the active pattern AT4 of CT4 on the substrate; the orthographic projection of V21 on the substrate at least partially overlaps with the orthographic projection of the active pattern AT3 of CT3 on the substrate;

[0834] The orthographic projection of EN on the substrate at least partially overlaps with the orthographic projection of the first electrode plate CC21 of CC2 on the substrate; the orthographic projection of EN on the substrate at least partially overlaps with the orthographic projection of the second electrode plate CC22 of CC2 on the substrate;

[0835] The orthographic projection of EN on the substrate at least partially overlaps with the orthographic projection of the active pattern AT9 of CT9 on the substrate; the orthographic projection of EN on the substrate at least partially overlaps with the orthographic projection of the active pattern AT8 of CT8 on the substrate;

[0836] The orthographic projection of V22 on the substrate at least partially overlaps with the orthographic projection of the first electrode plate CC21 of CC2 on the substrate; the orthographic projection of V22 on the substrate at least partially overlaps with the orthographic projection of the second electrode plate CC22 of CC2 on the substrate;

[0837] The orthographic projection of V22 on the substrate at least partially overlaps with the orthographic projection of the active pattern AT10 of CT10 on the substrate; the orthographic projection of V22 on the substrate at least partially overlaps with the orthographic projection of the active pattern AT7 of CT7 on the substrate;

[0838] The orthographic projection of V31 on the substrate at least partially overlaps with the orthographic projection of the active pattern A15 of T15 on the substrate; the orthographic projection of V31 on the substrate at least partially overlaps with the orthographic projection of the active pattern A16 of T16 on the substrate;

[0839] The orthographic projection of V31 on the substrate at least partially overlaps with the orthographic projection of the first electrode plate C51 of C5 on the substrate; the orthographic projection of V31 on the substrate at least partially overlaps with the orthographic projection of the second electrode plate C52 of C5 on the substrate;

[0840] The orthographic projection of V41 on the substrate at least partially overlaps with the orthographic projection of the active pattern A5 of T5 on the substrate; the orthographic projection of V41 on the substrate at least partially overlaps with the orthographic projection of the active pattern A6 of T6 on the substrate; the orthographic projection of V41 on the substrate at least partially overlaps with the orthographic projection of the active pattern A7 of T7 on the substrate;

[0841] The orthographic projection of V42 on the substrate at least partially overlaps with the orthographic projection of the active pattern A4 of T4 on the substrate; the orthographic projection of V42 on the substrate at least partially overlaps with the orthographic projection of the active pattern A1 of T1 on the substrate; the orthographic projection of V42 on the substrate at least partially overlaps with the orthographic projection of the active pattern A8 of T8 on the substrate;

[0842] The orthographic projection of V42 on the substrate at least partially overlaps with the orthographic projection of the first electrode plate C31 of C3 on the substrate; the orthographic projection of V42 on the substrate at least partially overlaps with the orthographic projection of the second electrode plate C32 of C3 on the substrate.

[0843] like Figures 42A-48 As shown, the display substrate further includes a second first clock signal line CK2 and a second second clock signal line CB2 disposed between V41 and V42;

[0844] The orthographic projection of CK2 on the substrate at least partially overlaps with the orthographic projection of the first electrode plate C41 of C4 on the substrate; the orthographic projection of CK2 on the substrate at least partially overlaps with the orthographic projection of the second electrode plate C42 of C4 on the substrate;

[0845] The orthographic projection of CK2 on the substrate at least partially overlaps with the orthographic projection of the active pattern A9 of T9 on the substrate; the orthographic projection of CK2 on the substrate at least partially overlaps with the orthographic projection of the active pattern A12 of T12 on the substrate;

[0846] The orthographic projection of CB2 on the substrate at least partially overlaps with the orthographic projection of the first electrode plate C41 of C4 on the substrate; the orthographic projection of CB2 on the substrate at least partially overlaps with the orthographic projection of the second electrode plate C42 of C4 on the substrate;

[0847] The orthographic projection of CB2 on the substrate at least partially overlaps with the orthographic projection of the first electrode plate C31 of C3 on the substrate; the orthographic projection of CB2 on the substrate at least partially overlaps with the orthographic projection of the second electrode plate C32 of C3 on the substrate.

[0848] In at least one embodiment of the present invention, the second voltage line includes a third second voltage line; the third second voltage line is arranged on a side of the second second voltage line away from the display area;

[0849] An orthographic projection of the third second voltage line on the substrate at least partially overlaps with an orthographic projection of an active pattern of at least one transistor included in the output inverter circuit on the substrate.

[0850] like Figures 42A-48 As shown, the second voltage line includes a third second voltage line V32, and V32 is arranged on a side of V22 away from the display area;

[0851] The orthographic projection of V32 on the substrate at least partially overlaps with the orthographic projection of the active pattern A15 of T15 on the substrate; the orthographic projection of V32 on the substrate at least partially overlaps with the orthographic projection of the active pattern A16 of T16 on the substrate;

[0852] The orthographic projection of V32 on the substrate at least partially overlaps with the orthographic projection of the active pattern AT11 of CT11 on the substrate; the orthographic projection of V32 on the substrate at least partially overlaps with the orthographic projection of the active pattern AT12 of CT12 on the substrate;

[0853] In at least one embodiment of the present invention, the orthographic projection of the second first voltage line on the substrate at least partially overlaps with the orthographic projection of at least part of the active pattern of the transistor included in the first control circuit on the substrate;

[0854] The orthographic projection of the second second voltage line on the substrate at least partially overlaps with the orthographic projection of the plate of the capacitor included in the first energy storage circuit on the substrate;

[0855] The orthographic projection of the second second voltage line on the substrate at least partially overlaps with the orthographic projection of the active pattern of at least part of the transistor included in the first control circuit on the substrate;

[0856] The orthographic projection of the second first voltage line on the substrate at least partially overlaps with the orthographic projection of the active pattern of at least part of the transistor included in the first control circuit on the substrate;

[0857] An orthographic projection of the second first voltage line on the substrate at least partially overlaps with an orthographic projection of active patterns of at least a portion of transistors included in the control signal generating circuit on the substrate.

[0858] In at least one embodiment of the present invention, the orthographic projection of each signal line on the substrate at least partially overlaps with the orthographic projection of the active pattern of the corresponding transistor on the substrate, and the signal line and the electrode plate of the corresponding capacitor are arranged to at least partially overlap with the orthographic projection on the substrate, so as to reduce the lateral space occupied by the driving circuit, thereby facilitating the realization of a narrow frame.

[0859] Fig.50A , Fig.50B and Fig.50C yes Fig.17 A second layout diagram of at least one embodiment of a driving circuit is shown.

[0860] Fig.51 yes Fig.50A Layout diagram of the first semiconductor layer in FIG. Fig.52 yes Fig.50A The layout diagram of the first gate metal layer in Fig.53 yes Fig.50A The layout diagram of the second gate metal layer in Fig.54 yes Fig.50A A layout diagram of the second semiconductor layer in FIG. Fig.55 yes Fig.50A The layout diagram of the third gate metal layer in Fig.56 yes Fig.50A Layout diagram of the first source and drain metal layer in, Fig.57 yes Fig.50A Layout diagram of the second source and drain metal layer in FIG. Fig.58 yes Fig.50A Layout diagram of the third source and drain metal layer in .

[0861] Fig.59A yes Fig.50A A schematic diagram of the superposition of the first semiconductor layer and the first gate metal layer; Fig.59B yes Fig.50A A schematic diagram of the superposition of the first gate metal layer and the second gate metal layer;

[0862] Fig.59C yes Fig.50A A schematic diagram of the superposition of the second gate metal layer and the second semiconductor layer; Fig.59D yes Fig.50A A schematic diagram of the superposition of the third gate metal layer and the second semiconductor layer; Fig.59E yes Fig.50A A schematic diagram of the superposition of the third gate metal layer and the first source and drain metal layer; Fig.59F yes Fig.50A A schematic diagram of the superposition of the first source-drain metal layer and the second source-drain metal layer; Figure 59G yes Fig.50A Schematic diagram of the superposition of the second source-drain metal layer and the third source-drain metal layer.

[0863] exist Fig.50A In at least one embodiment of the display substrate shown, the first semiconductor layer, the first gate metal layer, the second gate metal layer, the second semiconductor layer, the third gate metal layer, the first source-drain metal layer, the second source-drain metal layer and the third source-drain metal layer are arranged in sequence along a direction away from the substrate.

[0864] Fig.50A At least one embodiment of the display substrate shown is a driving circuit manufactured using an LTPO (low temperature polycrystalline oxide) process.

[0865] exist Fig.51 , 54 , AT1 is an active pattern of CT1, AT2 is an active pattern of CT2, AT3 is an active pattern of CT3, AT4 is an active pattern of CT4, AT5 is an active pattern of CT5, AT6 is an active pattern of CT6, AT7 is an active pattern of CT7, AT8 is an active pattern of CT8, AT9 is an active pattern of CT9, AT10 is an active pattern of CT10, AT11 is an active pattern of CT11, and AT12 is an active pattern of CT12;

[0866] A1 is the active pattern of T1, A2 is the active pattern of T2, A3 is the active pattern of T3, A4 is the active pattern of T4, A5 is the active pattern of T5, A6 is the active pattern of T6, A7 is the active pattern of T7, A8 is the active pattern of T8, A9 is the active pattern of T9, A10 is the active pattern of T10, A11 is the active pattern of T11, A12 is the active pattern of T12, A13 is the active pattern of T13, A14 is the active pattern of T14, A15 is the active pattern of T15, and A16 is the active pattern of T16.

[0867] exist Fig.52 , the first electrode plate labeled CC11 is CC1, the first electrode plate labeled CC21 is CC2, the first electrode plate labeled C31 is C3, the first electrode plate labeled C41 is C4, and the first electrode plate labeled C51 is C5.

[0868] exist Fig.53 , the second electrode plate labeled CC12 is CC1, the second electrode plate labeled CC22 is CC2, the second electrode plate labeled C32 is C3, the second electrode plate labeled C42 is C4, and the second electrode plate labeled C52 is C5.

[0869] like Figure 50A-Figure 58 As shown, the orthographic projection of the second second voltage line V22 on the substrate at least partially overlaps with the orthographic projection of the active pattern AT4 of CT4 on the substrate; the orthographic projection of the second second voltage line V22 on the substrate at least partially overlaps with the orthographic projection of the active pattern AT2 of CT2 on the substrate;

[0870] The orthographic projection of the second second voltage line V22 on the substrate at least partially overlaps with the orthographic projection of the first electrode plate CC11 of CC1 on the substrate; the orthographic projection of the second second voltage line V22 on the substrate at least partially overlaps with the orthographic projection of the second electrode plate CC12 of CC1 on the substrate;

[0871] The orthographic projection of the second second voltage line V22 on the substrate at least partially overlaps with the orthographic projection of the first electrode plate CC21 of CC2 on the substrate; the orthographic projection of the second second voltage line V22 on the substrate at least partially overlaps with the orthographic projection of the second electrode plate CC22 of CC2 on the substrate;

[0872] In at least one embodiment of the present invention, the orthographic projection of the second first voltage line on the substrate at least partially overlaps with the orthographic projection of the active pattern of at least one transistor included in the output inverter circuit on the substrate;

[0873] The enable signal line is arranged on a side of the second first voltage line away from the display area.

[0874] like Figure 50A-Figure 58 As shown, the orthographic projection of the second first voltage line V21 on the substrate at least partially overlaps with the orthographic projection of the active pattern AT12 of CT12 on the substrate; the orthographic projection of the second first voltage line V21 on the substrate at least partially overlaps with the orthographic projection of the active pattern AT11 of CT11 on the substrate;

[0875] The orthographic projection of the second first voltage line V21 on the substrate at least partially overlaps with the orthographic projection of the active pattern AT10 of CT10 on the substrate; the orthographic projection of the second first voltage line V21 on the substrate at least partially overlaps with the orthographic projection of the active pattern AT3 of CT3 on the substrate;

[0876] The enable signal line EN is disposed at a side of the second first voltage line V21 away from the display area.

[0877] like Figure 50A-Figure 58 As shown, the first voltage lines include a first first voltage line V11, a second first voltage line V21, a third first voltage line V31 and a fourth first voltage line V41 arranged in sequence along a direction away from the display area; the second voltage lines include a first second voltage line V12, a second second voltage line V22, a third second voltage line V32 and a fourth second voltage line V42 arranged in sequence along a direction away from the display area;

[0878] V11, V12, V22, V21, EN, V32, V31, VEL, V41, CK2, CB2 and V42 are arranged in sequence in a direction away from the display area;

[0879] V11, V12, V22, V21, EN, V32, V31, VEL, V41, CK2, CB2 and V42 are arranged in sequence along the vertical direction.

[0880] like Figure 50A-Figure 58 As shown, the orthographic projection of V11 on the substrate at least partially overlaps with the orthographic projection of the active pattern AT6 of CT6 on the substrate; the orthographic projection of V11 on the substrate at least partially overlaps with the orthographic projection of the active pattern AT5 of CT5 on the substrate;

[0881] The orthographic projection of V12 on the substrate at least partially overlaps with the orthographic projection of the active pattern AT6 of CT6 on the substrate; the orthographic projection of V12 on the substrate at least partially overlaps with the orthographic projection of the active pattern AT5 of CT5 on the substrate;

[0882] The orthographic projection of the enable signal line EN on the substrate at least partially overlaps with the orthographic projection of the active pattern AT9 of CT9 on the substrate;

[0883] The orthographic projection of V32 on the substrate at least partially overlaps with the orthographic projection of the active pattern A15 of T15 on the substrate; the orthographic projection of V32 on the substrate at least partially overlaps with the orthographic projection of the active pattern A16 of T16 on the substrate;

[0884] The orthographic projection of V31 on the substrate at least partially overlaps with the orthographic projection of the active pattern A15 of T15 on the substrate; the orthographic projection of V31 on the substrate at least partially overlaps with the orthographic projection of the active pattern A16 of T16 on the substrate;

[0885] The orthographic projection of V31 on the substrate at least partially overlaps with the orthographic projection of the first electrode plate C51 of C5 on the substrate; the orthographic projection of V31 on the substrate at least partially overlaps with the orthographic projection of the second electrode plate C52 of C5 on the substrate;

[0886] The orthographic projection of V41 on the substrate at least partially overlaps with the orthographic projection of the active pattern A5 of T5 on the substrate; the orthographic projection of V41 on the substrate at least partially overlaps with the orthographic projection of the active pattern A6 of T6 on the substrate; the orthographic projection of V41 on the substrate at least partially overlaps with the orthographic projection of the active pattern A7 of T7 on the substrate;

[0887] The orthographic projection of V42 on the substrate at least partially overlaps with the orthographic projection of the active pattern A4 of T4 on the substrate; the orthographic projection of V42 on the substrate at least partially overlaps with the orthographic projection of the active pattern A1 of T1 on the substrate; the orthographic projection of V42 on the substrate at least partially overlaps with the orthographic projection of the active pattern A8 of T8 on the substrate;

[0888] The orthographic projection of V42 on the substrate at least partially overlaps with the orthographic projection of the first electrode plate C31 of C3 on the substrate; the orthographic projection of V42 on the substrate at least partially overlaps with the orthographic projection of the second electrode plate C32 of C3 on the substrate;

[0889] The orthographic projection of CK2 on the substrate at least partially overlaps with the orthographic projection of the first electrode plate C41 of C4 on the substrate; the orthographic projection of CK2 on the substrate at least partially overlaps with the orthographic projection of the second electrode plate C42 of C4 on the substrate;

[0890] The orthographic projection of CK2 on the substrate at least partially overlaps with the orthographic projection of the active pattern A9 of T9 on the substrate; the orthographic projection of CK2 on the substrate at least partially overlaps with the orthographic projection of the active pattern A12 of T12 on the substrate;

[0891] The orthographic projection of CB2 on the substrate at least partially overlaps with the orthographic projection of the first electrode plate C41 of C4 on the substrate; the orthographic projection of CB2 on the substrate at least partially overlaps with the orthographic projection of the second electrode plate C42 of C4 on the substrate;

[0892] The orthographic projection of CB2 on the substrate at least partially overlaps with the orthographic projection of the first electrode plate C31 of C3 on the substrate; the orthographic projection of CB2 on the substrate at least partially overlaps with the orthographic projection of the second electrode plate C32 of C3 on the substrate.

[0893] like Fig.50A As shown, the active pattern of CT5 includes two independent active pattern parts, and the active pattern of CT6 includes two independent active pattern parts;

[0894] The two independent active pattern portions are spaced a certain distance apart to facilitate heat dissipation, so as to improve the performance of the transistor while ensuring the area of ​​the active pattern.

[0895] Fig.60A , Fig.60B and Fig.60C yes Fig. 20 A first layout diagram of at least one embodiment of a driving circuit is shown.

[0896] Fig.61 yes Fig.60A Layout diagram of the first semiconductor layer in FIG. Fig.62 yes Fig.60A The layout diagram of the first gate metal layer in Fig.63 yes Fig.60A The layout diagram of the second gate metal layer in Fig.64 yes Fig.60A Layout diagram of the first source and drain metal layer in, Fig.65 yes Fig.60A Layout diagram of the second source and drain metal layer in .

[0897] Fig.66A yes Fig.60A The superposition diagram of the first semiconductor layer and the first gate metal layer in FIG. Fig.66B yes Fig.60A An overlay diagram of a first gate metal layer and a second gate metal layer in FIG. Fig.66C yes Fig.60A An overlay diagram of the second gate metal layer and the first source and drain metal layer; Fig.66D yes Fig.60A An overlay diagram of the first source-drain metal layer and the second source-drain metal layer.

[0898] exist Fig.60A In at least one embodiment of the display substrate shown, the first semiconductor layer, the first gate metal layer, the second gate metal layer, the first source-drain metal layer, and the second source-drain metal layer are arranged in sequence along a direction away from the substrate.

[0899] Fig.60A At least one embodiment of the display substrate shown is a display substrate manufactured using a CMOS process.

[0900] exist Fig.61 , AT1 is the active pattern of CT1, AT2 is the active pattern of CT2, AT3 is the active pattern of CT3, AT4 is the active pattern of CT4, AT5 is the active pattern of CT5, AT6 is the active pattern of CT6, AT7 is the active pattern of CT7, and AT8 is the active pattern of CT8;

[0901] A17 is the active pattern of T17, A18 is the active pattern of T18, A19 is the active pattern of T19, A20 is the active pattern of T20, A21 is the active pattern of T21, A22 is the active pattern of T22, A23 is the active pattern of T23, and A24 is the active pattern of T24.

[0902] exist Fig.62 , the one labeled CC11 is the first electrode plate of CC1, the one labeled C61 is the first electrode plate of C6, and the one labeled C71 is the first electrode plate of C7.

[0903] exist Fig.63 , the one labeled CC12 is the second electrode plate of CC1, the one labeled C62 is the second electrode plate of C6, and the one labeled C72 is the second electrode plate of C7.

[0904] In at least one embodiment of the present invention, the first voltage line includes a first first voltage line, the second voltage line includes a first second voltage line, a second second voltage line and a third second voltage line sequentially arranged in a direction away from the display area; the enable signal line is arranged between the second second voltage line and the third second voltage line;

[0905] The orthographic projection of the first second voltage line on the substrate at least partially overlaps with the orthographic projection of the active pattern of at least part of the transistor included in the second control circuit on the substrate;

[0906] The orthographic projection of the first first voltage line on the substrate at least partially overlaps with the orthographic projection of the active pattern of at least part of the transistor included in the second control circuit on the substrate;

[0907] The orthographic projection of the first first voltage line on the substrate at least partially overlaps with the orthographic projection of the active pattern of at least part of the transistor included in the first control circuit on the substrate;

[0908] The orthographic projection of the first first voltage line on the substrate at least partially overlaps with the orthographic projection of the plate of the capacitor included in the first energy storage circuit on the substrate;

[0909] The orthographic projection of the first second voltage line on the substrate at least partially overlaps with the orthographic projection of the plate of the capacitor included in the first energy storage circuit on the substrate;

[0910] The orthographic projection of the second second voltage line on the substrate at least partially overlaps with the orthographic projection of the active pattern of at least part of the transistor included in the first control circuit on the substrate;

[0911] The orthographic projection of the enable signal line on the substrate at least partially overlaps with the orthographic projection of the active pattern of at least part of the transistor included in the control signal generating circuit on the substrate;

[0912] An orthographic projection of the third second voltage line on the substrate at least partially overlaps with an orthographic projection of active patterns of at least a portion of transistors included in the control signal generating circuit on the substrate.

[0913] In at least one embodiment of the present invention, the orthographic projection of each signal line on the substrate at least partially overlaps with the orthographic projection of the active pattern of the corresponding transistor on the substrate, and the signal line and the electrode plate of the corresponding capacitor are arranged to at least partially overlap with the orthographic projection on the substrate, so as to reduce the lateral space occupied by the driving circuit, thereby facilitating the realization of a narrow frame.

[0914] like Figure 60A-Figure 65 As shown, the first voltage line includes a first first voltage line V11, and the second voltage line includes a first second voltage line V12, a second second voltage line V22, and a third second voltage line V32 sequentially arranged in a direction away from the display area; the enable signal line EN is arranged between the second second voltage line V22 and the third second voltage line V32;

[0915] The orthographic projection of V12 on the substrate at least partially overlaps with the orthographic projection of the active pattern AT6 of CT6 on the substrate;

[0916] The orthographic projection of V12 on the substrate at least partially overlaps with the orthographic projection of the active pattern AT5 of CT5 on the substrate;

[0917] The orthographic projection of V11 on the substrate at least partially overlaps with the orthographic projection of the active pattern AT5 of CT5 on the substrate; the orthographic projection of V11 on the substrate at least partially overlaps with the orthographic projection of the active pattern AT1 of CT1 on the substrate; the orthographic projection of V11 on the substrate at least partially overlaps with the orthographic projection of the active pattern AT2 of CT2 on the substrate;

[0918] The orthographic projection of V11 on the substrate at least partially overlaps with the orthographic projection of the first electrode plate CC11 of CC1 on the substrate; the orthographic projection of V11 on the substrate at least partially overlaps with the orthographic projection of the second electrode plate CC12 of CC1 on the substrate;

[0919] The orthographic projection of V12 on the substrate at least partially overlaps with the orthographic projection of the first electrode plate CC11 of CC1 on the substrate; the orthographic projection of V12 on the substrate at least partially overlaps with the orthographic projection of the second electrode plate CC12 of CC1 on the substrate;

[0920] The orthographic projection of V22 on the substrate at least partially overlaps with the orthographic projection of the active pattern AT2 of CT2 on the substrate; the orthographic projection of V22 on the substrate at least partially overlaps with the orthographic projection of the active pattern AT1 of CT1 on the substrate; the orthographic projection of V22 on the substrate at least partially overlaps with the orthographic projection of the active pattern AT3 of CT3 on the substrate;

[0921] The orthographic projection of EN on the substrate at least partially overlaps with the orthographic projection of the active pattern AT7 of CT7 on the substrate; the orthographic projection of EN on the substrate at least partially overlaps with the orthographic projection of the active pattern AT8 of CT8 on the substrate; the orthographic projection of EN on the substrate at least partially overlaps with the orthographic projection of the active pattern AT4 of CT4 on the substrate;

[0922] The orthographic projection of V32 on the substrate at least partially overlaps with the orthographic projection of the active graphic AT7 of CT7 on the substrate; the orthographic projection of V32 on the substrate at least partially overlaps with the orthographic projection of the active graphic AT8 of CT8 on the substrate; the orthographic projection of V32 on the substrate at least partially overlaps with the orthographic projection of the active graphic AT4 of CT4 on the substrate.

[0923] In at least one embodiment of the present invention, the first voltage line includes a first first voltage line and a second first voltage line sequentially arranged along a direction away from the display area, and the second voltage line includes a first second voltage line, a second second voltage line, a third second voltage line and a fourth second voltage line sequentially arranged along a direction away from the display area;

[0924] The orthographic projection of the plate of the capacitor included in the third energy storage circuit on the substrate is arranged between the orthographic projection of the third second voltage line on the substrate and the orthographic projection of the second first voltage line on the substrate;

[0925] The orthographic projection of the second first voltage line on the substrate at least partially overlaps with the orthographic projection of the plate of the capacitor included in the first output node control circuit on the substrate;

[0926] The orthographic projection of the second first voltage line on the substrate at least partially overlaps with the orthographic projection of the active pattern of at least part of the transistor included in the output circuit on the substrate;

[0927] An orthographic projection of the fourth second voltage line on the substrate at least partially overlaps with an orthographic projection of active patterns of at least a portion of transistors included in the first output node control circuit on the substrate.

[0928] like Figure 60A-Figure 65 As shown, the first voltage lines include a first first voltage line V11 and a second first voltage line V21 sequentially arranged along a direction away from the display area, and the second voltage lines include a first second voltage line V12, a second second voltage line V22, a third second voltage line V32 and a fourth second voltage line V42 sequentially arranged along a direction away from the display area;

[0929] The orthographic projection of the first electrode plate C71 of C7 on the substrate is arranged between the orthographic projection of V32 on the substrate and the orthographic projection of V21 on the substrate; the orthographic projection of the second electrode plate C72 of C7 on the substrate is arranged between the orthographic projection of V32 on the substrate and the orthographic projection of V21 on the substrate;

[0930] The orthographic projection of V21 on the substrate at least partially overlaps with the orthographic projection of the first electrode plate C61 of C6 on the substrate; the orthographic projection of V21 on the substrate at least partially overlaps with the orthographic projection of the second electrode plate C62 of C6 on the substrate;

[0931] The orthographic projection of V21 on the substrate at least partially overlaps with the orthographic projection of the active pattern A23 of T23 on the substrate;

[0932] The orthographic projection of V42 on the substrate at least partially overlaps with the orthographic projection of the active pattern A17 of T17 on the substrate; the orthographic projection of V42 on the substrate at least partially overlaps with the orthographic projection of the active pattern A18 of T18 on the substrate.

[0933] like Figure 60A-Figure 65 As shown, the third first clock signal line CK3 and the third second clock signal line CB3 are arranged between V21 and V42;

[0934] The orthographic projection of CK3 on the substrate at least partially overlaps with the orthographic projection of the active pattern A20 of T20 on the substrate; the orthographic projection of CK on the substrate at least partially overlaps with the orthographic projection of the active pattern A21 of T21 on the substrate;

[0935] The orthographic projection of CB3 on the substrate at least partially overlaps with the orthographic projection of the active pattern A19 of T19 on the substrate.

[0936] like Figure 60A-Figure 65 As shown, V12, V11, V22, EN, V32, V21, CK3, CB3 and V42 are arranged in sequence in the direction away from the display area, and V12, V11, V22, EN, V32, V21, CK3, CB3 and V42 are all arranged in the vertical direction.

[0937] In at least one embodiment of the present invention, the first voltage line includes a first first voltage line, and the second voltage line includes a first second voltage line and a second second voltage line sequentially arranged in a direction away from the display area; the enable signal line is arranged between the first second voltage line and the second second voltage line;

[0938] The orthographic projection of the first second voltage line on the substrate at least partially overlaps with the orthographic projection of the active pattern of at least part of the transistor included in the second control circuit on the substrate;

[0939] The orthographic projection of the enable signal line on the substrate at least partially overlaps with the orthographic projection of the plate of the capacitor included in the first energy storage circuit on the substrate; the orthographic projection of the second second voltage line on the substrate at least partially overlaps with the orthographic projection of the active pattern of at least part of the transistor included in the control signal generating circuit on the substrate;

[0940] The orthographic projection of the first first voltage line on the substrate at least partially overlaps with the orthographic projection of the active pattern of at least part of the transistor included in the second control circuit on the substrate;

[0941] An orthographic projection of the first first voltage line on the substrate at least partially overlaps with an orthographic projection of active patterns of at least a portion of transistors included in the first control circuit on the substrate.

[0942] In at least one embodiment of the present invention, the first voltage line includes a first first voltage line and a second first voltage line sequentially arranged along a direction away from the display area, and the second voltage line includes a first second voltage line, a second second voltage line, a third second voltage line and a fourth second voltage line sequentially arranged along a direction away from the display area;

[0943] The orthographic projection of the third second voltage line on the substrate at least partially overlaps with the orthographic projection of the plate of the capacitor included in the third energy storage circuit on the substrate;

[0944] The orthographic projection of the second first voltage line on the substrate at least partially overlaps with the orthographic projection of the plate of the capacitor included in the first output node control circuit on the substrate;

[0945] The orthographic projection of the second first voltage line on the substrate at least partially overlaps with the orthographic projection of the active pattern of at least part of the transistor included in the output circuit on the substrate;

[0946] An orthographic projection of the fourth second voltage line on the substrate at least partially overlaps with an orthographic projection of active patterns of at least a portion of transistors included in the first output node control circuit on the substrate.

[0947] In at least one embodiment of the present invention, the orthographic projection of each signal line on the substrate at least partially overlaps with the orthographic projection of the active pattern of the corresponding transistor on the substrate, and the signal line and the electrode plate of the corresponding capacitor are arranged to at least partially overlap with the orthographic projection on the substrate, so as to reduce the lateral space occupied by the driving circuit, thereby facilitating the realization of a narrow frame.

[0948] Fig.67A , Fig.67B and Fig.67C Yes Fig. 20 A second layout diagram of a display substrate of at least one embodiment of the driving circuit shown;

[0949] Fig.68 yes Fig.67A Layout diagram of the first semiconductor layer in FIG. Fig.69 yes Fig.67A The layout diagram of the first gate metal layer in Fig.70 yes Fig.67A The layout diagram of the second gate metal layer in Fig.71 yes Fig.67A A layout diagram of the second semiconductor layer in FIG. Fig.72 yes Fig.67A The layout diagram of the third gate metal layer in Fig.73 yes Fig.67A Layout diagram of the first source and drain metal layer in, Fig.74 yes Fig.67A Layout diagram of the second source and drain metal layer in .

[0950] Fig.75A yes Fig.67A A layout diagram of the first semiconductor layer and the first gate metal layer in FIG. Fig.75B yes Fig.67A Layout diagram of the first gate metal layer and the second gate metal layer in FIG. Fig.75C yes Fig.67A A layout diagram of the second gate metal layer and the second semiconductor layer in FIG. Fig.75D yes Fig.67A Layout diagram of the third gate metal layer and the second semiconductor layer in FIG. Fig.75E yes Fig.67A Layout diagram of the third gate metal layer and the first source and drain metal layer in FIG. Fig.75F yes Fig.67ALayout diagram of the first source-drain metal layer and the second source-drain metal layer.

[0951] exist Fig.67A In at least one embodiment of the display substrate shown, the first semiconductor layer, the first gate metal layer, the second gate metal layer, the second semiconductor layer, the third gate metal layer, the first source-drain metal layer and the second source-drain metal layer are arranged in sequence in a direction away from the substrate.

[0952] Fig.67A At least one embodiment of the display substrate shown is a display substrate manufactured using the LTPO process.

[0953] exist Fig.68 , Fig.71 , AT1 is the active pattern of CT1, AT2 is the active pattern of CT2, AT3 is the active pattern of CT3, AT4 is the active pattern of CT4, AT5 is the active pattern of CT5, AT6 is the active pattern of CT6, AT7 is the active pattern of CT7, and AT8 is the active pattern of CT8;

[0954] A17 is the active pattern of T17, A18 is the active pattern of T18, A19 is the active pattern of T19, A20 is the active pattern of T20, A21 is the active pattern of T21, A22 is the active pattern of T22, A23 is the active pattern of T23, and A24 is the active pattern of T24.

[0955] exist Fig.69 , the one labeled CC11 is the first electrode plate of CC1, the one labeled C61 is the first electrode plate of C6, and the one labeled C71 is the first electrode plate of C7.

[0956] exist Fig.70 , the one labeled CC12 is the second electrode plate of CC1, the one labeled C62 is the second electrode plate of C6, and the one labeled C72 is the second electrode plate of C7.

[0957] like Figure 67A-Figure 74 As shown, the first voltage line includes a first first voltage line V11, and the second voltage line includes a first second voltage line V12 and a second second voltage line V22 sequentially arranged in a direction away from the display area; the enable signal line EN is arranged between the first second voltage line V12 and the second second voltage line V22;

[0958] The orthographic projection of V12 on the substrate at least partially overlaps with the orthographic projection of the active pattern AT6 of CT6 on the substrate;

[0959] The orthographic projection of EN on the substrate at least partially overlaps with the orthographic projection of the first plate CC11 of CC1 on the substrate; the orthographic projection of EN on the substrate at least partially overlaps with the orthographic projection of the second plate CC12 of CC1 on the substrate;

[0960] The orthographic projection of V22 on the substrate at least partially overlaps with the orthographic projection of the active pattern AT7 of CT7 on the substrate;

[0961] The orthographic projection of V11 on the substrate at least partially overlaps with the orthographic projection of the active graphic AT4 of CT4 on the substrate; the orthographic projection of V11 on the substrate at least partially overlaps with the orthographic projection of the active graphic AT3 of CT3 on the substrate; the orthographic projection of V11 on the substrate at least partially overlaps with the orthographic projection of the active graphic AT5 of CT5 on the substrate.

[0962] like Figure 67A-Figure 74 As shown, the first voltage lines include a first first voltage line V11 and a second first voltage line V21 sequentially arranged along a direction away from the display area, and the second voltage lines include a first second voltage line V12, a second second voltage line V22, a third second voltage line V32 and a fourth second voltage line V42 sequentially arranged along a direction away from the display area;

[0963] The orthographic projection of V32 on the substrate at least partially overlaps with the orthographic projection of the first electrode plate C71 of C7 on the substrate; the orthographic projection of V32 on the substrate at least partially overlaps with the orthographic projection of the second electrode plate C72 of C7 on the substrate;

[0964] The orthographic projection of V21 on the substrate at least partially overlaps with the orthographic projection of the active pattern A23 of T23 on the substrate;

[0965] The orthographic projection of V21 on the substrate at least partially overlaps with the orthographic projection of the first electrode plate C61 of C6 on the substrate; the orthographic projection of V21 on the substrate at least partially overlaps with the orthographic projection of the second electrode plate C62 of C6 on the substrate;

[0966] The orthographic projection of V42 on the substrate at least partially overlaps with the orthographic projection of the active pattern A17 of T17 on the substrate;

[0967] The orthographic projection of V42 on the substrate at least partially overlaps with the orthographic projection of the active pattern A18 of T18 on the substrate.

[0968] like Figure 67A-Figure 74 As shown, CK3 and CB3 are arranged between V21 and V42;

[0969] The orthographic projection of CK3 on the substrate at least partially overlaps with the orthographic projection of the active pattern A20 of T20 on the substrate; the orthographic projection of CK on the substrate at least partially overlaps with the orthographic projection of the active pattern A21 of T21 on the substrate;

[0970] The orthographic projection of CB3 on the substrate at least partially overlaps with the orthographic projection of the active pattern A19 of T19 on the substrate.

[0971] like Figure 67A-Figure 74 As shown, the active pattern AT6 of CT6 includes three independent active pattern parts;

[0972] The three mutually independent active pattern parts are spaced at a certain distance from each other to facilitate heat dissipation, so as to improve the performance of the transistor while ensuring the area of ​​the active pattern.

[0973] The display device described in the embodiment of the present invention includes the above-mentioned display substrate.

[0974] The above is a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A display substrate, characterized in that: It includes a substrate and a driving circuit arranged on the substrate; The display substrate includes a display area and a peripheral area; the driving circuit is arranged in the peripheral area; The driving circuit includes a driving signal generating circuit, a control signal generating circuit and a control circuit; The drive signal generating circuit is electrically connected to the first clock signal line and the second clock signal line respectively, and is used to generate and output the n-th level drive signal through the n-th level drive signal output terminal under the control of the first clock signal provided by the first clock signal line and the second clock signal provided by the second clock signal line; n is a positive integer; The control signal generating circuit is electrically connected to the enable signal line and the control signal terminal respectively, and is used to output a control signal to the control signal terminal according to the enable signal provided by the enable signal line; The control circuit is electrically connected to the control signal terminal and the n-th level driving output terminal respectively, and is used to output a signal to the n-th level driving output terminal under the control of the control signal.

2. The display substrate according to claim 1, wherein: The driving circuit also includes an output inverting circuit; The output inversion circuit is electrically connected to the n-th level driving signal output terminal and the n-th level inverted signal output terminal respectively, and is used to invert the n-th level driving signal to obtain and output the n-th level inverted driving signal through the n-th level inverted signal output terminal; The control signal generating circuit is also electrically connected to the n-1th level driving signal output terminal, the n-1th level inverted signal output terminal, the n-level driving signal output terminal and the n-level inverted signal output terminal respectively, and is used to generate a control signal according to an enable signal provided by an enable signal line under the control of the n-1th level driving signal, the n-1th level inverted signal, the n-level driving signal and the n-level inverted signal; The n-1th level driving signal output terminal is used to provide the n-1th level driving signal, and the n-1th level inverting signal output terminal is used to provide the n-1th level inverting signal; The control signal generating circuit is arranged on a side of the driving signal generating circuit close to the display area.

3. The display substrate according to claim 1, wherein: The control circuit in the driving circuit includes a first control circuit, a second control circuit and a first energy storage circuit; the control circuit is arranged on a side of the driving signal generating circuit close to the display area; The first control circuit is electrically connected to the control signal terminal, the n-th level drive signal output terminal, the first control voltage line, the second control voltage line and the control output terminal respectively, and is used to control the connection or disconnection between the control output terminal and the first control voltage line under the control of the control signal, control the connection or disconnection between the control output terminal and the first control voltage line under the control of the n-th level drive signal outputted by the n-th level drive signal output terminal, and control the connection or disconnection between the control output terminal and the second control voltage line under the control of the n-th level drive signal and the control signal; The second control circuit is electrically connected to the control output terminal, the n-th level driving output terminal, the first voltage line and the second voltage line respectively, and is used to control the connection or disconnection between the n-th level driving output terminal and the first voltage line, and control the connection or disconnection between the n-th level driving output terminal and the second voltage line under the control of the potential of the control output terminal; The first energy storage circuit is electrically connected to the control output terminal and is used to maintain the potential of the control output terminal; The control circuit also includes a second energy storage circuit; The second energy storage circuit is electrically connected to the control signal terminal and is used to maintain the potential of the control signal terminal; The second energy storage circuit is arranged on a side of the second control circuit away from the display area.

4. The display substrate according to claim 3, wherein: The first voltage lines include a first first voltage line and a second first voltage line sequentially arranged in a direction away from the display area, and the second voltage lines include a first second voltage line and a second second voltage line sequentially arranged in a direction away from the display area; The orthographic projection of at least part of the active pattern of the transistor included in the second control circuit on the substrate at least partially overlaps with the orthographic projection of the first first voltage line on the substrate; The orthographic projection of at least part of the active pattern of the transistor included in the second control circuit on the substrate at least partially overlaps with the orthographic projection of the first second voltage line on the substrate; The orthographic projection of the first second voltage line on the substrate at least partially overlaps with the orthographic projection of the plate of the capacitor included in the first energy storage circuit on the substrate; An orthographic projection of the enable signal line on the substrate at least partially overlaps with an orthographic projection of active patterns of at least a portion of transistors included in the control signal generating circuit on the substrate.

5. The display substrate according to claim 4, wherein: The orthographic projection of the first second voltage line on the substrate at least partially overlaps with the orthographic projection of the plate of the capacitor included in the second energy storage circuit on the substrate; An orthographic projection of the second second voltage line on the substrate at least partially overlaps with an orthographic projection of active patterns of at least a portion of transistors included in the control signal generating circuit on the substrate.

6. The display substrate according to claim 4, wherein: The orthographic projection of the second first voltage line on the substrate at least partially overlaps with the orthographic projection of the active pattern of at least part of the transistor included in the first control circuit on the substrate; The orthographic projection of the enabling signal line on the substrate at least partially overlaps with the orthographic projection of the plate of the capacitor included in the second energy storage circuit on the substrate; The orthographic projection of the second second voltage line on the substrate at least partially overlaps with the orthographic projection of the plate of the capacitor included in the second energy storage circuit on the substrate; An orthographic projection of the second second voltage line on the substrate at least partially overlaps with an orthographic projection of active patterns of at least a portion of transistors included in the control signal generating circuit on the substrate.

7. The display substrate according to claim 4, wherein: The orthographic projection of the second first voltage line on the substrate at least partially overlaps with the orthographic projection of the active pattern of at least part of the transistor included in the first control circuit on the substrate; The orthographic projection of the second second voltage line on the substrate at least partially overlaps with the orthographic projection of the plate of the capacitor included in the first energy storage circuit on the substrate; The orthographic projection of the second second voltage line on the substrate at least partially overlaps with the orthographic projection of the active pattern of at least part of the transistor included in the first control circuit on the substrate; The orthographic projection of the second first voltage line on the substrate at least partially overlaps with the orthographic projection of the active pattern of at least part of the transistor included in the first control circuit on the substrate; An orthographic projection of the second first voltage line on the substrate at least partially overlaps with an orthographic projection of active patterns of at least a portion of transistors included in the control signal generating circuit on the substrate.

8. The display substrate according to claim 4, wherein: The first first voltage line, the second first voltage line, the first second voltage line, the second second voltage line and the enable signal line all extend along a first direction; The width of the first first voltage line along the second direction is greater than the width of the second first voltage line along the second direction; The width of the first second voltage line along the second direction is greater than the width of the second second voltage line along the second direction; The first direction intersects the second direction.

9. The display substrate according to claim 4, wherein: The transistor included in the second control circuit is arranged on a side of the transistor included in the first control circuit close to the display area; The control signal generating circuit includes a transistor which is arranged on a side of the second control circuit away from the display area.

10. The display substrate according to claim 2, wherein: The orthographic projection of the enable signal line on the substrate at least partially overlaps with the orthographic projection of the active pattern of at least one transistor included in the output inverter circuit on the substrate.

11. The display substrate according to claim 4, wherein: The second voltage line includes a third second voltage line; the third second voltage line is arranged on a side of the second second voltage line away from the display area; An orthographic projection of the third second voltage line on the substrate at least partially overlaps with an orthographic projection of an active pattern of at least one transistor included in the output inverter circuit on the substrate.

12. The display substrate according to claim 4, wherein: The orthographic projection of the second first voltage line on the substrate at least partially overlaps with the orthographic projection of the active pattern of at least one transistor included in the output inverter circuit on the substrate; The enable signal line is arranged on a side of the second first voltage line away from the display area.

13. The display substrate according to claim 3, wherein: The drive signal generating circuit includes a first node control circuit, a second node control circuit, a first output node control circuit, a second output node control circuit, a potential maintaining circuit and an output circuit; The first node control circuit is electrically connected to the first node, the first first clock signal line, the second voltage line, and the second output node, respectively, and is used to control the connection between the first node and the second voltage line under the control of the first clock signal provided by the first first clock signal line, and to control the connection or disconnection between the first node and the first first clock signal line under the control of the potential of the second output node; The second node control circuit is electrically connected to the first node, the first intermediate node, the first voltage line, the first second clock signal line, the second node, the input terminal and the second voltage line respectively, and is used to control the connection between the first intermediate node and the first voltage line under the control of the potential of the first node, control the connection between the first intermediate node and the first second clock signal line under the control of the potential of the second node, and control the potential of the second node according to the potential of the first intermediate node, and control the connection between the input terminal and the second node under the control of the second clock signal provided by the first second clock signal line and the second voltage signal provided by the second voltage line; The first output node control circuit is electrically connected to the first output node, the first node, the first second clock signal line, the second intermediate node, the second output node and the first voltage line respectively, and is used to control the second intermediate node to be connected to the first second clock signal line under the control of the potential of the first node, control the potential of the second intermediate node according to the potential of the first node, control the second intermediate node to be connected to the first output node under the control of the second clock signal provided by the first second clock signal line, and control the first output node to be connected to the first voltage line under the control of the potential of the second output node; The second output node control circuit is electrically connected to the first second clock signal line, the input terminal, the control voltage line, the first voltage line, the second node, and the second output node, respectively, and is used to control the second output node to be connected to the input terminal under the control of the second clock signal provided by the first second clock signal line, control the potential of the second output node according to the potential of the second node, and control the second output node to be connected to the first voltage line under the control of the control voltage provided by the control voltage line; The potential maintaining circuit is electrically connected to the first output node, and is used to maintain the potential of the first output node; The output circuit is electrically connected to the first output node, the second output node, the first voltage line, the second voltage line and the n-th level drive signal output terminal, respectively, and is used to control the connection between the n-th level drive signal output terminal and the first voltage line under the control of the potential of the first output node, and control the connection between the n-th level drive signal output terminal and the second voltage line under the control of the potential of the second output node; The first voltage lines include a first first voltage line, a second first voltage line, and a third first voltage line sequentially arranged along a direction away from the display area, and the second voltage lines include a first second voltage line, a second second voltage line, and a third second voltage line sequentially arranged along a direction away from the display area; The orthographic projection of the second second voltage line on the substrate at least partially overlaps with the orthographic projection of the active pattern of at least one transistor included in the output circuit on the substrate; The orthographic projection of the second first voltage line on the substrate at least partially overlaps with the orthographic projection of the active pattern of at least one transistor included in the output circuit on the substrate; The orthographic projection of the second first voltage line on the substrate at least partially overlaps with the orthographic projection of the plate of the capacitor included in the potential maintaining circuit on the substrate; The orthographic projection of the third first voltage line on the substrate at least partially overlaps with the orthographic projection of the active pattern of at least one transistor included in the second output node control circuit on the substrate; The orthographic projection of the third second voltage line on the substrate at least partially overlaps with the orthographic projection of the plate of the capacitor included in the second node control circuit on the substrate; The orthographic projection of the third second voltage line on the substrate at least partially overlaps with the orthographic projection of the active pattern of at least one transistor included in the first node control circuit on the substrate; An orthographic projection of the third second voltage line on the substrate at least partially overlaps with an orthographic projection of an active pattern of at least one transistor included in the second node control circuit on the substrate.

14. The display substrate according to claim 13, wherein: The first first clock signal line and the first second clock signal line are arranged between the third first voltage line and the third second voltage line; The orthographic projection of the first first clock signal line on the substrate at least partially overlaps with the orthographic projection of the plate of the capacitor included in the first output node control circuit on the substrate; The orthographic projection of the first first clock signal line on the substrate at least partially overlaps with the orthographic projection of the active pattern of at least one transistor included in the second node control circuit on the substrate; The orthographic projection of the first first clock signal line on the substrate at least partially overlaps with the orthographic projection of the active pattern of at least one transistor included in the first output node control circuit on the substrate; The orthographic projection of the first second clock signal line on the substrate at least partially overlaps with the orthographic projection of the plate of the capacitor included in the first output node control circuit on the substrate; The orthographic projection of the first second clock signal line on the substrate at least partially overlaps with the orthographic projection of the plate of the capacitor included in the second node control circuit on the substrate.

15. The display substrate according to claim 3, wherein: The drive signal generating circuit includes a first node control circuit, a second node control circuit, a first output node control circuit, a second output node control circuit, a potential maintaining circuit and an output circuit; The first node control circuit is electrically connected to the first node, the second first clock signal line, the second voltage line, and the second output node, respectively, and is used to control the connection between the first node and the second voltage line under the control of the first clock signal provided by the second first clock signal line, and to control the connection or disconnection between the first node and the second first clock signal line under the control of the potential of the second output node; The second node control circuit is electrically connected to the first node, the first intermediate node, the first voltage line, the second second clock signal line, the second node, the input terminal and the second voltage line respectively, and is used to control the connection between the first intermediate node and the first voltage line under the control of the potential of the first node, control the connection between the first intermediate node and the second second clock signal line under the control of the potential of the second node, and control the potential of the second node according to the potential of the first intermediate node, and control the connection between the input terminal and the second node under the control of the second clock signal provided by the second second clock signal line and the second voltage signal provided by the second voltage line; The first output node control circuit is electrically connected to the first output node, the first node, the second second clock signal line, the second intermediate node, the second output node and the first voltage line respectively, and is used to control the second intermediate node to be connected to the second second clock signal line under the control of the potential of the first node, control the potential of the second intermediate node according to the potential of the first node, control the second intermediate node to be connected to the first output node under the control of the second clock signal provided by the second second clock signal line, and control the first output node to be connected to the first voltage line under the control of the potential of the second output node; The second output node control circuit is electrically connected to the second second clock signal line, the input terminal, the control voltage line, the first voltage line, the second node, and the second output node, respectively, and is used to control the second output node to be connected to the input terminal under the control of the second clock signal provided by the second second clock signal line, control the potential of the second output node according to the potential of the second node, and control the second output node to be connected to the first voltage line under the control of the control voltage provided by the control voltage line; The potential maintaining circuit is electrically connected to the first output node, and is used to maintain the potential of the first output node; The output circuit is electrically connected to the first output node, the second output node, the first voltage line, the second voltage line and the n-th level drive signal output terminal, respectively, and is used to control the connection between the n-th level drive signal output terminal and the first voltage line under the control of the potential of the first output node, and control the connection between the n-th level drive signal output terminal and the second voltage line under the control of the potential of the second output node; The first voltage lines include a first first voltage line, a second first voltage line, and a third first voltage line sequentially arranged along a direction away from the display area, and the second voltage lines include a first second voltage line, a second second voltage line, and a third second voltage line sequentially arranged along a direction away from the display area; The orthographic projection of the second second voltage line on the substrate at least partially overlaps with the orthographic projection of the active pattern of at least one transistor included in the output circuit on the substrate; The orthographic projection of the second first voltage line on the substrate at least partially overlaps with the orthographic projection of the active pattern of at least one transistor included in the output circuit on the substrate; The orthographic projection of the second first voltage line on the substrate at least partially overlaps with the orthographic projection of the plate of the capacitor included in the potential maintaining circuit on the substrate; The orthographic projection of the third first voltage line on the substrate at least partially overlaps with the orthographic projection of the active pattern of at least one transistor included in the second output node control circuit on the substrate; The orthographic projection of the third second voltage line on the substrate at least partially overlaps with the orthographic projection of the plate of the capacitor included in the second node control circuit on the substrate; The orthographic projection of the third second voltage line on the substrate at least partially overlaps with the orthographic projection of the active pattern of at least one transistor included in the first node control circuit on the substrate; An orthographic projection of the third second voltage line on the substrate at least partially overlaps with an orthographic projection of an active pattern of at least one transistor included in the second node control circuit on the substrate.

16. The display substrate according to claim 15, wherein: The second first clock signal line and the second second clock signal line are arranged between the third first voltage line and the third second voltage line; The orthographic projection of the second first clock signal line on the substrate at least partially overlaps with the orthographic projection of the plate of the capacitor included in the first output node control circuit on the substrate; The orthographic projection of the second first clock signal line on the substrate at least partially overlaps with the orthographic projection of the active pattern of at least one transistor included in the second node control circuit on the substrate; The orthographic projection of the second first clock signal line on the substrate at least partially overlaps with the orthographic projection of the active pattern of at least one transistor included in the first output node control circuit on the substrate; The orthographic projection of the second second clock signal line on the substrate at least partially overlaps with the orthographic projection of the plate of the capacitor included in the first output node control circuit on the substrate; The orthographic projection of the second second clock signal line on the substrate at least partially overlaps with the orthographic projection of the plate of the capacitor included in the second node control circuit on the substrate.

17. The display substrate according to claim 3, wherein: The drive signal generating circuit includes a first node control circuit, a second node control circuit, a first output node control circuit, a second output node control circuit, a potential maintaining circuit and an output circuit; The first node control circuit is electrically connected to the first node, the first first clock signal line, the second voltage line, and the second output node, respectively, and is used to control the connection between the first node and the second voltage line under the control of the first clock signal provided by the first first clock signal line, and to control the connection or disconnection between the first node and the first first clock signal line under the control of the potential of the second output node; The second node control circuit is electrically connected to the first node, the first intermediate node, the first voltage line, the first second clock signal line, the second node, the input terminal and the second voltage line respectively, and is used to control the connection between the first intermediate node and the first voltage line under the control of the potential of the first node, control the connection between the first intermediate node and the first second clock signal line under the control of the potential of the second node, and control the potential of the second node according to the potential of the first intermediate node, and control the connection between the input terminal and the second node under the control of the second clock signal provided by the first second clock signal line and the second voltage signal provided by the second voltage line; The first output node control circuit is electrically connected to the first output node, the first node, the first second clock signal line, the second intermediate node, the second output node and the first voltage line respectively, and is used to control the second intermediate node to be connected to the first second clock signal line under the control of the potential of the first node, control the potential of the second intermediate node according to the potential of the first node, control the second intermediate node to be connected to the first output node under the control of the second clock signal provided by the first second clock signal line, and control the first output node to be connected to the first voltage line under the control of the potential of the second output node; The second output node control circuit is electrically connected to the first second clock signal line, the input terminal, the control voltage line, the first voltage line, the second node, and the second output node, respectively, and is used to control the second output node to be connected to the input terminal under the control of the second clock signal provided by the first second clock signal line, control the potential of the second output node according to the potential of the second node, and control the second output node to be connected to the first voltage line under the control of the control voltage provided by the control voltage line; The potential maintaining circuit is electrically connected to the first output node, and is used to maintain the potential of the first output node; The output circuit is electrically connected to the first output node, the second output node, the first voltage line, the second voltage line and the n-th level drive signal output terminal, respectively, and is used to control the connection between the n-th level drive signal output terminal and the first voltage line under the control of the potential of the first output node, and control the connection between the n-th level drive signal output terminal and the second voltage line under the control of the potential of the second output node; The first voltage lines include a first first voltage line, a second first voltage line, a third first voltage line, and a fourth first voltage line sequentially arranged along a direction away from the display area, and the second voltage lines include a first second voltage line, a second second voltage line, a third second voltage line, and a fourth second voltage line sequentially arranged along a direction away from the display area; The orthographic projection of the third first voltage line on the substrate at least partially overlaps with the orthographic projection of the active pattern of at least one transistor included in the output circuit on the substrate; The orthographic projection of the third first voltage line on the substrate at least partially overlaps with the orthographic projection of the plate of the capacitor included in the potential maintaining circuit on the substrate; The orthographic projection of the third second voltage line on the substrate at least partially overlaps with the orthographic projection of the active pattern of at least one transistor included in the output circuit on the substrate; The orthographic projection of the fourth first voltage line on the substrate at least partially overlaps with the orthographic projection of the active pattern of at least one transistor included in the second output node control circuit on the substrate; The orthographic projection of the fourth second voltage line on the substrate at least partially overlaps with the orthographic projection of the active pattern of at least one transistor included in the first node control circuit on the substrate; An orthographic projection of the fourth second voltage line on the substrate at least partially overlaps with an orthographic projection of a plate of a capacitor included in the second node control circuit on the substrate.

18. The display substrate according to claim 17, wherein: The display substrate further includes a first first clock signal line and a first second clock signal line disposed between the fourth first voltage line and the fourth second voltage line; The orthographic projection of the first first clock signal line on the substrate at least partially overlaps with the orthographic projection of the plate of the capacitor included in the first output node control circuit on the substrate; The orthographic projection of the first second clock signal line on the substrate at least partially overlaps with the orthographic projection of the plate of the capacitor included in the first output node control circuit on the substrate; The orthographic projection of the first second clock signal line on the substrate at least partially overlaps with the orthographic projection of the plate of the capacitor included in the first output node control circuit on the substrate; The orthographic projection of the first first clock signal line on the substrate at least partially overlaps with the orthographic projection of the active pattern of at least part of the transistor included in the second node control circuit on the substrate; An orthographic projection of the first first clock signal line on the substrate at least partially overlaps with an orthographic projection of active patterns of at least a portion of transistors included in the first output node control circuit on the substrate.

19. The display substrate according to claim 3, wherein: The drive signal generating circuit includes a first node control circuit, a second node control circuit, a first output node control circuit, a second output node control circuit, a potential maintaining circuit and an output circuit; The first node control circuit is electrically connected to the first node, the second first clock signal line, the second voltage line, and the second output node, respectively, and is used to control the connection between the first node and the second voltage line under the control of the first clock signal provided by the second first clock signal line, and to control the connection or disconnection between the first node and the second first clock signal line under the control of the potential of the second output node; The second node control circuit is electrically connected to the first node, the first intermediate node, the first voltage line, the second second clock signal line, the second node, the input terminal and the second voltage line respectively, and is used to control the connection between the first intermediate node and the first voltage line under the control of the potential of the first node, control the connection between the first intermediate node and the second second clock signal line under the control of the potential of the second node, and control the potential of the second node according to the potential of the first intermediate node, and control the connection between the input terminal and the second node under the control of the second clock signal provided by the second second clock signal line and the second voltage signal provided by the second voltage line; The first output node control circuit is electrically connected to the first output node, the first node, the second second clock signal line, the second intermediate node, the second output node and the first voltage line respectively, and is used to control the second intermediate node to be connected to the second second clock signal line under the control of the potential of the first node, control the potential of the second intermediate node according to the potential of the first node, control the second intermediate node to be connected to the first output node under the control of the second clock signal provided by the second second clock signal line, and control the first output node to be connected to the first voltage line under the control of the potential of the second output node; The second output node control circuit is electrically connected to the second second clock signal line, the input terminal, the control voltage line, the first voltage line, the second node, and the second output node, respectively, and is used to control the second output node to be connected to the input terminal under the control of the second clock signal provided by the second second clock signal line, control the potential of the second output node according to the potential of the second node, and control the second output node to be connected to the first voltage line under the control of the control voltage provided by the control voltage line; The potential maintaining circuit is electrically connected to the first output node, and is used to maintain the potential of the first output node; The output circuit is electrically connected to the first output node, the second output node, the first voltage line, the second voltage line and the n-th level drive signal output terminal, respectively, and is used to control the connection between the n-th level drive signal output terminal and the first voltage line under the control of the potential of the first output node, and control the connection between the n-th level drive signal output terminal and the second voltage line under the control of the potential of the second output node; The first voltage lines include a first first voltage line, a second first voltage line, a third first voltage line, and a fourth first voltage line sequentially arranged along a direction away from the display area, and the second voltage lines include a first second voltage line, a second second voltage line, a third second voltage line, and a fourth second voltage line sequentially arranged along a direction away from the display area; The orthographic projection of the third first voltage line on the substrate at least partially overlaps with the orthographic projection of the active pattern of at least one transistor included in the output circuit on the substrate; The orthographic projection of the third first voltage line on the substrate at least partially overlaps with the orthographic projection of the plate of the capacitor included in the potential maintaining circuit on the substrate; The orthographic projection of the third second voltage line on the substrate at least partially overlaps with the orthographic projection of the active pattern of at least one transistor included in the output circuit on the substrate; The orthographic projection of the fourth first voltage line on the substrate at least partially overlaps with the orthographic projection of the active pattern of at least one transistor included in the second output node control circuit on the substrate; The orthographic projection of the fourth second voltage line on the substrate at least partially overlaps with the orthographic projection of the active pattern of at least one transistor included in the first node control circuit on the substrate; An orthographic projection of the fourth second voltage line on the substrate at least partially overlaps with an orthographic projection of a plate of a capacitor included in the second node control circuit on the substrate.

20. The display substrate according to claim 19, wherein: The display substrate further includes a second first clock signal line and a second second clock signal line disposed between the fourth first voltage line and the fourth second voltage line; The orthographic projection of the second first clock signal line on the substrate at least partially overlaps with the orthographic projection of the plate of the capacitor included in the first output node control circuit on the substrate; The orthographic projection of the second second clock signal line on the substrate at least partially overlaps with the orthographic projection of the plate of the capacitor included in the first output node control circuit on the substrate; The orthographic projection of the second second clock signal line on the substrate at least partially overlaps with the orthographic projection of the plate of the capacitor included in the first output node control circuit on the substrate; The orthographic projection of the second first clock signal line on the substrate at least partially overlaps with the orthographic projection of the active pattern of at least part of the transistor included in the second node control circuit on the substrate; An orthographic projection of the second first clock signal line on the substrate at least partially overlaps with an orthographic projection of active patterns of at least a portion of transistors included in the first output node control circuit on the substrate.

21. The display substrate according to claim 3, wherein: The first voltage line includes a first first voltage line, the second voltage line includes a first second voltage line, a second second voltage line and a third second voltage line sequentially arranged in a direction away from the display area; the enable signal line is arranged between the second second voltage line and the third second voltage line; The orthographic projection of the first second voltage line on the substrate at least partially overlaps with the orthographic projection of the active pattern of at least part of the transistor included in the second control circuit on the substrate; The orthographic projection of the first first voltage line on the substrate at least partially overlaps with the orthographic projection of the active pattern of at least part of the transistor included in the second control circuit on the substrate; The orthographic projection of the first first voltage line on the substrate at least partially overlaps with the orthographic projection of the active pattern of at least part of the transistor included in the first control circuit on the substrate; The orthographic projection of the first first voltage line on the substrate at least partially overlaps with the orthographic projection of the plate of the capacitor included in the first energy storage circuit on the substrate; The orthographic projection of the first second voltage line on the substrate at least partially overlaps with the orthographic projection of the plate of the capacitor included in the first energy storage circuit on the substrate; The orthographic projection of the second second voltage line on the substrate at least partially overlaps with the orthographic projection of the active pattern of at least part of the transistor included in the first control circuit on the substrate; The orthographic projection of the enable signal line on the substrate at least partially overlaps with the orthographic projection of the active pattern of at least part of the transistor included in the control signal generating circuit on the substrate; An orthographic projection of the third second voltage line on the substrate at least partially overlaps with an orthographic projection of active patterns of at least a portion of transistors included in the control signal generating circuit on the substrate.

22. The display substrate according to claim 3, wherein: The first voltage line includes a first first voltage line, and the second voltage line includes a first second voltage line and a second second voltage line sequentially arranged in a direction away from the display area; the enable signal line is arranged between the first second voltage line and the second second voltage line; The orthographic projection of the first second voltage line on the substrate at least partially overlaps with the orthographic projection of the active pattern of at least part of the transistor included in the second control circuit on the substrate; The orthographic projection of the enable signal line on the substrate at least partially overlaps with the orthographic projection of the plate of the capacitor included in the first energy storage circuit on the substrate; The orthographic projection of the second second voltage line on the substrate at least partially overlaps with the orthographic projection of the active pattern of at least part of the transistor included in the control signal generating circuit on the substrate; The orthographic projection of the first first voltage line on the substrate at least partially overlaps with the orthographic projection of the active pattern of at least part of the transistor included in the second control circuit on the substrate; An orthographic projection of the first first voltage line on the substrate at least partially overlaps with an orthographic projection of active patterns of at least a portion of transistors included in the first control circuit on the substrate.

23. The display substrate according to claim 3, wherein: The drive signal generating circuit comprises a first output node control circuit, a second output node control circuit, a third energy storage circuit and an output circuit; the drive signal generating circuit is arranged on a side of the control signal generating circuit included in the drive circuit away from the display area; the transistors in the output circuit are arranged on a side of the transistors included in the drive signal generating circuit except the transistors in the output circuit close to the display area; The first output node control circuit is electrically connected to the third first clock signal line, the second voltage line and the second output node respectively, and is used to control the first output node to be connected to the second voltage line under the control of the first clock signal provided by the third first clock signal line, and to control the first output node to be connected to the third first clock signal line under the control of the potential of the second output node, and to maintain the potential of the first output node; The second output node control circuit is electrically connected to the second output node, the third first clock signal line, the input terminal, the third second clock signal line, the first output node and the first voltage line respectively, and is used to control the second output node to be connected to the input terminal under the control of the first clock signal, and to control the second output node to be connected to the first voltage line under the control of the potential of the first output node and the second clock signal provided by the third second clock signal line; The first end of the third energy storage circuit is electrically connected to the second output node, the second end of the third energy storage circuit is electrically connected to the n-th stage drive signal output terminal, and the third energy storage circuit is used to store electric energy; The output circuit is electrically connected to the first output node, the second output node, the first voltage line, the second clock signal and the n-th level drive signal output terminal respectively, and is used to control the connection between the n-th level drive signal output terminal and the first voltage line under the control of the potential of the first output node, and control the connection between the n-th level drive signal output terminal and the third second clock signal line under the control of the potential of the second output node; The first voltage lines include a first first voltage line and a second first voltage line sequentially arranged along a direction away from the display area, and the second voltage lines include a first second voltage line, a second second voltage line, a third second voltage line and a fourth second voltage line sequentially arranged along a direction away from the display area; The orthographic projection of the plate of the capacitor included in the third energy storage circuit on the substrate is arranged between the orthographic projection of the third second voltage line on the substrate and the orthographic projection of the second first voltage line on the substrate; The orthographic projection of the second first voltage line on the substrate at least partially overlaps with the orthographic projection of the plate of the capacitor included in the first output node control circuit on the substrate; The orthographic projection of the second first voltage line on the substrate at least partially overlaps with the orthographic projection of the active pattern of at least part of the transistor included in the output circuit on the substrate; An orthographic projection of the fourth second voltage line on the substrate at least partially overlaps with an orthographic projection of active patterns of at least a portion of transistors included in the first output node control circuit on the substrate.

24. The display substrate according to claim 3, wherein: The drive signal generating circuit comprises a first output node control circuit, a second output node control circuit, a third energy storage circuit and an output circuit; the drive signal generating circuit is arranged on a side of the control signal generating circuit included in the drive circuit away from the display area; the transistors in the output circuit are arranged on a side of the transistors included in the drive signal generating circuit except the transistors in the output circuit close to the display area; The first output node control circuit is electrically connected to the third first clock signal line, the second voltage line and the second output node respectively, and is used to control the first output node to be connected to the second voltage line under the control of the first clock signal provided by the third first clock signal line, and to control the first output node to be connected to the third first clock signal line under the control of the potential of the second output node, and to maintain the potential of the first output node; The second output node control circuit is electrically connected to the second output node, the third first clock signal line, the input terminal, the third second clock signal line, the first output node and the first voltage line respectively, and is used to control the second output node to be connected to the input terminal under the control of the first clock signal, and to control the second output node to be connected to the first voltage line under the control of the potential of the first output node and the second clock signal provided by the third second clock signal line; The first end of the third energy storage circuit is electrically connected to the second output node, the second end of the third energy storage circuit is electrically connected to the n-th stage drive signal output terminal, and the third energy storage circuit is used to store electric energy; The output circuit is electrically connected to the first output node, the second output node, the first voltage line, the second clock signal and the n-th level drive signal output terminal respectively, and is used to control the connection between the n-th level drive signal output terminal and the first voltage line under the control of the potential of the first output node, and control the connection between the n-th level drive signal output terminal and the third second clock signal line under the control of the potential of the second output node; The first voltage lines include a first first voltage line and a second first voltage line sequentially arranged along a direction away from the display area, and the second voltage lines include a first second voltage line, a second second voltage line, a third second voltage line and a fourth second voltage line sequentially arranged along a direction away from the display area; The orthographic projection of the third second voltage line on the substrate at least partially overlaps with the orthographic projection of the plate of the capacitor included in the third energy storage circuit on the substrate; The orthographic projection of the second first voltage line on the substrate at least partially overlaps with the orthographic projection of the plate of the capacitor included in the first output node control circuit on the substrate; The orthographic projection of the second first voltage line on the substrate at least partially overlaps with the orthographic projection of the active pattern of at least part of the transistor included in the output circuit on the substrate; An orthographic projection of the fourth second voltage line on the substrate at least partially overlaps with an orthographic projection of active patterns of at least a portion of transistors included in the first output node control circuit on the substrate.

25. The display substrate according to claim 23 or 24, characterized in that: The third first clock signal line and the third second clock signal line are arranged between the second first voltage line and the fourth second voltage line; The orthographic projection of the third first clock signal line on the substrate at least partially overlaps with the orthographic projection of the active pattern of at least part of the transistor included in the second output node control circuit on the substrate; An orthographic projection of the third second clock signal line on the substrate at least partially overlaps with an orthographic projection of active patterns of at least a portion of transistors included in the second output node control circuit on the substrate.

26. The display substrate according to claim 3, wherein: The active pattern of at least part of the transistors included in the second control circuit includes at least two active pattern parts independent of each other.

27. A display device, characterized in that: The invention comprises a display substrate as claimed in any one of claims 1 to 26.

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