Printed circuit board and manufacturing method thereof

Abstract

According to an embodiment of the present disclosure, a printed circuit and a method of manufacturing the same are provided. The printed circuit board includes: a signal plane portion including a plurality of metal layers for transmitting signals; a power supply plane portion overlapping the signal plane portion through a connection layer and including a plurality of metal layers for supplying power; a plurality of power supply via holes, each extending from a surface of the signal plane portion back to the power supply plane portion, through the signal plane portion, the connection layer and the power supply plane portion, to a surface of the power supply plane portion back to the signal plane portion; and a plurality of signal vias each extending into the signal plane portion from a surface of the signal plane portion facing away from the power plane portion and not extending into the power plane portion, wherein a radial dimension of each of the plurality of signal vias is less than a radial dimension of each of the plurality of power vias.

Description

Technical Field

[0001] Embodiments of the present disclosure generally relate to the technical field of electronic devices, and more particularly, to a printed circuit board and a method for manufacturing the same. Background Art

[0002] The rate of signals transmitted by integrated circuit chips continues to increase, resulting in a further increase in the bandwidth required for the channel. In order to meet this requirement, the chip size continues to increase, the number of chip signal pins continues to increase, and the spacing between pins continues to decrease. The increase in the number of chip signal pins requires more signal planes, while the increase in chip power consumption requires more power planes.

[0003] In this case, the vias in the printed circuit board (PCB) used to carry the chip will be more dense, so it is necessary to use vias with a smaller diameter. In addition, due to the increase in bandwidth and the reduction in pin spacing, the crosstalk between signals is more difficult to control, and more via shielding is needed to solve the crosstalk problem. In addition, the increase in the number of layers of the signal plane leads to an increase in the thickness of the PCB, which will increase the length of the signal via. In addition to the signal plane, more power planes are required to ensure the current flow capacity of the chip, which leads to a further increase in the thickness of the PCB. In addition, the increase in board thickness and the decrease in via diameter will lead to an increase in the ratio of board thickness to the aperture of the via (also referred to as the thickness-to-diameter ratio in this article), which increases the difficulty of manufacturing the via and affects the processing yield of the PCB. In addition, the reduction in via diameter will cause the inductive load of the via to continue to increase, causing the signal via to reflect too much, affecting the signal integrity of the chip. At the same time, dense signal vias will affect the current flow capacity of the chip. Summary of the invention

[0004] In one aspect of the present disclosure, a printed circuit board is provided, comprising: a signal plane portion, comprising a plurality of metal layers for transmitting signals; a power plane portion, overlapping the signal plane portion through a connection layer, and comprising a plurality of metal layers for providing power; a plurality of power vias, each extending from a surface of the signal plane portion facing away from the power plane portion, through the signal plane portion, the connection layer and the power plane portion, to a surface of the power plane portion facing away from the signal plane portion; and a plurality of signal vias, each extending from a surface of the signal plane portion facing away from the power plane portion into the signal plane portion, and not extending into the power plane portion, wherein a radial dimension of each of the plurality of signal vias is smaller than a radial dimension of each of the plurality of power vias.

[0005] In another aspect of the present disclosure, a method for manufacturing a printed circuit board is provided, comprising: forming a signal plane portion, the signal plane portion comprising a plurality of metal layers for transmitting signals; forming a plurality of signal vias in the signal plane portion, the plurality of signal vias respectively extending from the surface of the signal plane portion into the signal plane portion; forming a power plane portion, the power plane portion comprising a plurality of metal layers for providing power; overlapping the power plane portion with the signal plane portion through a connecting layer, wherein the surface of the signal plane portion faces away from the power plane portion; and forming a plurality of power vias in the signal plane portion and the power plane portion, the plurality of power vias respectively extending from the surface of the signal plane portion to the surface of the power plane portion facing away from the signal plane portion, wherein a radial dimension of each of the plurality of signal vias is smaller than a radial dimension of each of the plurality of power vias.

[0006] It should be understood that the content described in this content section is not intended to limit the key features or important features of the embodiments of the present disclosure, nor is it intended to limit the scope of the present disclosure. Other features of the present disclosure will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The above and other features, advantages and aspects of the embodiments of the present disclosure will become more apparent with reference to the following detailed description in conjunction with the accompanying drawings. In the accompanying drawings, the same or similar reference numerals represent the same or similar elements, wherein:

[0008] Figure 1A and Figure 1B shows a schematic cross-sectional view of a conventional printed circuit board;

[0009] FIG. 2A to FIG. 2D An exemplary arrangement of conventional pads and vias is shown;

[0010] Figure 3 shows a schematic cross-sectional view of a printed circuit board according to some embodiments of the present disclosure;

[0011] Figure 4A and Figure 4B shows an exemplary arrangement of capacitive load pads relative to vias; and

[0012] FIG. 5A to FIG. 5E A manufacturing process of a printed circuit board according to some embodiments of the present disclosure is shown.

[0013] Description of reference numerals:

[0014] 100 printed circuit boards;

[0015] 110, 110' signal plane portion;

[0016] 111 a first surface;

[0017] 112 second surface;

[0018] 140, 140' metal layer;

[0019] 150, 150' dielectric layer;

[0020] 120, 120' power plane portion;

[0021] 123 third surface;

[0022] 124 fourth surface;

[0023] 130 connection layer;

[0024] 160, 160' power vias;

[0025] 161, 161' signal via;

[0026] 1611 first signal via;

[0027] 1612 second signal via;

[0028] 171, 171' signal pad;

[0029] 172, 172' power pad;

[0030] 180 capacitive load pad;

[0031] 181 first end portion;

[0032] 182 second end;

[0033] 183 third end;

[0034] 184 fourth end;

[0035] 190' trace. DETAILED DESCRIPTION

[0036] The preferred embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the preferred embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments set forth herein. On the contrary, these embodiments are provided to make the present disclosure more thorough and complete, and to fully convey the scope of the present disclosure to those skilled in the art.

[0037] As used herein, the term "including" and its variations mean open inclusion, i.e., "including but not limited to". Unless otherwise stated, the term "or" means "and / or". The term "based on" means "based at least in part on". The terms "an example embodiment" and "an embodiment" mean "at least one example embodiment". The term "another embodiment" means "at least one additional embodiment". The terms "first", "second", etc. may refer to different or the same objects.

[0038] As briefly mentioned above, the vias in PCBs are becoming more and more dense, so vias with smaller diameters need to be used. In addition, due to the increase in bandwidth and the reduction in pin spacing, crosstalk between signals is more difficult to control, and more via shielding needs to be added to solve the crosstalk problem. In addition, the increase in the number of layers of the signal plane leads to an increase in the thickness of the PCB, which increases the length of the signal via. In addition to the signal plane, more power planes are required to ensure the current flow capacity of the chip, which leads to a further increase in the thickness of the PCB. In addition, the increase in board thickness and the decrease in via diameter will lead to an increase in the ratio of board thickness to via aperture (also referred to as thickness-to-diameter ratio in this article), which makes the manufacturing difficulty of the vias increase and affects the processing yield of the PCB. In addition, the reduction in the size of the signal via will lead to a continuous increase in the inductive load of the via, making the signal via reflection too large, affecting the signal integrity of the chip. At the same time, dense signal vias will affect the current flow capacity of the chip. The following will combine Figures 1A to 2D This is described in further detail. Figure 1A and Figure 1B A schematic cross-sectional view of a conventional printed circuit board is shown. FIG. 2A to FIG. 2D An exemplary arrangement of conventional pads and vias is shown.

[0039] like Figure 1A As shown, a conventional printed circuit board includes a signal plane portion 110' and a power plane portion 120' located on both sides of the signal plane portion 110'. The signal plane portion 110' and the two power plane portions 120' are formed into a symmetrical stacked structure by one-time lamination. The signal plane portion 110' and the two power plane portions 120' each include a plurality of metal layers 140' and a dielectric layer 150' located between adjacent metal layers 140'. A signal via 161' extends from the surface of the power plane portion 120' into the signal plane portion 110'. A signal pad 171' connected to the signal via 161' is provided on the surface of the power plane portion 120'. The maximum length of the signal via 161' is the overall board thickness of the printed circuit board minus the thickness of the power plane portion 120' of the lower layer. As an example, when the board thickness of the printed circuit board is 6 millimeters (mm) and the thickness of each power plane portion 120' is 1.5 mm, the maximum length of the signal via 161' is 4.5 mm.

[0040] like Figure 1B As shown, another conventional printed circuit board includes a power plane portion 120' and a signal plane portion 110' located on both sides of the power plane portion 120'. The power plane portion 120' and the two signal plane portions 110' are formed into a symmetrical stacked structure by one-time lamination. The power plane portion 120' and the two signal plane portions 110' each include a plurality of metal layers 140' and a dielectric layer 150' located between adjacent metal layers 140'. A signal via 161' extends from the surface of one signal plane portion 110' to the surface of another signal plane portion 110'. A signal pad 171' connected to the signal via 161' is provided on the surface of the signal plane portion 110'. The maximum length of the signal via 161' is the overall board thickness of the printed circuit board. As an example, when the board thickness of the printed circuit board is 6 mm, the maximum length of the signal via 161' is 6 mm.

[0041] It should be noted that the numbers, values, etc. mentioned above and elsewhere in the present disclosure are exemplary and are not intended to limit the scope of the present disclosure in any way. Any other appropriate numbers and values ​​are possible.

[0042] like Figure 2A As shown, a plurality of signal pads 171' and a plurality of power pads 172' can be arranged in an array. Each of the signal pads 171' and the power pads 172' can have a diameter of 0.5 mm, and the spacing between adjacent pads can be 1 mm. A signal via 161' is provided at the center of each signal pad 171', and a power via 160' is provided at the center of each power pad 172'. Each via in the signal via 161' and the power via 160' can have a diameter of 0.3 mm. The spacing between adjacent vias can also be 1 mm.

[0043] like Figure 2B As shown, a plurality of signal pads 171' and a plurality of power pads 172' can be arranged in an array. Each of the signal pads 171' and the power pads 172' can have a diameter of 0.5mm, and the spacing between adjacent pads can be 1mm. A corresponding signal via 161' is provided on the outside of each signal pad 171', and the signal via 161' is connected to the signal pad 171' through a trace 190'. A power via 160' is provided on the outside of each power pad 172', and the power via 160' is connected to the power pad 172' through a trace 190'. Each via in the signal via 161' and the power via 160' can have a diameter of 0.3mm. The spacing between adjacent vias can also be 1mm.

[0044] Figure 2A and Figure 2BEach of the illustrated signal vias 161 ′ and the power vias 160 ′ may be formed in the printed circuit board by a drill having a radial dimension of 0.3 mm.

[0045] like Figure 2C As shown, as the pin density and signal rate of the chip increase, the spacing between adjacent pads in the signal pad 171' and the power pad 172' is further reduced. For example, in the case where the pad diameter is 0.5mm, the spacing between adjacent pads can be 0.8mm. The reduced spacing between adjacent pads makes it more difficult to control the crosstalk between signals. In addition, when the pad size and the via size remain unchanged, the reduced spacing between the vias will cause the impedance deviation of the vias to increase.

[0046] In order to reduce the signal crosstalk caused by the reduced spacing between vias, the spacing between vias and the via diameter can be reduced to optimize the shielding effect. Figure 2D As shown, when the pad diameter is 0.5 mm and the spacing between adjacent pads is 0.8 mm, each via in the signal via 161' and the power via 160' can have a diameter of 0.2 mm, and the spacing between adjacent vias can be reduced to 0.6 mm. In the case where the thickness of the printed circuit board is large, the thickness-to-diameter ratio of the printed circuit board will be too large. For example, when the thickness of the printed circuit board is 6 mm and the via diameter is 0.2 mm, the thickness-to-diameter ratio is 30:1. In addition, the thinning of the via will cause the inductive load of the signal via 161' to continue to increase, making the reflection of the signal via 161' too large, affecting the signal integrity of the chip. In addition, dense signal vias 161' will affect the current flow capacity of the chip.

[0047] The embodiments of the present disclosure provide a printed circuit board and a method for manufacturing the same, so as to achieve a smaller signal via diameter, reduce the spacing between vias, improve the processing yield of the circuit board, reduce the crosstalk between signals, reduce the inductive load, ensure the signal integrity, and improve the flow capacity. Figures 3 to 5E Embodiments of the present disclosure are described.

[0048] Figure 3 Schematic cross-sectional views of printed circuit boards according to some embodiments of the present disclosure are shown. Figure 3 As shown, the printed circuit board 100 described herein generally includes a signal plane portion 110 , a power plane portion 120 , a connection layer 130 , a plurality of power vias 160 , and a plurality of signal vias 161 .

[0049] The signal plane portion 110 includes a plurality of metal layers 140 for transmitting signals. Adjacent metal layers 140 of the signal plane portion 110 are separated by dielectric layers 150. Similarly, the power plane portion 120 includes a plurality of metal layers 140 for providing power. Adjacent metal layers 140 of the power plane portion 120 are separated by dielectric layers 150. The connection layer 130 is disposed between the power plane portion 120 and the signal plane portion 110 to connect the two together, so that the power plane portion 120 and the signal plane portion 110 overlap each other. Figure 1A and Figure 1B The symmetrical stacking structure of the printed circuit board shown in Figure 3 The printed circuit board 100 shown in the figure is an asymmetric stacked structure. Figure 3 When the printed circuit board 100 is placed in the orientation shown in FIG, the signal plane portion 110 is located above the power plane portion 120. It should be understood that when the printed circuit board 100 is placed in other orientations, the power plane portion 120 and the signal plane portion 110 may have other relative positional relationships.

[0050] like Figure 3 As shown, the power via 160 extends from the surface of the signal plane portion 110 facing away from the power plane portion 120, through the signal plane portion 110, the connection layer 130 and the power plane portion 120, to the surface of the power plane portion 120 facing away from the signal plane portion 110. The power via 160 can be electrically connected to the metal layer 140 in the power plane portion 120 and the signal plane portion 110. Figure 3 Only a single power via 160 is shown as an example to illustrate the principle of the present disclosure. It should be understood that other power vias 160 may also have a similar arrangement, extending from the surface of the signal plane portion 110 facing away from the power plane portion 120 to the surface of the power plane portion 120 facing away from the signal plane portion 110.

[0051] like Figure 3 As shown, power pads 172 electrically connected to the power vias 160 may be provided on the surfaces of the signal plane portion 110 and the power plane portion 120 for connection with corresponding pins on the chip.

[0052] like Figure 3 As shown, the signal via 161 extends from a surface of the signal plane portion 110 facing away from the power plane portion 120 into the signal plane portion 110 and does not extend into the power plane portion 120. The signal via 161 may be electrically connected to the metal layer 140 in the signal plane portion 110. Figure 3Only a single signal via 161 is shown as an example to illustrate the principles of the present disclosure. It should be understood that other signal vias 161 may also have a similar arrangement, that is, extending from the surface of the signal plane portion 110 facing away from the power plane portion 120 into the signal plane portion 110, and not extending into the power plane portion 120. The radial dimension of each signal via 161 in the plurality of signal vias 161 is smaller than the radial dimension of each power via 160 in the plurality of power vias 160. For example, in the case where the radial dimension of the power via 160 is 0.3 mm, the radial dimension of the signal via 161 may be 0.2 mm.

[0053] like Figure 3 As shown, a signal pad 171 electrically connected to the signal via 161 may be disposed on the surface of the signal plane portion 110 for connection with a corresponding pin on the chip.

[0054] As an example, the overall thickness of the printed circuit board 100 can be 6 mm, wherein the thickness of the power plane portion 120 is approximately 3.5 mm, the thickness of the signal plane portion 110 is approximately 2.5 mm, and the thickness of the connection layer 130 is relatively small and can be ignored. In this case, the aspect ratio of the signal plane portion 110 to the signal via 161 is 17.5:1, which is 41% lower than the aspect ratio of 30:1. The reduction of the aspect ratio can reduce the processing difficulty of the printed circuit board 100 and improve the processing yield.

[0055] In some embodiments, the signal plane portion 110 is formed in a first lamination process, the power plane portion 120 is formed in a second lamination process, and the signal plane portion 110 and the power plane portion 120 are stacked together through the connection layer 130 in a third lamination process. A plurality of signal vias 161 are formed in the power plane portion 120 after the first lamination process and before the third lamination process, and a plurality of power vias 160 are formed in the signal plane portion 110 and the power plane portion 120 after the third lamination process. By laminating the signal plane portion 110 and the power plane portion 120 separately, the signal vias 161 having a smaller diameter can be pre-formed in the signal plane portion 110, and the spacing between the signal vias 161 can be reduced, thereby solving the problem of crosstalk between signals.

[0056] In some embodiments, Figure 3 As shown, at least one signal via 161 extends from the surface of the signal plane portion 110 facing away from the power plane portion 120 to a metal layer 140 adjacent to the connection layer 130 among the multiple metal layers 140 of the signal plane portion 110. Of course, some of the multiple signal vias 161 may also extend from the surface of the signal plane portion 110 facing away from the power plane portion 120 to an intermediate metal layer 140 of the signal plane portion 110.

[0057] As described above, the reduction in the diameter of the signal via will cause the inductive load of the via to increase continuously, making the signal via reflection too large, affecting the signal integrity of the chip. At the same time, dense signal vias will affect the current flow capacity of the chip. To this end, a capacitive load pad can be set in the signal plane part 110 to alleviate the signal reflection caused by the inductive load. Figure 4A and Figure 4B An exemplary arrangement of capacitive load pads relative to vias is shown.

[0058] In some embodiments, Figure 4A and Figure 4B As shown, a plurality of capacitive load pads 180 are formed in a plurality of metal layers 140 of the signal plane portion 110, and are electrically connected to at least a portion of the signal vias 161 among the plurality of signal vias 161. In some embodiments, the capacitive load pads 180 may be provided in each metal layer 140 of the signal plane portion 110. In some embodiments, the capacitive load pads 180 may be provided in only a portion of the metal layers 140 of the signal plane portion 110. The capacitive load pads 180 to which each signal via 161 is connected may form a capacitor. Figure 4A and Figure 4B Only two signal vias 161 are shown as examples to illustrate the arrangement of the capacitive load pads 180. It should be understood that other signal vias 161 can also be connected to corresponding capacitive load pads 180. By providing the capacitive load pads 180, the problem of excessive signal reflection caused by the inductive load can be solved, ensuring the integrity of the signal.

[0059] In some embodiments, Figure 4A and Figure 4B As shown, at least one pair of adjacent signal vias 161 among the plurality of signal vias 161 may be respectively connected to at least two capacitive load pads 180 among the plurality of capacitive load pads 180. Each pair of adjacent signal vias 161 among the at least one pair of adjacent signal vias 161 may include a first signal via 1611 and a second signal via 1612. At least two capacitive load pads 180 connected to the first signal via 1611 may be offset in a direction away from the corresponding second signal via 1612, and at least two capacitive load pads 180 connected to the second signal via 1612 may be offset in a direction away from the corresponding first signal via 1611. By setting the capacitive load pads 180 offset, a smaller spacing between adjacent signal vias 161 can be achieved while avoiding a short circuit between adjacent signal vias 161.

[0060] In some embodiments, Figure 4A and Figure 4BAs shown, each of the plurality of capacitive load pads 180 is elliptical. Each of the at least two capacitive load pads 180 connected to the first signal via 1611 has a first end 181 and a second end 182 along the long axis direction. The first end 181 is closer to the second signal via 1612 than the second end 182, and the first end 181 is closer to the first signal via 1611 than the second end 182. Each of the at least two capacitive load pads 180 connected to the second signal via 1612 has a third end 183 and a fourth end 184 along the long axis direction, the third end 183 is closer to the first signal via 1611 than the fourth end 184, and the third end 183 is closer to the second signal via 1612 than the fourth end 184. With this arrangement, the inductive load of the adjacent signal vias 161 can be reliably reduced, and a smaller spacing can be achieved to avoid the occurrence of short circuits.

[0061] It should be understood that the capacitive load pad 180 may have any other suitable shape, such as a circle, a polygon, etc.

[0062] Next, we will combine FIG. 5A to FIG. 5E An example manufacturing process of the printed circuit board 100 is described.

[0063] like Figure 5A As shown, a signal plane portion 110 is formed. The signal plane portion 110 includes a plurality of metal layers 140 for transmitting signals. Adjacent metal layers 140 of the signal plane portion 110 are separated by a dielectric layer 150. The signal plane portion 110 includes a first surface 111 and a second surface 112 opposite to each other.

[0064] like Figure 5B As shown, a plurality of signal vias 161 are formed in the signal plane portion 110 , and the plurality of signal vias 161 extend from the first surface 111 of the signal plane portion 110 into the signal plane portion 110 , respectively. Figure 5B Only a single signal via 161 is shown as an example to illustrate the principle of the present disclosure. It should be understood that other signal vias 161 may also have a similar arrangement.

[0065] In some embodiments, Figure 5B As shown, at least one signal via 161 extends from the first surface 111 of the signal plane portion 110 to a metal layer 140 adjacent to the second surface 112 of the plurality of metal layers 140 of the signal plane portion 110. Of course, some of the plurality of signal vias 161 may also extend from the first surface 111 of the signal plane portion 110 to an intermediate metal layer 140 of the signal plane portion 110.

[0066] In some embodiments, Figure 5C As shown, a power plane portion 120 is formed. The power plane portion 120 includes a plurality of metal layers 140 for providing power. Adjacent metal layers 140 of the power plane portion 120 are separated by a dielectric layer 150. The power plane portion 120 includes a third surface 123 and a fourth surface 124 opposite to each other.

[0067] like Figure 5D As shown, the power plane portion 120 overlaps the signal plane portion 110 via a connection layer 130. A first surface 111 of the signal plane portion 110 faces away from the power plane portion 120.

[0068] like Figure 5E As shown, a plurality of power vias 160 are formed in the signal plane portion 110 and the power plane portion 120. The plurality of power vias 160 extend from the first surface 111 of the signal plane portion 110 to the fourth surface 124 of the power plane portion 120 facing away from the signal plane portion 110. The radial dimension of each of the plurality of signal vias 161 is smaller than the radial dimension of each of the plurality of power vias 160.

[0069] In some embodiments, the signal plane portion 110 is formed in a first lamination process, the power plane portion 120 is formed in a second lamination process, and the signal plane portion 110 and the power plane portion 120 are stacked together through the connection layer 130 in a third lamination process.

[0070] In some embodiments, forming the signal plane portion 110 further includes forming a plurality of capacitive loading pads 180 in the plurality of metal layers 140 of the signal plane portion 110, such as Figure 4A and Figure 4B The plurality of capacitive load pads 180 are used to be electrically connected to at least a portion of the plurality of signal vias 161 .

[0071] In some embodiments, at least one pair of adjacent signal vias 161 among a plurality of signal vias 161 are respectively connected to at least two capacitive load pads 180 among a plurality of capacitive load pads 180, each pair of adjacent signal vias 161 among at least one pair of adjacent signal vias 161 includes a first signal via 1611 and a second signal via 1612, at least two capacitive load pads 180 connected to the first signal via 1611 are offset in a direction away from the corresponding second signal via 1612, and at least two capacitive load pads 180 connected to the second signal via 1612 are offset in a direction away from the corresponding first signal via 1611.

[0072] In some embodiments, each of the multiple capacitive load pads 180 is elliptical, wherein each of the at least two capacitive load pads 180 connected to the first signal via 1611 has a first end and a second end along the long axis direction, the first end is closer to the second signal via 1612 than the second end, and the first end is closer to the first signal via 1611 than the second end, and wherein each of the at least two capacitive load pads 180 connected to the second signal via 1612 has a third end and a fourth end along the long axis direction, the third end is closer to the first signal via 1611 than the fourth end, and the third end is closer to the second signal via 1612 than the fourth end.

[0073] Embodiments of the present disclosure are also embodied in the following examples.

[0074] Example 1. A printed circuit board comprising:

[0075] A signal plane portion, including a plurality of metal layers for transmitting signals;

[0076] A power plane portion, overlapping the signal plane portion through a connection layer, and comprising a plurality of metal layers for providing power;

[0077] a plurality of power vias, each extending from a surface of the signal plane portion facing away from the power plane portion, through the signal plane portion, the connection layer and the power plane portion, to a surface of the power plane portion facing away from the signal plane portion; and

[0078] A plurality of signal vias each extend from a surface of the signal plane portion facing away from the power plane portion into the signal plane portion and do not extend into the power plane portion, wherein a radial dimension of each of the plurality of signal vias is smaller than a radial dimension of each of the plurality of power vias.

[0079] Example 2. The printed circuit board according to Example 1, wherein the signal plane portion is formed in a first lamination process, the power plane portion is formed in a second lamination process, and the signal plane portion and the power plane portion are stacked together through the connection layer in a third lamination process, and

[0080] The plurality of signal vias are formed in the power plane portion after the first lamination process and before the third lamination process, and the plurality of power vias are formed in the signal plane portion and the power plane portion after the third lamination process.

[0081] Example 3. A printed circuit board according to Example 1, wherein at least one of the plurality of signal vias extends from a surface of the signal plane portion facing away from the power plane portion to a metal layer of the plurality of metal layers of the signal plane portion that is adjacent to the connection layer.

[0082] Example 4. The printed circuit board according to any one of Examples 1 to 3, further comprising:

[0083] A plurality of capacitive load pads are formed in the plurality of metal layers of the signal plane portion and are electrically connected to at least a portion of the plurality of signal vias.

[0084] Example 5. A printed circuit board according to Example 4, wherein at least one pair of adjacent signal vias among the plurality of signal vias is respectively connected to at least two capacitive load pads among the plurality of capacitive load pads, each pair of adjacent signal vias among the at least one pair of adjacent signal vias includes a first signal via and a second signal via, the at least two capacitive load pads connected to the first signal via are offset in a direction away from the corresponding second signal via, and the at least two capacitive load pads connected to the second signal via are offset in a direction away from the corresponding first signal via.

[0085] Example 6. The printed circuit board of Example 5, wherein each of the plurality of capacitive load pads is elliptical in shape,

[0086] wherein each of the at least two capacitive load pads connected to the first signal via has a first end and a second end along the long axis direction, the first end is closer to the second signal via than the second end, and the first end is closer to the first signal via than the second end, and

[0087] Each of the at least two capacitive load pads connected to the second signal via has a third end and a fourth end along the long axis direction, the third end is closer to the first signal via than the fourth end, and the third end is closer to the second signal via than the fourth end.

[0088] Example 7. A method for manufacturing a printed circuit board, comprising:

[0089] forming a signal plane portion, the signal plane portion comprising a plurality of metal layers for transmitting signals;

[0090] forming a plurality of signal vias in the signal plane portion, wherein the plurality of signal vias extend from a surface of the signal plane portion into the signal plane portion respectively;

[0091] forming a power plane portion, the power plane portion comprising a plurality of metal layers for providing power;

[0092] overlapping the power plane portion and the signal plane portion through a connection layer, wherein the surface of the signal plane portion faces away from the power plane portion; and

[0093] A plurality of power vias are formed in the signal plane portion and the power plane portion, and the plurality of power vias extend from the surface of the signal plane portion to the surface of the power plane portion facing away from the signal plane portion, respectively, wherein a radial dimension of each of the plurality of signal vias is smaller than a radial dimension of each of the plurality of power vias.

[0094] Example 8. A method according to Example 7, wherein the signal plane portion is formed in a first lamination process, the power plane portion is formed in a second lamination process, and the signal plane portion and the power plane portion are stacked together through the connection layer in a third lamination process.

[0095] Example 9. The method of Example 7, wherein at least one of the plurality of signal vias extends from the surface of the signal plane portion to a metal layer of the plurality of metal layers of the signal plane portion that is adjacent to the connection layer.

[0096] Example 10. A method according to any one of Examples 7 to 9, wherein forming the signal plane portion further comprises forming a plurality of capacitive load pads in the plurality of metal layers of the signal plane portion, the plurality of capacitive load pads being used to electrically connect to at least a portion of the plurality of signal vias.

[0097] Example 11. A method according to Example 10, wherein at least one pair of adjacent signal vias among the plurality of signal vias are respectively connected to at least two capacitive load pads among the plurality of capacitive load pads, each pair of adjacent signal vias among the at least one pair of adjacent signal vias includes a first signal via and a second signal via, the at least two capacitive load pads connected to the first signal via are offset in a direction away from the corresponding second signal via, and the at least two capacitive load pads connected to the second signal via are offset in a direction away from the corresponding first signal via.

[0098] Example 12. The method of Example 11, wherein each of the plurality of capacitive load pads is elliptical in shape,

[0099] wherein each of the at least two capacitive load pads connected to the first signal via has a first end and a second end along the long axis direction, the first end is closer to the second signal via than the second end, and the first end is closer to the first signal via than the second end, and

[0100] Each of the at least two capacitive load pads connected to the second signal via has a third end and a fourth end along the long axis direction, the third end is closer to the first signal via than the fourth end, and the third end is closer to the second signal via than the fourth end.

[0101] The embodiments of the present disclosure have been described above, and the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and changes will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The selection of terms used herein is intended to best explain the principles of the embodiments, practical applications, or technical improvements in the market, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A printed circuit board (100), comprising: A signal plane portion (110) including a plurality of metal layers (140) for transmitting signals; A power plane portion (120) overlaps the signal plane portion (110) via a connection layer (130) and includes a plurality of metal layers (140) for providing power; A plurality of power vias (160), each extending from a surface of the signal plane portion (110) facing away from the power plane portion (120), through the signal plane portion (110), the connection layer (130) and the power plane portion (120), to a surface of the power plane portion (120) facing away from the signal plane portion (110); as well as A plurality of signal vias (161), each extending from a surface of the signal plane portion (110) facing away from the power plane portion (120) into the signal plane portion (110) and not extending into the power plane portion (120), wherein a radial dimension of each signal via (161) in the plurality of signal vias (161) is smaller than a radial dimension of each power via (160) in the plurality of power vias (160).

2. The printed circuit board (100) according to claim 1, wherein the signal plane portion (110) is formed in a first lamination process, the power plane portion (120) is formed in a second lamination process, and the signal plane portion (110) and the power plane portion (120) are stacked together through the connection layer (130) in a third lamination process, and The plurality of signal vias (161) are formed in the power plane portion (120) after the first lamination process and before the third lamination process, and the plurality of power vias (160) are formed in the signal plane portion (110) and the power plane portion (120) after the third lamination process.

3. The printed circuit board (100) according to claim 1, wherein at least one of the plurality of signal vias (161) extends from a surface of the signal plane portion (110) facing away from the power plane portion (120) to a metal layer (140) of the plurality of metal layers (140) of the signal plane portion (110) that is adjacent to the connection layer (130).

4. The printed circuit board (100) according to any one of claims 1 to 3, further comprising: A plurality of capacitive load pads (180) are formed in the plurality of metal layers (140) of the signal plane portion (110) and are electrically connected to at least a portion of the plurality of signal vias (161).

5. The printed circuit board (100) according to claim 4, wherein at least one pair of adjacent signal vias (161) among the plurality of signal vias (161) is respectively connected to at least two capacitive load pads (180) among the plurality of capacitive load pads (180), each pair of adjacent signal vias (161) among the at least one pair of adjacent signal vias (161) comprises a first signal via (1611) and a second signal via (1612), the at least two capacitive load pads (180) connected to the first signal via (1611) are offset in a direction away from the corresponding second signal via (1612), and the at least two capacitive load pads (180) connected to the second signal via (1612) are offset in a direction away from the corresponding first signal via (1611).

6. The printed circuit board (100) according to claim 5, wherein each of the plurality of capacitive load pads (180) is elliptical in shape, wherein each of the at least two capacitive load pads (180) connected to the first signal via (1611) has a first end (181) and a second end (182) along the long axis direction, the first end (181) is closer to the second signal via (1612) than the second end (182), and the first end (181) is closer to the first signal via (1611) than the second end (182), and Each of the at least two capacitive load pads (180) connected to the second signal via (1612) has a third end (183) and a fourth end (184) along the long axis direction, the third end (183) is closer to the first signal via (1611) than the fourth end (184), and the third end (183) is closer to the second signal via (1612) than the fourth end (184).

7. A method for manufacturing a printed circuit board (100), comprising: forming a signal plane portion (110), wherein the signal plane portion (110) includes a plurality of metal layers (140) for transmitting signals; A plurality of signal vias (161) are formed in the signal plane portion (110), wherein the plurality of signal vias (161) extend from a surface of the signal plane portion (110) into the signal plane portion (110); forming a power plane portion (120), the power plane portion (120) comprising a plurality of metal layers (140) for providing power; The power plane part (120) is stacked on the signal plane part (110) via a connection layer (130), wherein the surface of the signal plane part (110) faces away from the power plane part (120); as well as A plurality of power vias (160) are formed in the signal plane portion (110) and the power plane portion (120), and the plurality of power vias (160) respectively extend from the surface of the signal plane portion (110) to the surface of the power plane portion (120) facing away from the signal plane portion (110), wherein a radial dimension of each signal via (161) in the plurality of signal vias (161) is smaller than a radial dimension of each power via (160) in the plurality of power vias (160).

8. The method according to claim 7, wherein the signal plane portion (110) is formed in a first lamination process, the power plane portion (120) is formed in a second lamination process, and the signal plane portion (110) and the power plane portion (120) are stacked together through the connecting layer (130) in a third lamination process.

9. The method according to claim 7, wherein at least one signal via (161) among the plurality of signal vias (161) extends from the surface of the signal plane portion (110) to a metal layer (140) among the plurality of metal layers (140) of the signal plane portion (110) that is adjacent to the connection layer (130).

10. The method according to any one of claims 7 to 9, wherein forming the signal plane portion (110) further comprises forming a plurality of capacitive load pads (180) in the plurality of metal layers (140) of the signal plane portion (110), the plurality of capacitive load pads (180) being used to electrically connect to at least a portion of the plurality of signal vias (161).

11. The method according to claim 10, wherein at least one pair of adjacent signal vias (161) among the plurality of signal vias (161) is respectively connected to at least two capacitive load pads (180) among the plurality of capacitive load pads (180), each pair of adjacent signal vias (161) among the at least one pair of adjacent signal vias (161) comprises a first signal via (1611) and a second signal via (1612), the at least two capacitive load pads (180) connected to the first signal via (1611) are offset in a direction away from the corresponding second signal via (1612), and the at least two capacitive load pads (180) connected to the second signal via (1612) are offset in a direction away from the corresponding first signal via (1611).

12. The method according to claim 11, wherein each of the plurality of capacitive load pads (180) is elliptical in shape, wherein each of the at least two capacitive load pads (180) connected to the first signal via (1611) has a first end (181) and a second end (182) along the long axis direction, the first end (181) is closer to the second signal via (1612) than the second end (182), and the first end (181) is closer to the first signal via (1611) than the second end (182), and Each of the at least two capacitive load pads (180) connected to the second signal via (1612) has a third end (183) and a fourth end (184) along the long axis direction, the third end (183) is closer to the first signal via (1611) than the fourth end (184), and the third end (183) is closer to the second signal via (1612) than the fourth end (184).

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