Compiling method and device, equipment and storage medium

Abstract

The invention discloses a compiling method, device and equipment and a storage medium, and belongs to the field of compilers, and the method comprises the steps that an instruction sequence in a loop BB is circularly unfolded, and a triple BB and a triple DAG corresponding to the triple BB are generated; the triple BB comprises an instruction sequence circulating for three times; the triple DAG is used for indicating a data dependency relationship among instructions in the triple BB; window scheduling is carried out based on the triple BB, and a target scheduling window is determined; the window scheduling is used for dividing an instruction sequence in the circulating BB into two parts according to a scheduling window; the target scheduling window is a scheduling window of which the execution time meets a time condition, and the execution time is time required for executing an instruction in the window and calculated according to a data dependency relationship in the triple DAG; and according to a scheduling result corresponding to the target scheduling window, compiling to obtain a target code of the circulating BB in the target program. According to the method, the compiling and executing efficiency of the loop BB can be improved.

Description

Technical Field

[0001] The present application relates to the field of compilers, and in particular to a compilation method, apparatus, device and storage medium. Background Art

[0002] In recent years, with the rapid development of artificial intelligence (AI), it has brought revolutionary technological changes to many fields, such as natural language processing, computer vision, e-commerce, smart cities, drug research and development, etc.

[0003] In order to build a complete application ecosystem, it is necessary to design and develop an AI supporting tool chain, among which the AI ​​compiler is a key task. The AI ​​compiler is used to compile the algorithm of the AI ​​model into executable machine code, that is, to generate a target program that can run on the AI ​​chip based on the program of the AI ​​model.

[0004] However, in the basic computing unit operators of AI models, there are a large number of loop instruction structures, which consume a large part of the AI ​​chip execution time. In order to reduce the execution time of the loop instruction structure, soft pipelining optimization is introduced to optimize the compilation algorithm of the loop instruction structure. Summary of the invention

[0005] The present application provides a compilation method, apparatus, device and storage medium, wherein the method provides a soft pipelining algorithm, which can improve the compilation and execution efficiency of loop BB. The technical solution includes the following contents.

[0006] According to one aspect of the present application, a compilation method is provided, the method comprising the following steps.

[0007] Loop unrolling an instruction sequence in a loop BB (Basic Block) to generate a triple BB and a triple DAG (Directed Acyclic Graph) corresponding to the triple BB; the triple BB includes the instruction sequence looped three times; the triple DAG is used to indicate data dependency between instructions in the triple BB;

[0008] Window scheduling is performed based on the triple BB to determine a target scheduling window; the window scheduling is used to divide the instruction sequence in the loop BB into two parts according to the scheduling window, so that the second part of the instruction sequence in the current loop is executed synchronously with the first part of the instruction sequence in the next loop; the target scheduling window is a scheduling window whose execution time meets the time condition, and the execution time is the time required for executing instructions in the window calculated according to the data dependency relationship in the triple DAG;

[0009] According to the scheduling result corresponding to the target scheduling window, the target code of the loop BB in the target program is compiled.

[0010] According to another aspect of the present application, a compiling device is provided, and the device includes the following modules.

[0011] A loop module, used for loop-unrolling an instruction sequence in a loop basic block BB, generating a triple BB and a triple directed acyclic graph DAG corresponding to the triple BB; the triple BB includes the instruction sequence looped three times; the triple DAG is used to indicate the data dependency relationship between the instructions in the triple BB;

[0012] A scheduling module is used to perform window scheduling based on the triple BB and determine a target scheduling window; the window scheduling is used to divide the instruction sequence in the loop BB into two parts according to the scheduling window, so that the second part of the instruction sequence in the current loop is executed synchronously with the first part of the instruction sequence in the next loop; the target scheduling window is a scheduling window whose execution time meets the time condition, and the execution time is the time required for the execution of instructions in the window calculated according to the data dependency relationship in the triple DAG;

[0013] The compiling module is used to compile and obtain the target code of the loop BB in the target program according to the scheduling result corresponding to the target scheduling window.

[0014] According to one aspect of the present application, a computer device is provided, the computer device comprising: a processor and a memory, the memory storing a computer program, and the computer program is loaded and executed by the processor to implement the above compilation method.

[0015] According to another aspect of the present application, a computer-readable storage medium is provided, wherein the storage medium stores a computer program, and the computer program is loaded and executed by a processor to implement the above compilation method.

[0016] According to another aspect of the present application, a computer program product or computer program is provided, the computer program product or computer program includes computer instructions, the computer instructions are stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions, so that the computer device executes the above-mentioned compilation method.

[0017] The beneficial effects brought about by the technical solution provided in the embodiments of the present application include at least the following.

[0018] A soft pipeline algorithm is provided to compile the loop BB in the AI ​​model. The loop BB is divided into two parts, front and back, using a window scheduling algorithm, so that the front part of the next loop and the back part of the current loop are executed synchronously, saving instruction execution time. In order to find the best split position and minimize the execution time, the loop BB is copied three times to obtain a triple BB and a triple DAG, and multiple scheduling windows are tried on the triple BB. The scheduling window box selects the back part of the instructions in the first loop BB and the front part of the instructions in the second loop BB. And according to the data dependency relationship of each instruction indicated in the triple DAG, the execution time required for the two parts of the instructions in each scheduling window to be executed synchronously is calculated. Then, the scheduling window with the shortest execution time is selected from multiple scheduling windows as the final target scheduling window, and the split position corresponding to the target scheduling window is the best split position. Compiling the loop BB according to the scheduling result from the target scheduling window can improve the compilation efficiency of the loop BB and minimize the execution time of the target code of the compiled target program. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0020] Figure 1 is a schematic diagram of the processing process of an AI compiler provided by an embodiment of the present application;

[0021] Figure 2 is a schematic diagram of a pseudo code of a table scheduling algorithm provided by an embodiment of the present application;

[0022] Figure 3 is a schematic diagram of a module scheduling algorithm provided by an embodiment of the present application;

[0023] Figure 4 is a flow chart of a module scheduling algorithm provided by an embodiment of the present application;

[0024] Figure 5 is a schematic diagram of a window scheduling algorithm provided by an embodiment of the present application;

[0025] Figure 6 is a flow chart of a window scheduling algorithm provided by an embodiment of the present application;

[0026] Figure 7 is a schematic diagram of a window scheduling algorithm provided by an embodiment of the present application;

[0027] Figure 8is a schematic diagram of a compilation method provided by an embodiment of the present application;

[0028] Fig. 9 is a flowchart of a compilation method provided by an embodiment of the present application;

[0029] Fig.10 is a flowchart of a compilation method provided by an embodiment of the present application;

[0030] Fig.11 is a flowchart of a compilation method provided by an embodiment of the present application;

[0031] Fig.12 is a flowchart of a compilation method provided by an embodiment of the present application;

[0032] Fig.13 is a schematic diagram of a specific compilation example provided by an embodiment of the present application;

[0033] Fig.14 is a schematic diagram of a specific compilation example provided by an embodiment of the present application;

[0034] Fig.15 is a schematic diagram of a specific compilation example provided by an embodiment of the present application;

[0035] Fig.16 is a schematic diagram of a specific compilation example provided by an embodiment of the present application;

[0036] Fig.17 is a schematic diagram of a specific compilation example provided by an embodiment of the present application;

[0037] Fig.18 is a schematic diagram of a specific compilation example provided by an embodiment of the present application;

[0038] Fig.19 is a schematic diagram of a specific compilation example provided by an embodiment of the present application;

[0039] Fig. 20 It is an application schematic diagram provided by an embodiment of the present application;

[0040] Fig.21 This is a schematic diagram of the application effect provided by an embodiment of the present application;

[0041] Fig. 22 is a schematic diagram of a terminal device provided by an embodiment of the present application;

[0042] Fig.23 is a flowchart of a compilation method provided by an embodiment of the present application;

[0043] Fig.24 is a flowchart of a compilation method provided by an embodiment of the present application;

[0044] Fig.25 is a structural block diagram of a compiling device provided by an embodiment of the present application;

[0045] Fig.26 It is a structural block diagram of a computer device provided by an embodiment of the present application. DETAILED DESCRIPTION

[0046] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below with reference to the accompanying drawings.

[0047] First, the nouns involved in the embodiments of the present application are briefly introduced.

[0048] AI: refers to the technology that can present human intelligence through ordinary computer programs. AI is a new technical science that studies and develops theories, methods, technologies and application systems for simulating, extending and expanding human intelligence.

[0049] Artificial Intelligence (AI) is the theory, method, technology and application system that uses digital computers or machines controlled by digital computers to simulate, extend and expand human intelligence, perceive the environment, acquire knowledge and use knowledge to obtain the best results. In other words, artificial intelligence is a comprehensive technology in computer science that attempts to understand the essence of intelligence and produce a new intelligent machine that can respond in a similar way to human intelligence. Artificial intelligence is to study the design principles and implementation methods of various intelligent machines so that machines have the functions of perception, reasoning and decision-making.

[0050] Artificial intelligence technology is a comprehensive discipline that covers a wide range of fields, including both hardware-level and software-level technologies. Basic artificial intelligence technologies generally include sensors, dedicated artificial intelligence chips, cloud computing, distributed storage, big data processing technology, pre-trained model technology, operation / interaction systems, mechatronics and other technologies. Among them, the pre-trained model is also called a large model or a basic model. After fine-tuning, it can be widely used in downstream tasks in various major directions of artificial intelligence. Artificial intelligence software technology mainly includes computer vision technology, speech processing technology, natural language processing technology, and machine learning / deep learning.

[0051] With the research and progress of artificial intelligence technology, artificial intelligence technology has been studied and applied in many fields, such as common smart homes, smart wearable devices, virtual assistants, smart speakers, smart marketing, driverless cars, autonomous driving, drones, digital twins, virtual humans, robots, artificial intelligence generated content (Artificial Intelligence Generated Content, AIGC), conversational interaction, smart medical care, smart customer service, game AI, etc. It is believed that with the development of technology, artificial intelligence technology will be applied in more fields and play an increasingly important role.

[0052] Operator: Operator is the basic computing unit of machine learning models.

[0053] Software Pipelining: It is a type of loop instruction scheduling algorithm in the compiler field.

[0054] Modulo Scheduling: It is a classic soft-pipeline algorithm in the field of compilers.

[0055] List Scheduling: It is a type of non-loop instruction scheduling method in the compiler field and is the basic scheduling algorithm in the compiler.

[0056] Basic Block (BB): In the compiler, it represents a linearly executed instruction. BB has a single entry instruction and a single end instruction. The compiler will decompose a program into a combination of basic blocks.

[0057] DAG (Directed Acyclic Graph): If a directed graph cannot return to any vertex through several edges, then the graph is a directed acyclic graph. DAG is used in this application to indicate the dependency relationship between instructions. For example, the data generated by instruction A is passed to instruction B through a register. In the DAG, there is a directed edge from node A to node B. The weight of this directed edge is the minimum number of waiting beats (delay time) from instruction A emitting data to passing the data to instruction B.

[0058] II (Initiation Interval): refers to the time difference between the start of execution of the corresponding instructions of two cycles in module scheduling.

[0059] Heuristic Algorithm: In contrast to the optimization algorithm, the heuristic algorithm does not solve the optimization problem mathematically, but is an algorithm constructed based on intuition or experience, and is widely used in the compiler field. This application uses a heuristic method to find a set of offset positions of the scheduling window.

[0060] Stall cycle: refers to the processor cycle when the pipeline execution is paused due to data or resource conflicts. In the window scheduling algorithm, the result of each table scheduling needs to calculate the number of stall cycles introduced between two cycles.

[0061] AI compiler: A domain-specific compiler that converts machine learning models in different formats into compiler intermediate representation (IR) and optimizes them, ultimately generating executable code for the corresponding hardware platform. AI compilers usually use the classic front-end and back-end structures to connect the model generated by the machine learning framework with the underlying chip. The overall structure of an AI compiler is as follows: Figure 1 shown.

[0062] exist Figure 1 In the code generation process, the AI ​​compiler reads the machine learning model 101 generated from machine learning frameworks such as TensorFlow and Pytorch. The AI ​​compiler first performs model parsing 102 on the model 101 at the front end, parsing it into a high-level IR (Intermediate Representation) (usually a computational graph), and then performs target-independent optimization (optimization independent of the target hardware) 103, such as arithmetic simplification, operator fusion, etc., and outputs the optimized high-level IR. Next, it enters the target-related optimization 104 of the back end, such as dedicated instruction mapping, memory allocation, memory access latency hiding, etc., and outputs the device-related low-level IR; finally, it enters the code generation stage 105 of the back end to generate a target program 106 that can run on the AI ​​chip.

[0063] The compilation method provided in this application is in the code generation stage 105 in the AI ​​compiler.

[0064] During the code generation phase, the AI ​​compiler divides the acquired high-level computer language code into multiple basic blocks (BB), which is a linear program code. For a basic block, the compiler performs instruction scheduling on the code in the basic block to obtain an instruction sequence. The instructions in the instruction sequence are packaged to obtain multiple instruction packets, and then each instruction packet is converted into a series of binary data of fixed or non-fixed length. The converted instruction packets are sent to the hardware (AI chip) for execution to complete the BB compilation process. The AI ​​chip processes one instruction packet in parallel in one clock cycle.

[0065] Instruction scheduling: Instruction scheduling can reorder the order of instruction issuance, improve the parallelism of instruction execution, and reduce the total time required for operator execution. Instruction scheduling is subject to many constraints when selecting instructions, such as instruction dependency constraints, hardware resource constraints, register constraints, etc. The main goal of instruction scheduling is to minimize pipeline pauses and seek the optimal solution under these existing constraints.

[0066] Instruction scheduling optimization algorithms include table scheduling algorithm, module scheduling algorithm and window scheduling algorithm.

[0067] The table scheduling algorithm is a method of adjusting the instruction order based on a greedy algorithm and a heuristic algorithm. The algorithm uses the basic block as the basic interval, and continuously selects and adjusts the instruction order within this range according to conditions such as instruction dependency and hardware resource usage. Figure 2 The pseudo code of the table scheduling algorithm provided by the related art is shown.

[0068] exist Figure 2 In the code, Op represents an instruction, D represents a directed acyclic graph of instruction dependencies, D = (N, E), N is a node, representing an instruction; E is an edge, representing the minimum interval between two nodes. The variable Cycle is a simulated hardware clock cycle, initialized to 1, and will be accumulated during the code execution. Whenever Cycle+1 occurs, all instructions completed by the previous Cycle are deleted from the Active list, and each successor node of these instructions in D is checked, and the available instructions are moved into the Ready list. The Ready list contains all instructions used in the current Cycle without affecting the correctness of continuous execution, initialized to all child nodes of the parent node in D. The Active list contains all instructions that can actually be emitted at present.

[0069] The module scheduling algorithm is a kind of soft pipelining algorithm. In the code generation process of the AI ​​compiler backend, soft pipelining is an important optimization stage. Operators, which are the basic computing units of AI models, have a large number of loop instruction structures, which consume the main chip execution time. Soft pipelining optimization is a type of compilation algorithm specifically used to optimize loop instruction structures. At present, the mainstream soft pipelining optimization algorithm in the industry is the module scheduling algorithm. Its main algorithm ideas are as follows: Figure 3 shown.

[0070] exist Figure 3 In , assume that the total number of loops of a loop instruction structure is N. The instruction sequence in its core loop takes T beats in each loop, where T can be divided into 3 equal segments. Figure 3In part (A), each loop starts after the previous loop is completed. Each loop is represented by I(n), where n∈[0, 1, 2, ..., N-2, N-1]. For a loop, each equally divided code segment is represented by S(n). Figure 3 Each code segment is divided into 3 segments, namely n∈[0, 1, 2]. The code after modular scheduling is as follows Figure 3 As shown in part (B), the instructions of loop I(n+1) can start executing in advance without waiting for loop I(n) to complete. The time difference between the start of I(n) and I(n+1) is called the start interval II. II is equal to the number of beats occupied by a piece of code in one loop. Figure 3 In part (B) of , II = T / 3. Analyzing the folded loop, we can find that there is a stable code structure, such as Figure 3 As shown in part (C), Figure 3 The (C) part is the code structure after the module scheduling. It contains three stages, namely the filling stage, including the beginning part of the code in the first two loops; the core stage, including part of the code in three consecutive loops; and the emptying stage, including the end part of the code in the last two loops.

[0071] For a specific instruction in a loop, if it is issued at the Kth beat relative to the first instruction of a certain loop, then its issuance time in the core stage after folding is T = K mod II, which is the origin of the name of modular scheduling. For example, if the issuance time of instruction A before folding is at the 16th beat relative to the first instruction of this loop, and II is 10 beats, then the folded instruction A is issued at the 6th beat, and the execution time of the core loop is also compressed to 10 beats.

[0072] The basic algorithm flow of modular scheduling is as follows Figure 4 shown.

[0073] Step 401, start.

[0074] Step 402: Construct a directed acyclic graph. Construct a DAG (directed acyclic graph) according to the input instructions. The DAG is used to represent the dependency relationship between instructions.

[0075] Step 403: Calculate scheduling parameters, such as the initial value and maximum value of the start interval, the depth and height of the nodes in the DAG graph, etc.

[0076] Step 404: Sort the instructions. The scheduling order of the instructions is adjusted according to the node-related parameters calculated in step 403.

[0077] Step 405, traverse the start intervals in sequence. Starting from the initial start interval, try to find out whether a reasonable scheduling result can be found in sequence until the start interval is equal to the maximum value.

[0078] Step 406: Use a search algorithm to traverse the instructions and calculate the scheduling results. Search each instruction in order to see if it can be successfully scheduled, that is, there is no resource conflict and unreasonable dependency between the instruction and the scheduled instructions.

[0079] Step 407, determine whether to stop searching. Determine whether to stop searching. If so, execute step 408; if scheduling is unsuccessful, return to execute step 405.

[0080] Step 408, determine whether the scheduling is successful. If the scheduling is successful, execute step 409, if the scheduling is unsuccessful, execute step 410.

[0081] Step 409: Adjust the code. If the scheduling is successful, a complete code structure is generated according to the scheduling result, including a filling stage, a core stage, and an emptying stage.

[0082] Step 410, end. The scheduling fails, and the original code remains unchanged.

[0083] Window scheduling is also a soft pipelining algorithm. Compared with the modular scheduling algorithm, in AI accelerator architectures with more resource conflicts, window scheduling has a high scheduling success rate and guaranteed performance.

[0084] like Figure 5 As shown in (A) in the figure, assuming that loop BB has M instructions, and the window scheduling selects an offset position K to establish the scheduling window, then the scheduling window contains MK instructions in cycle n-1 and K instructions in cycle n. These instructions in the scheduling window are table-scheduled. If the execution time of the scheduled instruction is the shortest, the current scheduling result is the optimal result. Finally, after traversing all offset positions, as shown in Figure 5 As shown in (B) in the figure, the final code including prolog (filling stage), kernel (core stage) and epilog (emptying stage) is generated according to the optimal window offset position.

[0085] In an optional embodiment, the window scheduling algorithm process is as follows: Figure 6 As shown, the method includes the following steps.

[0086] Step 501, back up the original BB (circular BB).

[0087] Step 502: Make two copies of the original BB to generate a DoubleBB (twice the BB), and establish a DoubleDAG (twice the DAG).

[0088] Step 503, starting from the first instruction of DoubleBB, the scheduling window is moved one by one.

[0089] Step 504: After the scheduling window is moved, an instruction that is moved out of the scheduling window is added to the back of the original DoubleDAG to update the DoubleDAG. For example, if the first instruction in the last scheduling window is instruction A, then after the scheduling window is moved, instruction A is moved out of the scheduling window, and instruction A is added to the back of DoubleDAG to update DoubleDAG.

[0090] Step 505, perform table scheduling within the scheduling window to obtain a scheduling result of the table scheduling.

[0091] Step 506: Analyze and update the scheduling result of the table scheduling, and calculate the increased stall cycle according to the scheduling result.

[0092] Step 507: If the scheduling result of the current table scheduling does not exceed the limit and the scheduling window has not been traversed completely, return to step 503.

[0093] Step 508, determining whether the scheduling result is reasonable, including whether the performance after scheduling meets the requirements.

[0094] Step 509: If the scheduling result is reasonable, it is expanded into a code structure that ultimately includes prolog (filling), kernel (core) and epilog (draining).

[0095] Step 510: otherwise, restore the original BB state before scheduling.

[0096] From the perspective of algorithm effect, window scheduling can be equivalent to a modular scheduling algorithm that is fixedly divided into two segments. This is the basis for window scheduling to improve instruction-level parallelism and achieve better performance.

[0097] Modulo scheduling algorithms usually use a greedy algorithm to search for the scheduling results of instructions. When given an II, the modulo scheduling algorithm will sequentially try to schedule all instructions between time 0 and (II-1). If all instructions can find such an issuance time, that is, the data dependencies between all instructions are satisfied, and the hardware resources used by the instructions will not conflict, then the modulo scheduling is successful.

[0098] The problem with modular scheduling is that as the number of scheduling instructions increases and when there are more resource conflicts between instructions, the greedy algorithm's search capability is insufficient and scheduling is often unsuccessful. If a more complex search algorithm is used, such as backtracking search, the algorithm complexity will increase exponentially, and the compilation process will often fail because it takes too long.

[0099] For AI accelerators, hardware instructions are often complex, and many hardware resources are shared between instructions, which easily leads to conflicts. In addition, instruction execution takes a long time, often requiring more than 10 beats to output results, which further increases the difficulty of scheduling algorithms. Therefore, when modular scheduling is used in the development of AI accelerator operators, scheduling failures often occur.

[0100] Since modulo scheduling is prone to failure, try using the above-mentioned window scheduling in the AI ​​compiler. Window scheduling can effectively solve the problem of modulo scheduling being prone to failure, because the table scheduling algorithm used by window scheduling when traversing offsets will definitely produce scheduling results, and the performance difference is not much with the modulo scheduling results.

[0101] However, window scheduling is also a complex scheduling algorithm. The above window scheduling method has two problems:

[0102] Problem (1) DoubleDAG needs to be updated after the scheduling window is moved. In order to establish the dependency between instructions in two cycles, it is necessary to copy two instructions based on the original BB and establish a new BB (DoubleBB). Then, a DAG is established for this new BB, which is DoubleDAG, to describe the dependency between instructions in the scheduling window. Each time the scheduling window is moved, the instructions before the scheduling window offset position need to be connected to the end of DoubleDAG, that is, DoubleDAG needs to be updated synchronously to ensure that DoubleDAG contains the dependency of all instructions in the scheduling window.

[0103] The main purpose of updating the DoubleDAG is that by folding the instruction nodes before the scheduling window to the nodes below the DoubleDAG, the compiler can establish dependencies between instructions that cross loop definitions and use the same registers.

[0104] like Figure 7 As shown, the shaded portion represents the scheduling window 107. When the scheduling window 107 moves to Figure 7 , all instructions before the scheduling window 107 (including instruction B') need to be moved from the original position in the DoubleDAG to the new position below the DoubleDAG. Note that there is actually no instruction movement here, only the DoubleDAG is updated. At this time, instruction A and instruction B' have a new direct data dependency, and instruction B and instruction B' correspond to the same instruction, so the emission time is the same. At this time, the data dependency relationship between instruction A and instruction B' can be determined based on the data dependency relationship between instruction A and instruction B', and then the Stall Cycle (pause time) that needs to be added after the table scheduling is completed can be determined.

[0105] The calculation formula of Stall Cycle (pause time) is as follows:

[0106] Stall Cycle=DefCycle+Latency(A,B)-MaxCycle-UseCycle

[0107] Among them, DefCycle is the emission time of instruction A; Latency(A,B) is the delay from the data output by instruction A to the input of instruction B; MaxCycle refers to the time when all instructions in the scheduling window are executed; UseCycle is the emission time of instruction B. The above formula means that if instruction A in the current cycle outputs data to instruction B in the next cycle, if the delay relationship is not satisfied, some Stall Cycles need to be added.

[0108] For example, according to Figure 7 , then before executing instruction B of the second cycle, it is necessary to ensure that instruction A' of the first cycle is executed and the data reaches instruction B (that is, the emission time of instruction A' of the first cycle plus the delay time of instruction A' must be before the emission time of instruction B of the second cycle). If this relationship is not satisfied, it is necessary to increase the Stall Cycle to increase the execution time of the scheduling window, thereby delaying the start time of instruction B of the second cycle to ensure that the data of instruction A' of the first cycle can be passed to instruction B of the second cycle.

[0109] In the above process, appending an instruction to the lower part of DoubleDAG requires complex graph operations and large amount of calculation.

[0110] Problem (2) The efficiency of moving the window instruction by instruction is low. Although the above window scheduling algorithm includes Limit for early exit algorithm, the window moving process is still performed instruction by instruction. In actual application, this is still very time-consuming, and the difference between two adjacent offset instructions is often not large, so the search efficiency of sliding the window instruction by instruction is low.

[0111] In order to solve the above problem (1), the present application proposes a TripleDAG method.

[0112] like Figure 8 As shown in the figure, before the instruction is scheduled, TripleBB and the corresponding TripleDAG are established. During the sliding of the scheduling window, there is no need to adjust and update TripleDAG, because all dependencies have been built in TripleDAG, so the Stall Cycle introduced by instructions A and B can be directly calculated, thus avoiding the problem of updating DAG during the scheduling process.

[0113] For example, Figure 8 As shown, the shaded portion represents the scheduling window 107. When the scheduling window 107 moves to Figure 8 When the position in the scheduling window is found, the data dependency of all instructions in the scheduling window needs to be obtained to calculate the Stall Cycle. At this time, the data dependency of instruction A and instruction B' in TripleDAG can be directly determined based on the data dependency of instruction A and instruction B', because instruction B and instruction B' correspond to the same instruction and have the same emission time. Then, based on the data dependency of instruction A and instruction B, the Stall Cycle (pause time) that needs to be added after the table scheduling is completed is determined.

[0114] It can be seen that since TripleDAG already contains the data dependency relationship between instruction A and instruction B", there is no need to update TripleDAG after each movement of the scheduling window. The data dependency relationship between instruction A and instruction B can be directly queried from TripleDAG, and then the data dependency relationship between instruction A and instruction B can be determined, which greatly reduces the amount of calculation and improves the calculation efficiency of the Stall Cycle.

[0115] The loop in the operator is usually expanded 4 or 8 times, and the number of instructions is usually 100 to 200. At this time, the efficiency of moving the scheduling window instruction by instruction is very low, and because there are a large number of repeated instructions, the scheduling results of two adjacent windows are often the same or very different. Therefore, in order to solve the above problem (2), this application uses a different heuristic method to give a more efficient search offset position. This application uses a heuristic algorithm with adaptive step size based on statistical results:

[0116] (1) When the number of instructions to be scheduled (the total number of instructions in the loop BB) is less than or equal to M, the offset step size of the scheduling window is adjusted to 1;

[0117] (2) When the number of instructions to be scheduled is greater than M and less than or equal to 2M, the offset step size of the scheduling window is adjusted to 2;

[0118] (3) When the number of instructions to be scheduled is greater than 2M and less than or equal to 3M, the offset step size of the scheduling window is adjusted to 4;

[0119] (4) When the number of instructions to be scheduled is greater than 3M and less than or equal to 4M, the offset step size of the scheduling window is adjusted to 6;

[0120] (5) When the number of instructions to be scheduled is greater than 4M, the offset step of the scheduling window is adjusted to 8.

[0121] After testing, it was found that when a suitable M value was selected, the compilation speed increased by more than 50% to 60% and the performance decreased by no more than 5%.

[0122] The method provided in this application can be used in the AI ​​compiler tool chain, located in the back-end code generation module of the AI ​​compiler. Its typical application scenarios include in the AI ​​compiler supporting the AI ​​chip. This method can significantly speed up the compilation time of the operator core loop.

[0123] In addition, the method provided in this application can also be used in traditional compilers to speed up the compilation time of the core loop generated by the compiler backend.

[0124] like Fig. 9 As shown, the input of the system is the instruction sequence in the loop core BB (loop BB) 108. The loop core BB 108 needs to meet the following constraints: the loop body only includes one BB instead of multiple BBs; the number of instructions in the BB is within a certain range; the BB should not contain assembly or other instructions with side effects (modifying the predetermined state of the machine).

[0125] The fast window scheduler 109 is the core facility of the present application. It schedules the input instructions according to the input loop core instruction sequence through the window scheduling algorithm provided by the present application. It needs to establish auxiliary data structures such as TripleBB and TripleDAG, and use heuristic algorithms to improve the efficiency of window traversal, while ensuring the performance of generated code, reducing the compilation time of window scheduling.

[0126] The instruction scheduling result 110 generated by the fast window scheduler 109 includes the scheduled instruction, the time when the instruction is issued, the stage to which the instruction belongs, the optimal II obtained by scheduling, and the offset step of the corresponding scheduling window.

[0127] The soft-pipeline instruction extender 111 is usually a basic module provided by the compiler. It uses the instruction scheduling result 110 to first generate the core BB (execution time is II) after window scheduling; then it supplements the logic of the Prologue (filling) and Epilogue (emptying) parts, and finally obtains the correct code after soft-pipelining.

[0128] This application is for Figure 6 The DoubleBB window scheduling algorithm shown in the figure is improved. The main process is as follows Fig.10 As shown, Figure 6 The main differences of the method shown are step 602, step 603 and step 605. The method comprises the following steps.

[0129] Step 601, back up the original BB as OriBB.

[0130] Step 602, copy the backup OriBB three times to generate a new TripleBB, and generate a corresponding TripleDAG.

[0131] Step 603, using a heuristic algorithm to obtain a set of window offset values; taking out a window offset value, and obtaining the scheduling window on TripleBB accordingly.

[0132] Step 604: Use table scheduling to schedule the instructions in the scheduling window. Table scheduling is a basic function module provided by the compiler.

[0133] Step 605: Analyze the scheduling result of the table scheduling using TripleDAG, and store the analysis result in a corresponding data structure.

[0134] Step 606: If the search for all offset positions is completed, proceed to step 607; otherwise, return to step 603 to search for the next offset value.

[0135] Step 607 , analyzing the rationality of the scheduling result, for example, whether the execution time after scheduling is improved, etc. If it is reasonable, proceed to step 609 ; otherwise, proceed to step 608 .

[0136] Step 608, using OriBB to restore the original cycle BB.

[0137] Step 609, using the soft pipeline instruction extender provided by the compiler, obtain the corresponding soft pipeline code according to the scheduling result of the scheduling window.

[0138] At this point, the processing process of the fast soft pipelining algorithm based on window scheduling is completed.

[0139] For step 605 in the above process, the main purpose of analyzing the scheduling results of the table scheduling is to analyze the issuance time of each instruction and the overall execution time of the sequence instructions (i.e., the corresponding II) from the scheduled instruction sequence output by the table scheduling. This execution time includes the maximum issuance time and pause time of the instruction sequence.

[0140] Among them, the algorithm process for calculating the maximum instruction emission time is as follows: Fig.11 As shown, the following steps are included.

[0141] Step 701, obtaining a DAG generated during table scheduling, the DAG consisting of instructions in the scheduling window; obtaining an instruction resource manager provided by the compiler, the instruction resource manager is responsible for checking whether there is a resource conflict between instructions.

[0142] Among them, instructions are executed by hardware resources in the AI ​​chip. One instruction can be executed by one or more hardware resources. When the hardware resources corresponding to an instruction are occupied by other instructions, there is a resource conflict between the instruction and other instructions. When the hardware resources corresponding to the instruction are not occupied by other instructions, there is no resource conflict between the instruction and other instructions.

[0143] Optionally, if there is a resource conflict between the instruction and other instructions at the current transmission time, the transmission time of the instruction can be adjusted to continue to detect whether there is a resource conflict at the new transmission time.

[0144] Step 702, initialize the current time to 0 beats.

[0145] Step 703, taking out an instruction from the instruction sequence scheduled by the table.

[0146] Step 704, determine whether the instruction should be issued at the current moment. Through DAG analysis, if there is no previous instruction, or the previous instruction has been issued, and the current moment is greater than or equal to the previous instruction issuance time plus the corresponding data delay, then the instruction can be issued at the current moment, and the process goes to step 706; otherwise, the process goes to step 705. The previous instruction refers to the source instruction of the input data of the current instruction. For example, the output data a of instruction A is the input data that instruction B depends on, that is, the input data of instruction B is data a, and the output data of instruction B is data b, then instruction A is the previous instruction of instruction B.

[0147] Step 705, add one beat to the current moment.

[0148] Step 706, using the instruction resource manager, determines whether there is a resource conflict between the current instruction and the previously scheduled instruction. If there is no resource conflict, proceed to step 707, otherwise proceed to step 705.

[0149] Step 707: the current time is the time of issuing the current instruction, and the resources occupied by the current instruction are recorded in the instruction resource manager.

[0150] Step 708, if all instructions have been traversed, go to step 709, otherwise go to step 703.

[0151] Step 709: After all instructions have been traversed, the current time plus 1 is the maximum transmission time of the instruction sequence.

[0152] The process of calculating instruction pause time is as follows Fig.12 As shown, the following steps are included.

[0153] Step 801: Acquire the TripleDAG initially established by window scheduling.

[0154] Step 802, initialize the maximum pause time to 0 beats.

[0155] Step 803, taking out an instruction from the instruction sequence scheduled by the table.

[0156] Step 804, determine whether the current instruction will generate a pause time. The determination is based on calculating the Stall Cycle (pause time) of the instruction according to the data dependency of the instruction in TripleDAG. If the Stall Cycle is greater than 0, proceed to step 805; otherwise, proceed to step 803.

[0157] Step 805, the Stall Cycle calculated according to the calculation formula of the Stall Cycle is the stall time caused by the current instruction.

[0158] Step 806: If the current pause time is greater than the maximum pause time, the maximum pause time is updated with the current pause time.

[0159] Step 807, if all instructions have been traversed, go to step 808; otherwise go to step 803.

[0160] Step 808, obtaining the maximum pause time of the instruction sequence.

[0161] An exemplary embodiment of the method provided by the present application is given below to illustrate the application process of the present application. Select a loop core (loop BB) of an operator, and after a series of processing by the compiler, it reaches the soft pipeline stage. Its instruction sequence is as follows: Fig.13 shown.

[0162] The instruction name is represented by an uppercase string, such as PHI, VLD, VNEG, etc. Registers are represented by the "%" character plus a lowercase string or number, such as %1, %2, etc. Constants are directly represented by numbers; instructions that output data to registers use "=" to link the output register and the instruction name; input registers and constants follow the instruction name and are separated by ",". It should be noted that the PHI instruction here is a compiler pseudo-instruction used to represent the code as a static single assignment form and does not participate in window scheduling.

[0163] like Fig.14 As shown, the original loop BB is expanded to TripleBB, and the registers used need to be updated synchronously during the expansion. That is, Fig.13 The first and second instructions in (PHI instructions are not copied), and the remaining 9 instructions are copied three times to obtain Fig.14 There are 29 instructions in (2 PHI instructions plus 3×9 loop instructions).

[0164] exist Fig.14 In the TripleBB sequence shown in Figure 1, data is transferred between instructions and between instructions and memory through registers. The data transfer between instructions is represented by a directed acyclic graph. The corresponding TripleBB is a TripleDAG as follows: Fig.15 shown.

[0165] exist Fig.15 In the example, the instruction sequence is converted into nodes in the order of precedence, and the node number is the input order. A directed edge is added between instructions with data transfer, and its weight represents the delay number of data transmission. For example, the weight of the directed edge between node 0 and node 2 is 1, which means that the instruction corresponding to node 2 can be issued at least 1 beat after the instruction corresponding to node 0 is issued. The directed edge of the node indicates that in this cycle, data is transferred from the source node to the target node. In the following description, nodes and instructions can be considered equivalent, and the two correspond one to one.

[0166] Next, the heuristic algorithm is used to calculate the set of window offsets. According to the heuristic algorithm given above, assuming that M = 10, and the total number of instructions in the current loop BB is 11, the offset step length of the scheduling window can be obtained to be 2. Therefore, the offset position set of the scheduling window is {0, 2, 4}.

[0167] Taking node offset position 4 as an example, from Fig.14 The instruction sequence with offset position 4 and scheduling window length equal to 9 is intercepted in the above example. The scheduling window includes Fig.16 The instruction sequence shown (the first two PHI instructions do not participate in window scheduling, so when the offset position is 4, the first instruction in the corresponding scheduling window is instruction 7).

[0168] right Fig.16 The instructions in the scheduling window shown in the table are scheduled, and the obtained scheduled instruction sequence is as follows Fig.17 As shown, the order of several instructions has changed:

[0169] Next, TripleDAG is used to schedule Fig.17 Analyze the instruction sequence in (the scheduling result of table scheduling). Take VADDS_f32 as an example. It depends on the VEXP_f32 instruction. The VEXP_f32 instruction is issued at the 5th beat, with a relative delay of 10 beats. Therefore, the earliest issuance time is 15 beats. The current time is 16 beats, so it can be issued. Then determine the resource conflict between it and other scheduled instructions, and finally determine its issuance time to be 16 beats. At this time, all instructions have been analyzed, so the maximum issuance time of the instruction sequence is 17 beats.

[0170] Continue to determine the pause time of the instruction sequence. Still taking VADDS_f32 as an example, according to the calculation formula of Stall Cycle, its Stall Cycle = 16 + 3-16-0 = 3 beats. At this time, all instructions have been analyzed and the final pause time is 3 beats. Therefore, the final II is 17 + 3 = 20 beats, which corresponds to the offset position of 4. The specific scheduling results are as follows Fig.18 shown.

[0171] Similarly, when the offset position of the scheduling window is 0 and 2, the II obtained are 22 beats and 15 beats respectively. It can be seen that the II when the offset position is 2 is the shortest. Therefore, the scheduling result when the offset position is 2 is taken as the final scheduling result of the window scheduling.

[0172] Finally, based on the scheduling results, the soft pipeline instruction expander provided by the compiler generates the prologue, kernel and epilogue parts.

[0173] like Fig.19 As shown in the figure, the instructions corresponding to the kernel part are shown. It should be noted that the soft pipeline instruction extender has updated the PHI instruction according to the code semantics, while other instructions remain consistent with the results of the previous scheduling.

[0174] For example, the common operator Swish in neural networks is used to analyze the application effect of the method provided by this application in detail. In order to improve instruction parallelism, the core loop of Swish is expanded 8 times in advance. The following compares the effects of using modulo scheduling, DoubleBB window scheduling and the method of this application. The specific test parameter settings are as follows: Fig. 20 As shown in Table 1.

[0175] Under the above test parameters, each algorithm was executed 5 times and the average time consumed was calculated. The results are as follows: Fig.21 As shown in Table 2.

[0176] From the above results, we can see that on the AI ​​accelerator, the modular scheduling algorithm fails to search and times out after the swish operator is expanded 8 times, so the scheduling fails; DoubleBB window scheduling needs to traverse all offset positions, and the algorithm complexity is high, so it takes 1.44 seconds; while the method of this application takes 0.38 seconds, and the compilation time is reduced by 73.6%. DoubleBB window scheduling and the method of this application both search for 50 beats of II, so the performance of the generated code remains consistent.

[0177] In addition, the large-scale test results of local projects are basically the same. Compared with DoubleBB window scheduling, the compilation time of the method of the present application can be reduced by 60% to 80%, and the core cycle execution performance is slightly reduced within 5%.

[0178] Therefore, the method of the present application can solve the problem of module scheduling failure in complex compilation scenarios; at the same time, compared with classic window scheduling, it can significantly reduce compilation time while ensuring that code performance remains basically unchanged.

[0179] Next, the compilation method provided by this application will be introduced.

[0180] Fig. 22A schematic diagram of a terminal device provided by an exemplary embodiment of the present application is shown. The compilation method provided by the embodiment of the present application is executed by the terminal device 112, and the terminal device 112 can be a mobile phone, a computer, an intelligent voice interaction device, a smart home appliance, a vehicle terminal, etc. A compiler is installed in the terminal device, and the compilation method provided by the embodiment of the present application is executed by the compiler in the terminal device.

[0181] Fig.23 A flowchart of an instruction packing method provided by an exemplary embodiment of the present application is shown. Fig. 22 The compiler execution in the terminal device shown is used as an example to illustrate that the method includes the following steps.

[0182] Step 210, loop-unroll the instruction sequence in loop BB to generate a triple BB and a triple DAG corresponding to the triple BB; the triple BB includes an instruction sequence that loops three times; the triple DAG is used to indicate the data dependency between the instructions in the triple BB.

[0183] Exemplarily, the loop BB may be a loop BB in an AI model, an AI model may include at least one loop BB, and each loop BB may be compiled using the method provided in the embodiment of the present application. Optionally, an operator of an AI model may include at least one loop BB.

[0184] The loop BB has only a single entry instruction and a single end instruction, and the loop BB includes a loop body, which will be repeatedly executed. The loop BB may refer to a loop core BB, and the loop body of the loop core BB has only one BB. When the second loop body is nested in the first loop body, and no other loop bodies are nested in the second loop body, the second loop body may be the loop core BB (the loop body includes at least one instruction). Exemplarily, the total number of instructions in the loop BB is less than the quantity threshold, and the loop BB does not contain assembly or other instructions with side effects (modification and its predetermined state).

[0185] The loop BB includes a sequence of instructions that can be executed repeatedly, namely the loop body. This sequence of instructions will be executed repeatedly until a certain termination condition is met. The loop BB has only one entry instruction and one exit instruction. The entry instruction is the instruction that starts the loop, and the exit instruction is the instruction that ends the loop.

[0186] Loop unrolling loop BB means: copy loop BB three times to get triple BB. Triple BB includes the instruction sequence for looping loop BB three times. That is, loop BB includes loop BB of the first loop, loop BB of the second loop and loop BB of the third loop. The loop BBs of the three loops are all obtained by copying the original loop BB. For example, if a loop BB includes instructions A, B and C, then the triple BB obtained after copying three times includes: instructions A, B, C, A', B', C', A", B", C". Among them, instructions A, A' and A" correspond to instruction A; instructions B, B' and B" correspond to instructions B; instructions C, C' and C" correspond to instructions C.

[0187] The triple DAG is constructed based on the data input-output relationship of each instruction indicated in the triple BB and the delay time of each instruction. The triple DAG includes the data dependency relationship and delay time of each instruction in the triple BB.

[0188] In the triple DAG, each instruction of the triple BB corresponds to a node. When the output data of instruction A is the input data of instruction B, a directed line segment will be used in the triple DAG to connect node A corresponding to instruction A and node B corresponding to instruction B. The directed line segment points from node A to node B, and the weight value on the directed line segment is the delay time corresponding to instruction A.

[0189] Among them, data dependencies include: dependent relationships and dependent relationships. The dependent relationships refer to which other instructions the instruction depends on (that is, the output data of the instruction needs to be input into other instructions as input data), and the dependent relationships refer to which other instructions the instruction depends on (that is, the input data of the instruction is the output data of other instructions).

[0190] An instruction can have at least one data dependency, which is represented as a directed line segment in the triple DAG. When there is a directed line segment between node A (instruction A) and node B (instruction B) in the triple DAG, it means that there is a data dependency between instruction A and instruction B, and when the directed line segment is from node A to node B, it means that instruction A is dependent on instruction B (the input data of instruction B is the output data of instruction A).

[0191] Each data dependency has a corresponding delay time, that is, the weight of each directed line segment in the triple DAG is the delay time. For example, if the directed line segment between instruction A and instruction B is marked with a weight of 1, it means that the output data obtained by instruction A needs to be transmitted to instruction B after 1 beat. Exemplarily, the delay time is determined by instruction A and the hardware resources that execute instruction A.

[0192] Based on the data dependency in the triple DAG, the emission time of each instruction in the scheduling window can be determined, and then the maximum emission time when all instructions in the scheduling window are executed, as well as the maximum pause time, are determined. The maximum pause time is to ensure that the input data required by each instruction in the next cycle can reach the instruction before its emission time. Therefore, the execution time of each scheduling window can be calculated based on the triple DAG, and the scheduling window with the shortest execution time is selected as the final target scheduling window.

[0193] Step 220, perform window scheduling based on the triple BB to determine the target scheduling window; the window scheduling is used to divide the instruction sequence in the loop BB into two parts according to the scheduling window, so that the second part of the instruction sequence in the current loop is executed synchronously with the first part of the instruction sequence in the next loop; the target scheduling window is a scheduling window whose execution time meets the time condition, and the execution time is the time required to execute the instructions in the window calculated based on the data dependency relationship in the triple DAG.

[0194] Optionally, after obtaining the triple BB and triple DAG, multiple scheduling windows can be tried on the triple BB, and a target scheduling window whose execution time meets the requirement (time condition) can be selected according to the instruction execution time of each scheduling window. For example, the time condition can be: the shortest execution time, or the execution time is close to the target value, or the longest execution time.

[0195] Exemplarily, when performing window scheduling, the sliding range of the scheduling window includes: starting from the first instruction of the first cycle to the last instruction of the second cycle. That is, the scheduling window only slides in the instruction sequence of the first two cycles. The third cycle in the triple BB is used to generate a triple DAG, so that when the scheduling window slides to the instruction in the second cycle, the execution time of the scheduling window can be calculated according to the data dependency relationship between the instructions in the second cycle and the instructions in the third cycle.

[0196] Step 230, compile and obtain the target code of loop BB in the target program according to the scheduling result corresponding to the target scheduling window.

[0197] Exemplarily, after determining the target scheduling window, the loop BB is compiled according to the scheduling result corresponding to the target scheduling window, so that the running time of the compiled target code can be minimized, thereby improving the compilation and running efficiency of the loop BB.

[0198] In summary, the method provided by the embodiment of the present application provides a soft pipeline algorithm to compile the loop BB in the AI ​​model. The loop BB is divided into two parts, front and back, using the window scheduling algorithm, so that the front part of the next loop and the back part of the current loop are executed synchronously, saving the instruction execution time. In order to find the best split position and minimize the execution time, the loop BB is copied three times to obtain a triple BB and a triple DAG, and multiple scheduling windows are tried on the triple BB. The back part of the instructions in the first loop BB and the front part of the instructions in the second loop BB are selected by the scheduling window frame. And according to the data dependency relationship of each instruction indicated in the triple DAG, the execution time required for the two parts of the instructions in each scheduling window to be executed synchronously is calculated. Then, the scheduling window with the shortest execution time is selected from multiple scheduling windows as the final target scheduling window, and the split position corresponding to the target scheduling window is the best split position. Compiling the loop BB according to the scheduling result from the target scheduling window can improve the compilation efficiency of the loop BB, so that the target code execution time of the target program obtained after compilation is the shortest.

[0199] An exemplary embodiment of window scheduling based on triple BB and triple DAG is given.

[0200] Fig.24 A flowchart of an instruction packing method provided by an exemplary embodiment of the present application is shown. Fig. 22 The compiler execution in the terminal device shown is illustrated as an example, based on Fig.23 In the illustrated embodiment, step 220 includes repeatedly executing steps 221 to 224 to traverse all candidate offset positions.

[0201] Step 221, obtain a candidate scheduling window corresponding to a candidate offset position; the candidate scheduling window selects a window instruction sequence in the triple BB, and the window instruction sequence includes the second part of the instruction sequence in the first cycle and the first part of the instruction sequence in the second cycle in the triple BB; the second part of the instruction sequence and the first part of the instruction sequence are sequentially connected in the triple BB.

[0202] Exemplarily, the window length of the scheduling window is equal to the total number of instructions in the cycle BB. For example, if the cycle BB includes 10 instructions, the window length of the scheduling window is equal to 10 instructions.

[0203] If the loop BB includes 10 instructions, then theoretically, the number of candidate scheduling windows can be 10. Starting from the first instruction of the first loop, each instruction can be the first instruction of a candidate scheduling window, that is, with one instruction as the sliding step, the sliding scheduling window can slide from the first instruction of the first loop to the last instruction of the first loop, and a total of 10 candidate scheduling windows can be obtained. Calculate the execution time corresponding to each of the 10 candidate scheduling windows, and then select a candidate scheduling window with the shortest execution time as the target scheduling window.

[0204] However, when there are a large number of instructions in the loop BB, for example, 100 instructions or 1000 instructions, determining the candidate scheduling window according to the above method requires calculating the execution time 100 times or 1000 times, which is too much calculation. And for a loop BB with a large number of instructions, the difference in execution time between adjacent candidate scheduling windows is small. Therefore, the embodiment of the present application adopts a heuristic algorithm to determine the sliding step (offset step) of the candidate scheduling window, and determines the offset step according to the number of instructions in the loop BB. The more instructions there are, the larger the offset step.

[0205] Exemplarily, the offset step of the scheduling window is determined according to the total number of instructions in the loop BB; and the candidate offset position is determined according to the offset step. The candidate offset position may refer to the first instruction in the candidate scheduling window.

[0206] Optionally, when the total number of instructions is less than or equal to the first value, the offset step is determined to be the first step; when the total number of instructions is greater than the first value and less than or equal to the second value, the offset step is determined to be the second step; when the total number of instructions is greater than the second value and less than or equal to the third value, the offset step is determined to be the third step; when the total number of instructions is greater than the third value and less than or equal to the fourth value, the offset step is determined to be the fourth step; when the total number of instructions is greater than the fourth value, the offset step is determined to be the fifth step.

[0207] Among them, the first value, the second value, the third value and the fourth value are in an arithmetic progression; the first step length, the second step length, the third step length, the fourth step length and the fifth step length increase in sequence.

[0208] For example, the first value is 10, the second value is 20, the third value is 30, and the fourth value is 40. The first step length is 1, the second step length is 2, the third step length is 4, the fourth step length is 8, and the fifth step length is 16. When the loop BB includes 33 instructions, the offset step length is 8, and the starting positions of the candidate scheduling windows are: the first instruction, the ninth instruction, the seventeenth instruction, the twenty-fifth instruction, and the thirty-third instruction, respectively, and a total of five candidate scheduling windows are obtained. Subsequently, one candidate scheduling window can be selected from the five candidate scheduling windows to execute step 221.

[0209] Exemplarily, other methods may be used to determine the candidate offset positions. For example, a predetermined instruction in the loop BB is used as a candidate offset position, and the predetermined instruction may be an instruction with a long execution time or an instruction with a long delay time. For example, the predetermined instruction may be a reciprocal instruction, an exponential instruction, etc. By using the instruction with the longest delay time as the first instruction of the candidate scheduling window, other instructions can be executed synchronously with the first instruction, thereby shortening the execution time of the candidate scheduling window. Optionally, this method may be combined with the above-mentioned heuristic algorithm method, for example, determining the offset step of the scheduling window according to the total number of instructions in the loop BB, determining the first group of candidate offset positions according to the offset step; and determining the second group of candidate offset positions according to the predetermined instructions in the loop BB.

[0210] Exemplarily, the candidate offset position may also be determined based on a predetermined data dependency. For example, when instruction x is dependent on n instructions, when n is greater than a threshold, instruction x may be used as a candidate offset position. Alternatively, when instruction x is dependent on m instructions, when m is greater than a threshold, instruction x may be used as a candidate offset position. Similarly, the method may be combined with at least one of the above-mentioned heuristic algorithms and predetermined instructions to determine the candidate offset position.

[0211] Exemplarily, a neural network model may be used to obtain candidate offset positions. For example, the neural network model may be trained to predict candidate offset positions. After the training is completed, the neural network model may be used to output candidate offset positions according to the input triple BB. Similarly, the method may be combined with at least one of the above-mentioned heuristic algorithm, predetermined instruction, and predetermined data dependency to determine the candidate offset positions.

[0212] Step 222: Use a table scheduling algorithm to schedule the window instruction sequence in the candidate scheduling window to obtain a scheduling result corresponding to the candidate scheduling window.

[0213] Exemplarily, a table scheduling algorithm is used for the instruction sequence in the candidate scheduling window to obtain a table scheduling result after table scheduling.

[0214] For example, if loop BB includes 10 instructions, a candidate scheduling window may include the last 6 instructions of the first loop BB and the first 4 instructions of the second loop BB. After executing table scheduling, the table scheduling algorithm adjusts the order of the 10 instructions based on the data dependencies of each instruction to obtain the scheduled instruction sequence (scheduling result). The instruction sequence order after scheduling may be different from the instruction sequence order in the candidate scheduling window.

[0215] Step 223, calculating the execution time corresponding to the candidate scheduling window according to the scheduling result and the triple DAG.

[0216] The execution time of the instructions in the candidate scheduling window is equal to the sum of the maximum emission time and the maximum pause time. The maximum emission time is the time when the last instruction in the candidate scheduling window is finished after the table is scheduled. The maximum pause time is the maximum value of the pause times corresponding to each instruction in the candidate scheduling window.

[0217] Exemplarily, the maximum transmission time corresponding to the candidate scheduling window is calculated according to the scheduling result; the maximum pause time corresponding to the candidate scheduling window is calculated according to the scheduling result and the triple DAG; and the sum of the maximum transmission time and the maximum pause time is determined as the execution time corresponding to the candidate scheduling window.

[0218] Among them, the calculation method of the maximum emission time includes: initializing the current time to 0; repeatedly executing the following steps 1) to 3), traversing all instructions in the scheduling results, determining the emission time corresponding to each instruction, and adding one to the maximum emission time to determine the maximum emission time.

[0219] Step 1), obtain the ith instruction from the scheduling result port, where i is a positive integer; when the ith instruction is allowed to be issued at the current moment and there is no resource conflict between the ith instruction and the scheduled instructions, determine the current moment as the issuance moment of the ith instruction.

[0220] Exemplarily, when the i-th instruction is allowed to be emitted at the current moment, and the input data on which the i-th instruction depends has arrived (i.e., the delay time of the instruction on which the i-th instruction depends is satisfied at the current moment), and there is no resource conflict between the i-th instruction and the scheduled instructions, the current moment is determined to be the emission moment of the i-th instruction.

[0221] Step 2), when the i-th instruction is not allowed to be issued at the current moment, or when there is a resource conflict between the i-th instruction and the scheduled instruction, determine the current moment plus one.

[0222] Step 3), when i is not equal to n, let i be equal to i+1, and n is the number of all instructions.

[0223] The calculation method of the maximum pause time includes: initializing the maximum pause time to 0; and repeatedly executing the following steps 1> to 3> to traverse all instructions in the scheduling result.

[0224] Step 1>, get the i-th instruction from the scheduling result, where i is a positive integer.

[0225] Step 2>, when the i-th instruction corresponds to a pause time and the pause time is greater than the maximum pause time, the pause time is determined as the new maximum pause time.

[0226] If the i-th instruction has no pause time, continue to execute step 3>. Alternatively, if the i-th instruction has a pause time but the pause time is not greater than the maximum pause time, continue to execute step 3>.

[0227] Step 3>, when i is not equal to n, let i be equal to i+1, and n is the number of all instructions.

[0228] Among them, the pause time is calculated based on the data dependency corresponding to the i-th instruction in the triple DAG.

[0229] Exemplarily, assuming that the ith instruction has a data dependency relationship with the xth instruction, and x is a positive integer, the calculation method of the pause time of the ith instruction is: calculate the sum of the emission time of the ith instruction and the delay time to obtain a first value; the delay time is the delay time required for the data output by the ith instruction to be input to the xth instruction; calculate the difference between the first value and the maximum emission time to obtain a second value; calculate the difference between the second value and the emission time of the xth instruction to obtain the pause time corresponding to the ith instruction.

[0230] That is, the pause time = the emission time of the i-th instruction + the delay time for the output data of the i-th instruction to reach the x-th instruction - the time when all instructions in the candidate scheduling window are executed (maximum emission time) - the emission time of the x-th instruction.

[0231] Exemplarily, an example of determining instruction dependencies based on a triple DAG is given. Assume that loop BB includes instruction 1 and instruction 2, and triple BB includes: first instruction 1, first instruction 2, second instruction 1, second instruction 2, third instruction 1, and third instruction 2 obtained by copying loop BB; it is indicated in the triple DAG that: second instruction 1 depends on first instruction 2, and third instruction 1 depends on second instruction 2; the candidate scheduling window includes second instruction 1 and second instruction 2. Then, when the i-th instruction is second instruction 2, according to the indication in the triple DAG that third instruction 1 depends on second instruction 2, it is determined that second instruction 2 has a data dependency relationship with second instruction 1.

[0232] Step 224: When the execution time is less than the stored value, the candidate scheduling window is determined as the target scheduling window, and the execution time is determined as the new stored value.

[0233] Exemplarily, the initial value of the stored value can be set to a maximum value, such as 999. The stored value is the minimum value of the execution time in the currently calculated candidate scheduling window. If the execution time of the currently calculated candidate scheduling window is not less than the stored value, it means that the current candidate scheduling window is not the scheduling window with the shortest execution time, and the execution time of the next candidate scheduling window will continue to be calculated.

[0234] Exemplarily, determine whether all candidate offset positions have been traversed. If not, select a candidate offset position from the untraversed candidate offset positions to continue executing step 221. If the traversal is complete, end and obtain the target scheduling window and the execution time corresponding to the target scheduling window.

[0235] In summary, the method provided by the embodiment of the present application provides a soft pipeline algorithm to compile the loop BB in the AI ​​model. The loop BB is divided into two parts, front and back, using the window scheduling algorithm, so that the front part of the next loop and the back part of the current loop are executed synchronously, saving the instruction execution time. In order to find the best split position and minimize the execution time, the loop BB is copied three times to obtain a triple BB and a triple DAG, and multiple scheduling windows are tried on the triple BB. The back part of the instructions in the first loop BB and the front part of the instructions in the second loop BB are selected by the scheduling window frame. And according to the data dependency relationship of each instruction indicated in the triple DAG, the execution time required for the two parts of the instructions in each scheduling window to be executed synchronously is calculated. Then, the scheduling window with the shortest execution time is selected from multiple scheduling windows as the final target scheduling window, and the split position corresponding to the target scheduling window is the best split position. Compiling the loop BB according to the scheduling result from the target scheduling window can improve the compilation efficiency of the loop BB, so that the target code execution time of the target program obtained after compilation is the shortest.

[0236] Fig.25 A structural block diagram of a compiling device provided by an exemplary embodiment of the present application is shown, the device comprising:

[0237] A loop module 301 is used for loop-unrolling an instruction sequence in a loop basic block BB to generate a triple BB and a triple directed acyclic graph DAG corresponding to the triple BB; the triple BB includes the instruction sequence looped three times; the triple DAG is used to indicate the data dependency relationship between the instructions in the triple BB;

[0238] The scheduling module 302 is used to perform window scheduling based on the triple BB and determine a target scheduling window; the window scheduling is used to divide the instruction sequence in the loop BB into two parts according to the scheduling window, so that the second part of the instruction sequence in the current loop is executed synchronously with the first part of the instruction sequence in the next loop; the target scheduling window is a scheduling window whose execution time meets the time condition, and the execution time is the time required for executing instructions in the window calculated according to the data dependency relationship in the triple DAG;

[0239] The compiling module 303 is used to compile and obtain the target code of the loop BB in the target program according to the scheduling result corresponding to the target scheduling window.

[0240] In an optional embodiment, the scheduling module 302 is used to repeatedly perform the following steps to traverse all candidate offset positions:

[0241] A candidate scheduling window corresponding to a candidate offset position is obtained; the candidate scheduling window selects a window instruction sequence in the triple BB, the window instruction sequence includes the second part of the instruction sequence in the first cycle and the first part of the instruction sequence in the second cycle in the triple BB; the second part of the instruction sequence and the first part of the instruction sequence are sequentially connected in the triple BB;

[0242] Using a table scheduling algorithm to schedule the window instruction sequence in the candidate scheduling window, to obtain a scheduling result corresponding to the candidate scheduling window;

[0243] Calculate the execution time corresponding to the candidate scheduling window according to the scheduling result and the triple DAG;

[0244] When the execution time is less than the stored value, the candidate scheduling window is determined as the target scheduling window, and the execution time is determined as a new stored value.

[0245] In an optional embodiment, the scheduling module 302 is used to calculate the maximum transmission time corresponding to the candidate scheduling window according to the scheduling result;

[0246] The scheduling module 302 is used to calculate the maximum pause time corresponding to the candidate scheduling window according to the scheduling result and the triple DAG;

[0247] The scheduling module 302 is used to determine the sum of the maximum transmission time and the maximum pause time as the execution time corresponding to the candidate scheduling window.

[0248] In an optional embodiment, the scheduling module 302 is used to initialize the current time to 0;

[0249] The scheduling module 302 is used to repeatedly execute the following steps to traverse all instructions in the scheduling result, determine the emission time corresponding to each instruction, and add one to the maximum emission time to determine the maximum emission time:

[0250] Obtain the i-th instruction from the scheduling result port, where i is a positive integer;

[0251] When the i-th instruction is allowed to be issued at the current moment and there is no resource conflict between the i-th instruction and the scheduled instructions, determining the current moment as the issuing moment of the i-th instruction;

[0252] In the case that the i-th instruction is not allowed to be issued at the current time, or there is a resource conflict between the i-th instruction and a scheduled instruction, determining that the current time is incremented by one;

[0253] When i is not equal to n, let i be equal to i+1, and n is the number of all instructions.

[0254] In an optional embodiment, the scheduling module 302 is used to initialize the maximum pause time to 0;

[0255] The scheduling module 302 is used to repeatedly execute the following steps to traverse all instructions in the scheduling result:

[0256] Obtaining the i-th instruction from the scheduling result, where i is a positive integer;

[0257] When the i-th instruction corresponds to a pause time and the pause time is greater than the maximum pause time, the pause time is determined as the new maximum pause time;

[0258] When i is not equal to n, let i be equal to i+1, and n be the number of all instructions;

[0259] The pause time is calculated according to the data dependency relationship corresponding to the i-th instruction in the triple DAG.

[0260] In an optional embodiment, the i-th instruction has a data dependency relationship with the x-th instruction, and x is a positive integer;

[0261] The scheduling module 302 is used to calculate the sum of the emission time of the i-th instruction and the delay time to obtain a first value; the delay time is the delay time required for the data output by the i-th instruction to be input to the x-th instruction;

[0262] The scheduling module 302 is used to calculate the difference between the first value and the maximum transmission time to obtain a second value;

[0263] The scheduling module 302 is used to calculate the difference between the second value and the issuance time of the x-th instruction to obtain the pause time corresponding to the ith instruction.

[0264] In an optional embodiment, the loop BB includes instruction 1 and instruction 2, and the triple BB includes: first instruction 1, first instruction 2, second instruction 1, second instruction 2, third instruction 1, and third instruction 2 obtained by copying the loop BB; it is indicated in the triple DAG that: the second instruction 1 depends on the first instruction 2, and the third instruction 1 depends on the second instruction 2; the candidate scheduling window includes the second instruction 1 and the second instruction 2;

[0265] The scheduling module 302 is used to determine that the second instruction two has the data dependency relationship with the second instruction one according to the third instruction one indicated in the triple DAG being dependent on the second instruction two when the i-th instruction is the second instruction two.

[0266] In an optional embodiment, the scheduling module 302 is used to determine the offset step size of the scheduling window according to the total number of instructions in the loop BB;

[0267] The scheduling module 302 is configured to determine the candidate offset position according to the offset step size.

[0268] In an optional embodiment, the scheduling module 302 is used to determine the offset step size as the first step size when the total number of instructions is less than or equal to the first value;

[0269] The scheduling module 302 is configured to determine that the offset step is a second step when the total number of instructions is greater than the first value and less than or equal to a second value;

[0270] The scheduling module 302 is configured to determine that the offset step is a third step when the total number of instructions is greater than the second value and less than or equal to a third value;

[0271] The scheduling module 302 is configured to determine that the offset step is a fourth step when the total number of instructions is greater than the third value and less than or equal to a fourth value;

[0272] The scheduling module 302 is configured to determine that the offset step is a fifth step when the total number of instructions is greater than the fourth value;

[0273] Among them, the first value, the second value, the third value and the fourth value are in an arithmetic progression; the first step length, the second step length, the third step length, the fourth step length and the fifth step length increase in sequence.

[0274] Fig.26The block diagram of the structure of a computer device 2100 provided by an exemplary embodiment of the present application is shown. The computer device 2100 may be a portable mobile terminal, such as a smart phone, a tablet computer, an MP3 player (Moving Picture Experts Group Audio Layer III), an MP4 player (Moving Picture Experts Group Audio Layer IV), a laptop computer or a desktop computer. The computer device 2100 may also be called a user device, a portable terminal, a laptop terminal, a desktop terminal or other names.

[0275] Typically, the computer device 2100 includes a processor 2101 and a memory 2102 .

[0276] The processor 2101 may include one or more processing cores, such as a 4-core processor, an 8-core processor, etc. The processor 2101 may be implemented in at least one hardware form of DSP (Digital Signal Processing), FPGA (Field-Programmable Gate Array), and PLA (Programmable Logic Array). The processor 2101 may also include a main processor and a coprocessor. The main processor is a processor for processing data in the awake state, also known as a CPU (Central Processing Unit); the coprocessor is a low-power processor for processing data in the standby state. In some embodiments, the processor 2101 may be integrated with a GPU (Graphics Processing Unit, video encoder), and the GPU is responsible for rendering and drawing the content to be displayed on the display screen. In some embodiments, the processor 2101 may also include an AI (Artificial Intelligence) processor, which is used to process computing operations related to machine learning.

[0277] The memory 2102 may include one or more computer-readable storage media, which may be non-transitory. The memory 2102 may also include a high-speed random access memory, and a non-volatile memory, such as one or more disk storage devices, flash memory storage devices. In some embodiments, the non-transitory computer-readable storage medium in the memory 2102 is used to store at least one instruction, which is used to be executed by the processor 2101 to implement the compilation method provided in the method embodiment of the present application.

[0278] In some embodiments, the computer device 2100 may further optionally include: a peripheral device interface 2103 and at least one peripheral device. The processor 2101, the memory 2102 and the peripheral device interface 2103 may be connected via a bus or a signal line. Each peripheral device may be connected to the peripheral device interface 2103 via a bus, a signal line or a circuit board. For example, the peripheral device may include: at least one of a radio frequency circuit 2104, a display screen 2105, a camera assembly 2106, an audio circuit 2107 and a power supply 2108.

[0279] The peripheral device interface 2103 may be used to connect at least one peripheral device related to I / O (Input / Output) to the processor 2101 and the memory 2102. In some embodiments, the processor 2101, the memory 2102, and the peripheral device interface 2103 are integrated on the same chip or circuit board; in some other embodiments, any one or two of the processor 2101, the memory 2102, and the peripheral device interface 2103 may be implemented on a separate chip or circuit board, which is not limited in this embodiment.

[0280] The radio frequency circuit 2104 is used to receive and transmit RF (Radio Frequency) signals, also known as electromagnetic signals. The radio frequency circuit 2104 communicates with the communication network and other communication devices through electromagnetic signals. The radio frequency circuit 2104 converts the electrical signal into an electromagnetic signal for transmission, or converts the received electromagnetic signal into an electrical signal. Optionally, the radio frequency circuit 2104 includes: an antenna system, an RF transceiver, one or more amplifiers, a tuner, an oscillator, a digital signal processor, a codec chipset, a user identity module card, etc. The radio frequency circuit 2104 can communicate with other terminals through at least one wireless communication protocol. The wireless communication protocol includes but is not limited to: the World Wide Web, a metropolitan area network, an intranet, various generations of mobile communication networks (2G, 3G, 4G and 5G), a wireless local area network and / or a WiFi (Wireless Fidelity) network. In some embodiments, the radio frequency circuit 2104 may also include circuits related to NFC (Near Field Communication), which is not limited in this application.

[0281] The display screen 2105 is used to display a UI (User Interface). The UI may include graphics, text, icons, videos, and any combination thereof. When the display screen 2105 is a touch display screen, the display screen 2105 also has the ability to collect touch signals on the surface or above the surface of the display screen 2105. The touch signal can be input to the processor 2101 as a control signal for processing. At this time, the display screen 2105 can also be used to provide virtual buttons and / or virtual keyboards, also known as soft buttons and / or soft keyboards. In some embodiments, the display screen 2105 can be one, arranged on the front panel of the computer device 2100; in other embodiments, the display screen 2105 can be at least two, respectively arranged on different surfaces of the computer device 2100 or in a folding design; in other embodiments, the display screen 2105 can be a flexible display screen, arranged on a curved surface or a folding surface of the computer device 2100. Even, the display screen 2105 can also be arranged as a non-rectangular irregular figure, that is, a special-shaped screen. The display screen 2105 can be made of materials such as LCD (Liquid Crystal Display) and OLED (Organic Light-Emitting Diode).

[0282] The camera assembly 2106 is used to capture images or videos. Optionally, the camera assembly 2106 includes a front camera and a rear camera. Typically, the front camera is arranged on the front panel of the terminal, and the rear camera is arranged on the back of the terminal. In some embodiments, there are at least two rear cameras, which are any one of a main camera, a depth of field camera, a wide-angle camera, and a telephoto camera, so as to realize the fusion of the main camera and the depth of field camera to realize the background blur function, the fusion of the main camera and the wide-angle camera to realize panoramic shooting and VR (Virtual Reality) shooting function or other fusion shooting functions. In some embodiments, the camera assembly 2106 may also include a flash. The flash can be a monochrome temperature flash or a dual-color temperature flash. A dual-color temperature flash refers to a combination of a warm light flash and a cold light flash, which can be used for light compensation at different color temperatures.

[0283] The audio circuit 2107 may include a microphone and a speaker. The microphone is used to collect sound waves from the user and the environment, and convert the sound waves into electrical signals and input them into the processor 2101 for processing, or input them into the radio frequency circuit 2104 to achieve voice communication. For the purpose of stereo acquisition or noise reduction, there may be multiple microphones, which are respectively arranged at different parts of the computer device 2100. The microphone may also be an array microphone or an omnidirectional acquisition microphone. The speaker is used to convert the electrical signal from the processor 2101 or the radio frequency circuit 2104 into sound waves. The speaker may be a traditional film speaker or a piezoelectric ceramic speaker. When the speaker is a piezoelectric ceramic speaker, it can not only convert the electrical signal into sound waves audible to humans, but also convert the electrical signal into sound waves inaudible to humans for purposes such as ranging. In some embodiments, the audio circuit 2107 may also include a headphone jack.

[0284] The power supply 2108 is used to power various components in the computer device 2100. The power supply 2108 can be an alternating current, a direct current, a disposable battery, or a rechargeable battery. When the power supply 2108 includes a rechargeable battery, the rechargeable battery can be a wired rechargeable battery or a wireless rechargeable battery. A wired rechargeable battery is a battery that is charged through a wired line, and a wireless rechargeable battery is a battery that is charged through a wireless coil. The rechargeable battery can also be used to support fast charging technology.

[0285] In some embodiments, the computer device 2100 further includes one or more sensors 2109 , including but not limited to: an acceleration sensor 2110 , a gyroscope sensor 2111 , a pressure sensor 2112 , an optical sensor 2113 , and a proximity sensor 2114 .

[0286] The acceleration sensor 2110 can detect the magnitude of acceleration on the three coordinate axes of the coordinate system established by the computer device 2100. For example, the acceleration sensor 2110 can be used to detect the components of gravity acceleration on the three coordinate axes. The processor 2101 can control the display screen 2105 to display the user interface in a horizontal view or a vertical view according to the gravity acceleration signal collected by the acceleration sensor 2110. The acceleration sensor 2110 can also be used to collect motion data of games or users.

[0287] The gyro sensor 2111 can detect the body direction and rotation angle of the computer device 2100, and the gyro sensor 2111 can cooperate with the acceleration sensor 2110 to collect the user's 3D actions on the computer device 2100. The processor 2101 can implement the following functions based on the data collected by the gyro sensor 2111: motion sensing (such as changing the UI according to the user's tilt operation), image stabilization during shooting, game control, and inertial navigation.

[0288] The pressure sensor 2112 can be set on the side frame of the computer device 2100 and / or the lower layer of the display screen 2105. When the pressure sensor 2112 is set on the side frame of the computer device 2100, it can detect the user's grip signal of the computer device 2100, and the processor 2101 performs left and right hand recognition or shortcut operations according to the grip signal collected by the pressure sensor 2112. When the pressure sensor 2112 is set on the lower layer of the display screen 2105, the processor 2101 controls the operability controls on the UI interface according to the user's pressure operation on the display screen 2105. The operability controls include at least one of a button control, a scroll bar control, an icon control, and a menu control.

[0289] The optical sensor 2113 is used to collect the ambient light intensity. In one embodiment, the processor 2101 can control the display brightness of the display screen 2105 according to the ambient light intensity collected by the optical sensor 2113. For example, when the ambient light intensity is high, the display brightness of the display screen 2105 is increased; when the ambient light intensity is low, the display brightness of the display screen 2105 is reduced. In another embodiment, the processor 2101 can also dynamically adjust the shooting parameters of the camera assembly 2106 according to the ambient light intensity collected by the optical sensor 2113.

[0290] The proximity sensor 2114, also called a distance sensor, is usually disposed on the front panel of the computer device 2100. The proximity sensor 2114 is used to collect the distance between the user and the front of the computer device 2100. In one embodiment, when the proximity sensor 2114 detects that the distance between the user and the front of the computer device 2100 is gradually decreasing, the processor 2101 controls the display screen 2105 to switch from the screen-on state to the screen-off state; when the proximity sensor 2114 detects that the distance between the user and the front of the computer device 2100 is gradually increasing, the processor 2101 controls the display screen 2105 to switch from the screen-off state to the screen-on state.

[0291] Those skilled in the art will understand that Fig.26 The structure shown in the figure does not constitute a limitation on the computer device 2100, and the computer device 2100 may include more or fewer components than shown in the figure, or combine some components, or adopt a different component arrangement.

[0292] The present application also provides a computer-readable storage medium, in which at least one instruction, at least one program, code set or instruction set is stored, and the at least one instruction, at least one program, code set or instruction set is loaded and executed by a processor to implement the compilation method provided by the above method embodiment. The present application provides a computer program product or a computer program, which includes a computer instruction, and the computer instruction is stored in a computer-readable storage medium. The processor of a computer device reads the computer instruction from the computer-readable storage medium, and the processor executes the computer instruction, so that the computer device executes the compilation method provided by the above method embodiment.

[0293] The serial numbers of the above-mentioned embodiments of the present application are for description only and do not represent the advantages or disadvantages of the embodiments.

[0294] A person skilled in the art will understand that all or part of the steps to implement the above embodiments may be accomplished by hardware or by instructing related hardware through a program, and the program may be stored in a computer-readable storage medium, and the above-mentioned storage medium may be a read-only memory, a disk or an optical disk, etc.

[0295] The above description is only an optional embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. A compilation method, It is characterized in that The method comprises: Loop unrolling an instruction sequence in a loop basic block BB to generate a triple BB and a triple directed acyclic graph DAG corresponding to the triple BB; the triple BB includes the instruction sequence looped three times; the triple DAG is used to indicate the data dependency relationship between the instructions in the triple BB; Window scheduling is performed based on the triple BB to determine a target scheduling window; the window scheduling is used to divide the instruction sequence in the loop BB into two parts according to the scheduling window, so that the second part of the instruction sequence in the current loop is executed synchronously with the first part of the instruction sequence in the next loop; the target scheduling window is a scheduling window whose execution time meets the time condition, and the execution time is the time required for executing instructions in the window calculated according to the data dependency relationship in the triple DAG; According to the scheduling result corresponding to the target scheduling window, the target code of the loop BB in the target program is compiled.

2. The method according to claim 1, It is characterized in that The performing window scheduling based on the triple BB and determining the target scheduling window includes: Repeat the following steps to traverse all candidate offset positions: A candidate scheduling window corresponding to a candidate offset position is obtained; the candidate scheduling window selects a window instruction sequence in the triple BB, the window instruction sequence includes the second part of the instruction sequence in the first cycle and the first part of the instruction sequence in the second cycle in the triple BB; the second part of the instruction sequence and the first part of the instruction sequence are sequentially connected in the triple BB; Using a table scheduling algorithm to schedule the window instruction sequence in the candidate scheduling window, to obtain a scheduling result corresponding to the candidate scheduling window; Calculate the execution time corresponding to the candidate scheduling window according to the scheduling result and the triple DAG; When the execution time is less than the stored value, the candidate scheduling window is determined as the target scheduling window, and the execution time is determined as a new stored value.

3. The method according to claim 2, It is characterized in that The calculating the execution time corresponding to the candidate scheduling window according to the scheduling result and the triple DAG includes: Calculate the maximum transmission time corresponding to the candidate scheduling window according to the scheduling result; Calculate the maximum pause time corresponding to the candidate scheduling window according to the scheduling result and the triple DAG; The sum of the maximum transmission time and the maximum pause time is determined as the execution time corresponding to the candidate scheduling window.

4. The method according to claim 3, It is characterized in that The calculating the maximum transmission time corresponding to the candidate scheduling window according to the scheduling result includes: Initialize the current time to 0; Repeat the following steps to traverse all instructions in the scheduling result, determine the emission time corresponding to each instruction, and add one to the maximum emission time to determine the maximum emission time: Obtain the i-th instruction from the scheduling result port, where i is a positive integer; When the i-th instruction is allowed to be issued at the current moment and there is no resource conflict between the i-th instruction and the scheduled instructions, determining the current moment as the issuing moment of the i-th instruction; In the case that the i-th instruction is not allowed to be issued at the current time, or there is a resource conflict between the i-th instruction and a scheduled instruction, determining that the current time is incremented by one; When i is not equal to n, let i be equal to i+1, and n is the number of all instructions.

5. The method according to claim 3, It is characterized in that The calculating the maximum pause time corresponding to the candidate scheduling window according to the scheduling result and the triple DAG includes: Initialize the maximum pause time to 0; Repeat the following steps to traverse all instructions in the scheduling result: Obtaining the i-th instruction from the scheduling result, where i is a positive integer; When the i-th instruction corresponds to a pause time and the pause time is greater than the maximum pause time, the pause time is determined as the new maximum pause time; When i is not equal to n, let i be equal to i+1, and n be the number of all instructions; The pause time is calculated according to the data dependency relationship corresponding to the i-th instruction in the triple DAG.

6. The method according to claim 5, It is characterized in that The i-th instruction has a data dependency relationship with the x-th instruction, where x is a positive integer; the method further includes: Calculating the sum of the emission time of the ith instruction and the delay time to obtain a first value; the delay time is the delay time required for the data output by the ith instruction to be input to the xth instruction; Calculating the difference between the first value and the maximum emission time to obtain a second value; The difference between the second value and the issuance time of the x-th instruction is calculated to obtain the pause time corresponding to the ith instruction.

7. The method according to claim 6, It is characterized in that The loop BB includes instruction 1 and instruction 2, and the triple BB includes: first instruction 1, first instruction 2, second instruction 1, second instruction 2, third instruction 1 and third instruction 2 obtained by copying the loop BB; in the triple DAG, it is indicated that: the second instruction 1 depends on the first instruction 2, and the third instruction 1 depends on the second instruction 2; the candidate scheduling window includes the second instruction 1 and the second instruction 2; The method further comprises: In the case where the i-th instruction is the second instruction two, according to the third instruction one indicated in the triple DAG as being dependent on the second instruction two, it is determined that the second instruction two has the data dependency relationship with the second instruction one.

8. The method according to any one of claims 2 to 7, It is characterized in that The method further comprises: Determining the offset step size of the scheduling window according to the total number of instructions in the loop BB; The candidate offset position is determined according to the offset step size.

9. The method according to claim 8, It is characterized in that Determining the offset step of the scheduling window according to the total number of instructions in the loop BB includes: When the total number of instructions is less than or equal to the first value, determining the offset step size to be the first step size; When the total number of instructions is greater than the first value and less than or equal to the second value, determining the offset step length to be the second step length; When the total number of instructions is greater than the second value and less than or equal to a third value, determining the offset step length to be a third step length; When the total number of instructions is greater than the third value and less than or equal to a fourth value, determining the offset step length to be a fourth step length; When the total number of instructions is greater than the fourth value, determining the offset step length to be a fifth step length; Among them, the first value, the second value, the third value and the fourth value are in an arithmetic progression; the first step length, the second step length, the third step length, the fourth step length and the fifth step length increase in sequence.

10. A compiling device, It is characterized in that The device comprises: A loop module, used for loop-unrolling an instruction sequence in a loop basic block BB, generating a triple BB and a triple directed acyclic graph DAG corresponding to the triple BB; the triple BB includes the instruction sequence looped three times; the triple DAG is used to indicate the data dependency relationship between the instructions in the triple BB; A scheduling module is used to perform window scheduling based on the triple BB and determine a target scheduling window; the window scheduling is used to divide the instruction sequence in the loop BB into two parts according to the scheduling window, so that the second part of the instruction sequence in the current loop is executed synchronously with the first part of the instruction sequence in the next loop; the target scheduling window is a scheduling window whose execution time meets the time condition, and the execution time is the time required for the execution of instructions in the window calculated according to the data dependency relationship in the triple DAG; The compiling module is used to compile and obtain the target code of the loop BB in the target program according to the scheduling result corresponding to the target scheduling window.

11. The device according to claim 10, It is characterized in that The scheduling module is used to repeatedly perform the following steps to traverse all candidate offset positions: A candidate scheduling window corresponding to a candidate offset position is obtained; the candidate scheduling window selects a window instruction sequence in the triple BB, the window instruction sequence includes the second part of the instruction sequence in the first cycle and the first part of the instruction sequence in the second cycle in the triple BB; the second part of the instruction sequence and the first part of the instruction sequence are sequentially connected in the triple BB; Using a table scheduling algorithm to schedule the window instruction sequence in the candidate scheduling window, to obtain a scheduling result corresponding to the candidate scheduling window; Calculate the execution time corresponding to the candidate scheduling window according to the scheduling result and the triple DAG; When the execution time is less than the stored value, the candidate scheduling window is determined as the target scheduling window, and the execution time is determined as a new stored value.

12. The device according to claim 11, It is characterized in that The scheduling module is used to calculate the maximum transmission time corresponding to the candidate scheduling window according to the scheduling result; The scheduling module is used to calculate the maximum pause time corresponding to the candidate scheduling window according to the scheduling result and the triple DAG; The scheduling module is used to determine the sum of the maximum transmission time and the maximum pause time as the execution time corresponding to the candidate scheduling window.

13. A computer device, It is characterized in that The computer device comprises: a processor and a memory, wherein the memory stores a computer program, and the computer program is loaded and executed by the processor to implement the compiling method according to any one of claims 1 to 9.

14. A computer-readable storage medium, It is characterized in that The computer-readable storage medium stores a computer program, and the computer program is loaded and executed by a processor to implement the compilation method according to any one of claims 1 to 9.

15. A computer program product, It is characterized in that The computer program product stores a computer program, and the computer program is loaded and executed by a processor to implement the compilation method according to any one of claims 1 to 9.

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