Device and method for testing performance of high-speed interface chip in mass production

Abstract

The invention provides a device and a method for mass production testing of high-speed interface chip performance, and belongs to the technical field of chip mass production testing. The system comprises a test machine and a test board, an attenuation loopback link is designed on the test board, the attenuation loopback link has a predetermined attenuation value, the test machine provides a test function and test resources, a chip is fixed on the test board through a socket, and the test board is connected with the test machine. An uplink and a downlink output by the chip are respectively connected with the attenuation loopback link through a multi-path sending end and a receiving end, and the test machine is connected with the test board through a JTAG (Joint Test Action Group) interface. Meanwhile, the SERDES performance of the chip is comprehensively tested through a series of operation processes including power-on, configuration, correct code stream test, error injection test and result judgment, so that the quality and the performance of the chip are ensured to meet the requirements.

Description

Technical Field

[0001] The invention belongs to the technical field of chip mass production testing, and in particular relates to a device and method for mass production testing of high-speed interface chip performance. Background Art

[0002] With the rapid development of computer hardware technology, the requirements for data transmission speed and stability are increasing. PCIE (Peripheral Component Interconnect Express), as a high-performance serial communication bus, is widely used in various computer devices. In order to ensure that PCIE chips are stable and have superior performance in actual applications, it is particularly important to conduct mass production tests to measure their physical layer (PHY) performance.

[0003] For the serializer-deserializer (SerDes) interface chip, in the ATE (Automated Test Equipment) test, the chip peripheral link design has a small attenuation, and the shortest loss test is usually used. This can screen out chips with normal functions, but it cannot directly screen out chips with high performance. Usually, in the system-level test, a small number of chips are selected and tested according to the loss specified in the protocol. If the test passes, it means that the chip supports the performance index, but the sample size of the laboratory test is small, so this method of judgment will have certain risks. At the same time, the performance index of the chip is related to the wafer process, process parameters, time, machine, etc. Most complex chips will use a double screening of mass production test (FT) plus system-level test (SLT). Double screening is time-consuming and inefficient, and it will also increase the test cost. For example, for the interface chip of PCIE5.0, the use of FT and SLT double screening will greatly increase the cost, and mass production is not realistic.

[0004] Therefore, in the mass production test of high-speed interface chips, it is of great significance to solve how to screen out high-performance chips at low cost. Summary of the invention

[0005] The purpose of the present invention is to provide a device and method for mass production testing of high-speed interface chip performance, so as to solve the technical problem of selecting high-performance chips at low cost for high-speed interface chips proposed in the above background technology.

[0006] To achieve the above object, the present invention provides the following technical solutions: A device for mass production testing of high-speed interface chip performance comprises a test machine and a test board. The test board is designed with an attenuation loopback link, the attenuation loopback link has a predetermined attenuation value, the test machine provides test functions and test resources, the chip is fixed to the test board via a socket, the uplink and downlink outputs of the chip are respectively connected to the attenuation loopback link via a multi-channel sending end and a receiving end, and the test machine is connected to the test board via a JTAG interface.

[0007] Furthermore, the attenuated loopback link is wound on a PCB board, and the loss is confirmed through simulation to formulate a predetermined attenuation value.

[0008] Furthermore, the attenuation value is adjusted according to the chip being tested.

[0009] Furthermore, the attenuation loopback link adopts a capacitive loopback.

[0010] Another object of the present invention is to provide a method for mass production testing of high-speed interface chip performance, based on the above device, comprising the following steps: S1: Design ATE test board; S2: placing the test board on the test machine, and fixing the chip to the test board through a socket; S3: Power on the chip using the test machine; S4: The tester configures registers through the JTAG interface to enable the SERDES of the chip to work, communicates with the chip through the JTAG interface, and sets the working mode and parameters of the chip; S5: The transmitter (TX) of the chip continuously sends a pseudo-random binary sequence pattern as a test signal; S6: The code stream is transmitted from the transmitting end to the receiving end (RX) through the capacitor component in the attenuation loopback link, simulating the signal transmission path in actual applications; S7: After receiving the code stream, the receiver (RX) compares it with the original code stream of the transmitter. If a difference is found, it is considered that a code error has occurred and the code error is recorded in the corresponding register. S8: The tester reads the bit error register. If there is a bit error, the chip is marked as fail and the test ends. If there is no bit error, subsequent tests can continue.

[0011] Preferably, in step S5, the pseudo-random binary sequence pattern adopts PRBS31.

[0012] Further, the subsequent test comprises the following steps: S9: The tester intentionally introduces at least one error in the pseudo-random binary sequence code stream sent by modifying the configuration of the register; S10: The bit stream with errors is transmitted to the receiving end (RX) again through the attenuated loopback link; S11: The receiving end (RX) compares the bit stream after the injection error. According to the injection error situation, if the number of bit errors actually detected does not match the expected number, it indicates that there is a problem with the chip; S12: The tester reads the value of the error counting register and determines whether the chip passes the test based on a preset standard.

[0013] Preferably, in step S9, an error is introduced.

[0014] Furthermore, the above method is performed in low temperature and high temperature environments respectively.

[0015] The present invention has the following beneficial effects: 1. Save costs.

[0016] 2. Save time and quickly mass-produce high-performance chips.

[0017] The present invention increases peripheral configuration in an ATE FT screen, designs a simulated loopback link on a PCB board, formulates a predetermined attenuation value through design simulation, simulates a high-performance link, screens out chips that do not meet the performance requirements through mass production testing, and tests out chips with excellent performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for describing the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative work.

[0019] Figure 1 This is the principle block diagram of the test device; Figure 2 This is a schematic diagram of the 35dB attenuation loopback link structure; Figure 3 The figure is a schematic diagram of the test process. DETAILED DESCRIPTION

[0020] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0021] See also Figure 1-2As shown, a device for mass production testing of high-speed interface chip performance includes a tester and a test board. The tester provides test functions and test resources, including high-precision power supply, accurate clock signal, complex test algorithm, data analysis capability and graphical display, etc. The tester can perform comprehensive functional test, performance test and reliability test on the chip by connecting with the test board. The test board is designed with a specific circuit layout and interface as an intermediate carrier connecting the chip and the tester, which can match the pins of the chip to ensure the correct transmission and reception of the signal. Figure 1 This is the principle block diagram of the test device.

[0022] Figure 1 In the chip, a PRBS generator and a PRBS detector are built in. The PRBS generator is used to generate a pseudo-random binary sequence signal. As the source of test data, the PRBS signal has a certain randomness and regularity, which can simulate the actual data transmission situation and is used to comprehensively test the performance of the SERDES chip in different data modes. The signal generated by the PRBS generator is transmitted to the SERDES chip for serialization processing so as to perform performance evaluation in the subsequent transmission process. The PRBS detector is used to detect the signal after the attenuated loopback link and the SERDES chip deserialization processing, and compare it with the original PRBS signal sent to determine whether the signal has an error during the transmission process. By detecting parameters such as the bit error rate, the performance of the SERDES chip can be evaluated. In this embodiment, the PRBS generator adopts the PRBS31 code type. The calibration resistor is used to adjust the resistance value in the circuit to ensure the transmission quality and stability of the signal. During the test process, the calibration resistor can be adjusted according to actual needs to optimize the test results. The reference clock input provides a clock signal for the SERDES chip to ensure the normal operation of the chip and the synchronization of data transmission. The stability and accuracy of the clock are crucial to the test results. In this embodiment, the reference clock adopts 100MHz. The power supply and ground provide power supply and reference potential for the entire test device, respectively, to ensure the normal operation of each electronic component. The stability of the power supply and the goodness of the grounding have an important impact on the test results.

[0023] The test board is designed with an analog attenuation loopback link, which is wound on the PCB board, and the loss is confirmed by simulation to formulate a predetermined attenuation value. The attenuation value is adjusted according to the chip being tested. In this embodiment, the attenuation value is 35dB, and the attenuation loopback link adopts a capacitor loopback to connect the uplink and downlink outputs of the chip to the 16-way transmitting end (TX) and receiving end (RX) respectively. The capacitor can play a role in signal coupling in the circuit, allowing signals of a specific frequency to pass through while blocking DC signals and other unnecessary frequency components. In the loopback path, the capacitor can help achieve signal transmission and isolation, and avoid interference and noise between different channels. In addition, choosing a suitable capacitance value can help achieve impedance matching of the circuit, reduce signal reflection and distortion, and improve signal integrity.

[0024] Figure 2 The diagram is a schematic diagram of the 35dB attenuation loopback link structure. The attenuation loopback link can simulate the signal attenuation in the actual communication system and attenuate the signal after being processed by the SERDES chip by a predetermined attenuation value. In this way, the performance of the chip when the signal is weak and its adaptability to different degrees of attenuation can be tested. The loopback design sends the attenuated signal back to the receiving end to form a loopback path, which is convenient for self-testing and performance evaluation. This loopback design can quickly detect whether the basic functions of the chip are normal and its stability under different working conditions.

[0025] The test machine is connected to the test board via a JTAG (Joint Test Action Group) interface. The JTAG interface is an interface used for chip debugging and testing. By connecting to the test machine, programming, configuration and status monitoring of the SERDES chip can be achieved.

[0026] See also Figure 3 As shown, a method for mass production testing of high-speed interface chip performance, the process is as follows: 1. Preparation S1: Design ATE test board. According to the principle block diagram Figure 1-2 Design test boards to ensure components connect and work together correctly.

[0027] S2: Place the test board on the test machine, and fix the chip to the test board through a socket to ensure that the connection between the chip and the test board is stable and reliable so as to perform subsequent test operations.

[0028] 2. Power-on and configuration phase S3: Use the test machine to power on the chip and provide the chip with the required power supply so that it can work normally.

[0029] S4: The tester configures registers through the JTAG interface to enable the SERDES of the chip to work, communicates with the chip using the JTAG interface, sets the working mode and parameters of the chip, and ensures that the SERDES function is started normally.

[0030] 3. Normal bitstream transmission, detection and judgment stage S5: The transmitter (TX) of the chip continuously sends a pseudo-random binary sequence (PRBS31) pattern as a test signal.

[0031] S6: The bit stream is transmitted from the transmitter to the receiver (RX) through components such as capacitors in the 35dB attenuation loopback link, simulating the signal transmission path in actual applications.

[0032] S7: After receiving the code stream, the receiver (RX) compares it with the original code stream of the transmitter. If a difference is found, it is considered that a code error has occurred and the code error is recorded in the corresponding register.

[0033] S8: The tester reads the error register to determine whether an error has occurred under the current test state, which provides a basis for subsequent operations. If an error has occurred, it indicates that there is a problem with the chip and the chip is marked as fail; if there is no error, it means that the chip performs well under the current test conditions and subsequent tests can continue.

[0034] 4. Error Testing Phase S9: The tester intentionally introduces at least one error in the transmitted PRBS code stream by modifying the register configuration to test the chip's ability to detect and handle errors.

[0035] S10: The bit stream with errors is transmitted to the receiving end (RX) again through the loopback link.

[0036] S11: The receiving end (RX) compares the bit stream after the error injection to determine whether the error can be correctly detected.

[0037] 5. Result judgment stage According to the error annotation, the receiver should be expected to detect the same number of errors as the transmitter. If the number of errors detected is different from the expected number, it may indicate a problem with the chip.

[0038] S12: The tester reads the value of the error count register and determines whether the chip passes the test based on the pre-set standard. If the number of error bits is within the acceptable range, the chip is marked as pass; otherwise, the chip is marked as fail.

[0039] In summary, the above process conducts a comprehensive test on the SERDES performance of the chip through a series of operations, including power-on, configuration, correct bit stream test, injection error test and result judgment, to ensure that the quality and performance of the chip meet the requirements.

[0040] In actual testing, the above process will be executed in low-temperature and high-temperature environments respectively, and finally chips that meet high-performance requirements at high and low temperatures will be selected.

[0041] The preferred embodiments of the present invention disclosed above are only used to help explain the present invention. The preferred embodiments do not describe all the details in detail, nor do they limit the invention to the specific implementation methods described. Obviously, many modifications and changes can be made according to the content of this specification. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can understand and use the present invention well.

Claims

1. A device for mass production testing of high-speed interface chip performance, comprising a test machine and a test board, characterized in that: The test board is designed with an attenuation loopback link, which has a predetermined attenuation value. The test machine provides test functions and test resources. The chip is fixed to the test board through a socket. The uplink and downlink outputs of the chip are respectively connected to the attenuation loopback link through a multi-channel transmitting end and a receiving end. The test machine is connected to the test board through a JTAG interface.

2. The device for mass production testing of high-speed interface chip performance according to claim 1, characterized in that: The attenuation loopback link is wound on a PCB board, and the loss is confirmed through simulation to formulate a predetermined attenuation value.

3. The device for mass production testing of high-speed interface chip performance according to claim 1, characterized in that: The attenuation value is adjusted according to the chip being tested.

4. The device for mass production testing of high-speed interface chip performance according to claim 1, characterized in that: The attenuated loopback link adopts a capacitive loopback.

5. A method for mass production testing of high-speed interface chip performance, based on the device according to any one of claims 1 to 4, characterized in that: The following steps are involved: S1: Design ATE test board; S2: placing the test board on the test machine, and fixing the chip to the test board through a socket; S3: Power on the chip using the test machine; S4: The tester configures registers through the JTAG interface to enable the SERDES of the chip to work, communicates with the chip through the JTAG interface, and sets the working mode and parameters of the chip; S5: The transmitter of the chip continuously sends a pseudo-random binary sequence pattern as a test signal; S6: The code stream is transmitted from the transmitting end to the receiving end through the capacitor component in the attenuation loopback link, simulating the signal transmission path in actual applications; S7: After receiving the code stream, the receiving end compares it with the original code stream of the sending end; if a difference is found, it is considered that a code error has occurred and the code error is recorded in the corresponding register; S8: The tester reads the bit error register. If there is a bit error, the chip is marked as fail and the test ends. If there is no bit error, subsequent tests can continue.

6. A method for mass production testing of high-speed interface chip performance according to claim 5, characterized in that: Step S5: the pseudo-random binary sequence pattern adopts PRBS31.

7. A method for mass production testing of high-speed interface chip performance according to claim 5 or 6, characterized in that: The subsequent testing includes the following steps: S9: The tester intentionally introduces at least one error in the pseudo-random binary sequence code stream sent by modifying the configuration of the register; S10: The bit stream with errors is transmitted to the receiving end again through the attenuated loopback link; S11: The receiving end compares the bit stream after the injection error. According to the injection error situation, if the number of bit errors actually detected does not match the expected number, it indicates that there is a problem with the chip; S12: The tester reads the value of the error counting register and determines whether the chip passes the test based on a preset standard.

8. The method for mass production testing of high-speed interface chip performance according to claim 7, characterized in that: Step S9, introducing an error.

9. The method for mass production testing of high-speed interface chip performance according to claim 7, characterized in that: The method steps are respectively performed under different temperature environments.

10. A method for mass production testing of high-speed interface chip performance according to any one of claims 5, 6 and 8, characterized in that: The method steps are respectively performed under different temperature environments.

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