Formation method of semiconductor structure

Abstract

A semiconductor structure forming method comprises the following steps: providing a substrate, and forming a structure to be deposited on the substrate; depositing a target layer on the to-be-deposited structure, wherein the material of the target layer contains an Si element, a C element and an N element; and performing thermal annealing treatment on the target layer, so that the material of the target layer is re-bonded to form a bonded structure, and the bonded structure comprises Si-C and Si-C-N. The thermal annealing treatment is performed on the target layer, so that the material of the target layer is re-bonded to form the bonding structure, the bonding structure comprises Si-C and Si-C-N, and the bonding polarity of the Si-C bonding structure is relatively small, so that the value of the relative dielectric constant of the target layer is reduced, and the parasitic capacitance is correspondingly reduced; and the C element is beneficial to improving the etching resistance of the target layer, and the N element is beneficial to improving the mechanical strength of the target layer, so that the relative dielectric constant of the target layer is reduced, and the etching resistance and the mechanical property of the target layer are improved.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular to a method for forming a semiconductor structure. Background Art

[0002] With the rapid growth of the semiconductor integrated circuit (IC) industry, semiconductor technology continues to move towards smaller process nodes driven by Moore's Law, making integrated circuits develop in the direction of smaller size, higher circuit precision and higher circuit complexity.

[0003] In the development of integrated circuits, the functional density (i.e. the number of internal connection structures of each chip) is gradually increasing, while the geometric size (i.e. the minimum component size that can be produced using process steps) is gradually decreasing, which correspondingly increases the difficulty and complexity of integrated circuit manufacturing.

[0004] At present, as technology nodes continue to shrink, how to reduce the parasitic capacitance of semiconductor devices and improve the performance of semiconductor structures has become a challenge. Summary of the invention

[0005] The problem solved by the embodiments of the present invention is to provide a method for forming a semiconductor structure to reduce the parasitic capacitance of the semiconductor device and improve the performance of the semiconductor structure.

[0006] To solve the above problems, an embodiment of the present invention also provides a method for forming a semiconductor structure, comprising: providing a substrate, on which a structure to be deposited is formed; depositing a target layer on the structure to be deposited, wherein the material of the target layer contains Si element, C element and N element; performing thermal annealing on the target layer so that the material of the target layer re-bonds to form a bonding structure, wherein the bonding structure includes a Si-C bonding structure and a Si-CN bonding structure.

[0007] Optionally, in the step of performing thermal annealing on the target layer to cause the material of the target layer to re-bond to form a bonding structure, the type of the Si—C bonding structure includes a grid-like bonding structure.

[0008] Optionally, in the step of performing thermal annealing on the target layer to cause the material of the target layer to re-bond to form a bonding structure, the type of the Si—CN bonding structure includes a ring bonding structure.

[0009] Optionally, in the step of depositing a target layer on the structure to be deposited, the material of the target layer further includes the O element; and in the step of performing thermal annealing on the target layer, the bonding structure further includes a Si-CO bonding structure.

[0010] Optionally, in the step of performing thermal annealing on the target layer, the type of the Si—CO bonding structure includes a ring bonding structure.

[0011] Optionally, in the step of providing a substrate, the structure to be deposited is a gate structure; and in the step of depositing a target layer on the structure to be deposited, the target layer is a gate sidewall.

[0012] Optionally, after depositing the gate sidewalls on the gate structure and before performing thermal annealing on the gate sidewalls, the method for forming the semiconductor structure also includes: forming source-drain doping layers in the substrate on both sides of the gate structure; after forming the source-drain doping layers, performing thermal annealing on the source-drain doping layers, and during the process of performing thermal annealing on the source-drain doping layers, simultaneously performing thermal annealing on the gate sidewalls.

[0013] Optionally, in the step of providing a substrate, the structure to be deposited includes a device layer structure or a front-layer interconnect structure; and in the step of forming the target layer, the target layer is an intermetallic dielectric layer.

[0014] Optionally, after depositing the target layer on the structure to be deposited and before performing thermal annealing on the target layer, the method for forming the semiconductor structure further includes: forming a protective layer covering the target layer.

[0015] Optionally, in the step of forming the protective layer, the material of the protective layer includes one or both of silicon nitride and silicon oxide.

[0016] Optionally, in the step of forming the protective layer, the thickness of the protective layer is in a range of 10 angstroms to 20 angstroms.

[0017] Optionally, after performing thermal annealing on the target layer, the forming method further includes: removing the protective layer.

[0018] Optionally, the process of removing the protective layer includes a wet etching process.

[0019] Optionally, the material of the protective layer is silicon nitride, and the process parameters of the wet etching process include: the etching solution includes a hydrofluoric acid solution or a phosphoric acid solution, the mass percentage concentration of the hydrofluoric acid solution is 0.5% to 1%, the mass percentage concentration of the phosphoric acid solution is 50% to 90%, the solution temperature is room temperature, and the etching time is 20 seconds to 60 seconds.

[0020] Optionally, in the step of providing a substrate, the structure to be deposited is a gate structure; in the step of depositing a target layer on the structure to be deposited, the target layer is a gate sidewall; after depositing the target layer on the structure to be deposited, before performing a thermal annealing treatment on the target layer, the method for forming a semiconductor structure further includes: forming a source-drain doped layer in the substrate on both sides of the gate structure; forming an etch stop layer covering the source-drain doped layer and the gate sidewall, the etch stop layer covering the gate sidewall being used as a protective layer.

[0021] Optionally, the process of performing thermal annealing on the target layer includes a rapid thermal annealing process, and process parameters of the rapid thermal annealing process include: a process temperature ranging from 800 degrees Celsius to 1100 degrees Celsius, and a process time ranging from 10 milliseconds to 30 minutes.

[0022] Optionally, the process of depositing the target layer on the structure to be deposited includes one or both of an atomic layer deposition process and a chemical vapor deposition process.

[0023] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0024] In the method for forming a semiconductor structure provided by an embodiment of the present invention, a target layer is deposited on the structure to be deposited, the material of the target layer contains Si element, C element and N element, and the target layer is subjected to thermal annealing treatment so that the material of the target layer is re-bonded to form a bonding structure, and the bonding structure includes a Si-C bonding structure and a Si-CN bonding structure. Since the bonding polarity of the Si-C bonding structure is small, the value of the relative dielectric constant (k) of the target layer is reduced, and the parasitic capacitance is correspondingly reduced; and the target layer contains C element and N element, C element is beneficial to improving the etching resistance of the target layer, and N element is beneficial to improving the mechanical strength of the target layer, thereby reducing the relative dielectric constant of the target layer while improving the etching resistance and mechanical properties of the target layer, thereby improving the performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figures 1 to 5 is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention;

[0026] Figure 6 is a structural formula of a material of the target layer before the target layer is subjected to thermal annealing in one embodiment of the present invention;

[0027] Figure 7 FIG. 4 is a structural formula of a material of a target layer after the target layer is subjected to thermal annealing in one embodiment of the present invention. DETAILED DESCRIPTION

[0028] At present, with the continuous shrinking of technology nodes, how to reduce the value of the relative dielectric constant of the dielectric material, thereby reducing the parasitic capacitance of the semiconductor device, and correspondingly reducing the delay between the resistor and the capacitor, and then improving the performance of the semiconductor structure, has become an urgent problem to be solved.

[0029] In order to solve the above technical problems, an embodiment of the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, on which a structure to be deposited is formed; depositing a target layer on the structure to be deposited, wherein the material of the target layer contains Si element, C element and N element; performing thermal annealing on the target layer so that the material of the target layer re-bonds to form a bonding structure, wherein the bonding structure includes a Si-C bonding structure and a Si-CN bonding structure.

[0030] In the method for forming a semiconductor structure provided by an embodiment of the present invention, a target layer is deposited on the structure to be deposited, the material of the target layer contains Si element, C element and N element, and the target layer is subjected to thermal annealing treatment so that the material of the target layer is re-bonded to form a bonding structure, and the bonding structure includes a Si-C bonding structure and a Si-CN bonding structure. Since the bonding polarity of the Si-C bonding structure is small, the value of the relative dielectric constant of the target layer is reduced, and the parasitic capacitance is correspondingly reduced; and the target layer contains C element and N element, C element is beneficial to improving the etching resistance of the target layer, and N element is beneficial to improving the mechanical strength of the target layer, thereby reducing the relative dielectric constant of the target layer while improving the etching resistance and mechanical properties of the target layer, thereby improving the performance of the semiconductor structure.

[0031] In order to make the above-mentioned purposes, features and advantages of the embodiments of the present invention more obvious and understandable, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0032] Figures 1 to 5 is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention; Figure 6 is the structural formula of the material of the target layer before the target layer is subjected to thermal annealing treatment; Figure 7 is the structural formula of the material of the target layer after the target layer is subjected to thermal annealing.

[0033] refer to Figure 1 , providing a substrate 100, on which a structure 110 to be deposited is formed.

[0034] The substrate 100 is used to provide a process platform for subsequent process steps.

[0035] In this embodiment, the substrate 100 is used to form a field effect transistor.

[0036] In this embodiment, the base 100 includes a substrate (not shown), which is a silicon substrate. In other embodiments, the material of the substrate may also be other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, and the substrate may also be other types of substrates such as a silicon-on-insulator substrate or a germanium-on-insulator substrate.

[0037] It should be noted that the substrate may be a planar substrate or a substrate having a channel protrusion.

[0038] The structure to be deposited 110 is used to provide a process basis for the subsequent deposition of a target layer.

[0039] In this embodiment, in the step of providing the substrate 100 , the structure to be deposited 110 is a gate structure.

[0040] It should be noted that the gate structure is a pseudo-gate structure, which is used to occupy a spatial position for the subsequent formation of a device gate structure.

[0041] Specifically, the material of the gate structure includes one or more of polysilicon, shaped silicon and amorphous carbon. As an example, the gate structure is polysilicon.

[0042] Of course, the present invention is not limited to this. In other embodiments, the gate structure may also be a device gate structure. When the device is working, the device gate structure is used to control the opening and closing of the conductive channel. The device gate structure includes a gate dielectric layer and a gate electrode layer covering the gate dielectric layer. The gate dielectric layer is used to isolate the gate electrode layer from the substrate. The device gate structure may be a metal gate structure, and therefore, the material of the gate electrode layer includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN and TiAlC. The gate electrode layer includes a work function layer and an electrode layer covering the work function layer, or may only include the work function layer. Accordingly, the gate dielectric layer includes a high-k gate dielectric layer. The material of the high-k gate dielectric layer is a high-k dielectric material, and the high-k dielectric material refers to a dielectric material having a relative dielectric constant greater than the relative dielectric constant of silicon oxide. Therefore, the material of the high-k gate dielectric layer may be selected from HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO or Al2O3, etc.

[0043] In other embodiments, in the step of providing a substrate, the structure to be deposited includes a device layer structure or a front layer interconnection structure. The device layer structure refers to a structure in which various devices (e.g., MOS transistors, diodes, etc.) have been formed; the front layer interconnection structure refers to a layer of interconnection structure in the back-end process (e.g., the first metal interconnection layer M1), which is used to electrically connect to specific devices in or on the substrate, thereby leading out the electrical properties of each device or realizing electrical connection between devices. It is understandable that the front layer interconnection structure usually includes a discrete interconnection layer.

[0044] refer to Figure 2 and Figure 6 , a target layer 120 is deposited on the structure to be deposited 110 , and a material of the target layer 120 contains Si element, C element and N element.

[0045] The target layer 120 is used to achieve electrical insulation between the structures to be deposited 110 , and the material of the target layer 120 is correspondingly a dielectric material.

[0046] Among them, the dielectric material generally contains Si element, and the C element is beneficial to reducing the etching rate, while the N element is beneficial to improving the mechanical strength of the film.

[0047] It should be noted that after the target layer 120 is deposited on the structure to be deposited 110, before the target layer 120 is subjected to thermal annealing, the material of the target layer 120 has not yet re-bonded to form a Si-C bonding structure and a Si-CN bonding structure. As an example, the structural formula of the material of the target layer 120 is as follows: Figure 6 shown.

[0048] Combined with reference Figure 6 In this embodiment, in the step of depositing the target layer 120 on the structure to be deposited 110, the material of the target layer 120 also includes O element.

[0049] The material of the target layer 120 also includes O element, which is beneficial to further reduce the value of the relative dielectric constant, thereby achieving a better effect of reducing the parasitic capacitance of the semiconductor device, and correspondingly achieving a better effect of reducing the delay between the resistor and the capacitor.

[0050] In this embodiment, in the step of providing the substrate 100, the structure to be deposited 110 is a gate structure. Correspondingly, in the step of depositing a target layer 120 on the structure to be deposited 110, the target layer 120 is a gate spacer.

[0051] The gate sidewall is used to protect the sidewall of the device gate structure. The gate sidewall can be a single-layer structure or a stacked structure.

[0052] In other embodiments, in the step of providing a substrate, the structure to be deposited includes a device layer structure or a front layer interconnection structure. Accordingly, in the step of forming the target layer, the target layer is an intermetallic dielectric layer (IMD). The intermetallic dielectric layer is used to achieve electrical insulation between interconnection layers formed in the intermetallic dielectric layer.

[0053] In this embodiment, the process of depositing the target layer 120 on the structure to be deposited 110 includes one or both of an atomic layer deposition process and a chemical vapor deposition process.

[0054] Among them, the atomic layer deposition process has good step coverage capability, which is beneficial to improving the thickness uniformity and coverage effect of the target layer 120. The chemical vapor deposition process has a high gap filling capability, and the process cost, stability and compatibility have great advantages.

[0055] refer to Figure 3 In this embodiment, after depositing the target layer 120 on the structure to be deposited 110 and before performing thermal annealing on the target layer 120 , the method for forming the semiconductor structure further includes: forming a protective layer 130 covering the target layer 120 .

[0056] The protective layer 130 is used to protect the target layer 120. During the subsequent thermal annealing process, after the material of the target layer 120 re-bonds to form a bonding structure, the bonding structure is not easily oxidized by oxygen in the external environment to change the formed Si-C bonding structure and Si-CN bonding structure.

[0057] In this embodiment, in the step of forming the protection layer 130 , the material of the protection layer 130 includes one or both of silicon nitride and silicon oxide.

[0058] Silicon nitride and silicon oxide are commonly used materials in semiconductor manufacturing. They are easy to obtain and have low process costs.

[0059] As an example, the material of the protection layer 130 includes silicon nitride.

[0060] It should be noted that silicon nitride does not contain O elements, so that the target layer 120 is less susceptible to interference from external O elements during the subsequent thermal annealing process, so that the material of the target layer 120 is re-bonded to form a Si-C bonding structure and a Si-CN bonding structure, and is not easy to affect the mass percentage content of each element in the material of the target layer 120, thereby reducing the value of the relative dielectric constant of the target layer 120, and improving the etching resistance or mechanical strength. In addition, silicon nitride has a large etching selectivity, which is also conducive to reducing the process difficulty of removing the protective layer 130 in the subsequent process.

[0061] It should be noted that in the step of forming the protective layer 130, the thickness of the protective layer 130 should not be too small or too large. If the thickness of the protective layer 130 is too small, it is easy for the protective layer 130 to be not easily oxidized by oxygen in the external environment after the material of the target layer 120 re-bonds to form a bonding structure during the subsequent thermal annealing process, thereby increasing the probability of changing the formed Si-C bonding structure and Si-CN bonding structure; if the thickness of the protective layer 130 is too large, it is easy to increase the process difficulty of the subsequent process (for example, increase the difficulty of patterning the protective layer 130, or increase the process difficulty of removing the protective layer 130). Therefore, in this embodiment, in the step of forming the protective layer 130, the thickness of the protective layer 130 ranges from 10 angstroms to 20 angstroms.

[0062] It should also be noted that, as an example, when the structure to be deposited 110 is a gate structure and the target layer 120 is a gate sidewall, the thickness of the protective layer 130 refers to the thickness in a direction perpendicular to the sidewall of the gate structure. In other embodiments, when the structure to be deposited includes a device layer structure or a front-layer interconnect structure and the target layer is an intermetallic dielectric layer, the thickness of the protective layer refers to the thickness in a normal direction to the top surface of the substrate.

[0063] refer to Figure 4 and Figure 7 , performing a thermal annealing treatment on the target layer 120 so that the material of the target layer 120 re-bonds to form a bonding structure, wherein the bonding structure includes a Si-C bonding structure and a Si-CN bonding structure.

[0064] A target layer 120 is deposited on the structure to be deposited 110, wherein the material of the target layer 120 contains Si, C and N elements, and the target layer 120 is subjected to thermal annealing treatment so that the material of the target layer 120 is rebonded to form a bonding structure, wherein the bonding structure includes a Si-C bonding structure and a Si-CN bonding structure. Since the bonding polarity of the Si-C bonding structure is relatively small, the relative dielectric constant of the target layer 120 is reduced, and the parasitic capacitance is correspondingly reduced; and the target layer 120 contains C and N elements, wherein the C element is beneficial to improving the etching resistance of the target layer 120, and the N element is beneficial to improving the mechanical strength of the target layer 120, thereby reducing the relative dielectric constant of the target layer 120 while improving the etching resistance and mechanical properties of the target layer, thereby improving the performance of the semiconductor structure.

[0065] It should be noted that, in the step of performing thermal annealing on the target layer 120 to allow the material of the target layer 120 to re-bond to form a bonding structure, the type of the Si—C bonding structure includes a grid-like bonding structure.

[0066] Compared with the target layer without a grid-like bonding structure, the target layer 120 with a grid-like bonding structure has a smaller film density, which correspondingly makes the value of the relative dielectric constant of the target layer 120 also smaller, further reducing the value of the relative dielectric constant of the target layer 120, which is beneficial to further reduce the parasitic capacitance and thus improve the performance of the semiconductor structure.

[0067] It should also be noted that, in the step of performing thermal annealing on the target layer 120 to allow the material of the target layer 120 to re-bond to form a bonding structure, the type of the Si—CN bonding structure includes a ring bonding structure.

[0068] Compared with the target layer without a ring-shaped bonding structure, the target layer 120 with a ring-shaped bonding structure has a smaller film density, which correspondingly makes the value of the relative dielectric constant of the target layer 120 also smaller, further reducing the value of the relative dielectric constant of the target layer 120, which is beneficial to further reduce the parasitic capacitance and thus improve the performance of the semiconductor structure.

[0069] As an example, after the target layer 120 is subjected to thermal annealing, the structural formula of the material of the target layer 120 is as follows: Figure 7 As shown, the material of the target layer 120 re-bonds to form a Si—C grid-like bonding structure and a Si—CN ring-like bonding structure.

[0070] Combined with reference Figure 7 In this embodiment, in the step of depositing the target layer 120 on the structure to be deposited 110, the material of the target layer 120 also includes the element O. Correspondingly, in the step of thermally annealing the target layer 120, the bonding structure also includes a Si-CO bonding structure.

[0071] The target layer 120 contains O element, which is beneficial to reducing the value of the relative dielectric constant, thereby further reducing the value of the relative dielectric constant of the target layer 120 .

[0072] Specifically, in the step of performing thermal annealing on the target layer 120 , the type of the Si—CO bonding structure further includes a ring bonding structure.

[0073] The types of the Si-CO bonding structure include a cyclic bonding structure. The description of the advantages of the Si-CO cyclic bonding structure is similar to the description of the advantages of the Si-CN cyclic bonding structure in the aforementioned embodiment, so it will not be repeated here.

[0074] In a specific embodiment, after depositing gate sidewalls on the gate structure 110 and before thermally annealing the gate sidewalls, the method for forming the semiconductor structure further includes: forming source-drain doping layers (not shown) in the substrate 100 on both sides of the gate structure 110 .

[0075] The source-drain doped layer is used as the source region and the drain region of the transistor. When the device is working, the source-drain doped layer is used to provide a carrier source.

[0076] In this embodiment, after the source-drain doping layer is formed, the source-drain doping layer is subjected to thermal annealing. During the thermal annealing of the source-drain doping layer, the gate sidewall is also subjected to thermal annealing.

[0077] In the process of thermally annealing the source-drain doping layer, the gate sidewall is also thermally annealed, which is beneficial to combining with the existing process, saving process steps and reducing process costs.

[0078] In this embodiment, the process of thermal annealing the target layer 120 includes a rapid thermal annealing process, and the process parameters of the rapid thermal annealing process include: a process temperature ranging from 800 degrees Celsius to 1100 degrees Celsius, and a process time ranging from 10 milliseconds to 30 minutes.

[0079] Rapid thermal annealing is widely used in semiconductor manufacturing processes and can be easily combined with existing process steps to save process steps and reduce process costs. As an example, the rapid thermal annealing process is a laser annealing process.

[0080] It should be noted that the process temperature of the rapid thermal annealing treatment should not be too low. If the process temperature is too low, the material of the target layer 120 is likely to be re-bonded to form a Si-C bonding structure and a Si-CN bonding structure, which is not effective, thereby reducing the value of the relative dielectric constant of the target layer 120. If the process temperature is too high, it is easy to cause the thermal budget to be too large. Therefore, in this embodiment, the process temperature ranges from 800 degrees Celsius to 1100 degrees Celsius.

[0081] It should also be noted that the process time of the rapid thermal annealing treatment should not be too short. If the process time is too short, the material of the target layer 120 is likely to re-bond to form a Si-C bonding structure and a Si-CN bonding structure, which is not effective, thereby reducing the value of the relative dielectric constant of the target layer 120. If the process time is too long, it is easy to cause the thermal budget to be too large. Therefore, in this embodiment, the process time ranges from 10 milliseconds to 30 minutes.

[0082] Furthermore, in other embodiments, a separate thermal annealing step may be used to allow the material of the target layer to re-bond to form a bonding structure.

[0083] refer to Figure 5 In this embodiment, after the target layer 120 is subjected to thermal annealing, the forming method further includes: removing the protective layer 130 .

[0084] Removing the protective layer 130 is a preparation for the subsequent process. Specifically, the process of removing the protective layer 130 includes a wet etching process.

[0085] The cost of the wet etching process is relatively low, and the operation steps are simple. It can also achieve a large etching selectivity ratio, which is beneficial to reduce the damage to other film layers (such as the structure to be deposited 110) during the removal of the protective layer 130.

[0086] In this embodiment, the material of the protective layer 130 includes one or both of silicon nitride and silicon oxide. Silicon nitride and silicon oxide can be easily removed by wet etching, thereby reducing the difficulty of removing the protective layer 130 .

[0087] As an example, the material of the protective layer 130 is silicon nitride. Therefore, the process parameters of the wet etching process include: the etching solution includes a hydrofluoric acid solution or a phosphoric acid solution, the mass percentage concentration of the hydrofluoric acid solution is 0.5% to 1%, the mass percentage concentration of the phosphoric acid solution is 50% to 90%, the solution temperature is room temperature, and the etching time is 20 seconds to 60 seconds.

[0088] Hydrofluoric acid solution and phosphoric acid solution are commonly used etching solutions in semiconductor processes, which are beneficial to improving process compatibility. In addition, the material of the protective layer 130 includes one or both of silicon nitride and silicon oxide. The hydrofluoric acid solution has a relatively high etching selectivity for the material of the protective layer 130 and other materials (such as the material of the structure 110 to be deposited). The phosphoric acid solution has a relatively high etching selectivity for the material of the protective layer 130 and other materials, which is beneficial to reduce the probability of damage to other film layers (such as the structure 110 to be deposited) during the process of removing the protective layer 130.

[0089] The mass percentage concentration of the etching solution should not be too large or too small. If the mass percentage concentration of the etching solution is too large, the etching ability of the etching solution will be too large, which will increase the probability of damage to other film layers; if the mass percentage concentration of the etching solution is too small, the etching ability of the etching solution will be too small, which will correspondingly make the etching time too long, and even make it difficult to completely remove the protective layer 130, thereby affecting the quality of subsequent film formation. Therefore, in this embodiment, the mass percentage concentration of the hydrofluoric acid solution is 0.5% to 1%, and the mass percentage concentration of the phosphoric acid solution is 50% to 90%.

[0090] The temperature of the etching solution should not be too high or too low. If the temperature is too low, the etching rate is too low, which is not conducive to improving the etching efficiency; if the temperature is too high, the etching selectivity is poor, which increases the probability of damage to other film layers. Therefore, in this embodiment, the solution temperature is room temperature.

[0091] The etching time will affect the etching amount accordingly. If the etching time is too short, it is easy to make it difficult to completely remove the protective layer 130, thereby affecting the quality of subsequent film formation. If the etching time is too long, it is easy to increase the probability of damage to other film layers. Therefore, in this embodiment, the etching time is 20 seconds to 60 seconds.

[0092] It should be noted that, in other embodiments, according to actual conditions, after the target layer is subjected to thermal annealing, the protective layer may also be retained, thereby saving process steps and improving manufacturing efficiency.

[0093] It should also be noted that, in other embodiments, the etch stop layer covering the source-drain doped layer may also be directly used as a protective layer. Specifically, after depositing the target layer on the structure to be deposited, before thermal annealing the target layer, the method for forming the semiconductor structure further includes: forming a source-drain doped layer in the substrate on both sides of the gate structure; forming an etch stop layer covering the source-drain doped layer and the gate sidewall, and the etch stop layer covering the gate sidewall is used as a protective layer.

[0094] The etch stop layer is used to define the etch stop position in the subsequent process of forming a source-drain interconnect layer (M0) or a source-drain plug (CT), thereby reducing the probability of the source-drain doped layer being damaged during the etching process.

[0095] Directly using the etch stop layer as a protective layer is conducive to combining with the existing process flow, saving process steps and reducing process costs.

[0096] Accordingly, in a solution in which the etch stop layer is used as a protective layer, the protective layer may be retained after the target layer is subjected to thermal annealing.

[0097] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, on which a structure to be deposited is formed; Depositing a target layer on the structure to be deposited, wherein the material of the target layer contains Si element, C element and N element; The target layer is subjected to thermal annealing treatment to allow the material of the target layer to re-bond to form a bonding structure, wherein the bonding structure includes a Si-C bonding structure and a Si-CN bonding structure.

2. The method for forming a semiconductor structure according to claim 1, wherein: In the step of performing a thermal annealing treatment on the target layer to allow the material of the target layer to re-bond to form a bonding structure, the type of the Si-C bonding structure includes a grid-like bonding structure.

3. The method for forming a semiconductor structure according to claim 1, wherein: In the step of performing a thermal annealing treatment on the target layer to allow the material of the target layer to re-bond to form a bonding structure, the type of the Si-CN bonding structure includes a cyclic bonding structure.

4. The method for forming a semiconductor structure according to claim 1, wherein: In the step of depositing a target layer on the structure to be deposited, the material of the target layer further includes an O element; In the step of performing thermal annealing on the target layer, the bonding structure further includes a Si-CO bonding structure.

5. The method for forming a semiconductor structure according to claim 4, wherein: In the step of performing a thermal annealing treatment on the target layer, the type of the Si—CO bonding structure includes a ring bonding structure.

6. The method for forming a semiconductor structure according to claim 1, wherein: In the step of providing a substrate, the structure to be deposited is a gate structure; In the step of depositing a target layer on the structure to be deposited, the target layer is a gate sidewall.

7. The method for forming a semiconductor structure according to claim 6, wherein: After depositing a gate spacer on the gate structure and before performing a thermal annealing treatment on the gate spacer, the method for forming the semiconductor structure further comprises: forming a source-drain doping layer in the substrate on both sides of the gate structure; After the source-drain doping layer is formed, the source-drain doping layer is subjected to thermal annealing. During the thermal annealing of the source-drain doping layer, the gate sidewall is subjected to thermal annealing at the same time.

8. The method for forming a semiconductor structure according to claim 1, wherein: In the step of providing a substrate, the structure to be deposited includes a device layer structure or a front layer interconnect structure; In the step of forming the target layer, the target layer is an intermetallic dielectric layer.

9. The method for forming a semiconductor structure according to any one of claims 1 to 8, wherein: After depositing a target layer on the structure to be deposited and before performing a thermal annealing process on the target layer, the method for forming a semiconductor structure further includes: forming a protection layer covering the target layer.

10. The method for forming a semiconductor structure according to claim 9, wherein: In the step of forming the protective layer, the material of the protective layer includes one or both of silicon nitride and silicon oxide.

11. The method for forming a semiconductor structure according to claim 9, wherein: In the step of forming the protective layer, the protective layer has a thickness ranging from 10 angstroms to 20 angstroms.

12. The method for forming a semiconductor structure according to claim 9, wherein: After the target layer is subjected to thermal annealing, the forming method further comprises: removing the protective layer.

13. The method for forming a semiconductor structure according to claim 12, wherein: The process of removing the protection layer includes a wet etching process.

14. The method for forming a semiconductor structure according to claim 13, wherein: The material of the protective layer is silicon nitride, and the process parameters of the wet etching process include: the etching solution includes a hydrofluoric acid solution or a phosphoric acid solution, the mass percentage concentration of the hydrofluoric acid solution is 0.5% to 1%, the mass percentage concentration of the phosphoric acid solution is 50% to 90%, the solution temperature is room temperature, and the etching time is 20 seconds to 60 seconds.

15. The method for forming a semiconductor structure according to any one of claims 1 to 7, characterized in that: In the step of providing a substrate, the structure to be deposited is a gate structure; In the step of depositing a target layer on the structure to be deposited, the target layer is a gate sidewall; After depositing a target layer on the structure to be deposited and before performing a thermal annealing treatment on the target layer, the method for forming the semiconductor structure further includes: forming a source-drain doping layer in the substrate on both sides of the gate structure; An etch stop layer covering the source / drain doping layer and the gate sidewall is formed, and the etch stop layer covering the gate sidewall is used as a protective layer.

16. The method for forming a semiconductor structure according to any one of claims 1 to 4, characterized in that: The process of thermally annealing the target layer includes a rapid thermal annealing process, and the process parameters of the rapid thermal annealing process include: a process temperature ranging from 800 degrees Celsius to 1100 degrees Celsius, and a process time ranging from 10 milliseconds to 30 minutes.

17. The method for forming a semiconductor structure according to any one of claims 1 to 4, characterized in that: The process of depositing the target layer on the structure to be deposited includes one or both of an atomic layer deposition process and a chemical vapor deposition process.

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