Data writing method, storage device and data writing system

Abstract

The embodiment of the invention discloses a data writing method, storage equipment and a data writing system. According to the embodiment of the invention, after the control unit of the storage device temporarily stores the to-be-written data to the source cache region, the source cache region is controlled to transmit the to-be-written data to the target cache region, and after the to-be-written data is transmitted, the source cache region is released, so that the target cache region is controlled to write the to-be-written data into the storage medium of the storage device. According to the embodiment of the invention, the occupation time of the source cache region is reduced by releasing the source cache region after the data transmission is finished, so that the writing efficiency of the data can be improved.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and more specifically, to a data writing method, a storage device and a data writing system. Background Art

[0002] The efficiency of data writing is limited by the write bandwidth, which is affected by the capacity of the buffer memory (i.e., cache) of the storage device. However, due to manufacturing costs and other reasons, the capacity of the cache of existing storage devices is limited. Therefore, when the amount of data is large, the cache will be occupied for a long time, resulting in low data writing efficiency. Summary of the invention

[0003] In view of this, an embodiment of the present invention provides a data writing method, a storage device and a data writing system, so as to reduce the occupation time of the source buffer area by releasing the source buffer area after the data transmission is completed, thereby improving the data writing efficiency.

[0004] In a first aspect, an embodiment of the present invention provides a data writing method, applicable to a control unit of a storage device, the method comprising:

[0005] Temporarily store the data to be written into the source buffer area;

[0006] Controlling the source buffer area to transfer the to-be-written data to the target buffer area;

[0007] In response to completion of transmission of the data to be written, releasing the source buffer area;

[0008] The target buffer area is controlled to write the data to be written into the storage medium of the storage device.

[0009] Optionally, the method further comprises:

[0010] Receive data writing request;

[0011] The data writing request is parsed to obtain the data to be written in the data writing request.

[0012] Optionally, the data to be written is input / output data, the source buffer area is an input / output data buffer area in a static random access memory of the control unit, and the target buffer area is an internal buffer area of ​​the storage medium.

[0013] Optionally, controlling the source buffer area to transfer the to-be-written data to the target buffer area includes:

[0014] The source buffer area is controlled to transfer the to-be-written data to the target buffer area through a direct memory access method.

[0015] Optionally, in response to the completion of the transmission of the data to be written, releasing the source buffer area includes:

[0016] In response to receiving a transmission completion signal of the data to be written, the available state of the source buffer area is modified to available.

[0017] Optionally, the method further comprises:

[0018] Receive data writing request;

[0019] Parsing the data writing request to obtain target data in the data writing request;

[0020] Verifying the target data to obtain verification data of the target data;

[0021] The verification data is determined as the data to be written.

[0022] Optionally, the data to be written is verification data of input and output data, the source cache area is the verification data cache area in the static random access memory of the control unit, and the target cache area is the verification data cache area in the dynamic random access memory of the control unit.

[0023] Optionally, controlling the target cache area to write the to-be-written data into a storage medium of the storage device comprises:

[0024] Controlling the target buffer area to transfer the data to be written to the internal buffer area of ​​the storage medium;

[0025] The internal buffer area is controlled to write the data to be written into the storage medium.

[0026] In a second aspect, an embodiment of the present invention provides a storage device, the storage device comprising:

[0027] Storage media;

[0028] Multiple buffers, including a source buffer and a target buffer for data to be written;

[0029] A control unit is configured to temporarily store the data to be written in a source cache area, send a data transfer instruction to the source cache area to control the source cache area to transfer the data to be written to a target cache area, release the source cache area in response to the completion of the transmission of the data to be written, and send a data write request to the target cache area to control the target cache area to write the data to be written into the storage medium.

[0030] In a third aspect, an embodiment of the present invention provides a data writing system, the data writing system comprising:

[0031] The storage device according to the second aspect;

[0032] The host is configured to send a data write request to the storage device.

[0033] In a fourth aspect, an embodiment of the present invention provides a data writing device, applicable to a control unit of a storage device, the device comprising:

[0034] A data temporary storage module, used to temporarily store the data to be written into the source buffer area;

[0035] A data transmission module, used for controlling the source buffer area to transmit the to-be-written data to the target buffer area;

[0036] A release module, configured to release the source buffer area in response to completion of transmission of the data to be written;

[0037] The data writing module is used to control the target buffer area to write the data to be written into the storage medium of the storage device.

[0038] In a fifth aspect, an embodiment of the present invention provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the method as described in any one of the first aspects is implemented.

[0039] In a sixth aspect, an embodiment of the present invention provides a computer program product, which, when executed on a computer, enables the computer to execute the method as described in any one of the methods in the first aspect.

[0040] After the control unit of the storage device of the embodiment of the present invention temporarily stores the data to be written in the source buffer area, it controls the source buffer area to transfer the data to be written to the target buffer area, and after the data to be written is transmitted, it releases the source buffer area, and then controls the target buffer area to write the data to be written into the storage medium of the storage device. The embodiment of the present invention reduces the occupation time of the source buffer area by releasing the source buffer area after the data transmission is completed, so that the data writing efficiency can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] The above and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

[0042] Figure 1 is a schematic diagram of the structure of a storage device according to an embodiment of the present invention;

[0043] Figure 2 is a flow chart of a data writing method according to an embodiment of the present invention;

[0044] Figure 3is a flow chart of a data writing method according to an embodiment of the present invention;

[0045] Figure 4 It is a schematic diagram of the existing data writing process;

[0046] Figure 5 is a schematic diagram of a data writing process according to an embodiment of the present invention;

[0047] Figure 6 is a flow chart of a data writing method according to an embodiment of the present invention;

[0048] Figure 7 It is a schematic diagram of the existing data writing process;

[0049] Figure 8 is a schematic diagram of a data writing process according to an embodiment of the present invention;

[0050] Fig. 9 is a schematic diagram of a data writing device according to an embodiment of the present invention;

[0051] Fig.10 Schematic diagram of a data access system according to an embodiment of the present invention. DETAILED DESCRIPTION

[0052] The present application is described below based on embodiments, but the present application is not limited to these embodiments. In the detailed description of the present application below, some specific details are described in detail. It is possible for those skilled in the art to fully understand the present application without the description of these details. In order to avoid confusing the essence of the present application, known methods, processes, flows, components and circuits are not described in detail.

[0053] In addition, persons of ordinary skill in the art will appreciate that the drawings provided herein are for illustration purposes and are not necessarily drawn to scale.

[0054] At the same time, it should be understood that in the following description, "circuit" refers to a conductive loop composed of at least one element or subcircuit through electrical connection or electromagnetic connection. When an element or circuit is said to be "connected to" another element or an element / circuit is said to be "connected between" two nodes, it can be directly coupled or connected to another element or there can be an intermediate element, and the connection between the elements can be physical, logical, or a combination thereof. On the contrary, when an element is said to be "directly coupled to" or "directly connected to" another element, it means that there is no intermediate element between the two.

[0055] Unless the context clearly requires otherwise, the words "include", "comprising" and similar words throughout the application should be interpreted as including rather than exclusive or exhaustive; that is, the meaning is "including but not limited to".

[0056] In the description of this application, it should be understood that the terms "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance. In addition, in the description of this application, unless otherwise specified, the meaning of "plurality" is two or more.

[0057] Flash memory is a low-cost, high-density non-volatile solid-state storage medium. Flash memory may include NOR flash memory and NAND flash memory, etc. Flash memory can perform operations such as reading, programming (i.e., writing) and erasing. Among them, NAND flash memory includes multiple blocks, each block is composed of a certain number of pages, each page is composed of a certain number of bit lines, and each bit line is composed of a certain number of memory cells, which enables NAND flash memory to store data in the storage cell in the form of bits. Therefore, NAND flash memory can perform erase operations at the block level and can perform programming operations or read operations at the page level. The embodiment of the present invention is mainly described by taking a storage device SSD (Solid State Disk) using NAND flash memory as a storage medium as an example. It should be understood that the present embodiment is not limited to this. Existing storage devices that can support corresponding functions or storage devices that can support corresponding functions with future technological development are all within the protection scope of the embodiment of the present invention.

[0058] The data write bandwidth refers to the amount of data that can be written to the storage device per unit time. The data write efficiency is limited by the write bandwidth. The larger the data write bandwidth, the higher the write efficiency. Therefore, in order to improve the write bandwidth of the storage device, and then improve the data write efficiency of the storage device, the control unit of the storage device is usually configured with an internal cache area, such as a static random access memory (SRAM) cache area, a dynamic random access memory (DRAM) cache area, a double data rate synchronous dynamic random access memory (DDRSDRAM or DDR, Double Data Rate Synchronous Dynamic Random Access Memory, a type of DRAM) cache area, etc.

[0059] Figure 1 Schematic diagram of the structure of a storage device according to an embodiment of the present invention. Figure 1As shown, the storage device 10 of the embodiment of the present invention includes a control unit 11 and a NAND storage medium 12. The control unit 11 includes a front end (FE) module 111, a flash translation layer (FTL) module 112, a back end (BE) module 113, an SRAM cache area 114 and a DDR cache area 115. The NAND storage medium 12 includes a cache area 121 and a storage area 122.

[0060] The FE module 111 is mainly responsible for interface communication and data transmission with the host, including receiving data write requests from the host, and preliminarily parsing and processing the data write requests, obtaining various information including the logical block address (LBA) of the data to be written and passing it to the FTL module 112, and temporarily storing the data to be written carried in the data write request in the SRAM cache area 114 or the DDR cache area 115.

[0061] The FTL module 112 is mainly responsible for mapping the logical block address of the data to be written to the physical block address (PBA) on the NAND storage medium 12, that is, the actual storage location of the data to be written in the storage area 122, and passing various information including the physical block address of the data to be written to the BE module 113. At the same time, the FTL module can also be responsible for the management tasks of the NAND storage medium 12 such as garbage collection, wear leveling, abnormal power failure recovery, etc.

[0062] The BE module 113 is connected to the NAND storage medium 12, and performs corresponding data writing operations according to the information transmitted by the FTL module 112, that is, controls the SRAM cache area 114 or the DDR cache area 115 to transfer the data to be written to the NAND storage medium 12, and the release operation of the SRAM cache area 114 or the DDR cache area 115, so that the SRAM cache area 114 or the DDR cache area 115 can store new data to be written.

[0063] During the data writing process, the BE module 113 will transfer the data to be written to the cache area 121 for temporary storage. The cache area 121 is the internal cache area of ​​the NAND storage medium 12, so after the data to be written is transmitted, the NAND storage medium 12 can write the data to be written into the corresponding storage unit in the storage area 122 according to the physical block address of the data to be written.

[0064] However, the manufacturing cost of the internal cache area of ​​the control unit is usually high. In order to reasonably control the manufacturing cost of the storage device, the capacity of the internal cache area of ​​the control unit is limited. In the prior art, the storage unit of the storage device will release the internal cache area only after the data is written to the storage medium. Therefore, when the amount of data is large, the cache will be occupied for a long time, resulting in low data writing efficiency.

[0065] Based on this, an embodiment of the present invention provides a data writing method, a storage device and a data writing system, so as to reduce the occupation time of the source buffer area by releasing the source buffer area after the data transmission is completed, thereby improving the data writing efficiency.

[0066] Figure 2 1 is a flow chart of a data writing method according to an embodiment of the present invention. Figure 2 As shown, the method of this embodiment includes the following steps:

[0067] Step S201, temporarily storing the data to be written into the source buffer area.

[0068] After acquiring the data to be written, in this step, the control unit of the storage device can temporarily store the data to be written in the internal cache area of ​​the control unit according to actual needs, and determine the internal cache area temporarily storing the data to be written as the source cache area.

[0069] by Figure 1 Taking the storage device shown as an example, the control unit of the storage device may temporarily store the data to be written in the SRAM cache area 114, or may temporarily store the data to be written in the DDR cache area, which is not limited in this embodiment.

[0070] Step S202: Control the source buffer area to transfer the data to be written to the target buffer area.

[0071] The actual capacity of the source cache area will affect the write bandwidth of the data to be written, and further limit the write efficiency of the data to be written. Therefore, in order to avoid the source cache area being occupied for a long time, in this step, the control unit of the storage device can control the source cache area to transfer the data to be written to the target cache area. Further, the control unit of the storage device can determine the transmission mode of the data to be written according to the source cache area and the target cache area, and control the source cache area to transfer the data to be written to the target cache area according to the corresponding transmission mode.

[0072] Still Figure 1 Taking the storage device shown as an example, when the source cache area is the SRAM cache area 114, the target cache area can be the DDR cache area 115, or the cache area 121 of the NAND storage medium 12; when the source cache area is the DDR cache area 115, the target cache area can be the cache area 121 of the NAND storage medium 12.

[0073] When the source cache area is the SRAM cache area 114 or the DDR cache area 115, and the target cache area is the cache area 121 of the NAND storage medium 12, the control unit 11 of the storage device 10 can control the SRAM cache area 114 or the DDR cache area 115 to transfer the data to be written to the cache area 121 of the NAND storage medium 12 in a direct memory access (DMA) manner through the internal data bus of the storage device 10, that is, the bus connected to the NAND storage medium 12. DMA is a hardware technology that allows devices, chips, etc. to exchange data directly without the intervention of the central processing unit (CPU), thereby saving the computing resources of the central processing unit and improving the transmission efficiency of the data to be written.

[0074] When the source cache area is the SRAM cache area 114 and the target cache area is the DDR cache area 115, the control unit 11 of the storage device 10 can control the SRAM cache area 114 to transmit the data to be written to the DDR cache area 115 through the internal data bus of the storage device 10, that is, the bus connected to the DDR cache area 115, so as to ensure the transmission efficiency of the data to be written.

[0075] Step S203, in response to the completion of the transmission of the data to be written, releasing the source buffer area.

[0076] When temporarily storing the data to be written in the source buffer area, the control unit of the storage device will modify the available state of the source buffer area to unavailable to prevent the new data to be written from being temporarily stored in the source buffer area and overwriting the original data to be written. Therefore, in this step, the control unit of the storage device can modify the available state of the source buffer area to available to release the source buffer area after the data to be written is transmitted.

[0077] Furthermore, the control unit of the storage device may obtain the transmission status of the to-be-written data in a corresponding manner according to the source cache area and the target cache area, thereby modifying the available status of the source cache area.

[0078] Still Figure 1 Taking the storage device shown in the figure as an example, when the source buffer area is the SRAM buffer area 114 or the DDR buffer area 115, and the target buffer area is the buffer area 121 of the NAND storage medium 12, the data transmission mechanism of DMA is such that after the data transmission is completed, a transmission completion signal, specifically DMA Done, will be sent to the control unit 11 of the storage device 10. Therefore, after receiving the transmission completion signal sent by the NAND storage medium 12, the control unit 11 of the storage device 10 can determine that the data to be written is transmitted.

[0079] When the source buffer is the SRAM buffer 114 and the target buffer is the DDR buffer 115, in a possible case, the control unit 11 of the storage device 10 may maintain an internal status flag for tracking the status of the SRAM buffer 114 and the DDR buffer 115, and update the status flag of the SRAM buffer 114 or the DDR buffer 115 after the data to be written is transmitted. Therefore, the control unit 11 of the storage device 10 can determine that the data to be written is transmitted by reading the status flag of the SRAM buffer 114 or the DDR buffer 115.

[0080] In a possible scenario, there may be a specific form of handshake protocol or completion signal between the SRAM buffer area 114 and the DDR buffer area 115, so after the data transmission is completed, the DDR buffer area 115 will send a transmission completion signal of the data to be written to the SRAM buffer area 114. Therefore, the control unit 11 of the storage device 10 can determine that the transmission of the data to be written is completed by monitoring the transmission completion signal.

[0081] In a possible case, in order to ensure the integrity and correctness of the data transmission, the control unit 11 of the storage device 10 may perform a verification operation on the data to be written. After determining that the data transmission to be written is completed through the above-mentioned status flag or the transmission completion signal, the control unit 11 of the storage device 10 may perform a verification operation on the data to be written in the DDR buffer area 115 to verify whether the data to be written in the DDR buffer area 115 is consistent with the original data to be written in the SRAM buffer area 114. If the verification passes, the control unit 11 of the storage device 10 can determine that the data transmission to be written is completed.

[0082] Step S204, controlling the target buffer area to write the data to be written into the storage medium of the storage device.

[0083] In this step, the control unit of the storage device can control the target cache area to write the data to be written into the corresponding storage unit in the storage medium according to the physical block address of the data to be written. Specifically, if the target cache area is the internal cache area of ​​the control unit of the storage device, the control unit of the storage device can control the target cache area to transfer the data to be written to the internal cache area of ​​the storage medium, and control the storage medium of the storage device to write the data to be written into the corresponding storage unit.

[0084] Still Figure 1Taking the storage device shown as an example, when the target cache area is the DDR cache area 115, the control unit 11 of the storage device 10 can control the DDR cache area 115 to transfer the data to be written to the cache area 121 of the NAND storage medium 12, and control the NAND storage medium 12 to write the data to be written in the cache area 121 of the NAND storage medium 12 into the corresponding storage unit in the storage area 122.

[0085] If the target cache area is an internal cache area of ​​a storage medium of the storage device, the control unit of the storage device may control the internal cache area of ​​the storage medium to write the to-be-written data into a corresponding storage unit in the storage medium of the storage device.

[0086] It is easy to understand that in this embodiment, step S203 and step S204 can be executed simultaneously or successively, and this embodiment does not limit this.

[0087] It takes a certain amount of time to write the data to be written from the internal buffer area of ​​the storage medium to the corresponding storage unit. Therefore, according to the prior art, even if the data to be written has been transferred to the target buffer area, the source buffer area will not be released until the data to be written is written. Therefore, this method will increase the occupancy time of the source buffer area, thereby reducing the write bandwidth of the data to be written. However, through the method of the embodiment of the present invention, the source buffer area can be released in advance, so the write bandwidth of the data to be written can be increased, thereby improving the write efficiency of the data to be written.

[0088] After the control unit of the storage device of the embodiment of the present invention temporarily stores the data to be written in the source buffer area, it controls the source buffer area to transfer the data to be written to the target buffer area, and after the data to be written is transmitted, it releases the source buffer area, and then controls the target buffer area to write the data to be written into the storage medium of the storage device. The embodiment of the present invention reduces the occupation time of the source buffer area by releasing the source buffer area after the data transmission is completed, so that the data writing efficiency can be improved.

[0089] Figure 3 1 is a flow chart of a data writing method according to an embodiment of the present invention. Figure 3 As shown, the method of this embodiment includes the following steps:

[0090] Step S301, receiving a data write request.

[0091] In this embodiment, the host may send a data write request to the control unit of the storage device through the bus, so in this step, the control unit of the storage device may receive the data write request.

[0092] Step S302: parse the data writing request to obtain the data to be written in the data writing request.

[0093] In this step, the control unit of the storage device may parse the data write request and determine the input / output data carried in the data write request, that is, I / O (Input / Output) data as the data to be written.

[0094] The parsing process of the data write request requires a higher data processing bandwidth, so the control unit of the storage device can use the cache area to complete the parsing process of the data write request and obtain the input and output data in the data write request. In practical applications, the data processing performance of SRAM is higher than that of DDR, so in this embodiment, the control unit of the storage device can use the SRAM cache area to parse the data write request.

[0095] In one possible scenario, according to actual needs, the SRAM cache area is divided into multiple data cache areas, and the multiple data cache areas include input and output data cache areas. Therefore, in this step, the control unit of the storage device can use the input and output data cache areas in the SRAM to parse the data write request.

[0096] Step S303, temporarily storing the data to be written into the source buffer area.

[0097] After obtaining the input and output data in the data write request, the control unit of the storage device can directly temporarily store the input and output data in the internal cache area of ​​the control unit, which can be specifically the high-speed cache area of ​​the control unit. In this embodiment, the high-speed cache area can be an SRAM cache area. Further, the control unit of the storage device can temporarily store the input and output data in the input and output data cache area in the SRAM of the control unit.

[0098] Step S304: Control the source buffer area to transfer the data to be written to the target buffer area.

[0099] In order to reduce the time that input and output data occupy the source cache area, and at the same time avoid the input and output data from placing an excessive data processing burden on the control unit of the storage device, the control unit of the storage device can determine the internal cache area of ​​the storage medium of the storage device as the target cache area for the input and output data, and control the internal cache area of ​​the control unit, which can specifically be the input and output data cache area in the SRAM, to transfer the input and output data to the internal cache area of ​​the storage medium of the storage device.

[0100] In this step, the control unit of the storage device may control the input / output data buffer area in the SRAM to transfer the input / output data to the internal buffer area of ​​the storage medium of the storage device through DMA.

[0101] Step S305 , in response to the completion of the transmission of the data to be written, releasing the source buffer area.

[0102] In this step, the control unit of the storage device can determine that the input and output data transmission is completed after receiving the transmission completion signal of the input and output data, and modify the available state of the internal buffer area of ​​the control unit to available, so as to release the internal buffer area of ​​the control unit. Specifically, the storage device can modify the available state of the input and output data buffer area in the SRAM to available.

[0103] Step S306, controlling the target buffer area to write the data to be written into the storage medium of the storage device.

[0104] In this step, the control unit of the storage device can control the internal buffer area of ​​the storage medium to write the data to be written into the corresponding storage unit in the storage medium of the storage device, thereby completing the writing process of the input and output data.

[0105] Figure 4 is a schematic diagram of the existing data writing process. Figure 4 As shown, in step S41, the FE module 111 can receive the data write request sent by the host 40, and parse the data write request, and then in step S42, temporarily store the I / O data carried in the data write request to the SRAM 114, which can be specifically the I / O data cache 1141 of the SRAM. In step S43, the I / O data cache 1141 of the SRAM is controlled to transfer the I / O data to the cache 121 of the NAND storage medium 12. In step S44, after the I / O data transmission is completed, the NAND storage medium 12 can send an I / O data transmission completion signal to the BE module 113, that is, DMA Done. In step S45, after the I / O data is written, the NAND storage medium 12 can send an I / O data write completion signal to the BE module 113, that is, NAND Done. In step S46 , after receiving the I / O data write completion signal, the BE module 113 may modify the available state of the SRAM I / O data buffer area 1141 to available to release the SRAM I / O data buffer area 1141 .

[0106] Figure 5 FIG. 1 is a schematic diagram of a data writing process according to an embodiment of the present invention. Figure 5As shown, in step S51, the FE module 111 can receive the data write request sent by the host 40, and parse the data write request, and then in step S52, temporarily store the I / O data carried in the data write request to the SRAM 114, which can be specifically the I / O data buffer area 1141 of the SRAM. In step S53, the I / O data buffer area 1141 of the SRAM is controlled to transfer the I / O data to the buffer area 121 of the NAND storage medium 12. In step S54, after the I / O data transmission is completed, the NAND storage medium 12 can send a transmission completion signal of the I / O data to the BE module 113, that is, DMA Done. In step S55, after receiving the transmission completion signal of the I / O data, the BE module 113 can modify the available state of the I / O data buffer area 1141 of the SRAM to available, so as to release the I / O data buffer area 1141 of the SRAM. In step S56, after the I / O data is written, the NAND storage medium 12 may send a write completion signal of the I / O data, ie, NAND Done, to the BE module 113.

[0107] By comparison Figure 4 and Figure 5 It can be determined that the embodiment of the present invention advances the release timing of the internal cache area of ​​the control unit from after receiving the write completion signal of the input and output data to after receiving the transmission completion signal of the input and output data, thereby effectively reducing the occupation time of the internal cache area of ​​the control unit by the input and output data and improving the utilization rate of the internal cache area of ​​the control unit, thereby effectively improving the writing efficiency of the input and output data.

[0108] After the control unit of the storage device of the embodiment of the present invention temporarily stores the data to be written in the source buffer area, it controls the source buffer area to transfer the data to be written to the target buffer area, and after the data to be written is transmitted, it releases the source buffer area, and then controls the target buffer area to write the data to be written into the storage medium of the storage device. The embodiment of the present invention reduces the occupation time of the source buffer area by releasing the source buffer area after the data transmission is completed, so that the data writing efficiency can be improved.

[0109] Figure 6 1 is a flow chart of a data writing method according to an embodiment of the present invention. Figure 6 As shown, the method of this embodiment includes the following steps:

[0110] Step S601, receiving a data write request.

[0111] In this embodiment, the implementation of step S601 is similar to the implementation of step S301 and will not be described in detail herein.

[0112] Step S602: parse the data writing request to obtain target data in the data writing request.

[0113] In this step, the control unit of the storage device may parse the data write request and determine the input and output data carried in the data write request as the target data.

[0114] Step S603, verifying the target data, and obtaining verification data of the target data in the data write request.

[0115] In order to ensure the consistency and security of data transmission, after the data transmission is completed, the control unit of the storage device can verify the input and output data and obtain the verification data of the input and output data. According to the actual setting, the control unit of the storage device can verify the input and output data after controlling the internal buffer area of ​​the storage device to transfer the input and output data to the internal buffer area of ​​the storage medium, or can verify the input and output data after the input and output data are transmitted according to the transmission mode of the input and output data, and this embodiment does not limit it.

[0116] The verification process of input and output data also requires a high data processing bandwidth, so the control unit of the storage device can use the cache area to complete the verification process of input and output data and obtain the verification data of the input and output data. In this embodiment, the cache area is an SRAM cache area.

[0117] In one possible scenario, according to actual needs, the SRAM cache area is divided into two data cache areas, namely the input and output data cache area and the verification data cache area. Therefore, in this step, the control unit of the storage device can use the verification data cache area in the SRAM to verify the input and output data.

[0118] In this step, the control unit of the storage device can use various existing verification methods to verify the input and output data, such as BBC (Block Check Character) XOR verification method, cyclic redundancy check (CRC, Cyclic Redundancy Check), ECC (Error Checking and Correcting) verification method, parity check, etc., which are not limited in this embodiment.

[0119] Step S604: determine the verification data as the data to be written.

[0120] After obtaining the verification data of the input and output data, the control unit of the storage device may determine the verification data as the data to be written.

[0121] Step S605, temporarily storing the data to be written into the source buffer area.

[0122] After obtaining the verification data of the input and output data, the control unit of the storage device can directly temporarily store the verification data of the input and output data in the internal cache area of ​​the control unit, which can be specifically the high-speed cache area of ​​the control unit. In this embodiment, the high-speed cache area can be an SRAM cache area. Further, the control unit of the storage device can temporarily store the verification data of the input and output data in the verification data cache area in the SRAM of the control unit.

[0123] Step S606: Control the source buffer area to transfer the data to be written to the target buffer area.

[0124] In actual applications, the storage device will also receive other types of data processing requests sent by the host, such as data read requests, data erase requests, etc. These data processing requests will be stored in the request queue so that the storage device can perform corresponding operations according to the principle of First Input First Output (FIFO). Therefore, when the number of requests is large, it will cause a high load on the storage medium of the storage device, and cause the data in the cache area of ​​the storage device to be unable to be transferred to the internal cache area of ​​the storage medium, thereby reducing the data processing capacity of the cache area. At the same time, the verification data of the input and output data does not have a high requirement for the write bandwidth.

[0125] Therefore, in order to ensure the data processing capability of the source cache area, the control unit of the storage device can control the cache area to transfer the check data of the input and output data to the non-cache area to reduce the time occupied by the check data of the input and output data in the cache area. The non-cache area can be a DDR cache area.

[0126] In one possible scenario, the DDR cache area is divided into multiple data cache areas, including a verification data cache area. Therefore, in this step, the control unit of the storage device can determine the verification data cache area in the DDR as the target cache area, and control the verification data cache area in the SRAM to transfer the verification data of the input and output data to the verification data cache area in the DDR.

[0127] Step S607, in response to the completion of the transmission of the data to be written, releasing the source buffer area.

[0128] In this step, the control unit of the storage device can modify the available state of the cache area of ​​the control unit to available after determining that the state flag of the source cache area or the target cache area indicates that the verification data of the input and output data has been transmitted, so as to release the cache area of ​​the control unit. Specifically, the storage device can modify the available state of the verification data cache area in the SRAM to available.

[0129] Step S608: Control the target buffer area to write the data to be written into the storage medium of the storage device.

[0130] Both the cache area and the non-cache area are internal cache areas of the control unit. Therefore, in this step, the control unit of the storage device can first control the target cache area to transfer the data to be written to the internal cache area of ​​the storage medium, and then control the storage medium of the storage device to write the data to be written into the corresponding storage unit, thereby completing the writing process of the verification data of the input and output data.

[0131] Optionally, the control unit of the storage device may release the target cache area after receiving a transmission completion signal sent by the storage medium, or may release the target cache area after receiving a write completion signal sent by the storage medium, which is not limited in this embodiment. The release method of the target cache area is similar to the release method of the source cache area, and will not be repeated here.

[0132] Figure 7 It is a schematic diagram of the existing data writing process. It is easy to understand that the process of generating verification data can refer to this embodiment. Figure 7 It will not be elaborated in detail. After the verification data of the I / O data is temporarily stored in the source buffer area, that is, the verification data buffer area 1142 of the SRAM, in step S71, the verification data buffer area 1142 of the SRAM is controlled to transfer the verification data of the I / O data to the buffer area 121 of the NAND storage medium 12. In step S72, after the verification data of the I / O data is transmitted, the NAND storage medium 12 can send a transmission completion signal of the verification data of the I / O data to the BE module 113, that is, DMA Done. In step S73, after the verification data of the I / O data is written, the NAND storage medium 12 can send a writing completion signal of the verification data of the I / O data to the BE module 113, that is, NAND Done. In step S74, after receiving the writing completion signal of the verification data of the I / O data, the BE module 113 can modify the available state of the verification data buffer area 1142 of the SRAM to available to release the verification data buffer area 1142 of the SRAM.

[0133] Figure 8 Schematic diagram of the data writing process of the embodiment of the present invention. It is easy to understand that the process of generating the verification data can also refer to this embodiment. Figure 8It will not be described in detail. After the check data of the I / O data is temporarily stored in the source buffer area, that is, the check data buffer area 1142 of the SRAM, in step S81, the BE module 113 controls the check data buffer area 1142 of the SRAM to transfer the check data of the I / O data to the DDR115, which can be specifically the check data buffer area 1151 of the DDR. In step S82, after determining that the check data of the I / O data has been transmitted, the BE module 113 can modify the available state of the check data buffer area 1142 of the SRAM to available, so as to release the check data buffer area 1142 of the SRAM. In step S83, the BE module 113 controls the check data buffer area 1151 of the DDR to transfer the check data of the I / O data to the buffer area 121 of the NAND storage medium 12. In step S84, after the check data of the I / O data has been transmitted, the NAND storage medium 12 can send a transmission completion signal of the check data of the I / O data to the BE module 113, that is, DMA Done. In step S85 , after the verification data of the I / O data is written, the NAND storage medium 12 may send a writing completion signal of the verification data of the I / O data, ie, NANDDone, to the BE module 113 .

[0134] By comparison Figure 7 and Figure 8 It can be determined that the embodiment of the present invention advances the release timing of the cache area of ​​the control unit from after receiving the write completion signal of the verification data of the input and output data or after receiving the transmission completion signal of the verification data of the input and output data to after the verification data of the input and output data is transmitted to the non-cache area, and controls the non-cache area to complete the subsequent data writing process, thereby effectively reducing the occupation time of the internal cache area of ​​the control unit by the input and output data, and improving the utilization rate of the internal cache area of ​​the control unit, thereby effectively improving the writing efficiency of the input and output data.

[0135] After the control unit of the storage device of the embodiment of the present invention temporarily stores the data to be written in the source buffer area, it controls the source buffer area to transfer the data to be written to the target buffer area, and after the data to be written is transmitted, it releases the source buffer area, and then controls the target buffer area to write the data to be written into the storage medium of the storage device. The embodiment of the present invention reduces the occupation time of the source buffer area by releasing the source buffer area after the data transmission is completed, so that the data writing efficiency can be improved.

[0136] Fig. 9 Schematic diagram of a data writing device according to an embodiment of the present invention, which is applicable to a control unit of a storage device. Fig. 9 As shown, the data writing device of this embodiment includes a data temporary storage module 901 , a data transmission module 902 , a release module 903 and a data writing module 904 .

[0137] Among them, the data temporary storage module 901 is used to temporarily store the data to be written in the source cache area; the data transmission module 902 is used to control the source cache area to transfer the data to be written to the target cache area; the release module 903 is used to release the source cache area in response to the completion of the transmission of the data to be written; the data writing module 904 is used to control the target cache area to write the data to be written into the storage medium of the storage device.

[0138] After the control unit of the storage device of the embodiment of the present invention temporarily stores the data to be written in the source buffer area, it controls the source buffer area to transfer the data to be written to the target buffer area, and after the data to be written is transmitted, it releases the source buffer area, and then controls the target buffer area to write the data to be written into the storage medium of the storage device. The embodiment of the present invention reduces the occupation time of the source buffer area by releasing the source buffer area after the data transmission is completed, so that the data writing efficiency can be improved.

[0139] Fig.10 Schematic diagram of a data access system according to an embodiment of the present invention. Fig.10 As shown, the data access system includes a host 1001 and a storage device 1002. The host 1001 is configured to send a data write request to the storage device 1002. The host 1001 and the storage device 1002 can be connected to each other through a corresponding bus 1003. The storage device 1002 includes at least a plurality of cache areas and a storage medium, and the plurality of cache areas include a source cache area and a target cache area. The specific circuit structure can be referred to Figure 1 The control unit in the storage device 1002 can execute corresponding instructions to implement the above data writing method.

[0140] The above-mentioned product can execute the method provided in the embodiment of the present application, and has the functional modules and beneficial effects corresponding to the execution method. For technical details not fully described in this embodiment, please refer to the method provided in the embodiment of the present application.

[0141] After the control unit of the storage device of the embodiment of the present invention temporarily stores the data to be written in the source buffer area, it controls the source buffer area to transfer the data to be written to the target buffer area, and after the data to be written is transmitted, it releases the source buffer area, and then controls the target buffer area to write the data to be written into the storage medium of the storage device. The embodiment of the present invention reduces the occupation time of the source buffer area by releasing the source buffer area after the data transmission is completed, so that the data writing efficiency can be improved.

[0142] Another embodiment of the present invention relates to a non-volatile storage medium for storing a computer-readable program, wherein the computer-readable program is used for a computer to execute part or all of the above method embodiments.

[0143] That is, those skilled in the art can understand that all or part of the steps in the above-mentioned embodiment method can be completed by instructing the relevant hardware through a program, and the program is stored in a storage medium, including a number of instructions to enable a device (which can be a single-chip microcomputer, chip, etc.) or a processor to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk and other media that can store program codes.

[0144] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A data writing method, applicable to a control unit of a storage device, characterized in that: The method comprises: Temporarily store the data to be written into the source buffer area; Controlling the source buffer area to transfer the to-be-written data to the target buffer area; In response to completion of transmission of the data to be written, releasing the source buffer area; The target buffer area is controlled to write the data to be written into the storage medium of the storage device.

2. The method according to claim 1, characterized in that The method further comprises: Receive data writing request; The data writing request is parsed to obtain the data to be written in the data writing request.

3. The method according to claim 2, characterized in that The data to be written is input / output data, the source buffer area is an input / output data buffer area in a static random access memory of the control unit, and the target buffer area is an internal buffer area of ​​the storage medium.

4. The method according to claim 3, characterized in that The controlling the source buffer area to transfer the to-be-written data to the target buffer area comprises: The source buffer area is controlled to transfer the to-be-written data to the target buffer area through a direct memory access method.

5. The method according to claim 4, characterized in that In response to the data to be written being transmitted being completed, releasing the source buffer area comprises: In response to receiving a transmission completion signal of the data to be written, the available state of the source buffer area is modified to available.

6. The method according to claim 1, characterized in that The method further comprises: Receive data writing request; Parsing the data writing request to obtain target data in the data writing request; Verifying the target data to obtain verification data of the target data; The verification data is determined as the data to be written.

7. The method according to claim 6, characterized in that The data to be written is verification data of input and output data, the source buffer area is the verification data buffer area in the static random access memory of the control unit, and the target buffer area is the verification data buffer area in the dynamic random access memory of the control unit.

8. The method according to claim 7, characterized in that The controlling the target buffer area to write the to-be-written data into the storage medium of the storage device comprises: Controlling the target buffer area to transfer the to-be-written data to the internal buffer area of ​​the storage medium; The internal buffer area is controlled to write the data to be written into the storage medium.

9. A storage device, characterized in that: The storage device comprises: Storage media; Multiple buffers, including a source buffer and a target buffer for data to be written; A control unit is configured to temporarily store the data to be written in a source cache area, send a data transfer instruction to the source cache area to control the source cache area to transfer the data to be written to a target cache area, release the source cache area in response to the completion of the transmission of the data to be written, and send a data write request to the target cache area to control the target cache area to write the data to be written into the storage medium.

10. A data writing system, characterized in that: The data writing system comprises: The storage device as claimed in claim 9; The host is configured to send a data write request to the storage device.

11. A data writing device, suitable for a control unit of a storage device, characterized in that: The device comprises: A data temporary storage module, used to temporarily store the data to be written into the source buffer area; A data transmission module, used for controlling the source buffer area to transmit the to-be-written data to the target buffer area; A release module, configured to release the source buffer area in response to completion of transmission of the data to be written; The data writing module is used to control the target buffer area to write the data to be written into the storage medium of the storage device.

12. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the method according to any one of claims 1 to 8 is implemented.

13. A computer program product, characterized in that When the computer program product is run on a computer, the computer is caused to execute the method according to any one of claims 1 to 8.

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