Analog-to-digital conversion system, automatic gain selection method, and gain deviation calibration method

Abstract

The present invention relates to the field of analog-to-digital conversion technology, and provides an analog-to-digital conversion system, an automatic gain selection method, and a gain deviation calibration method. The analog-to-digital conversion system includes: a main analog-to-digital converter, an auxiliary analog-to-digital converter, a gain selection module, and a recovery module. The main analog-to-digital converter and the auxiliary analog-to-digital converter both include sampling capacitors and conversion capacitor arrays. The auxiliary analog-to-digital converter samples the input signal simultaneously with the main analog-to-digital converter, and the auxiliary analog-to-digital converter preferentially pre-converts the sampled signal to obtain a pre-conversion result. The gain selection module is used to determine the position of the current input signal in the full scale of the main analog-to-digital converter according to the pre-conversion result of the auxiliary analog-to-digital converter, thereby determining the number of sampling capacitors that the main analog-to-digital converter needs to connect to sample the current input signal, so as to adjust the gain of the main analog-to-digital converter. The present invention can ensure that each sampling point does not cause ADC overload or accuracy reduction, and ensure that all signals can obtain high-precision sampling.

Description

Technical Field

[0001] The present invention relates to the technical field of analog-to-digital conversion, and in particular to an analog-to-digital conversion system, an automatic gain selection method, and a gain deviation calibration method. Background Art

[0002] In an analog-to-digital converter chip, a signal conditioning circuit (such as an amplifier) ​​is usually added in front of the ADC (Analogue to Digital Converter) core to condition the signal to an amplitude suitable for conversion by the ADC.

[0003] like Figure 1 As shown, it is assumed that the signal that the signal chain needs to process is a ±10V single-ended signal. The full scale of the ADC core is determined by VREF, that is, its differential full scale is ±VREF. If the signal that needs to be processed in the application is a ±5V single-ended signal. If the ±10V range is used, the signal can only occupy half of the dynamic range of the ADC core, which will cause the accuracy of the entire signal chain to drop by half. More extremely, if the signal that needs to be processed is a ±1V single-ended signal, when the same amplification factor as ±10V is used, the accuracy of the entire signal chain will drop to 1 / 10 of the original. To solve this problem, the gain of the amplifier in the signal chain can be set to adjustable. Figure 1 For example, the amplifier gain A = Rf / Rin. For input signals of varying amplitudes, the amplifier gain can be adjusted to maintain optimal signal chain performance. For example, assuming VREF = 4V, and input signal amplitudes of ±10V, ±5V, and ±1V, the amplifier gains are 0.4, 0.8, and 4, respectively, resulting in a ±4V output (differential).

[0004] In current analog-to-digital converter chips, the signal conditioning circuit's gain can be adjusted to maintain high precision when processing different signals. However, before the chip begins analog-to-digital conversion, the signal conditioning circuit's gain must be configured. Once the conversion begins, adjusting the gain requires some time to stabilize due to the amplifier's limited bandwidth. During this time, the converter's output is incorrect, neither matching the gain before nor after the adjustment. Furthermore, existing analog-to-digital converter chips cannot automatically adjust the amplifier's gain based on the input signal's amplitude to ensure high-precision sampling for all signals.

[0005] In the fields of communications, the system automatically adjusts the gain of the signal conditioning circuit by setting up an automatic gain control (AGC) circuit. Figure 2As shown in the figure, the DSP (digital signal processing) module behind the ADC core analyzes the amplitude of the ADC core's data to determine whether the input signal exceeds the full-scale range of the ADC chip at that time or is far below the full-scale range of the ADC chip. This determines whether the gain of the signal conditioning circuit should be reduced or increased. However, this method cannot guarantee that every transition point of the ADC is optimal, because the system needs to determine the gain of subsequent transition points based on the amplitude of the previous conversion result. In practical applications, this approach is prone to inference errors, causing some points to exceed or fall far below the full-scale range of the ADC core. Summary of the Invention

[0006] In order to solve the above technical defects, the present invention provides an analog-to-digital conversion system and a gain deviation calibration method.

[0007] In one aspect, the present invention provides an analog-to-digital conversion system, comprising: a main analog-to-digital converter, an auxiliary analog-to-digital converter, a gain selection module, and a recovery module, wherein the main analog-to-digital converter and the auxiliary analog-to-digital converter both include a sampling capacitor and a conversion capacitor array;

[0008] The auxiliary analog-to-digital converter and the main analog-to-digital converter sample the input signal simultaneously, and the auxiliary analog-to-digital converter preferentially pre-converts the sampled signal to obtain a pre-conversion result;

[0009] The gain selection module is used to determine the position of the current input signal corresponding to the full scale of the main analog-to-digital converter based on the pre-conversion result of the auxiliary analog-to-digital converter, and determine the number of sampling capacitors that need to be connected to the main analog-to-digital converter to sample the current input signal based on the position of the current input signal corresponding to the full scale of the main analog-to-digital converter, so as to adjust the gain of the main analog-to-digital converter;

[0010] The recovery module is used to restore the conversion result of the main analog-to-digital converter after gain adjustment to a result corresponding to the standard range of the main analog-to-digital converter.

[0011] In an embodiment of the present invention, the main analog-to-digital converter includes n groups of sampling capacitors and a group of conversion capacitor arrays, and each group of sampling capacitors includes a positive-end sampling capacitor and a negative-end sampling capacitor.

[0012] In the embodiment of the present invention, the capacitance value of the conversion capacitor array of the main analog-to-digital converter is set in a form of successive approximation.

[0013] In an embodiment of the present invention, at least one redundant capacitor is provided in the conversion capacitor array of the main analog-to-digital converter.

[0014] In the embodiment of the present invention, the capacitance value multiple relationship of each capacitor in the conversion capacitor array of the main analog-to-digital converter is less than 2.

[0015] In an embodiment of the present invention, the auxiliary analog-to-digital converter includes at least one group of sampling capacitors and one group of conversion capacitor arrays, and each group of sampling capacitors includes a positive-end sampling capacitor and a negative-end sampling capacitor.

[0016] In an embodiment of the present invention, the number of sampling capacitors of the auxiliary analog-to-digital converter is less than the number of sampling capacitors of the main analog-to-digital converter;

[0017] The number of bits of the conversion capacitor array of the auxiliary analog-to-digital converter is less than the number of bits of the conversion capacitor array of the main analog-to-digital converter.

[0018] In an embodiment of the present invention, in the first stage working sequence of the analog-to-digital conversion system, the lower plate of the sampling capacitor of the main analog-to-digital converter is connected to the input signal, the lower plate of the conversion capacitor of the main analog-to-digital converter is connected to the common-mode voltage, the lower plate of the sampling capacitor of the auxiliary analog-to-digital converter is connected to the input signal, and the lower plate of the conversion capacitor of the auxiliary analog-to-digital converter is connected to the common-mode voltage.

[0019] In an embodiment of the present invention, in the second phase operation sequence of the analog-to-digital conversion system, upon receiving a sampling end signal, the upper plate of the sampling capacitor of the auxiliary analog-to-digital converter and the upper plate of the conversion capacitor are disconnected from the common mode voltage; after the upper plate of the sampling capacitor of the main analog-to-digital converter is disconnected from the common mode voltage, the upper plate of the conversion capacitor of the main analog-to-digital converter is disconnected from the common mode voltage;

[0020] After the upper plates of the sampling capacitors of the auxiliary analog-to-digital converter and the main analog-to-digital converter are disconnected from the common-mode voltage, the lower plates of the sampling capacitors of the auxiliary analog-to-digital converter and the main analog-to-digital converter are disconnected from the input signal, and the auxiliary analog-to-digital converter performs successive approximation conversion to obtain a pre-conversion result.

[0021] In the embodiment of the present invention, in the third phase operation sequence of the analog-to-digital conversion system, how many sampling capacitors in the main analog-to-digital converter are connected to the circuit of the main analog-to-digital converter is determined according to the pre-conversion result of the auxiliary analog-to-digital converter.

[0022] In an embodiment of the present invention, determining how many sampling capacitors in a main analog-to-digital converter are connected to a circuit of the main analog-to-digital converter based on a pre-conversion result of the auxiliary analog-to-digital converter includes selecting a combination of sampling capacitors corresponding to a maximum gain based on the pre-conversion result of the auxiliary analog-to-digital converter and a proportional relationship between the capacitance values ​​of the sampling capacitors, and connecting the sampling capacitors of this combination to the circuit of the main analog-to-digital converter.

[0023] In the embodiment of the present invention, in the fourth phase working sequence of the analog-to-digital conversion system, the lower plate of the conversion capacitor of the main analog-to-digital converter is connected to the reference voltage, and the final conversion result is obtained through successive approximation conversion.

[0024] In the embodiment of the present invention, in the fifth phase of the working sequence of the analog-to-digital conversion system, the final conversion result is restored to a code value of a standard range by a recovery module.

[0025] In the embodiment of the present invention, in the sixth phase of the operation sequence of the analog-to-digital conversion system, each capacitor of the main analog-to-digital converter and the auxiliary analog-to-digital converter is reset, and the system enters the next sampling phase.

[0026] In the embodiment of the present invention, the conversion capacitor of the main analog-to-digital converter is a segmented capacitor, and the conversion capacitors of each segment are connected via a bridge capacitor.

[0027] In the embodiment of the present invention, the main analog-to-digital converter is a two-stage analog-to-digital converter, the conversion capacitor of the first-stage analog-to-digital converter has n bits, and the conversion capacitor of the second-stage analog-to-digital converter has m bits.

[0028] In an embodiment of the present invention, the system further comprises: a linear-to-logarithmic module, configured to convert the voltage of the input signal into a logarithmic voltage;

[0029] The auxiliary analog-to-digital converter converts the logarithmic voltage to obtain a logarithmic value conversion result.

[0030] In an embodiment of the present invention, the linear-to-logarithmic module includes: a first amplifier, a current mirror, a transistor, and a second amplifier; the negative input terminal of the first amplifier is connected to the input signal, the output terminal of the first amplifier is connected to the input terminal of the second amplifier and the emitter of the transistor through the current mirror, and the base and collector of the transistor are grounded.

[0031] In an embodiment of the present invention, the current mirror includes a first transistor M1 and a second transistor M2. The gate of the first transistor M1 is connected to the gate of the second transistor M2 and is connected to the output end of the first amplifier. The source of the first transistor M1 and the source of the second transistor M2 are connected to the power supply end VDD. The drain of the first transistor M1 is grounded via a resistor R1. The drain of the second transistor M2 is connected to the input end of the second amplifier and the emitter of the transistor.

[0032] In an embodiment of the present invention, the system further includes: an exponential conversion module, configured to convert a logarithmic value conversion result obtained by the auxiliary analog-to-digital converter into a linear conversion result.

[0033] Another aspect of the present invention provides a method for automatically selecting a gain of the analog-to-digital conversion system, comprising:

[0034] The auxiliary analog-to-digital converter and the main analog-to-digital converter sample the input signal simultaneously, and the auxiliary analog-to-digital converter is used to pre-convert the sampled signal to obtain a pre-conversion result;

[0035] The gain selection module determines the position of the current input signal in the full scale of the main analog-to-digital converter according to the pre-conversion result of the auxiliary analog-to-digital converter, and determines the number of sampling capacitors that need to be connected to the main analog-to-digital converter to sample the current input signal according to the position of the current input signal in the full scale of the main analog-to-digital converter, so as to achieve gain selection of the main analog-to-digital converter;

[0036] The recovery module is used to restore the conversion result of the main analog-to-digital converter after gain adjustment to a result corresponding to the standard range of the main analog-to-digital converter.

[0037] Furthermore, the auxiliary analog-to-digital converter and the main analog-to-digital converter simultaneously sample the input signal, and the auxiliary analog-to-digital converter preferentially pre-converts the sampled signal to obtain a pre-conversion result, including:

[0038] During the sampling phase, the lower plate of the sampling capacitor of the main analog-to-digital converter is connected to the input signal, the lower plate of the conversion capacitor of the main analog-to-digital converter is connected to the common mode voltage, the lower plate of the sampling capacitor of the auxiliary analog-to-digital converter is connected to the input signal, and the lower plate of the conversion capacitor of the auxiliary analog-to-digital converter is connected to the common mode voltage;

[0039] At the end of sampling, the upper plate of the sampling capacitor of the auxiliary analog-to-digital converter and the upper plate of the conversion capacitor are disconnected from the common mode voltage; after the upper plate of the sampling capacitor of the main analog-to-digital converter is disconnected from the common mode voltage, the upper plate of the conversion capacitor of the main analog-to-digital converter is disconnected from the common mode voltage; after the upper plates of the sampling capacitors of the auxiliary analog-to-digital converter and the main analog-to-digital converter are disconnected from the common mode voltage, the lower plates of the sampling capacitors of the auxiliary analog-to-digital converter and the main analog-to-digital converter are disconnected from the input signal, and the auxiliary analog-to-digital converter performs successive approximation conversion to obtain a pre-conversion result.

[0040] Furthermore, the number of sampling capacitors required to be connected to the main analog-to-digital converter for sampling the current input signal is determined based on the pre-conversion result of the auxiliary analog-to-digital converter, including: selecting a combination of sampling capacitors corresponding to the maximum gain based on the pre-conversion result of the auxiliary analog-to-digital converter and the proportional relationship between the capacitance values ​​of the respective sampling capacitors, and connecting the sampling capacitors of this combination to the circuit of the main analog-to-digital converter to achieve gain selection of the main analog-to-digital converter.

[0041] Furthermore, a recovery module is used to restore the conversion result of the main analog-to-digital converter after gain adjustment to a result corresponding to the standard range of the main analog-to-digital converter, including: after sampling is completed, connecting the lower plate of the conversion capacitor of the main analog-to-digital converter to a reference voltage, and obtaining the final conversion result through successive approximation conversion; and restoring the final conversion result to a code value of the standard range through the recovery module.

[0042] Furthermore, after the voltage of the input signal is converted into a logarithmic voltage by the linear-to-logarithmic module, the logarithmic voltage is converted by the auxiliary analog-to-digital converter to obtain a logarithmic value conversion result;

[0043] The logarithmic conversion result obtained by the auxiliary analog-to-digital converter is converted into a linear conversion result through the exponential conversion module.

[0044] The present invention also provides a gain deviation calibration method for the above analog-to-digital conversion system, the method comprising:

[0045] Get the actual weight of the total sampling capacitance;

[0046] Get the actual weight of the highest weight capacitor of the conversion capacitor;

[0047] The actual gain is obtained according to the actual weight of the total sampling capacitor and the actual weight of the highest weight capacitor of the conversion capacitor;

[0048] Replace the original gain with the actual gain.

[0049] In the embodiment of the present invention, obtaining the actual weight of the total sampling capacitance includes:

[0050] During the sampling phase, the sampling capacitor to be calibrated is connected to the upper reference voltage, and the remaining capacitors are connected to the lower reference voltage;

[0051] Connect the sampling capacitor to be calibrated to the common mode voltage and convert it in a successive approximation manner to obtain a digital code starting from the lowest bit.

[0052] Obtaining actual weights of the respective sampling capacitors according to the digital code starting from the least significant bit and the actual weights of the capacitors starting from the least significant bit;

[0053] The actual weights of the individual sampling capacitors are added together to obtain the actual weight of the total sampling capacitor.

[0054] In the embodiment of the present invention, obtaining the actual weight of the highest weight capacitor of the conversion capacitor includes:

[0055] During the sampling phase, the highest weight capacitor in the conversion capacitor is connected to the reference voltage;

[0056] After sampling, the highest-weight capacitor in the conversion capacitor is connected to the common-mode voltage, and the other capacitors in the conversion capacitor are successively converted to obtain the digital code of each bit.

[0057] According to the digital code of each bit and the actual weight of each capacitor, the actual weight of the highest weight capacitor of the conversion capacitor is obtained.

[0058] In the embodiment of the present invention, the ratio of the actual weight of the total sampling capacitor to the actual weight of the highest weight capacitor of the conversion capacitor is used as the actual gain.

[0059] The present invention also provides a chip, which includes the above analog-to-digital conversion system.

[0060] In the analog-to-digital conversion system of the present invention, during the sampling phase, the auxiliary analog-to-digital converter and the main analog-to-digital converter simultaneously sample the input signal. The auxiliary analog-to-digital converter preferentially pre-converts the sampled signal to obtain a pre-conversion result. A gain selection module then determines the position of the current input signal within the full scale of the main analog-to-digital converter based on the pre-conversion result, thereby determining the number of sampling capacitors required to be connected to the main analog-to-digital converter to sample the current input signal, and further adjusting the gain of the main analog-to-digital converter. The analog-to-digital conversion system of the present invention can automatically detect the amplitude of the input signal and automatically adjust the gain of the ADC based on the amplitude of the input signal, thereby better utilizing the dynamic range of the ADC, reducing quantization noise, and improving the accuracy of the analog-to-digital conversion. Because the gain is determined and adjusted at the current sampling point rather than through methods such as data statistics, the analog-to-digital conversion system of the present invention can ensure that each sampling point does not cause ADC overload or accuracy degradation, ensuring that all signals can be sampled with high precision, meeting the industrial demand for accuracy at each sampling point.

[0061] Other features and advantages of the technical solution of the present invention will be described in detail in the specific implementation section below. BRIEF DESCRIPTION OF THE DRAWINGS

[0062] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0063] Figure 1 It is an existing analog-to-digital conversion structure;

[0064] Figure 2 It is another existing analog-to-digital conversion structure;

[0065] Figure 3 is an architecture diagram of an analog-to-digital conversion system provided in Embodiment 1 of the present invention;

[0066] Figure 4 1 is a schematic structural diagram of a main analog-to-digital converter (main ADC) of the analog-to-digital conversion system provided in the first embodiment of the present invention;

[0067] Figure 5 1 is a schematic structural diagram of an auxiliary analog-to-digital converter (Sub-ADC) of an analog-to-digital conversion system provided in a first embodiment of the present invention;

[0068] Figure 6 This is a working timing diagram of the analog-to-digital conversion system provided in the first embodiment of the present invention;

[0069] Figure 7 1 is a schematic diagram of the connection state of the main analog-to-digital converter (main ADC) in the sampling phase provided by the first embodiment of the present invention;

[0070] Figure 8 1 is a schematic diagram of the connection state of the auxiliary analog-to-digital converter (Sub-ADC) provided in the sampling phase according to the first embodiment of the present invention;

[0071] Figure 9 1 is a schematic diagram comparing the signal-to-noise ratio of the analog-to-digital conversion system provided in the first embodiment of the present invention and the signal-to-noise ratio of a traditional ADC;

[0072] Figure 10 is a structural diagram of an analog-to-digital conversion system provided in Embodiment 2 of the present invention;

[0073] Figure 11 1 is a schematic structural diagram of an analog-to-digital conversion system provided in Embodiment 3 of the present invention;

[0074] Figure 12 1 is a schematic structural diagram of an analog-to-digital conversion system provided in a fourth embodiment of the present invention;

[0075] Figure 13 1 is a circuit schematic diagram of a linear-to-logarithmic module of an analog-to-digital conversion system provided in a fourth embodiment of the present invention;

[0076] Figure 14 1 is a schematic structural diagram of an analog-to-digital conversion system provided in a fifth embodiment of the present invention;

[0077] Figure 15 1 is a schematic structural diagram of an analog-to-digital conversion system provided in a sixth embodiment of the present invention;

[0078] Figure 16 is a flow chart of a gain deviation calibration method provided in Embodiment 7 of the present invention;

[0079] Figure 17 1 is a signal connection diagram of an analog-to-digital conversion system corresponding to sampling capacitor calibration of a gain deviation calibration method provided in a seventh embodiment of the present invention. DETAILED DESCRIPTION

[0080] To make the technical solutions and advantages of the embodiments of the present invention more clearly understood, exemplary embodiments of the present invention are further described in detail below with reference to the accompanying drawings. It should be noted that the embodiments described are only a portion of the embodiments of the present invention, and are not an exhaustive list of all embodiments. It should be noted that the embodiments of the present invention and the features thereof may be combined with each other unless they conflict.

[0081] In the description of the present invention, it should be understood that the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, "plurality" means at least two, for example, two, three, etc., unless otherwise specifically defined.

[0082] In the present invention, unless otherwise expressly specified or limited, terms such as "connected" and "connection" should be understood in a broad sense. For example, they may refer to fixed or detachable connections, or integration; mechanical or electrical connections, or communication; direct or indirect connections through an intermediate medium; and internal communication between two components or interaction between two components. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on specific circumstances.

[0083] As described in the background technology, in existing analog-to-digital converter chips, the automatic gain control (AGC) needs to judge the amplitude of the previous conversion result and then determine the gain of the subsequent conversion point. In practical applications, this can easily lead to inference errors, causing some points to exceed or be far less than the full scale of the ADC core. As a result, it is impossible to ensure that each conversion point of the analog-to-digital converter is optimal, that is, it cannot guarantee that all signals can obtain high-precision sampling.

[0084] In response to the above problems, an embodiment of the present invention provides an analog-to-digital conversion system, comprising: a main analog-to-digital converter, an auxiliary analog-to-digital converter, and a gain selection module. In the sampling phase, the auxiliary analog-to-digital converter and the main analog-to-digital converter simultaneously sample the input signal. The auxiliary analog-to-digital converter is used to pre-convert the sampled signal to obtain a pre-conversion result. The gain selection module is then used to determine the position of the current input signal in the full scale of the main analog-to-digital converter based on the pre-conversion result, thereby determining the number of sampling capacitors required for the main analog-to-digital converter to sample the current input signal, and then adjusting the gain of the main analog-to-digital converter. The analog-to-digital conversion system of the present invention can automatically detect the amplitude of the input signal and automatically adjust the gain of the ADC according to the amplitude of the input signal, thereby better utilizing the dynamic range of the ADC, reducing quantization noise, and improving the accuracy of the analog-to-digital conversion. Since the judgment and gain adjustment are made at the current sampling point, rather than adjusting the gain through data statistics or other methods, the analog-to-digital conversion system of the present invention can ensure that each sampling point does not cause ADC overload or accuracy reduction, ensuring that all signals can obtain high-precision sampling, meeting the industrial demand for accuracy at each sampling point.

[0085] Example 1

[0086] like Figure 3As shown, the analog-to-digital conversion system provided in this embodiment includes: a main analog-to-digital converter, an auxiliary analog-to-digital converter, a gain selection module and a recovery module. The main analog-to-digital converter and the auxiliary analog-to-digital converter both include sampling capacitors and conversion capacitor arrays; the auxiliary analog-to-digital converter and the main analog-to-digital converter simultaneously sample the input signal, and the auxiliary analog-to-digital converter preferentially pre-converts the sampled signal to obtain a pre-conversion result; the gain selection module is used to determine the position of the current input signal in the full scale of the main analog-to-digital converter corresponding to the pre-conversion result of the auxiliary analog-to-digital converter, and determine the number of sampling capacitors that need to be connected to the main analog-to-digital converter to sample the current input signal according to the position of the current input signal in the full scale of the main analog-to-digital converter, so as to adjust the gain of the main analog-to-digital converter; the recovery module is used to restore the conversion result of the main analog-to-digital converter after gain adjustment to the result corresponding to the standard range of the main analog-to-digital converter.

[0087] like Figure 4 As shown, the main analog-to-digital converter of the analog-to-digital conversion system includes n groups of sampling capacitors and a group of conversion capacitor arrays. Each group of sampling capacitors includes a positive sampling capacitor and a negative sampling capacitor. The n positive sampling capacitors are Csp1, Csp1, ..., Cspn, and the n negative sampling capacitors are Csn1, Csn1, ..., Csnn. The conversion capacitor array is set after the sampling capacitors, and the capacitance value of the conversion capacitor array is set in the form of successive approximation, for example, according to the capacitor array form of SAR ADC (successive approximation register ADC, successive approximation analog-to-digital converter). In this embodiment, the capacitance value of the conversion capacitor array is 2 n *Cu, 2 (n-1) *Cu, 2 (n-2) *Cu, ..., 2*Cu, Cu. At least one redundant capacitor may be provided in the conversion capacitor array of the main analog-to-digital converter; or the capacitance value multiple of each capacitor in the conversion capacitor array may be less than 2 to improve the fault tolerance of the conversion.

[0088] like Figure 5As shown, the auxiliary analog-to-digital converter of the analog-to-digital conversion system includes at least one group of sampling capacitors and a group of conversion capacitor arrays, and each group of sampling capacitors includes a positive sampling capacitor and a negative sampling capacitor. The number of sampling capacitors of the auxiliary analog-to-digital converter is less than the number of sampling capacitors of the main analog-to-digital converter, and the number of bits of the conversion capacitor array of the auxiliary analog-to-digital converter is less than the number of bits of the conversion capacitor array of the main analog-to-digital converter, that is, the accuracy of the auxiliary analog-to-digital converter is lower than the accuracy of the main analog-to-digital converter. The auxiliary analog-to-digital converter can select a low-precision SAR ADC with a low number of bits. In this embodiment, there is only one positive sampling capacitor and one negative sampling capacitor, and the capacitance values ​​of the sampling capacitor and the conversion capacitor are small. For example, the total capacitance of the auxiliary analog-to-digital converter (Sub-ADC) is less than 1pF. The capacitance in the main analog-to-digital converter (main ADC) needs to reach more than ten or even dozens of pF due to the noise affecting the entire signal chain.

[0089] During the sampling phase, the sub-ADC samples alongside the main ADC, with the sub-ADC prioritizing pre-conversion of the sampled signal to produce a pre-conversion result. Based on this pre-conversion result, the sub-ADC can determine the approximate full-scale position of the current signal and, therefore, determine how many sampling capacitors should be connected to the main ADC circuit after sampling. Depending on the number of sampling capacitors used, the main ADC can achieve different gains, maximizing the accuracy of the sampling point. For example, if the sub-ADC detects a low input signal, it connects more sampling capacitors to the circuit, increasing the gain of the main ADC. This reduces the noise level in the main ADC to a level lower than the signal, enabling high-precision sampling. Conversely, if the sub-ADC detects a high input signal, it connects fewer sampling capacitors, resulting in no gain or a reduction in gain for the main ADC to prevent overload.

[0090] like Figure 6 As shown, the work flow of the ADC in the analog-to-digital conversion system provided by this embodiment mainly includes two stages: sampling and conversion, and specifically includes six working timing stages: step1, step2, step3, step4, step5, and step6.

[0091] like Figure 7 As shown, in the sampling phase step 1 working sequence, the lower plates of the sampling capacitors Csp1, Csp2, ..., Cspn, Csn1, Csn2, ..., Csnn of the main ADC are connected to the input signals Vadc_p and Vadc_m, and the lower plates of all the conversion capacitors are connected to VCM (Common Mode Voltage).

[0092] like Figure 8As shown, in the sampling phase step 1 working sequence, the lower plates of the sampling capacitors Csp_aux and Csn_aux of the Sub-ADC are connected to the input signals Vadc_p and Vadc_m, and the lower plates of all the conversion capacitors are connected to VCM.

[0093] In the main ADC, the sampling capacitors Csp1, Csp2, and Cspn can be arranged in a 1:2:n relationship. Different numbers of binary capacitors can also be inserted between the sampling capacitors. For example, if n is 4, Csp1:Csp2:Csp3:Csp4 = 1:2:4:8. The capacitors at the negative terminal of the ADC are also set in this ratio. For example, Csp1 is set to 2*2^n*Cu. Furthermore, during the sampling phase, a portion of the conversion capacitors can be added to the sampling capacitors.

[0094] In Sub-ADC, the relationship between the sampling capacitor Csp_aux and the conversion capacitor is Csp_aux = 2 4 *Cu_aux, which means the sampling capacitor is twice the maximum conversion capacitor. Similarly, during the sampling phase, a portion of the conversion capacitor can be added to the sampling capacitor. Due to the proportional relationship between the capacitors, the gain of the sub-ADC is always maintained at 1.

[0095] In step 2, upon receiving the external sampling end signal, the main ADC and sub-ADC complete sampling and begin successive approximation conversion. During the conversion phase, the top plates of all sub-ADC capacitors (sampling capacitors and conversion capacitor array) are disconnected from VCM. Disconnecting the top plates of the main ADC capacitors is done in stages. During the conversion phase, the main ADC first opens switches SW_s(1:n), freezing the input signal on the sampling capacitors. It then disconnects the top plates of the conversion capacitors from VCM.

[0096] In this embodiment, the main ADC and the Sub-ADC adopt a SAR ADC (successive approximation register ADC) with capacitor switching or a monotonically switched SAR ADC. After disconnecting the upper plate of the capacitor in sequence, the connection between the lower plate of the capacitor and the ADC input signal is disconnected. Since the SAR ADC adopts the sampling method of the lower plate sampling (the upper plate is disconnected first and the lower plate is disconnected later), it can effectively avoid the accuracy degradation caused by the switch charge injection. After the sampling capacitor is disconnected from the input signal, the sampling capacitor is connected to VCM. Among them, VCM = 1 / 2*VREFP, VREFP (upper reference voltage) can be selected as 4V or other voltages, and VREFN (lower reference voltage) is generally 0V.

[0097] In this embodiment, the VCM-based Sub-ADC is used as an example for illustration, but other capacitor switching methods are also protected if they are consistent with the method in this application, including but not limited to SAR ADC with traditional capacitor switching method and SAR ADC with monotonic switching. After sampling is completed, the Sub-ADC performs successive approximation conversion first to obtain the pre-conversion result code_Sub. Taking the 5-bit Sub-ADC as an example, after sampling is completed, for the VCM-based ADC structure, a comparison can be performed immediately, and the result is recorded as d4; if d4=1, it means that Vadc_p>Vadc_m. At this time, the lower plate of the highest bit of the P-end conversion capacitor is connected to the upper reference voltage VREFP, and the lower plate of the highest bit of the N-end conversion capacitor is connected to the lower reference voltage VREFN. The comparator then compares and obtains d3~d0 according to the successive approximation method. The Sub-ADC obtains the conversion result code_Sub= <d4:d0>; The 5-bit Sub-ADC can determine where the current input signal is in the full scale.

[0098] In step 3, the sub-ADC conversion result, code_Sub, determines the number of sampling capacitors connected to the main ADC circuit. For the main ADC, adding different numbers of sampling capacitors results in different gains. In practice, the main ADC gain can be adjusted to a fractional value by setting the capacitors to a fractional value.

[0099] In this embodiment, the sampling capacitor combination corresponding to the maximum gain is selected based on the conversion results of the sub-ADC and the ratio of the capacitance values ​​of the various sampling capacitors, and this sampling capacitor combination is connected to the main ADC circuit. Taking the sampling capacitor ratio Csp1:Csp2:Csp3:Csp4 = 1:2:4:8 as an example, the relationship between the sampling capacitors reconnected to the main ADC circuit and the gain of the main ADC is shown in the following table:

[0100] Reconnected sampling capacitor Main ADC gain Csp1 1 Csp2 2 Csp1+Csp2 3 Csp3 4 Csp3+Csp1 5 Csp3+Csp2 6 Csp3+Csp2+Csp1 7 Csp4 8 Csp4+Csp1 9 Csp4+Csp2 10 Csp4+Csp2+Csp1 11 Csp4+Csp3 12 Csp4+Csp3+Csp1 13 Csp4+Csp3+Csp2 14 Csp4+Csp3+Csp2+Csp1 15

[0101] When selecting a magnification, select less than The maximum gain is as follows:

[0102]

[0103]

[0104] Referring to the above table, in step 3, different sampling capacitors are connected to the main ADC circuit according to the selected gain to achieve the corresponding amplification factor.

[0105] In the step 4 working sequence, the main ADC can control the lower plate of the conversion capacitor in the main ADC to connect to the reference voltage VREFP and VREFN according to the result of the comparator in a successive approximation manner, and obtain the final conversion result Code_main through the successive approximation conversion. In other embodiments, the result of the Sub-ADC (5 bits) can also be directly loaded into the first 5 bits of the main ADC after calculation, that is, Code_main(n:n-5)=code_Sub*gain, gain represents gain; the subsequent capacitors are then converted according to the normal successive approximation method, and finally Code_main can also be obtained. In this way, the conversion speed of the main ADC can be accelerated and the conversion power consumption can be reduced. Redundant capacitors can also be set in the main ADC. If there are some errors in the Sub-ADC, the reasonable redundant bits in the main ADC can absorb the errors of the first 5 bits and obtain the correct final result.

[0106] In step 5, the final conversion result can be restored to the standard range code value through the recovery module (dynamic range restorer). The calculation formula is: Code_final = Code_main / gain.

[0107] In step 6, the user can read the final data Code_final, reset the capacitors of the main ADC and sub-ADC, and return to sampling mode to enter the next sampling phase.

[0108] The analog-to-digital conversion system of the present invention can fully utilize the full scale of the main ADC. For the entire signal chain, when the input signal is small, the energy equivalent to the input end of the quantization noise does not increase compared to the traditional method. Figure 9 As shown in the figure, the signal-to-noise ratio (SNR) of a traditional ADC decreases as the input signal decreases. In the analog-to-digital conversion system of the present invention, if the noise of circuits such as the comparator in the ADC accounts for a small proportion, the SNR of the ADC will not decrease as the input signal decreases.

[0109] Example 2

[0110] In one embodiment, as the number of bits of the main ADC increases, a larger resolution can be achieved with smaller capacitors by capacitor segmentation or amplifiers. Figure 10 As shown in the figure, the main ADC's conversion capacitor array is a segmented capacitor. Bridge capacitors Cc divide the main ADC's conversion capacitor array into two segments: the front segment has n bits, and the back segment has m bits. This approach achieves a high bit count without a significant disparity in capacitor ratios. Furthermore, the capacitor array can be divided into more segments by adding more bridge capacitors Cc, achieving even higher resolution.

[0111] Example 3

[0112] like Figure 11 As shown, this embodiment provides a two-stage analog-to-digital conversion system. A two-stage ADC is formed using an interstage amplifier. The conversion capacitors of the first-stage ADC have n bits, and the conversion capacitors of the second-stage ADC have m bits. Redundant capacitors can be added to either the first-stage ADC or the second-stage ADC. Using a two-stage ADC can increase ADC accuracy, achieving an n+m-bit ADC.

[0113] Example 4

[0114] Since multiple conversion results corresponding to the same gain may occur during the conversion process of a sub-ADC, the performance of the sub-ADC is not fully utilized. Therefore, an embodiment of the present invention provides a logarithmic ADC.

[0115] like Figure 12 As shown, in Figure 10 Based on the segmented ADC shown in the figure, a linear-to-logarithmic conversion module and an exponential conversion module are added. The corresponding relationship between the conversion result code_Sub of the Sub-ADC and the amplification factor is shown in the following table:

[0116] code_Sub Magnification 8～15-8～-15 1 5～7-5～-7 2 4-4 3 3-3 4 2-2 7 1-1 15

[0117] In one specific example, the voltage data Vin is converted using a linear-to-logarithmic module. For example, the amplitudes of different gears are converted to logarithmic voltages according to the formula Vlog = ln(vin) * 5.77. Sub-ADC conversion is then performed to obtain the logarithmic conversion result code_log. The ADC gain can then be set accordingly according to the table below.

[0118] code_Sub(code_line) code_log Magnification 8～15-8～-15 12～15-12～-15 1 5～7-5～-7 9～11-9～-11 2 4-4 7～8-7～-8 3 3-3 5～6-5～-6 4 2-2 3～4-3～-4 7 1-1 -2～2 15

[0119] In the table above, code_Sub represents the sub-ADC conversion result before logarithmization, and code_log represents the sub-ADC conversion result after logarithmization. As can be seen from the table, taking the logarithm makes the Code_Sub value range for each amplification factor more uniform, thus relaxing the accuracy requirements for the Sub-ADC. Besides taking the logarithm, other methods, including table lookup, can also be used to improve the accuracy of numerical changes.

[0120] In addition, the exponential conversion module can be used to restore the digital code of the sub-ADC to the code consistent with that before logarithmic conversion, that is, code_line = exp(code_log / 5.77); the aforementioned dynamic range restorer can also be used for code recovery.

[0121] like Figure 13 As shown, the linear-to-logarithmic module includes a first amplifier AMP1, a current mirror, a transistor B1, and a second amplifier AMP2. The negative input of the first amplifier AMP1 is connected to the input signal VIN, the positive input of the first amplifier AMP1 is grounded via a resistor R1, and the output of the first amplifier AMP1 is connected to the input of the second amplifier AMP2 and the emitter of the transistor B1 via a current mirror. The base and collector of the transistor B1 are grounded. The current mirror includes a first transistor M1 and a second transistor M2. The gate of the first transistor M1 is connected to the gate of the second transistor M2 and is connected to the output of the first amplifier AMP1. The source of the first transistor M1 and the source of the second transistor M2 are connected to the power supply VDD. The drain of the first transistor M1 is grounded via a resistor R1. The drain of the second transistor M2 is connected to the input of the second amplifier AMP2 and the emitter of the transistor B1.

[0122] The feedback circuit formed by the first amplifier AMP1 and the first transistor M1 applies the input signal VIN to the resistor R1, thereby forming a current through the first transistor M1: I = VIN / R1. Because the second transistor M2 is a mirror image of the first transistor M1, the current through M2 is equal to the current through M1.

[0123] Among them, the voltage of the emitter of transistor B1 is:

[0124]

[0125] Where, Vt = 26mV, Is is the saturation current of the transistor;

[0126] By properly setting the gain of the second amplifier AMP2, we can obtain:

[0127]

[0128] Example 5

[0129] For the main ADC, as the amplification factor increases, the capacitance added to the capacitor array increases.

[0130] The voltage of the least significant bit (LSB) converted by the main ADC is:

[0131]

[0132] Where Cs is the total sampling capacitance used in the current conversion, Convst is the sum of the total conversion capacitance, and Cu is the smallest unit capacitance in the conversion capacitance.

[0133] As the gain increases, Cs gradually increases, and V_LSB becomes very small. In a high-resolution ADC, the comparator noise may become much larger than V_LSB, causing the comparison results of the lowest bits of the ADC to be overwhelmed by the noise, making it impossible to obtain an accurate result.

[0134] In order to solve the above problems, this embodiment provides a two-stage analog-to-digital conversion system, which is improved based on the analog-to-digital conversion structure of the third embodiment. Figure 14 As shown in Figure 1, this analog-to-digital conversion system reduces the number of bits in the first-stage ADC, reducing the number of bits n to 2 or even 0. This means that after the sampling capacitor completes sampling, the second-stage ADC following the amplifier directly converts the data. This way, the comparator noise has little impact on the ADC's performance.

[0135] Example 6

[0136] like Figure 15 As shown, this embodiment provides an analog-to-digital conversion system that divides the sampling capacitor (each Cs) into two equal capacitors. During the sampling phase, the upper plates of half of the sampling capacitors are connected to the power supply terminal VDD, and the upper plates of the other half of the sampling capacitors are connected to VSS. After sampling, all the upper plates are connected together, and no additional VCM voltage is required. The voltage of the upper plate is VDD / 2. The analog-to-digital conversion system of this embodiment does not use the VCM voltage during the sampling phase, and the sampling phase has zero power consumption, saving power.

[0137] The analog-to-digital conversion system of the above embodiment can also be improved to a P-terminal and N-terminal structure, where the P-terminal and N-terminal operate as single-ended devices during the initial conversion phase. A single-ended ADC is placed on each of the P-terminal and N-terminal terminals, and the capacitance of the main capacitor array on the P-terminal or N-terminal terminals is independently controlled, thereby achieving different gains for the positive and negative terminals and processing any common-mode input signal.

[0138] The analog-to-digital conversion system provided by the present invention uses a lower-precision auxiliary analog-to-digital converter to modify the sampling capacitor size after pre-conversion at the current sampling point to achieve ADCs with different gains. The recovery module then processes and recovers the data. This improves the dynamic range of the signal chain when input signals of varying amplitudes are boosted across the entire system.

[0139] Compared with a fixed-gain signal chain, the present invention can automatically detect the signal input amplitude and automatically adjust the ADC gain, thereby better utilizing the ADC dynamic range, reducing quantization noise, and improving the accuracy of analog-to-digital conversion.

[0140] Compared with traditional automatic gain control, the present invention makes a judgment and adjusts the gain at the current sampling point, rather than adjusting the gain through methods such as data statistics. This can ensure that each sampling point does not cause ADC overload or accuracy degradation. It is very suitable for industrial fields and other fields that require accurate analog-to-digital conversion systems at each sampling point.

[0141] Based on the analog-to-digital conversion system provided in the above embodiment, an embodiment of the present invention further provides a method for automatically selecting a gain of the analog-to-digital conversion system, the method comprising:

[0142] The auxiliary analog-to-digital converter and the main analog-to-digital converter sample the input signal simultaneously, and the auxiliary analog-to-digital converter is used to pre-convert the sampled signal to obtain a pre-conversion result;

[0143] The gain selection module determines the position of the current input signal in the full scale of the main analog-to-digital converter according to the pre-conversion result of the auxiliary analog-to-digital converter, and determines the number of sampling capacitors that need to be connected to the main analog-to-digital converter to sample the current input signal according to the position of the current input signal in the full scale of the main analog-to-digital converter, so as to achieve gain selection of the main analog-to-digital converter;

[0144] The recovery module is used to restore the conversion result of the main analog-to-digital converter after gain adjustment to a result corresponding to the standard range of the main analog-to-digital converter.

[0145] Furthermore, the auxiliary analog-to-digital converter and the main analog-to-digital converter simultaneously sample the input signal, and the auxiliary analog-to-digital converter is used to preferentially pre-convert the sampled signal to obtain a pre-conversion result, specifically comprising: in a sampling phase, connecting the lower plate of the sampling capacitor of the main analog-to-digital converter to the input signal, connecting the lower plate of the conversion capacitor of the main analog-to-digital converter to the common-mode voltage, connecting the lower plate of the sampling capacitor of the auxiliary analog-to-digital converter to the input signal, and connecting the lower plate of the conversion capacitor of the auxiliary analog-to-digital converter to the common-mode voltage; at the end of sampling, disconnecting the upper plate of the sampling capacitor of the auxiliary analog-to-digital converter and the upper plate of the conversion capacitor from the common-mode voltage; after disconnecting the upper plate of the sampling capacitor of the main analog-to-digital converter from the common-mode voltage, disconnecting the upper plate of the conversion capacitor of the main analog-to-digital converter from the common-mode voltage; after disconnecting the upper plates of the sampling capacitors of the auxiliary analog-to-digital converter and the main analog-to-digital converter from the common-mode voltage, disconnecting the lower plates of the sampling capacitors of the auxiliary analog-to-digital converter and the main analog-to-digital converter from the input signal, and the auxiliary analog-to-digital converter performs successive approximation conversion to obtain the pre-conversion result.

[0146] Furthermore, the number of sampling capacitors required to be connected to the main analog-to-digital converter for sampling the current input signal is determined based on the pre-conversion result of the auxiliary analog-to-digital converter, specifically including: selecting a combination of sampling capacitors corresponding to the maximum gain based on the pre-conversion result of the auxiliary analog-to-digital converter and the proportional relationship between the capacitance values ​​of the respective sampling capacitors, and connecting the sampling capacitors of this combination to the circuit of the main analog-to-digital converter, thereby realizing gain selection and adjustment of the main analog-to-digital converter.

[0147] Furthermore, a recovery module is used to restore the conversion result of the main analog-to-digital converter after gain adjustment to a result corresponding to the standard range of the main analog-to-digital converter, specifically including: after the sampling is completed, the lower plate of the conversion capacitor of the main analog-to-digital converter is connected to the reference voltage, and the final conversion result is obtained through successive approximation conversion; and the final conversion result is restored to the code value of the standard range through the recovery module.

[0148] Furthermore, the voltage of the input signal can be converted into a logarithmic voltage through a linear-to-logarithmic module, and then the logarithmic voltage can be converted into a logarithmic value conversion result through an auxiliary analog-to-digital converter; and the logarithmic value conversion result obtained by the auxiliary analog-to-digital converter can be converted into a linear conversion result through an exponential conversion module.

[0149] Example 7

[0150] During integrated circuit manufacturing, random capacitor mismatches can occur during the manufacturing process. The sampling and conversion capacitors in analog-to-digital conversion systems can exhibit random deviations. This deviation can cause gain to deviate from its ideal value, while deviations between the conversion capacitors can degrade ADC linearity, necessitating calibration to account for these deviations.

[0151] This embodiment provides a method for calibrating the gain deviation caused by the deviation between the sampling capacitor and the conversion capacitor. Figure 16 As shown, the method includes the following steps:

[0152] The first step is to obtain the actual weight of the total sampling capacitance;

[0153] The second step is to obtain the actual weight of the highest weight capacitor of the conversion capacitor;

[0154] In the third step, based on the actual weight of the total sampling capacitor and the actual weight of the highest weight capacitor of the conversion capacitor, the ratio between the actual sampling capacitor and the conversion capacitor is obtained as the actual gain, which is calculated as follows:

[0155]

[0156] Where gain_cal is the actual gain, Cs_cal is the actual weight of the total sampling capacitor, and C_msb_cal is the actual weight of the highest-weight (MSB) capacitor of the conversion capacitor.

[0157] The fourth step is to use the actual gain to replace the original gain in the process of restoring the result to the code value of the standard range through the recovery module (dynamic range restorer), that is, to use gain_cal to replace the gain in the calculation formula Code_final = Code_main / gain of the recovery module.

[0158] In the first step above, since the weight of the sampling capacitor is usually large, it is necessary to calibrate the sampling capacitors Cs1 to Csn in sequence. If the weight of one sampling capacitor is greater than the sum of the weights of all conversion capacitors, the sampling capacitor can be divided into several parts for calibration and then superimposed. The specific method to obtain the actual weight of the total sampling capacitor is: refer to Figure 17 Taking the calibration of sampling capacitors Csp1 and Csn1 as an example, during the sampling phase, the input signal is not connected to the main ADC. The sampling capacitor to be calibrated is connected to VREFP (upper reference voltage), and the remaining capacitors are connected to VREFN (lower reference voltage). Then, the upper plate is disconnected, and the sampling capacitors Csp1 and Csn1 to be calibrated are connected to VCM. The low-order ADC converts the digital code using successive approximation, obtaining a digital code starting from the lowest bit. The actual weight Cs1_cal of the sampling capacitor Cs1 (i.e., Csp1 + Csn1) is:

[0159]

[0160] Among them, d i It is a digital code that starts from the lowest bit, that is, the least significant bit (LSB) digital code; C i The actual weight of the capacitor starting from the lowest bit (the lowest bits (such as 1 to 7) are not calibrated, and the latter (capacitors above 8) may be calibrated weights). For example, C1 represents the actual weight of the capacitor Cu, C2 represents the actual weight of the capacitor 2*Cu, and Cn represents the actual weight of the capacitor 2 n *Actual weight of Cu.

[0161] The weights of Csp2 and Csn2, up to Cspn and Csnn, are calibrated in sequence to obtain the actual weight Cs2_cal of Cs2 (ie, Csp2+Csn2), up to the actual weight Csn_cal of Csn (ie, Cspn+Csnn).

[0162] Finally, the actual weight values ​​of all sampling capacitors determined to be used after conversion by the auxiliary analog-to-digital converter are added together to obtain the actual weight Cs_cal of the total sampling capacitor.

[0163] In the second step above, the method for obtaining the actual weight of the highest weight capacitor of the conversion capacitor is similar to the method for obtaining the actual weight of the total sampling capacitor. Specifically, during the sampling phase, the lower plates of all sampling capacitors are connected to VCM, and the highest weight (MSB) capacitor 2 in the conversion capacitor to be calibrated is connected to VCM. n *The lower plate of Cu is connected to the reference voltage VREFP and VREFN; after the sampling is completed, the lower plate of the MSB capacitor is restored to VCM, and the capacitor 2 (n-1) *Cu, 2 (n-2) *Cu, ..., 2*Cu, Cu are converted in successive approximations.

[0164] Through the above operations, we can get the digital code d for each bit i According to the digital code d of each bit i And the actual weight C of each capacitor i , using the formula The actual weight C_msb_cal of the highest weight capacitor of the conversion capacitor is calculated.

[0165] By adopting the above-mentioned gain deviation calibration method, the deviation between the sampling capacitor and the conversion capacitor in the analog-to-digital conversion system can be calibrated, thereby further improving the accuracy of the analog-to-digital conversion system.

[0166] An embodiment of the present invention further provides a chip, which includes the above-mentioned analog-to-digital conversion system.

[0167] It will be understood by those skilled in the art that the embodiments of the present invention may be provided as methods, systems, or computer program products. Therefore, the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Furthermore, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code. The solutions in the embodiments of the present invention may be implemented in various computer languages, for example, the object-oriented programming language Java and the interpreted scripting language JavaScript.

[0168] The present invention is described with reference to flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowcharts and / or block diagrams, as well as combinations of processes and / or blocks in the flowcharts and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowcharts and / or block diagrams. Figure 1 a process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0169] These computer program instructions may also be stored in a computer readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 a process or multiple processes and / or boxes Figure 1 The function specified in one or more boxes.

[0170] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing the instructions executed on the computer or other programmable device for implementing the process. Figure 1 a process or multiple processes and / or boxes Figure 1 The steps for the function specified in one or more boxes.

[0171] The optional embodiments of the present invention are described in detail above in conjunction with the accompanying drawings. However, the embodiments of the present invention are not limited to the specific details in the above embodiments. Within the technical concept of the embodiments of the present invention, a variety of simple variations can be made to the technical solutions of the embodiments of the present invention, and these simple variations all fall within the scope of protection of the embodiments of the present invention. It should also be noted that the various specific technical features described in the above specific embodiments can be combined in any appropriate manner without contradiction, and as long as the combination does not violate the concept of the embodiments of the present invention, it should also be regarded as the content disclosed in the embodiments of the present invention.

Claims

1. An analog-to-digital conversion system, characterized in that: include: A main analog-to-digital converter, an auxiliary analog-to-digital converter, a gain selection module, and a recovery module, wherein the main analog-to-digital converter and the auxiliary analog-to-digital converter both include sampling capacitors and conversion capacitor arrays; The auxiliary analog-to-digital converter and the main analog-to-digital converter sample the input signal simultaneously, and the auxiliary analog-to-digital converter preferentially pre-converts the sampled signal to obtain a pre-conversion result; The gain selection module is used to determine the position of the current input signal corresponding to the full scale of the main analog-to-digital converter based on the pre-conversion result of the auxiliary analog-to-digital converter, and determine the number of sampling capacitors that need to be connected to the main analog-to-digital converter to sample the current input signal based on the position of the current input signal corresponding to the full scale of the main analog-to-digital converter, so as to adjust the gain of the main analog-to-digital converter; The recovery module is used to restore the conversion result of the main analog-to-digital converter after gain adjustment to a result corresponding to the standard range of the main analog-to-digital converter.

2. The analog-to-digital conversion system according to claim 1, wherein: The main analog-to-digital converter includes n groups of sampling capacitors and a group of conversion capacitor arrays, and each group of sampling capacitors includes a positive-end sampling capacitor and a negative-end sampling capacitor.

3. The analog-to-digital conversion system according to claim 2, wherein: The capacitance value of the conversion capacitor array of the main analog-to-digital converter is set in a form of successive approximation.

4. The analog-to-digital conversion system according to claim 3, wherein: At least one redundant capacitor is provided in the conversion capacitor array of the main analog-to-digital converter.

5. The analog-to-digital conversion system according to claim 3, wherein: The capacitance value multiple relationship of each capacitor in the conversion capacitor array of the main analog-to-digital converter is less than 2.

6. The analog-to-digital conversion system according to claim 2, wherein: The auxiliary analog-to-digital converter includes at least one group of sampling capacitors and a group of conversion capacitor arrays, and each group of sampling capacitors includes a positive-end sampling capacitor and a negative-end sampling capacitor.

7. The analog-to-digital conversion system according to claim 6, wherein: The number of sampling capacitors of the auxiliary analog-to-digital converter is less than the number of sampling capacitors of the main analog-to-digital converter; The number of bits of the conversion capacitor array of the auxiliary analog-to-digital converter is less than the number of bits of the conversion capacitor array of the main analog-to-digital converter.

8. The analog-to-digital conversion system according to claim 6, wherein: In the first stage working sequence of the analog-to-digital conversion system, the lower plate of the sampling capacitor of the main analog-to-digital converter is connected to the input signal, the lower plate of the conversion capacitor of the main analog-to-digital converter is connected to the common-mode voltage, the lower plate of the sampling capacitor of the auxiliary analog-to-digital converter is connected to the input signal, and the lower plate of the conversion capacitor of the auxiliary analog-to-digital converter is connected to the common-mode voltage.

9. The analog-to-digital conversion system according to claim 6, wherein: In the second phase operation sequence of the analog-to-digital conversion system, upon receiving a sampling end signal, disconnecting the upper plate of the sampling capacitor and the upper plate of the conversion capacitor of the auxiliary analog-to-digital converter from the common mode voltage; after disconnecting the upper plate of the sampling capacitor of the main analog-to-digital converter from the common mode voltage, disconnecting the upper plate of the conversion capacitor of the main analog-to-digital converter from the common mode voltage; After the upper plates of the sampling capacitors of the auxiliary analog-to-digital converter and the main analog-to-digital converter are disconnected from the common-mode voltage, the lower plates of the sampling capacitors of the auxiliary analog-to-digital converter and the main analog-to-digital converter are disconnected from the input signal, and the auxiliary analog-to-digital converter performs successive approximation conversion to obtain a pre-conversion result.

10. The analog-to-digital conversion system according to claim 6, wherein: In the third phase of the analog-to-digital conversion system, how many sampling capacitors in the main analog-to-digital converter are connected to the circuit of the main analog-to-digital converter is determined according to the pre-conversion result of the auxiliary analog-to-digital converter.

11. The analog-to-digital conversion system according to claim 10, wherein: Determining how many sampling capacitors in the main analog-to-digital converter are connected to the circuit of the main analog-to-digital converter according to the pre-conversion result of the auxiliary analog-to-digital converter includes: A combination of sampling capacitors corresponding to the maximum gain is selected according to the pre-conversion result of the auxiliary analog-to-digital converter and the proportional relationship between the capacitance values ​​of the sampling capacitors, and the sampling capacitors of the combination are connected to the circuit of the main analog-to-digital converter.

12. The analog-to-digital conversion system according to claim 6, wherein: In the fourth phase of the analog-to-digital conversion system, the lower plate of the conversion capacitor of the main analog-to-digital converter is connected to the reference voltage, and the final conversion result is obtained through successive approximation conversion.

13. The analog-to-digital conversion system according to claim 6, wherein: In the fifth phase of the working sequence of the analog-to-digital conversion system, the final conversion result is restored to a code value of a standard range through a recovery module.

14. The analog-to-digital conversion system according to claim 6, wherein: In the sixth phase of the working sequence of the analog-to-digital conversion system, each capacitor of the main analog-to-digital converter and the auxiliary analog-to-digital converter is reset, and the system enters the next sampling phase.

15. The analog-to-digital conversion system according to claim 2, wherein: The conversion capacitor of the main analog-to-digital converter is a segmented capacitor, and the conversion capacitors of each segment are connected via a bridge capacitor.

16. The analog-to-digital conversion system according to claim 2, wherein: The main analog-to-digital converter is a two-stage analog-to-digital converter, the conversion capacitor of the first-stage analog-to-digital converter has n bits, and the conversion capacitor of the second-stage analog-to-digital converter has m bits.

17. The analog-to-digital conversion system according to claim 1, wherein: The system further comprises: The linear-to-logarithmic module is used to convert the voltage of the input signal into a logarithmic voltage; The auxiliary analog-to-digital converter converts the logarithmic voltage to obtain a logarithmic value conversion result.

18. The analog-to-digital conversion system according to claim 17, wherein: The linear-to-logarithmic module includes: a first amplifier, a current mirror, a transistor and a second amplifier; The negative input terminal of the first amplifier is connected to the input signal, the output terminal of the first amplifier is connected to the input terminal of the second amplifier and the emitter of the transistor through a current mirror, and the base and collector of the transistor are grounded.

19. The analog-to-digital conversion system according to claim 18, wherein: The current mirror includes a first transistor and a second transistor, wherein the gate of the first transistor is connected to the gate of the second transistor and is connected to the output end of the first amplifier; The source of the first transistor and the source of the second transistor are connected to the power supply end, the drain of the first transistor is grounded through a resistor, and the drain of the second transistor is connected to the input end of the second amplifier and the emitter of the triode.

20. The analog-to-digital conversion system according to claim 17, wherein: The system further comprises: The exponential conversion module is used to convert the logarithmic conversion result obtained by the auxiliary analog-to-digital converter into a linear conversion result.

21. A method for automatically selecting gain of an analog-to-digital conversion system, characterized in that: The analog-to-digital conversion system includes a main analog-to-digital converter, an auxiliary analog-to-digital converter, a gain selection module, and a recovery module. The main analog-to-digital converter and the auxiliary analog-to-digital converter both include a sampling capacitor and a conversion capacitor array. The method includes: The auxiliary analog-to-digital converter and the main analog-to-digital converter sample the input signal simultaneously, and the auxiliary analog-to-digital converter is used to pre-convert the sampled signal to obtain a pre-conversion result; The gain selection module determines the position of the current input signal in the full scale of the main analog-to-digital converter according to the pre-conversion result of the auxiliary analog-to-digital converter, and determines the number of sampling capacitors that need to be connected to the main analog-to-digital converter to sample the current input signal according to the position of the current input signal in the full scale of the main analog-to-digital converter, so as to achieve gain selection of the main analog-to-digital converter; The recovery module is used to restore the conversion result of the main analog-to-digital converter after gain adjustment to a result corresponding to the standard range of the main analog-to-digital converter.

22. The automatic gain selection method of the analog-to-digital conversion system according to claim 21, characterized in that: The auxiliary analog-to-digital converter and the main analog-to-digital converter simultaneously sample the input signal, and the auxiliary analog-to-digital converter preferentially pre-converts the sampled signal to obtain a pre-conversion result, including: During the sampling phase, the lower plate of the sampling capacitor of the main analog-to-digital converter is connected to the input signal, the lower plate of the conversion capacitor of the main analog-to-digital converter is connected to the common mode voltage, the lower plate of the sampling capacitor of the auxiliary analog-to-digital converter is connected to the input signal, and the lower plate of the conversion capacitor of the auxiliary analog-to-digital converter is connected to the common mode voltage; At the end of sampling, the upper plate of the sampling capacitor of the auxiliary analog-to-digital converter and the upper plate of the conversion capacitor are disconnected from the common mode voltage; after the upper plate of the sampling capacitor of the main analog-to-digital converter is disconnected from the common mode voltage, the upper plate of the conversion capacitor of the main analog-to-digital converter is disconnected from the common mode voltage; after the upper plates of the sampling capacitors of the auxiliary analog-to-digital converter and the main analog-to-digital converter are disconnected from the common mode voltage, the lower plates of the sampling capacitors of the auxiliary analog-to-digital converter and the main analog-to-digital converter are disconnected from the input signal, and the auxiliary analog-to-digital converter performs successive approximation conversion to obtain a pre-conversion result.

23. The automatic gain selection method of the analog-to-digital conversion system according to claim 21, characterized in that: The number of sampling capacitors required for the main analog-to-digital converter to sample the current input signal is determined based on the pre-conversion result of the auxiliary analog-to-digital converter, including: A combination of sampling capacitors corresponding to the maximum gain is selected based on the pre-conversion result of the auxiliary analog-to-digital converter and the proportional relationship between the capacitance values ​​of the various sampling capacitors. The sampling capacitors of this combination are connected to the circuit of the main analog-to-digital converter to achieve gain selection of the main analog-to-digital converter.

24. The automatic gain selection method of the analog-to-digital conversion system according to claim 21, characterized in that: The recovery module is used to restore the conversion result of the main analog-to-digital converter after gain adjustment to the result corresponding to the standard range of the main analog-to-digital converter, including: After the sampling is completed, the lower plate of the conversion capacitor of the main analog-to-digital converter is connected to the reference voltage, and the final conversion result is obtained through successive approximation conversion; The final conversion result is restored to the code value of the standard range through the recovery module.

25. The automatic gain selection method of the analog-to-digital conversion system according to claim 21, characterized in that: The method further comprises: After the voltage of the input signal is converted into a logarithmic voltage by the linear-to-logarithmic module, the logarithmic voltage is converted into a logarithmic value by the auxiliary analog-to-digital converter; The logarithmic conversion result obtained by the auxiliary analog-to-digital converter is converted into a linear conversion result through the exponential conversion module.

26. A gain deviation calibration method based on the analog-to-digital conversion system according to claim 1, characterized in that: The method comprises: Get the actual weight of the total sampling capacitance; Get the actual weight of the highest weight capacitor of the conversion capacitor; The actual gain is obtained according to the actual weight of the total sampling capacitor and the actual weight of the highest weight capacitor of the conversion capacitor; Replace the original gain with the actual gain.

27. The gain deviation calibration method according to claim 26, characterized in that: The obtaining of the actual weight of the total sampling capacitance includes: During the sampling phase, the sampling capacitor to be calibrated is connected to the upper reference voltage, and the remaining capacitors are connected to the lower reference voltage; Connect the sampling capacitor to be calibrated to the common mode voltage and convert it in a successive approximation manner to obtain a digital code starting from the lowest bit. Obtaining actual weights of the respective sampling capacitors according to the digital code starting from the least significant bit and the actual weights of the capacitors starting from the least significant bit; The actual weights of the individual sampling capacitors are added together to obtain the actual weight of the total sampling capacitor.

28. The gain deviation calibration method according to claim 26, wherein: The obtaining of the actual weight of the highest weight capacitor of the conversion capacitor includes: During the sampling phase, the highest weight capacitor in the conversion capacitor is connected to the reference voltage; After sampling, the highest-weight capacitor in the conversion capacitor is connected to the common-mode voltage, and the other capacitors in the conversion capacitor are successively converted to obtain the digital code of each bit. According to the digital code of each bit and the actual weight of each capacitor, the actual weight of the highest weight capacitor of the conversion capacitor is obtained.

29. The gain deviation calibration method according to claim 26, wherein: The actual gain is obtained according to the actual weight of the total sampling capacitor and the actual weight of the highest weight capacitor of the conversion capacitor, including: The ratio of the actual weight of the total sampling capacitor to the actual weight of the highest weight capacitor of the conversion capacitor is used as the actual gain.

30. A chip, characterized in that: The chip includes the analog-to-digital conversion system according to any one of claims 1-20.

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