CAN bus deconcentrator circuit
By designing the CAN bus splitter circuit and using logic gate circuit to arbitrate data transmission, the delay and rate problems of existing CAN bus networks when overload load and message competition are solved, and information interoperability and complex topological structures of multiple networks are realized. support.
Patent Information
- Application Number
- CN202411401281.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-09
- Publication Date
- 2025-01-03
AI Technical Summary
When the existing CAN bus network is too heavy to have heavy load and fierce competition in messages, it is easy to lead to high data transmission delay and low transmission rate, and cannot meet the complex and flexible communication needs, making it prone to network deadlock.
A CAN bus splitter circuit was designed, and the controller interface was divided into main line and branch line networks through signal transmission interface and logic gate circuit. The logic gate circuit arbitrates data transmission to realize the information interoperability of multiple CAN bus networks and reduces delays. And increase the transmission rate.
It effectively reduces latency, improves transmission rate, avoids deadlock in bus transmission, and supports the construction of complex CAN network topology.
Smart Images
Figure CN119254565A_ABST
Abstract
Description
Technical Field
[0001] The invention relates to the technical field of splitters, and in particular to a CAN bus splitter circuit. Background Art
[0002] Controller Area Network (CAN) is a serial communication protocol bus for real-time applications. It can use twisted pair cables to transmit signals and is one of the most widely used fieldbuses in the world. The CAN protocol is used for communication between various components in the car to replace expensive and bulky distribution harnesses. The robustness of the protocol extends its use to other automation and industrial applications. The characteristics of the CAN protocol include complete serial data communication, real-time support, transmission speeds up to 1Mb / s, and 11-bit addressing and error detection capabilities.
[0003] CAN bus uses differential signal transmission, and usually only two signal lines are needed for normal communication. In differential signals, logic 0 and logic 1 are represented by the voltage difference between two differential signal lines. When in logic 1, the voltage difference between CAN_High and CAN_Low is less than 0.5V, which is called recessive level; when in logic 0, the voltage difference between CAN_High and CAN_Low is greater than 0.9V, which is called dominant level. The network topology of CAN bus is usually "hand in hand" to reduce the impact of impedance discontinuity and signal reflection; while other connection methods such as "tree topology" and "ring topology" need to rely on splitters or repeaters to build other bus topologies. When the network load is too heavy, the message competition is fierce, and the node priority is not set properly, it is easy to cause the message on the network to fail to pass correctly, so that the data transmission in the network cannot continue, and it cannot meet the complex and flexible communication needs. When multiple interfaces are communicating, it is easy to have high delays and low transmission rates. Summary of the invention
[0004] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.
[0005] The purpose of the present invention is to solve the shortcomings in the prior art and to propose a CAN bus splitter circuit.
[0006] In order to achieve the above-mentioned object, in a first aspect, the present invention provides a CAN bus splitter circuit, which is applied to an information transmission system composed of a CAN controller, a CAN splitter and a CAN transceiver, comprising:
[0007] A signal transmission interface and a logic gate circuit, wherein the logic gate circuit and the signal transmission interface are electrically connected, and the logic gate circuit electrically connects the CAN splitter with the CAN controller and the CAN transceiver through the signal transmission interface;
[0008] The signal transmission interface includes a group of controller interfaces, at least one group of main line network transceiver interfaces and at least one group of secondary line network transceiver interfaces. The signal transmission interface is used to transmit data sent by the CAN controller and the CAN transceiver.
[0009] In some embodiments, the controller interface includes a controller input interface T1 and a controller output interface R1, the main line network transceiver interface includes a first transceiver input interface R2 and a first transceiver output interface T2, and the secondary line network transceiver interface includes a second transceiver input interface R3 and a second transceiver output interface T3.
[0010] In some embodiments, the logic gate circuit includes OR gate U1A, OR gate U1B, OR gate U1C, OR gate U1D, AND gate U2A, AND gate U2B, AND gate U3A, NOT gate U4A, NOT gate U4B, NOT gate U5A, NOT gate U5B.
[0011] In some embodiments, the controller input interface T1 and the first transceiver input interface R2 are electrically connected to pin 13 of an OR gate U1D, and the controller output interface R1 is electrically connected to pin 2 of an AND gate U3A.
[0012] In some embodiments, pin 8 of the OR gate U1C is electrically connected to pin 12 of the OR gate U1D, and pin 11 of the OR gate U1D is electrically connected to the second transceiver output interface T3 and pin 2 of the AND gate U2A.
[0013] In some embodiments, the first transceiver input interface R2 is electrically connected to pin 3 of the NOT gate U4B and pin 13 of the OR gate U1D, respectively, the first transceiver output interface T2 is electrically connected to pin 7 of the AND gate U3A, and pin 4 of the NOT gate U4B is electrically connected to pin 6 of the AND gate U2B.
[0014] In some embodiments, the second transceiver input interface R3 is electrically connected to pin 1 of the OR gate U1A and pin 1 of the NOT gate U4A, and the second transceiver output interface T3 is electrically connected to pin 1 of the NOT gate U5A.
[0015] In some embodiments, pin 6 of the NOT gate U5A is electrically connected to pin 4 of the OR gate U1B, pin 5 of the OR gate U1B is electrically connected to pin 3 of the AND gate U2B, and pin 6 of the OR gate U1B is electrically connected to pin 2 of the OR gate U1A.
[0016] In some embodiments, pin 3 of the OR gate U1A is electrically connected to pin 1 of the AND gate U3A, pin 5 of the AND gate U2B, and pin 3 of the NOT gate U5B, respectively, and pin 4 of the NOT gate U5B is electrically connected to pin 10 of the OR gate U1C.
[0017] In some embodiments, pin 6 of the NOT gate U4A is electrically connected to pin 1 of the AND gate U2A, and pin 7 of the AND gate U2A is electrically connected to pin 9 of the OR gate U1C.
[0018] The present invention has the following beneficial effects:
[0019] In the present invention, the logic gate circuit divides the controller CAN interface into two or more parts, one of which is normally connected to the main line network, and the other is connected to the branch line network. The main line and the branch line data are interconnected, and information interconnection of multiple CAN bus networks is realized, which effectively reduces the delay, improves the transmission rate, avoids deadlock during bus transmission, and can adapt and build a complex CAN network topology according to usage requirements. BRIEF DESCRIPTION OF THE DRAWINGS
[0020] Figure 1 It is the schematic diagram of the CAN bus transmission system;
[0021] Figure 2 The principle of the CAN bus splitter circuit proposed by the present invention Figure 1 ;
[0022] Figure 3 The principle of the CAN bus splitter circuit proposed by the present invention Figure 2 ;
[0023] Figure 4 The principle of the CAN bus splitter circuit proposed by the present invention Figure 3 ;
[0024] Figure 5 The principle of the CAN bus splitter circuit proposed by the present invention Figure 4 ;
[0025] Figure 6 The principle of the CAN bus splitter circuit proposed by the present invention Figure 5 . DETAILED DESCRIPTION
[0026] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.
[0027] Please refer to the following examples for details:
[0028] Reference Figure 1-Figure 6 An embodiment of a CAN bus splitter circuit provided by the present invention is applied to an information transmission system composed of a CAN controller, a CAN splitter and a CAN transceiver. The specific structure includes: a signal transmission interface and a logic gate circuit. The logic gate circuit and the signal transmission interface are electrically connected. The logic gate circuit electrically connects the CAN splitter to the CAN controller and the CAN transceiver through the signal transmission interface.
[0029] Exemplarily, the signal transmission interface includes a group of controller interfaces, at least one group of main line network transceiver interfaces and at least one group of secondary line network transceiver interfaces. The signal transmission interface is used to transmit data sent by the CAN controller and the CAN transceiver, and cooperates with the logic gate circuit to realize CAN bus arbitration, so that the end that enters the dominant level first obtains the dominant right. Taking one controller port and two transceiver ports as an example, the information of the three ports can be intercommunication, and the two transceiver ports can connect two different CAN network topologies to realize communication between the two CAN network topologies.
[0030] Specifically, the controller interface includes a controller input interface T1 and a controller output interface R1, the main line network transceiver interface includes a first transceiver input interface R2 and a first transceiver output interface T2, and the secondary line network transceiver interface includes a second transceiver input interface R3 and a second transceiver output interface T3.
[0031] Furthermore, the logic gate circuit includes an OR gate U1A, an OR gate U1B, an OR gate U1C, an OR gate U1D, an AND gate U2A, an AND gate U2B, an AND gate U3A, a NOT gate U4A, a NOT gate U4B, a NOT gate U5A, and a NOT gate U5B.
[0032] Please continue reading Figure 1-Figure 6 The controller input interface T1 and the first transceiver input interface R2 are electrically connected to pin 13 of the OR gate U1D, and the controller output interface R1 is electrically connected to pin 2 of the AND gate U3A; pin 8 of the OR gate U1C is electrically connected to pin 12 of the OR gate U1D, and pin 11 of the OR gate U1D is electrically connected to the second transceiver output interface T3 and pin 2 of the AND gate U2A.
[0033] Furthermore, the first transceiver input interface R2 is electrically connected to pin 3 of NOT gate U4B and pin 13 of OR gate U1D respectively, the first transceiver output interface T2 is electrically connected to pin 7 of AND gate U3A, and pin 4 of NOT gate U4B is electrically connected to pin 6 of AND gate U2B.
[0034] Further, the second transceiver input interface R3 is electrically connected to pin 1 of the OR gate U1A and pin 1 of the NOT gate U4A, and the second transceiver output interface T3 is electrically connected to pin 1 of the NOT gate U5A; pin 6 of the NOT gate U5A is electrically connected to pin 4 of the OR gate U1B, pin 5 of the OR gate U1B is electrically connected to pin 3 of the AND gate U2B, pin 6 of the OR gate U1B is electrically connected to pin 2 of the OR gate U1A, pin 3 of the OR gate U1A is respectively electrically connected to pin 1 of the AND gate U3A, pin 5 of the AND gate U2B and pin 3 of the NOT gate U5B, pin 4 of the NOT gate U5B is electrically connected to pin 10 of the OR gate U1C, pin 6 of the NOT gate U4A is electrically connected to pin 1 of the AND gate U2A, and pin 7 of the AND gate U2A is electrically connected to pin 9 of the OR gate U1C.
[0035] Working principle:
[0036] The entire splitter circuit includes three inputs (controller input interface T1, first transceiver input interface R2, second transceiver input interface R3) and three outputs (controller output interface R1, first transceiver output interface T2, second transceiver output interface T3). The states of the three outputs are the results obtained after the timing combination of the three input signals is calculated through the logic gate circuit.
[0037] (1) If there is no message on the bus, the controller input interface T1, the first transceiver input interface R2, and the second transceiver input interface R3 are all high level, so by default the potentials of each point are as follows: Figure 3 As shown ("H" indicates high level, "L" indicates low level);
[0038] (2) If the network connected to transceiver 1 enters the dominant level first (i.e., the first transceiver input interface R2 becomes a low level), transceiver 1 first obtains the right to use the bus, and the potential of each point will change as follows: Figure 4As shown: at this time, the controller output interface R1 will also become low level, so that the controller receives the information of transceiver 1, and the second transceiver output interface T3 will also become low level, so that the network connected to transceiver 2 will also enter the dominant level synchronously, and the information of transceiver 1 will be synchronized to transceiver 2; and after the network connected to transceiver 2 enters the dominant level, the second transceiver input interface R3 will also become low level, and the levels of other points will not change. When the first transceiver input interface R2 returns to the high level again, the status of each point returns to the default level, and the controller output interface R1 and the second transceiver output interface T3 both return to the high level, so that the data of transceiver 1 is synchronously sent to the controller and transceiver 2.
[0039] (3) If the network connected to transceiver 2 enters the dominant level first (i.e., the second transceiver input interface R3 becomes a low level), similar to the case where the first transceiver input interface R2 is pulled low, transceiver 2 first obtains the right to use the bus, and the potential of each point will change as follows: Figure 5 As shown: the controller output interface R1 and the first transceiver output interface T2 will also become low level, so that the data of transceiver 2 is synchronously sent to the controller and transceiver 1.
[0040] (4) If the controller enters the dominant level first (i.e. the controller input interface T1 becomes low level), the potential of each point will change as follows Figure 6 As shown: the first transceiver output interface T2 and the second transceiver output interface T3 will also become a low level, sending the controller information to the two networks connected to transceiver 1 and transceiver 2.
[0041] Through the above technical solution, the present application divides the controller CAN interface into two or more parts through a logic gate circuit, one path is normally connected to the main line network, and the other path can be connected to the branch network. Information exchange of multiple CAN bus networks is realized through transceiver interface 1, transceiver interface 2 and controller interface, which effectively reduces the delay, improves the transmission rate, avoids deadlock during bus transmission, and can adapt and build complex CAN network topology according to usage requirements.
[0042] Finally, it should be noted that the above is only a preferred embodiment of the present invention and is not intended to limit the present invention. Although the present invention has been described in detail with reference to the aforementioned embodiments, it is still possible for those skilled in the art to modify the technical solutions described in the aforementioned embodiments or to make equivalent substitutions for some of the technical features therein. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.
Claims
1. A CAN bus splitter circuit, applied to an information transmission system consisting of a CAN controller, a CAN splitter and a CAN transceiver, characterized in that: include: A signal transmission interface and a logic gate circuit, wherein the logic gate circuit and the signal transmission interface are electrically connected, and the logic gate circuit electrically connects the CAN splitter with the CAN controller and the CAN transceiver through the signal transmission interface; The signal transmission interface includes a group of controller interfaces, at least one group of main line network transceiver interfaces and at least one group of secondary line network transceiver interfaces. The signal transmission interface is used to transmit data sent by the CAN controller and the CAN transceiver.
2. A CAN bus splitter circuit according to claim 1, characterized in that: The controller interface includes a controller input interface T1 and a controller output interface R1, the main line network transceiver interface includes a first transceiver input interface R2 and a first transceiver output interface T2, and the secondary line network transceiver interface includes a second transceiver input interface R3 and a second transceiver output interface T3.
3. A CAN bus splitter circuit according to claim 1, characterized in that: The logic gate circuit includes an OR gate U1A, an OR gate U1B, an OR gate U1C, an OR gate U1D, an AND gate U2A, an AND gate U2B, an AND gate U3A, a NOT gate U4A, a NOT gate U4B, a NOT gate U5A, and a NOT gate U5B.
4. A CAN bus splitter circuit according to claim 2, characterized in that: The controller input interface T1 and the first transceiver input interface R2 are electrically connected to the pin 13 of the OR gate U1D, and the controller output interface R1 is electrically connected to the pin 2 of the AND gate U3A.
5. A CAN bus splitter circuit according to claim 4, characterized in that: Pin 8 of the OR gate U1C is electrically connected to pin 12 of the OR gate U1D, and pin 11 of the OR gate U1D is electrically connected to the second transceiver output interface T3 and pin 2 of the AND gate U2A.
6. A CAN bus splitter circuit according to claim 2, characterized in that: The first transceiver input interface R2 is electrically connected to pin 3 of NOT gate U4B and pin 13 of OR gate U1D respectively, the first transceiver output interface T2 is electrically connected to pin 7 of AND gate U3A, and pin 4 of NOT gate U4B is electrically connected to pin 6 of AND gate U2B.
7. A CAN bus splitter circuit according to claim 2, characterized in that: The second transceiver input interface R3 is electrically connected to pin 1 of the OR gate U1A and pin 1 of the NOT gate U4A, and the second transceiver output interface T3 is electrically connected to pin 1 of the NOT gate U5A.
8. A CAN bus splitter circuit according to claim 7, characterized in that: Pin 6 of the NOT gate U5A is electrically connected to pin 4 of the OR gate U1B, pin 5 of the OR gate U1B is electrically connected to pin 3 of the AND gate U2B, and pin 6 of the OR gate U1B is electrically connected to pin 2 of the OR gate U1A.
9. A CAN bus splitter circuit according to claim 8, characterized in that: Pin 3 of the OR gate U1A is electrically connected to pin 1 of the AND gate U3A, pin 5 of the AND gate U2B, and pin 3 of the NOT gate U5B, respectively. Pin 4 of the NOT gate U5B is electrically connected to pin 10 of the OR gate U1C.
10. A CAN bus splitter circuit according to claim 8, characterized in that: Pin 6 of the NOT gate U4A is electrically connected to pin 1 of the AND gate U2A, and pin 7 of the AND gate U2A is electrically connected to pin 9 of the OR gate U1C.