Display panel and display device

Abstract

The invention discloses a display panel and a display device. The display panel comprises a first display area, a second display area and a first functional area, the second display area comprises a first signal line extending in the second direction, and the first signal line comprises a first branch and a second branch which are separated by the first functional area; the first display area comprises a first sub-display area, the first sub-display area comprises a third signal line extending in the second direction, and the third signal line is electrically connected with the first branch part and the second branch part; in the same pixel circuit of the first sub-display area, the second signal line and the third signal line are located on the same side of the fourth signal line. According to the display panel and the display device provided by the embodiment of the invention, the third signal line is additionally arranged in the first sub display area to connect the first branch part and the second branch part in the second display area, so that the number of signal lines at the frame position of the first functional area can be reduced, the frame area of the first functional area is reduced, and the screen-to-body ratio of the display panel is improved.

Description

[0001] This application is a divisional application of application number 202210773013.7, application date June 30, 2022, and invention name “A display panel and display device”. Technical Field

[0002] The present invention relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0003] In existing display devices, due to the need to integrate front cameras, fingerprint recognition components, infrared sensing components, etc., holes are dug on the display panel to form functional areas, and external light can enter the photosensitive components located below the display panel through the functional areas on the display panel.

[0004] Since the signal lines around the functional area need to be connected accordingly around the functional area, a wider border needs to be set around the functional area to provide sufficient winding space, which affects the screen-to-body ratio of the display panel and cannot meet the market demand for narrow borders. Summary of the invention

[0005] The present invention provides a display panel and a display device, so as to reduce the frame area around the functional area and improve the screen-to-body ratio.

[0006] According to one aspect of the present invention, there is provided a display panel, comprising:

[0007] A first display area, a second display area and a first functional area, wherein in a first direction, the first display area is adjacent to the first functional area, and in a second direction, the second display area is adjacent to the first functional area, and the first direction intersects with the second direction;

[0008] The second display area includes a first signal line extending along the second direction, the first signal line is used to provide a first type of signal to the pixel circuit of the second display area, and the first signal line includes a first sub-section and a second sub-section separated by the first functional area;

[0009] The first display area includes a first sub-display area;

[0010] The first sub-display area includes a second signal line and a third signal line extending along the second direction; the second signal line is used to provide the first type of signal to the pixel circuit of the first sub-display area, and the third signal line is electrically connected to the first sub-section and the second sub-section respectively;

[0011] The display panel further includes a fourth signal line extending along the second direction, and the fourth signal line is used to transmit a second type of signal;

[0012] In the same pixel circuit of the first sub-display area, the second signal line and the third signal line are located on the same side of the fourth signal line.

[0013] According to another aspect of the present invention, a display device is provided, comprising the display panel according to the first aspect.

[0014] The display panel and the display device provided by the embodiments of the present invention, by setting a first sub-display area in the first display area, and adding a third signal line in the first sub-display area, the first section and the second section of the first signal line separated by the first functional area in the second display area are connected through the third signal line, thereby providing a first type of signal to the pixel circuit electrically connected to the same first signal line. At the same time, the first section and the second section are connected through the third signal line set in the first sub-display area. Compared with the prior art in which the first signal line is wound from the border position of the first functional area, the number of signal lines at the border position of the first functional area is reduced, thereby reducing the border area of ​​the first functional area and improving the screen-to-body ratio of the display panel.

[0015] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0017] Figure 1 A schematic diagram of the structure of a display panel provided by an embodiment of the present invention;

[0018] Figure 2 for Figure 1 A schematic diagram of the enlarged structure at A;

[0019] Figure 3 A schematic diagram of the structure of another display panel provided by an embodiment of the present invention;

[0020] Figure 4 for Figure 3 A schematic diagram of the enlarged structure at B;

[0021] Figure 5 A schematic diagram of a partial structure of a display panel provided by an embodiment of the present invention;

[0022] Figure 6A schematic diagram of a partial structure of another display panel provided by an embodiment of the present invention;

[0023] Figure 7 A schematic diagram of a partial structure of another display panel provided by an embodiment of the present invention;

[0024] Figure 8 A schematic diagram of a partial structure of another display panel provided by an embodiment of the present invention;

[0025] Fig. 9 A schematic diagram of the layout structure of a pixel circuit group provided by an embodiment of the present invention;

[0026] Fig.10 A schematic diagram of a partial structure of another display panel provided by an embodiment of the present invention;

[0027] Fig.11 A schematic diagram of a partial cross-sectional structure of a display panel provided by an embodiment of the present invention;

[0028] Fig.12 A schematic diagram of a partial cross-sectional structure of another display panel provided by an embodiment of the present invention;

[0029] Fig.13 A schematic diagram of the structure of a pixel circuit provided by an embodiment of the present invention;

[0030] Fig.14 A schematic diagram of a partial cross-sectional structure of another display panel provided by an embodiment of the present invention;

[0031] Fig.15 A schematic diagram of a partial cross-sectional structure of another display panel provided by an embodiment of the present invention;

[0032] Fig.16 A schematic diagram of a partial cross-sectional structure of another display panel provided by an embodiment of the present invention;

[0033] Fig.17 A schematic diagram of a partial cross-sectional structure of another display panel provided by an embodiment of the present invention;

[0034] Fig.18 A schematic diagram of a partial structure of another display panel provided by an embodiment of the present invention;

[0035] Fig.19 A schematic diagram of a partial structure of another display panel provided by an embodiment of the present invention;

[0036] Fig. 20 A schematic diagram of a partial structure of another display panel provided by an embodiment of the present invention;

[0037] Fig.21A schematic diagram of a partial structure of another display panel provided by an embodiment of the present invention;

[0038] Fig. 22 A schematic diagram of a partial structure of another display panel provided by an embodiment of the present invention;

[0039] Fig.23 A partial structural diagram of another display panel provided by an embodiment of the present invention

[0040] Fig.24 A schematic diagram of a partial cross-sectional structure of another display panel provided by an embodiment of the present invention;

[0041] Fig.25 A schematic diagram of a partial structure of another display panel provided by an embodiment of the present invention;

[0042] Fig.26 A schematic diagram of a partial structure of another display panel provided by an embodiment of the present invention;

[0043] Fig. 27 A schematic diagram of a partial structure of another display panel provided by an embodiment of the present invention;

[0044] Fig.28 A partial structural diagram of another display panel provided by an embodiment of the present invention

[0045] Fig.29 A schematic diagram of a partial cross-sectional structure of another display panel provided by an embodiment of the present invention;

[0046] Fig.30 A schematic structural diagram of a display device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0047] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0048] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0049] Figure 1 A schematic diagram of the structure of a display panel provided by an embodiment of the present invention, Figure 2 for Figure 1 The enlarged structural diagram at A is shown in Figure 1 and Figure 2 As shown, the display panel provided by the embodiment of the present invention includes a first display area 10, a second display area 11 and a first functional area 12. In the first direction X, the first display area 10 is adjacent to the first functional area 12, and in the second direction Y, the second display area 11 is adjacent to the first functional area 12, and the first direction X intersects with the second direction Y. The second display area 11 includes a first signal line 13 extending along the second direction Y, the first signal line 13 is used to provide a first type of signal to the pixel circuit 14 of the second display area 11, and the first signal line 13 includes a first sub-portion 131 and a second sub-portion 132 separated by the first functional area 12. The first display area 10 includes a first sub-display area 101, and the first sub-display area 101 includes a second signal line 15 and a third signal line 16 extending along the second direction Y, the second signal line 15 is used to provide a first type of signal to the pixel circuit 14 of the first sub-display area 101, and the third signal line 16 is electrically connected to the first sub-portion 131 and the second sub-portion 132, respectively. The display panel further includes a fourth signal line 17 extending along the second direction Y, the fourth signal line 17 is used to transmit the second type of signal, and in the same pixel circuit 14 of the first sub-display area 101 , the second signal line 15 and the third signal line 16 are located on the same side of the fourth signal line 17 .

[0050] Specifically, Figure 1 and Figure 2 As shown, the first functional area 12 is used to place a photosensitive element, which may be a camera, a light sensor, a distance sensor, a depth sensor, an iris recognition sensor, an infrared sensor, etc., but is not limited thereto.

[0051] Optionally, the first functional area 12 may be a non-display area, that is, the first functional area 12 does not emit light, so as to reduce the impact on the performance of the photosensitive element.

[0052] In addition, the first functional area 12 can be a rectangular area, a circular area or an elliptical area, etc. The position of the first functional area 12 can be set on any side of the display panel. Technical personnel in this field can set the shape and position of the first functional area 12 according to actual needs, and the embodiment of the present invention is not limited to this.

[0053] Continue to refer Figure 1 and Figure 2 A first display area 10 and a second display area 11 are arranged around the first functional area 12. The first display area 10 and the second display area 11 include a plurality of pixel circuits 14 and a plurality of light-emitting elements (not shown in the figure) arranged in an array. The pixel circuits 14 are arranged corresponding to the light-emitting elements. The pixel circuits 14 are used to drive the corresponding light-emitting elements to emit light to realize the display function.

[0054] Among them, the first display area 10 and the second display area 11 are provided with signal lines electrically connected to the pixel circuit 14, and the signal lines may include data signal lines, scanning signal lines, light-emitting control signal lines, reference voltage signal lines and power signal lines, etc., so as to provide the pixel circuit 14 with various signals required to drive the light-emitting elements to emit light.

[0055] Specifically, Figure 1 and Figure 2 As shown, part of the first display area 10 is divided into a first sub-display area 101, and a second signal line 15 extending along the second direction Y is provided in the first sub-display area 101, for providing a first type of signal to the pixel circuit 14 in the first sub-display area 101, wherein, since the first display area 10 is adjacent to the first functional area 12 in the first direction X (the direction intersecting the second direction Y), each second signal line 15 is not separated by the first functional area 12, and is a continuous routing.

[0056] In the second display area 11, a first signal line 13 extending along the second direction Y is provided for providing a first type of signal to the pixel circuit 14 in the second display area 11. Since the second display area 11 is adjacent to the first functional area 12 in the second direction Y, the first signal line 13 is divided into a first section 131 and a second section 132 by the first functional area 12.

[0057] In this embodiment, in order to provide the first type of signal for the pixel circuit 14 electrically connected to the same first signal line 13, a third signal line 16 extending along the second direction Y is provided in the first sub-display area 101, and the first sub-section 131 and the second sub-section 132 separated from the same first signal line 13 are connected by the third signal line 16. The first sub-section 131 and the second sub-section 132 of the first signal line 13 separated from the first functional area 12 are connected by the third signal line 16 provided in the first sub-display area 101, and the first signal line 13 does not need to be wound from the frame position of the first functional area 12, thereby reducing the number of signal lines at the frame position of the first functional area 12, thereby reducing the frame area of ​​the first functional area 12, and improving the screen ratio of the display panel.

[0058] Among them, the first signal line 13 and the second signal line 15 can be any one of a data signal line, a scan signal line, a light-emitting control signal line, a reference voltage signal line and a power signal line, that is, the first type of signal can be any one of a data signal, a scan signal, a light-emitting control signal, a reference voltage signal and a power signal, and the embodiment of the present invention does not make any specific limitation on this.

[0059] Continue to refer Figure 1 and Figure 2 The display panel also includes a fourth signal line 17 extending along the second direction Y, and the fourth signal line 17 is used to transmit a second type of signal, wherein the second type of signal can also be any one of a data signal, a scan signal, a light control signal, a reference voltage signal and a power signal, but the second type of signal is different from the first type of signal.

[0060] In the same pixel circuit 14 of the first sub-display area 101, the second signal line 15 and the third signal line 16 are located on the same side of the fourth signal line 17, that is, among the second signal line 15, the third signal line 16 and the fourth signal line 17 corresponding to the same pixel circuit 14, the second signal line 15 and the third signal line 16 are concentrated on the same side of the fourth signal line 17, so that the distance between the second signal line 15 and the third signal line 16 is closer. With this arrangement, the parasitic capacitance between the second signal line 15 and the third signal line 16 and other metal film layers or signal nodes in the pixel circuit 14 is at a similar level, which helps to reduce the loss difference between the first type of signals transmitted on the second signal line 15 and the third signal line 16, thereby helping to improve display uniformity.

[0061] Optionally, the first type of signal and the second type of signal are AC signals.

[0062] Among them, the second signal line 15 corresponding to the pixel circuit 14 refers to the second signal line 15 connected to the pixel circuit 14, the fourth signal line 17 corresponding to the pixel circuit 14 refers to the fourth signal line 17 connected to the pixel circuit 14, and the third signal line 16 corresponding to the pixel circuit 14 refers to the third signal line 16 overlapping with the pixel circuit 14 or closest to the pixel circuit 14.

[0063] It should be noted that Figure 1 and Figure 2 It is taken as an example that the first display area 10 includes one first sub-display area 101 and the first sub-display area 101 is only located at one side of the second display area 11 , but the present invention is not limited thereto.

[0064] In addition, in order to more clearly illustrate each signal line, the fourth signal line 17 is bolded in some drawings of the present application, that is, the fourth signal line 17 is represented by a thicker line segment in some drawings, and the remaining thinner line segments are used to transmit the first type of signal, which does not constitute a limitation on the scope of protection of the present invention.

[0065] Figure 3 A schematic diagram of the structure of another display panel provided by an embodiment of the present invention, Figure 4 for Figure 3 The enlarged structural diagram at B is as follows: Figure 3 and Figure 4 As shown, optionally, the first display area 10 includes two first sub-display areas 101, and the two first sub-display areas 101 are respectively located on both sides of the second display area 11, which helps to reduce the connection distance between the third signal line 16 and the first signal line 13, thereby helping to reduce the transmission loss of the first type of signal.

[0066] In other embodiments, the first display area 10 may further include more first sub-display areas 101 , and the number and positions of the first sub-display areas 101 may be set according to actual needs, which is not limited in the embodiment of the present invention.

[0067] To summarize, the display panel provided by the embodiment of the present invention sets a first sub-display area 101 in the first display area 10, and adds a third signal line 16 in the first sub-display area 101, and connects the first division 131 and the second division 132 of the first signal line 13 in the second display area 11 separated by the first functional area 12 through the third signal line 16, thereby providing a first type of signal to the pixel circuit 14 electrically connected to the same first signal line 13. At the same time, the first division 131 and the second division 132 are connected through the third signal line 16 set in the first sub-display area 101. Compared with the prior art in which the first signal line 13 is wound from the border position of the first functional area 12, the number of signal lines at the border position of the first functional area 12 is reduced, thereby reducing the border area of ​​the first functional area 12 and improving the screen-to-body ratio of the display panel.

[0068] Furthermore, by arranging the second signal line 15 and the third signal line 16 on the same side of the fourth signal line 17 in the same pixel circuit 14 of the first sub-display area 101, the second signal line 15 and the third signal line 16 are placed centrally, so that the parasitic capacitance between the second signal line 15 and the third signal line 16 and other metal film layers or signal nodes in the pixel circuit 14 are at a similar level, which helps to reduce the loss difference between the data signals transmitted on the second signal line 15 and the third signal line 16, thereby helping to improve display uniformity.

[0069] Continue to refer Figure 1 and Figure 2 Optionally, the fourth signal line 17 is the first power signal line 18, and the second type of signal is the first power signal.

[0070] Specifically, the first power signal line 18 is used to provide a first power signal for the pixel circuit 14, wherein the first power signal is a DC signal rather than an AC signal, and therefore, the first power signal line 18 can provide a constant voltage for the pixel circuit 14. The first power signal line 18 can be, for example, a PVDD signal line or a PVEE signal line, which is not limited in the embodiment of the present invention.

[0071] In this embodiment, in the same pixel circuit 14 of the first sub-display area 101, the second signal line 15 and the third signal line 16 are arranged on the same side of the first power signal line 18, that is, among the second signal line 15, the third signal line 16 and the first power signal line 18 corresponding to the same pixel circuit 14, the second signal line 15 and the third signal line 16 are concentrated on the same side of the first power signal line 18, so that the distance between the second signal line 15 and the third signal line 16 is closer. With this arrangement, the parasitic capacitance between the second signal line 15 and the third signal line 16 and other metal film layers or signal nodes in the pixel circuit 14 is at a similar level, which helps to reduce the loss difference between the data signals transmitted on the second signal line 15 and the third signal line 16, thereby helping to improve display uniformity.

[0072] Continue to refer Figure 1 and Figure 2 Optionally, along the thickness direction of the display panel, the second signal line 15 , the third signal line 16 and the fourth signal line 17 all overlap with the pixel circuit 14 of the first sub-display area 101 .

[0073] Specifically, Figure 1 and Figure 2 As shown, the vertical projections of the second signal line 15, the third signal line 16 and the fourth signal line 17 on the plane where the display panel is located overlap with the vertical projection of the pixel circuit 14 on the plane where the display panel is located, so that the second signal line 15, the third signal line 16 and the fourth signal line 17 do not need to occupy additional space, which is beneficial to increase the pixel density of the display panel and enhance the display effect.

[0074] It should be noted that the pixel circuit 14 includes multiple transistors, and the multiple transistors of the same pixel circuit 14 are usually concentrated together, and the multiple transistors can be regarded as an integrated transistor combination structure. In the present application, the vertical projection of the signal line on the plane where the display panel is located overlaps with the vertical projection of the pixel circuit 14 on the plane where the display panel is located, which means that the vertical projection of the signal line on the plane where the display panel is located overlaps with the vertical projection of the transistor combination structure of the pixel circuit 14 on the plane where the display panel is located, that is, the vertical projection of the signal line on the plane where the display panel is located overlaps with the vertical projection of at least one transistor of the pixel circuit 14 on the plane where the display panel is located, which will not be repeated later.

[0075] The plurality of transistors may include a first light emission control transistor, a data signal writing transistor, a driving transistor, a compensation transistor, a first reset transistor, a second light emission control transistor and a light emission reset transistor, but is not limited thereto.

[0076] In addition, if Figure 1 and Figure 2As shown, along the thickness direction of the display panel, the third signal line 16 overlaps with the pixel circuit 14 of the first sub-display area 101, but the third signal line 16 is not electrically connected to the pixel circuit 14 of the first sub-display area 101, that is, the third signal line 16 and the pixel circuit 14 overlapping therewith are insulated, thereby reducing the mutual interference between the third signal line 16 and the pixel circuit 14 in the first sub-display area 101.

[0077] Figure 5 A partial structural diagram of a display panel provided by an embodiment of the present invention is shown in FIG. Figure 5 As shown, optionally, the second signal line 15 and the third signal line 16 may also be located in the first sub-display area 101. Such a configuration can avoid the formation of parasitic capacitance between the first signal line 13 and the second signal line 15 and the metal film layers in the pixel circuit 14, thereby reducing the impact of the first signal line 13 and the second signal line 15 on the performance of the pixel circuit 14.

[0078] Similarly, in other embodiments, the fourth signal line 17 may also be located between two adjacent pixel circuits 14 in the first sub-display area 101 to avoid the formation of parasitic capacitance between the first signal line 13 and the second signal line 15 and the metal film layers in the pixel circuit 14, thereby reducing the influence of the first signal line 13 and the second signal line 15 on the performance of the pixel circuit 14. The embodiments of the present invention do not specifically limit this.

[0079] As described above, in the present application, the signal line 16 is located between two adjacent pixel circuits 14, which means that the signal line is located between the transistor combination structure of two adjacent pixel circuits 14, that is, the vertical projection of the signal line on the plane where the display panel is located does not overlap with the vertical projection of the transistor of the pixel circuit 14 on the plane where the display panel is located, which will not be repeated here.

[0080] Continue to refer Figure 1-Figure 5 Optionally, in the same pixel circuit 14 , the third signal line 16 is located on a side of the second signal line 15 close to the fourth signal line 17 , or the third signal line 16 is located on a side of the second signal line 15 far from the fourth signal line 17 .

[0081] For example, Figure 1-Figure 5 As shown, among the second signal line 15, the third signal line 16 and the fourth signal line 17 corresponding to the same pixel circuit 14, the third signal line 16 can be located on the side of the second signal line 15 away from the fourth signal line 17, which helps to reduce the connection distance between the second signal line 15 and the pixel circuit 14, thereby helping to reduce the transmission loss of the first type of signal.

[0082] Figure 6 A partial structural diagram of another display panel provided by an embodiment of the present invention is shown in FIG. Figure 6As shown, exemplarily, among the second signal line 15, the third signal line 16 and the fourth signal line 17 corresponding to the same pixel circuit 14, the third signal line 16 may also be located on the side of the second signal line 15 close to the fourth signal line 17, which can improve the flexibility of the design of the third signal line 16 so that the third signal line 16 is matched with the pixel circuit 14. For example, when there is a large spacing between the second signal line 15 and the fourth signal line 17 in the pixel circuit 14, the third signal line 16 may be arranged between the second signal line 15 and the fourth signal line 17, which is beneficial to improve the pixel density of the display panel.

[0083] Figure 7 A partial structural diagram of another display panel provided by an embodiment of the present invention is shown. Figure 8 A partial structural diagram of another display panel provided by an embodiment of the present invention is shown. Fig. 9 A schematic diagram of a layout structure of a pixel circuit group provided by an embodiment of the present invention is shown in FIG. Figure 7-Figure 9 As shown, optionally, the display panel provided by the embodiment of the present invention includes a pixel circuit group 19, the pixel circuit group 19 includes a first pixel circuit 20 and a second pixel circuit 21 adjacently arranged along a first direction X, and the first pixel circuit 20 and the second pixel circuit 21 are arranged in a mirror image.

[0084] Specifically, Figure 7-Figure 9 As shown, the pixel circuit 14 is divided into a plurality of pixel circuit groups 19, and the pixel circuit group 19 includes two adjacent pixel circuits 14, namely a first pixel circuit 20 and a second pixel circuit 21. By setting the first pixel circuit 20 and the second pixel circuit 21 in a mirror-image arrangement, when the first pixel circuit 20 and the second pixel circuit 21 are connected to part of the signal lines, the first pixel circuit 20 and the second pixel circuit 21 can share a connecting through hole, thereby reducing the number of punch holes, helping to improve the transmittance of the display panel, and when an optical sensor device such as an under-screen fingerprint recognition module is provided in the display panel, it helps to improve the performance of the optical sensor device.

[0085] For example, Fig. 9As shown, the connecting through holes C1, C2, C3 and C4 are connecting through holes between the pixel circuit 14 and the corresponding signal lines, respectively. If the first pixel circuit 20 and the second pixel circuit 21 are not arranged in a mirror image, a group of connecting through holes C1, C2, C3 and C4 needs to be set in the first pixel circuit 20, and a group of C1, C2, C3 and C4 also needs to be set in the second pixel circuit 21, that is, two groups of connecting through holes C1, C2, C3 and C4 need to be set in one pixel circuit group 19. In this embodiment, by arranging the first pixel circuit 20 and the second pixel circuit 21 in a mirror image, the first pixel circuit 20 and the second pixel circuit 21 can share a group of connecting through holes C1, C2, C3 and C4, thereby reducing the setting of a group of connecting through holes C1, C2, C3 and C4. One pixel circuit group 19 only needs to set a group of connecting through holes C1, C2, C3 and C4 to meet the potential requirements of the first pixel circuit 20 and the second pixel circuit 21, thereby improving the transmittance of the display panel.

[0086] It should be noted that Fig. 9 The first pixel circuit 20 and the second pixel circuit 21 shown in FIG. 2 share the connecting through holes C1 and C2, while the connecting through holes C3 and C4 marked in the second pixel circuit 21 are Fig. 9 The second pixel circuit 21 is shared with the first pixel circuit 20 (not shown in the figure) adjacent to its right side. It can be understood that the two adjacent pixel circuits 14 are arranged in a mirror image, and the junction of the two adjacent pixel circuits 14 can reduce the number of connecting through holes by sharing a connecting through hole, thereby improving the transmittance of the display panel.

[0087] It is worth noting that Fig. 9 As shown, in the same pixel circuit 14 of the first sub-display area 101, the second signal line 15 and the third signal line 16 are located on the same side of the fourth signal line 17, that is, among the second signal line 15, the third signal line 16 and the fourth signal line 17 corresponding to the same pixel circuit 14, the second signal line 15 and the third signal line 16 are concentrated on the same side of the fourth signal line 17, so that the distance between the second signal line 15 and the third signal line 16 is closer. With this arrangement, the parasitic capacitance between the second signal line 15 and the third signal line 16 and other metal film layers or signal nodes in the pixel circuit 14 is at a similar level, which helps to reduce the loss difference between the first type of signals transmitted on the second signal line 15 and the third signal line 16, thereby helping to improve display uniformity.

[0088] It should be noted that in order to clearly illustrate the positional relationship between the second signal line 15 and the third signal line 16, Fig. 9 The outlines of the second signal line 15 and the third signal line 16 are thickened, which does not constitute a limitation on the protection scope of the present invention.

[0089] Continue to refer Figure 7-Figure 9 Optionally, in the same pixel circuit group 19 of the first sub-display area 101 , along the first direction X, the second signal line 15 is located between two third signal lines 16 ; or, the third signal line 16 is located between two second signal lines 15 .

[0090] Specifically, Figure 7 and Figure 8 As shown, taking the third signal line 16 being located between two second signal lines 15 as an example, the two third signal lines 16 can be placed together. Compared with the second signal lines 15 and the third signal lines 16 being alternately arranged along the first direction X, this helps to reduce the mutual interference between the second signal lines 15 and the third signal lines 16, so that the first type of signal transmitted on the second signal lines 15 and the third signal lines 16 is more accurate and stable, which helps to improve the driving performance of the pixel circuit 14.

[0091] Fig.10 A partial structural diagram of another display panel provided by an embodiment of the present invention is shown in FIG. Fig. 9 and Fig.10 As shown, optionally, in the same pixel circuit group 19 of the first sub-display area 101, the second signal line 15 is located between two third signal lines 16, thereby placing the two second signal lines 15 in a concentrated manner. Compared with the second signal lines 15 and the third signal lines 16 being alternately arranged along the first direction X, this helps to reduce mutual interference between the second signal lines 15 and the third signal lines 16, so that the first type of signal transmitted on the second signal lines 15 and the third signal lines 16 is more accurate and stable, which helps to improve the driving performance of the pixel circuit 14.

[0092] It should be noted that Fig. 9 The pixel circuit group shown in FIG. 1 is located in the first sub-display area 101 .

[0093] Fig.11 A partial cross-sectional structure diagram of a display panel provided by an embodiment of the present invention is shown in FIG. Fig. 9 and Fig.11 As shown, optionally, the second signal line 15 and the third signal line 16 are located in the same film layer.

[0094] Among them, Fig. 9 and Fig.11As shown, by arranging the second signal line 15 and the third signal line 16 in the same film layer, along the thickness direction of the display panel, the vertical distances between the second signal line 15 and the third signal line 16 and other metal film layers in the pixel circuit 14 are basically consistent, so that the parasitic capacitances between the second signal line 15 and the third signal line 16 and other metal film layers in the pixel circuit 14 can be at a similar level, which helps to reduce the loss difference between the data signals transmitted on the second signal line 15 and the third signal line 16, thereby helping to improve display uniformity.

[0095] At the same time, by arranging the second signal line 15 and the third signal line 16 in the same film layer, there is no need to arrange an additional metal layer for the third signal line 16, and the arrangement of one metal layer can be reduced, thereby achieving the purpose of reducing production costs and reducing the thickness of the display panel. In addition, the third signal line 16 can be made of the same material as the second signal line 15, so that the third signal line 16 and the second signal line 15 can be prepared in the same process, thereby shortening the process time.

[0096] It should be noted that the specific film layer positions of the second signal line 15 and the third signal line 16 can be set according to actual needs.

[0097] For example, Fig.11 As shown, the pixel circuit 14 includes a first thin film transistor 22, and the first thin film transistor 22 includes a first active layer 24, a first gate layer 25 and a first source-drain electrode layer 26 stacked on one side of the substrate 23. The second signal line 15 and the third signal line 16 can be arranged on the side of the first source-drain electrode layer 26 away from the substrate 23, wherein the second signal line 15 and the third signal line 16 can be formed by a Ti / Al / Ti metal stack, wherein Al has a relatively small resistance, thereby reducing the resistance of the second signal line 15 and the third signal line 16, reducing the line loss of the first type of signal on the second signal line 15 and the third signal line 16, and further reducing the voltage drop of the first type of signal on the second signal line 15 and the third signal line 16, which helps to improve display uniformity.

[0098] It should be noted that the specific film layer positions of the second signal line 15 and the third signal line 16 are not limited to the above embodiments. In other embodiments, the second signal line 15 and the third signal line 16 may also be arranged in the same layer as any metal film layer such as the first gate layer 25, the first source and drain electrode layer 26, etc. The embodiments of the present invention are not limited to this.

[0099] For example, Fig.11As shown, the pixel circuit 14 also includes a storage capacitor 40, the storage capacitor 40 includes a first electrode plate 401 and a second electrode plate 402, the first electrode plate 401 is located on the side of the second electrode plate 402 away from the base substrate 23, and the second signal line 15 and the third signal line 16 can also be arranged on the same layer as the first electrode plate 401 or the second electrode plate 402.

[0100] In addition, if Fig.11 As shown, a light shielding metal layer 41 may be further provided on the side of the first active layer 24 close to the base substrate 23. Along the thickness direction of the display panel, the light shielding metal layer 41 overlaps with the first active layer 24. The light shielding metal layer 41 is used to shield the channel formed by the first active layer 24 to prevent light from irradiating the first active layer 24, thereby preventing the first active layer 24 from affecting the off-state current of the first thin film transistor 22 due to light exposure, and preventing light from causing adverse effects on the first thin film transistor 22. Optionally, the second signal line 15 and the third signal line 16 may also be provided on the same layer as the light shielding metal layer 41, but are not limited to the above embodiment.

[0101] Continue to refer Fig. 9 and Fig.11 Optionally, along the first direction X, a distance between the second signal line 15 and the third signal line 16 is d1, wherein d1≥2.5 μm.

[0102] Among them, Fig.11 As shown, by setting the spacing d1 between the second signal line 15 and the third signal line 16 to be greater than or equal to 2.5 μm, the distance between the second signal line 15 and the third signal line 16 can be prevented from being too close to cause mutual interference between the second signal line 15 and the third signal line 16, so that the first type of signal transmitted on the second signal line 15 and the third signal line 16 is more accurate and stable, thereby improving the driving performance of the pixel circuit 14.

[0103] It should be noted that the specific value of the spacing d1 between the second signal line 15 and the third signal line 16 can be set according to actual needs, and the embodiment of the present invention is not limited to this. It can be understood that the larger the spacing d1 between the second signal line 15 and the third signal line 16, the smaller the mutual interference between the second signal line 15 and the third signal line 16; but the smaller the spacing d1 between the second signal line 15 and the third signal line 16, the more conducive it is to compress the size of the pixel circuit 14, thereby helping to improve the pixel density of the display panel.

[0104] Fig.12 A partial cross-sectional structural diagram of another display panel provided by an embodiment of the present invention is shown in FIG. Fig.12 As shown, optionally, the second signal line 15 and the third signal line 16 are located in different film layers, and along the thickness direction of the display panel, the second signal line and the third signal line at least partially overlap.

[0105] Specifically, Fig.12 As shown, by arranging the second signal line 15 and the third signal line 16 in different layers, compared with arranging the second signal line 15 and the third signal line 16 in the same layer, along the thickness direction of the display panel, the second signal line 15 and the third signal line 16 can at least partially overlap, thereby reducing the overall projection area of ​​the second signal line 15 and the third signal line 16 on the plane where the display panel is located, which helps to improve the transmittance of the display panel.

[0106] For example, Fig.12 As shown, the second signal line 15 can be arranged on the side of the first source-drain electrode layer 26 away from the base substrate 23, wherein the second signal line 15 can be formed by a Ti / Al / Ti metal stack. Since Al has a smaller resistance, the resistance of the second signal line 15 can be reduced, and the line loss of the first type of signal on the second signal line 15 can be reduced, thereby reducing the voltage drop of the first type of signal on the second signal line 15, which helps to improve display uniformity.

[0107] At the same time, the third signal line 16 can be arranged in the same layer as the first source-drain electrode layer 26, wherein the metal film layer where the first source-drain electrode layer 26 is located is usually formed by a Ti / Al / Ti metal stack. Setting the third signal line 16 in the film layer where the first source-drain electrode layer 26 is located can reduce the line loss of the first type of signal on the third signal line 16, thereby reducing the voltage drop of the first type of signal on the third signal line 16, which helps to improve display uniformity.

[0108] It should be noted that the specific film layer positions of the second signal line 15 and the third signal line 16 are not limited to the above-mentioned embodiments. In other embodiments, the second signal line 15 and the third signal line 16 may also be arranged in the same layer as any metal film layer such as the first gate layer 25, the first source-drain electrode layer 26, the first electrode 401, the second electrode 402 or the shading metal layer 41, and the embodiments of the present invention are not limited to this.

[0109] Optionally, the first type of signal is a data signal.

[0110] The first signal line 13 and the second signal line 15 may be data signal lines, and the first type of signal transmitted on the first signal line 13 and the second signal line 15 is a data signal.

[0111] Fig.13 A schematic diagram of a pixel circuit provided by an embodiment of the present invention is shown in FIG. Fig. 9 and Fig.13As shown, exemplarily, the pixel circuit 14 includes a data signal writing transistor 27, a driving transistor 28 and a compensation transistor 29, the driving transistor 28 is connected in series between the first power signal line 18 and the light-emitting element 30, the first electrode D3 of the driving transistor 28 is electrically connected to the first electrode S2 of the data signal writing transistor 27, the second electrode S3 of the driving transistor 28 is electrically connected to the first electrode D4 of the compensation transistor 29, the second electrode S4 of the compensation transistor 29 is electrically connected to the gate G3 of the driving transistor 28, in the pixel circuit 14 of the first sub-display area 101, the second electrode D2 of the data signal writing transistor 27 is electrically connected to the second signal line 15; in the pixel circuit 14 of the second display area 11, the second electrode D2 of the data signal writing transistor 27 is electrically connected to the first signal line 13.

[0112] The light emitting element 30 is used to emit light in the light emitting stage to realize the light emitting or display function of the display panel.

[0113] The driving transistor 28 can be turned on according to the potential of its gate, and the driving current formed by the turning on of the driving transistor 28 is used to drive the light emitting element 30 to emit light.

[0114] The driving process of the pixel circuit 14 may include:

[0115] In the data signal voltage writing stage, the data writing transistor 27 and the compensation transistor 29 are turned on, and the driving transistor 28 is also turned on. In the pixel circuit 14 of the first sub-display area 101, the data signal voltage on the second signal line 15 is applied to the first node N1 (i.e., the gate G3 of the driving transistor 28) through the data signal writing transistor 27, the driving transistor 28 and the compensation transistor 29; in the pixel circuit 14 of the second display area 11, the data signal voltage on the first signal line 13 is applied to the first node N1 (i.e., the gate G3 of the driving transistor 28) through the data signal writing transistor 27, the driving transistor 28 and the compensation transistor 29.

[0116] In the light emitting stage, the first power signal on the first power signal line 18 is transmitted to the light emitting element 30 through the driving transistor 28 , so that the driving current generated by the driving transistor 28 is provided to the light emitting element 30 , driving the light emitting element 30 to emit light.

[0117] In this embodiment, a first signal line 13 and a second signal line 15 are provided to transmit data signals, and a third signal line 16 added in the first sub-display area 101 is used to connect the first section 131 and the second section 132 of the first signal line 13 in the second display area 11 which are separated by the first functional area 12, thereby providing a data signal to the pixel circuit 14 electrically connected to the same first signal line 13, wherein the first signal line 13 no longer needs to be wound from the border position of the first functional area 12, thereby reducing the number of data signal lines at the border position of the first functional area 12, reducing the border area of ​​the first functional area 12, and improving the screen-to-body ratio of the display panel.

[0118] Furthermore, if Fig. 9 As shown, taking the fourth signal line 17 as the first power signal line 18 as an example, the extension directions of the second signal line 15, the third signal line 16 and the first power signal line 18 are all the same. In the same pixel circuit 14 of the first sub-display area 101, the second signal line 15 and the third signal line 16 are arranged on the same side of the first power signal line 18 so that the second signal line 15 and the third signal line 16 are concentratedly placed, so that the parasitic capacitance between the second signal line 15 and the third signal line 16 and other metal film layers or signal nodes in the pixel circuit 14 are at a similar level, which helps to reduce the loss difference between the data signals transmitted on the second signal line 15 and the third signal line 16, thereby helping to improve display uniformity.

[0119] It should be noted that the first type of signal transmitted by the second signal line 15 and the third signal line 16 is not limited to the above-mentioned embodiment. In other embodiments, the first type of signal transmitted on the second signal line 15 and the third signal line 16 may also be a scanning signal or a light-emitting control signal, etc., which is not limited in this embodiment of the present invention.

[0120] Exemplarily, the first signal line 13 and the second signal line 15 may also be scanning signal lines, and the first type of signal transmitted on the first signal line 13 and the second signal line 15 is a scanning signal. The scanning signal is transmitted by setting the first signal line 13 and the second signal line 15, and the third signal line 16 added in the first sub-display area 101 connects the first sub-section 131 and the second sub-section 132 of the first signal line 13 in the second display area 11 separated by the first functional area 12, thereby providing a scanning signal for the pixel circuit 14 electrically connected to the same first signal line 13, wherein the first signal line 13 does not need to be wound from the border position of the first functional area 12, thereby reducing the number of scanning signal lines at the border position of the first functional area 12, reducing the border area of ​​the first functional area 12, and improving the screen-to-body ratio of the display panel.

[0121] Among them, when the first type of signal transmitted on the first signal line 13 and the second signal line 15 is a scanning signal, the second signal line 15 and the third signal line 16 can be arranged in different layers, and along the thickness direction of the display panel, the second signal line 15 and the third signal line 16 can at least partially overlap, thereby reducing the overall projection area of ​​the second signal line 15 and the third signal line 16 on the plane where the display panel is located, which helps to improve the transmittance of the display panel. At the same time, when the first type of signal transmitted on the first signal line 13 and the second signal line 15 is a scanning signal, the above-mentioned setting method also helps to reduce the signal coupling between the second signal line 15 and the third signal line 16, which helps to improve the driving performance of the pixel circuit 14.

[0122] Continue to refer Figure 1-10 Optionally, the display panel provided in the embodiment of the present invention further includes a first connecting line 31 extending along the first direction X, and the first connecting line 31 is used to connect the first signal line 13 in the second display area 11 to the third signal line 16 in the first sub-display area 101.

[0123] Among them, Figure 1-10 As shown, by setting a first connecting line 31 extending along the first direction X, the first sub-portion 131 and the second sub-portion 132 of the third signal line 16 are led out to the first sub-display area 101 to achieve connection between the first sub-portion 131 and the second sub-portion 132 and the third signal line 16.

[0124] Continue to refer Figure 2 , Figure 4 , Figure 6 , Figure 7 , Fig. 9 and Fig.10 Optionally, along the thickness direction of the display panel, the first connection line 31 overlaps with the pixel circuit 14 .

[0125] Among them, Figure 2 , Figure 4 , Figure 6 , Figure 7 , Fig. 9 and Fig.10 As shown, the vertical projection of the first connection line 31 on the plane where the display panel is located overlaps with the vertical projection of the pixel circuit 14 on the plane where the display panel is located, so that the first connection line 31 does not need to occupy additional space, which is beneficial to improving the pixel density of the display panel.

[0126] Continue to refer Figure 5 and Figure 8 Optionally, the first connection line 31 may also be located between two adjacent pixel circuits 14, thereby avoiding the formation of parasitic capacitance between the first connection line 31 and each metal film layer in the pixel circuit 14, thereby reducing the impact of the first connection line 31 on the performance of the pixel circuit 14.

[0127] It should be noted that the first connecting line 31 is located in the display area (specifically in the first sub-display area 101 and the second display area 11), which can reduce the number of connecting lines set in the border of the first functional area 12, and may not even set connecting lines in the border of the first functional area 12. Therefore, the border area of ​​the first functional area 12 can be reduced and the screen-to-body ratio of the array substrate can be increased.

[0128] Fig.14 A partial cross-sectional structural diagram of another display panel provided by an embodiment of the present invention is shown in FIG. Fig. 9 and Fig.14 As shown, optionally, the first connecting line 31 and the third signal line 16 are located in different film layers.

[0129] Specifically, Fig. 9 and Fig.14 As shown, the first connection line 31 and the third signal line 16 are located in different film layers, and the first connection line 31 and the third signal line 16 to be connected thereto can be connected by punching.

[0130] like Figure 1-10 As shown, the first connection line 31 extends along the first direction X, and the first signal line 13, the second signal line 15, the third signal line 16 and the fourth signal line 17 all extend along the second direction Y. Therefore, the first connection line 31 will overlap with part of the first signal line 13, the second signal line 15, the third signal line 16 and the fourth signal line 17. In this embodiment, by setting the first connection line 31 and the third signal line 16 in different layers, when the first connection line 31 needs to be connected to the third signal line 16, it is connected by punching; when the first connection line 31 does not need to be connected to the third signal line 16, it is not necessary to punch, and the preparation process is simple and easy to implement. In addition, when the third signal line 16 is set in the same layer as any signal line of the first signal line 13, the second signal line 15 and the fourth signal line 17, since the first connection line 31 and the third signal line 16 are located in different film layers, the first connection line 31 does not need to avoid the signal line in the same layer as the third signal line 16 by crossing the line, making the structure simpler and helping to improve the reliability of the display panel.

[0131] For example, Fig. 9 and Fig.14 As shown, the third signal line 16 can be arranged on the side of the first source-drain electrode layer 26 away from the base substrate 23, wherein the third signal line 16 can be formed by a Ti / Al / Ti metal stack. Since Al has a smaller resistance, the resistance of the third signal line 16 can be reduced, and the line loss of the first type of signal on the third signal line 16 can be reduced, thereby reducing the voltage drop of the first type of signal on the third signal line 16, which helps to improve display uniformity.

[0132] At the same time, the first connecting line 31 can be arranged in the same layer as the first source-drain electrode layer 26, wherein the metal film layer where the first source-drain electrode layer 26 is located is usually formed by a Ti / Al / Ti metal stack. Setting the first connecting line 31 in the film layer where the first source-drain electrode layer 26 is located can reduce the line loss of the first type of signal on the first connecting line 31, thereby reducing the voltage drop of the first type of signal on the first connecting line 31, which helps to improve display uniformity.

[0133] Furthermore, if Fig. 9 and Fig.14 As shown, the first connection line 31 and the third signal line 16 are located in adjacent metal film layers. Along the thickness direction of the display panel, the distance between the first connection line 31 and the third signal line 16 can be relatively close, thereby facilitating punching connection.

[0134] It should be noted that the specific film layer positions of the first connecting line 31 and the third signal line 16 are not limited to the above-mentioned embodiments. In other embodiments, the first connecting line 31 and the third signal line 16 may also be arranged in the same layer as any metal film layer such as the first gate layer 25, the first source-drain electrode layer 26, the first electrode plate 401, the second electrode plate 402 or the shading metal layer 41, and the embodiments of the present invention are not limited to this.

[0135] Fig.15 A partial cross-sectional structural diagram of another display panel provided by an embodiment of the present invention is shown in FIG. Fig. 9 and Fig.15 As shown, optionally, the display panel also includes a reference voltage signal line 32 extending along the first direction X, the reference voltage signal line 32 is used to provide a reference voltage signal for the pixel circuit 14, the first connection line 31 is insulated from the reference voltage signal line 32, and along the thickness direction of the display panel, the first connection line 31 and the reference voltage signal line 32 at least partially overlap.

[0136] Specifically, Fig. 9 and Fig.15 As shown, the first connection line 31 and the reference voltage signal line 32 extend in the same direction, and the first connection line 31 and the reference voltage signal line 32 are insulated from each other to avoid mutual interference between the signals on the first connection line 31 and the reference voltage signal line 32 .

[0137] Among them, Fig. 9 and Fig.15 As shown, the vertical projection of the first connecting line 31 on the plane where the display panel is located and the vertical projection of the reference voltage signal line 32 on the plane where the display panel is located at least partially overlap, thereby reducing the overall projection area of ​​the first connecting line 31 and the reference voltage signal line 32 on the plane where the display panel is located, which helps to improve the transmittance of the display panel. When an optical sensor device such as an under-screen fingerprint recognition module is provided in the display panel, it helps to improve the performance of the optical sensor device.

[0138] At the same time, since the reference voltage signal transmitted by the reference voltage signal line 32 is a DC signal, that is, the voltage on the reference voltage signal line 32 is a constant voltage, along the thickness direction of the display panel, the first connecting line 31 and the reference voltage signal line 32 at least partially overlap, which can reduce the mutual interference between the first connecting line 31 and the reference voltage signal line 32.

[0139] Moreover, since the voltage on the reference voltage signal line 32 is a constant voltage, by setting the first connecting line 31 and the reference voltage signal line 32 to at least partially overlap, the reference voltage signal line 32 can also shield the first connecting line 31, thereby reducing the impact between the first connecting line 31 and other metal film layers or signal nodes in the pixel circuit 14.

[0140] Fig.16 A partial cross-sectional structural diagram of another display panel provided by an embodiment of the present invention is shown in FIG. Fig.16 As shown, optionally, the first connection line 31 and the reference voltage signal line 32 are located in the same film layer.

[0141] Among them, Fig.16 As shown, by arranging the first connection line 31 and the reference voltage signal line 32 in the same film layer, there is no need to arrange an additional metal layer for the first connection line 31, thereby reducing the arrangement of one metal layer, thereby achieving the purpose of reducing production costs and reducing the thickness of the display panel. In addition, the first connection line 31 can be made of the same material as the reference voltage signal line 32, so that the first connection line 31 and the reference voltage signal line 32 can be prepared in the same process, thereby shortening the process time.

[0142] Continue to refer Fig. 9 , Fig.13 and Fig.15 Optionally, the display panel provided in the embodiment of the present invention further includes a first power signal line 18, and the first power signal line 18 is used to transmit a first power signal. The reference voltage signal line 32 includes a first reference voltage signal line 321, and the pixel circuit 14 includes a driving transistor 28 and a first reset transistor 33, and the driving transistor 28 is connected in series between the first power signal line 18 and the light-emitting element 30, and the gate G3 of the driving transistor 28 is electrically connected to the first electrode S5 of the first reset transistor 33, and the second electrode D5 of the first reset transistor 33 is electrically connected to the first reference voltage signal line 321, and the first connection line 31 and the first reference voltage signal line 321 are located in different film layers, and along the thickness direction of the display panel, the first connection line 31 and the first reference voltage signal line 321 at least partially overlap.

[0143] The driving transistor 28 can be turned on according to the potential of its gate, and the driving current formed by the turning on of the driving transistor 28 is used to drive the light emitting element 30 to emit light.

[0144] The driving process of the pixel circuit 14 may further include:

[0145] In the initialization stage, the first reset transistor 33 is turned on, and the first reference voltage on the first reference voltage signal line 321 is applied to the first node N1 through the first reset transistor 33, that is, the potential of the first node N1 is the first reference voltage. At this time, the potential of the gate G3 of the driving transistor 28 is also the reference voltage, thereby resetting the first node N1 (the gate G3 of the driving transistor 28).

[0146] Among them, Fig. 9 and Fig.15 As shown, the vertical projection of the first connecting line 31 on the plane where the display panel is located at least partially overlaps with the vertical projection of the first reference voltage signal line 321 on the plane where the display panel is located, thereby reducing the overall projection area of ​​the first connecting line 31 and the first reference voltage signal line 321 on the plane where the display panel is located, which helps to improve the transmittance of the display panel. When an optical sensor device such as an under-screen fingerprint recognition module is provided in the display panel, it helps to improve the performance of the optical sensor device.

[0147] At the same time, since the first reference voltage signal transmitted by the first reference voltage signal line 321 is a DC signal, that is, the voltage on the first reference voltage signal line 321 is a constant voltage, along the thickness direction of the display panel, the first connecting line 31 and the first reference voltage signal line 321 at least partially overlap, which can reduce the mutual interference between the first connecting line 31 and the first reference voltage signal line 321.

[0148] Furthermore, since the voltage on the first reference voltage signal line 321 is a constant voltage, by setting the first connecting line 31 and the first reference voltage signal line 321 to at least partially overlap, the first reference voltage signal line 321 can also shield the first connecting line 31, thereby reducing the impact between the first connecting line 31 and other metal film layers or signal nodes in the pixel circuit 14.

[0149] Fig.17 A partial cross-sectional structural diagram of another display panel provided by an embodiment of the present invention is shown in FIG. Fig. 9 , Fig.13 and Fig.17As shown, optionally, the display panel further includes a first power signal line 18, and the first power signal line 18 is used to transmit a first power signal. The reference voltage signal line 32 includes a second reference voltage signal line 322, and the pixel circuit 14 includes a driving transistor 28 and a light emitting reset transistor 34, the driving transistor 28 is connected in series between the first power signal line 18 and the light emitting element 30, the anode of the light emitting element 30 is electrically connected to the first electrode S7 of the light emitting reset transistor 34, and the second electrode D7 of the light emitting reset transistor 34 is electrically connected to the second reference voltage signal line 322.

[0150] like Fig.17 As shown, the first connection line 31 and the second reference voltage signal line 322 are located in different film layers, and along the thickness direction of the display panel, the first connection line 31 and the second reference voltage signal line 322 at least partially overlap.

[0151] The driving transistor 28 can be turned on according to the potential of its gate, and the driving current formed by the turning on of the driving transistor 28 is used to drive the light emitting element 30 to emit light.

[0152] The driving process of the pixel circuit 14 may further include:

[0153] During the data signal voltage writing stage, the light emitting reset transistor 34 is turned on, and the light emitting reset transistor 34 writes the second reference voltage on the second reference voltage signal line 322 into the anode of the light emitting element 30 to reset the anode potential of the light emitting element 30, which can reduce the influence of the anode voltage of the light emitting element 30 in the previous frame on the anode voltage of the light emitting element 30 in the next frame, and helps to improve display uniformity.

[0154] Among them, Fig.17 As shown, the vertical projection of the first connecting line 31 on the plane where the display panel is located and the vertical projection of the second reference voltage signal line 322 on the plane where the display panel is located at least partially overlap, thereby reducing the overall projection area of ​​the first connecting line 31 and the second reference voltage signal line 322 on the plane where the display panel is located, which helps to improve the transmittance of the display panel. When an optical sensor device such as an under-screen fingerprint recognition module is provided in the display panel, it helps to improve the performance of the optical sensor device.

[0155] At the same time, since the second reference voltage signal transmitted by the second reference voltage signal line 322 is a DC signal, that is, the voltage on the second reference voltage signal line 322 is a constant voltage, along the thickness direction of the display panel, the first connecting line 31 and the second reference voltage signal line 322 at least partially overlap, which can reduce the mutual interference between the first connecting line 31 and the second reference voltage signal line 322.

[0156] Furthermore, since the voltage of the second reference voltage signal line 322 is a constant voltage, by setting the first connection line 31 and the second reference voltage signal line 322 to at least partially overlap, the second reference voltage signal line 322 can also shield the first connection line 31, thereby reducing the impact between the first connection line 31 and other metal film layers or signal nodes in the pixel circuit 14.

[0157] like Fig. 9 As shown, optionally, the first reference voltage signal line 321 and the second reference voltage signal line 322 are located in different film layers.

[0158] For example, Fig. 9 and Fig.15 As shown, the first reference voltage signal line 321 can be arranged in the same layer as the first electrode plate 401, thereby reducing the arrangement of one metal layer, thereby achieving the purpose of reducing production costs and reducing the thickness of the display panel. In addition, the first reference voltage signal line 321 can be made of the same material as the first electrode plate 401, so that the first reference voltage signal line 321 and the first electrode plate 401 can be prepared in the same process, thereby shortening the process time.

[0159] Furthermore, if Fig. 9 and Fig.17 As shown, the second reference voltage signal line 322 can be disposed in the same layer as the first source-drain electrode layer 26, thereby reducing the provision of a metal layer, thereby achieving the purpose of reducing production costs and reducing the thickness of the display panel. In addition, the second reference voltage signal line 322 can be made of the same material as the first source-drain electrode layer 26, so that the second reference voltage signal line 322 and the first source-drain electrode layer 26 can be prepared in the same process, thereby shortening the process time.

[0160] Furthermore, when the first connection line 31 and the first reference voltage signal line 321 are arranged in different layers, and the first connection line 31 and the first reference voltage signal line 321 at least partially overlap along the thickness direction of the display panel, the first connection line 31 and the second reference voltage signal line 322 can be arranged in the same layer, thereby reducing the arrangement of one metal layer, achieving the purpose of reducing production costs and reducing the thickness of the display panel. In addition, the first connection line 31 can be made of the same material as the second reference voltage signal line 322, so that the first connection line 31 and the second reference voltage signal line 322 can be prepared in the same process, thereby shortening the process time.

[0161] Furthermore, when the first connection line 31 and the second reference voltage signal line 322 are arranged in different layers, and the first connection line 31 and the second reference voltage signal line 322 at least partially overlap along the thickness direction of the display panel, the first connection line 31 and the first reference voltage signal line 321 can be arranged in the same layer, thereby reducing the arrangement of one metal layer, achieving the purpose of reducing production costs and reducing the thickness of the display panel. In addition, the first connection line 31 can be made of the same material as the first reference voltage signal line 321, so that the first connection line 31 and the first reference voltage signal line 321 can be prepared in the same process, thereby shortening the process time.

[0162] It should be noted that the specific film layer positions of the first reference voltage signal line 321 and the second reference voltage signal line 322 are not limited to the above-mentioned embodiments. In other embodiments, the first reference voltage signal line 321 and the second reference voltage signal line 322 may also be arranged in the same layer as any metal film layer such as the first gate layer 25, the first source-drain electrode layer 26, the first electrode 401, the second electrode 402 or the shading metal layer 41, and the embodiments of the present invention are not limited to this.

[0163] Continue to refer Fig. 9 Optionally, the display panel further includes a first power signal line 18, and the first power signal line 18 is used to transmit a first power signal. The pixel circuit 14 includes a data signal writing transistor 27, a driving transistor 28 and a compensation transistor 29, the driving transistor 28 is connected in series between the first power signal line 18 and the light emitting element 30, the first electrode D3 of the driving transistor 28 is electrically connected to the first electrode S2 of the data signal writing transistor 27, the second electrode S3 of the driving transistor 28 is electrically connected to the first electrode D4 of the compensation transistor 29, and the second electrode S4 of the compensation transistor 29 is electrically connected to the gate G3 of the driving transistor 28. In the pixel circuit 14 of the first sub-display area 101, the second electrode D2 of the data signal writing transistor 27 is electrically connected to the second signal line 15 through the first via hole 35. Along the second direction Y, the spacing between the first connection line 13 and the first via hole 35 is d2, where d2>0.

[0164] The light emitting element 30 is used to emit light in the light emitting stage to realize the light emitting or display function of the display panel.

[0165] The driving transistor 28 can be turned on according to the potential of its gate, and the driving current formed by the turning on of the driving transistor 28 is used to drive the light emitting element 30 to emit light.

[0166] The driving process of the pixel circuit 14 may include:

[0167] In the data signal voltage writing stage, the data writing transistor 27 and the compensation transistor 29 are turned on, and the driving transistor 28 is also turned on. In the pixel circuit 14 of the first sub-display area 101, the data signal voltage on the second signal line 15 is applied to the first node N1 (i.e., the gate G3 of the driving transistor 28) through the data signal writing transistor 27, the driving transistor 28 and the compensation transistor 29; in the pixel circuit 14 of the second display area 11, the data signal voltage on the first signal line 13 is applied to the first node N1 (i.e., the gate G3 of the driving transistor 28) through the data signal writing transistor 27, the driving transistor 28 and the compensation transistor 29.

[0168] In the light emitting stage, the first power signal on the first power signal line 18 is transmitted to the light emitting element 30 through the driving transistor 28 , so that the driving current generated by the driving transistor 28 is provided to the light emitting element 30 , driving the light emitting element 30 to emit light.

[0169] Exemplarily, the second electrode D2 of the data signal write transistor 27 is located at the first source-drain electrode layer 26, and the second signal line 15 can be arranged on the side of the first source-drain electrode layer 26 away from the substrate 23. The data signal write transistor 27 and the second signal line 15 are electrically connected through the first via 35, so that the first type of signal on the second signal line 15 is transmitted to the data signal write transistor 27 through the first via 35.

[0170] like Fig. 9 As shown, along the second direction Y, the spacing d2 between the first connecting line 13 and the first via hole 35 is set to be greater than 0, that is, there is a gap between the first connecting line 13 and the first via hole 35 to avoid a short circuit between the first connecting line 13 and the second signal line 15, thereby ensuring the reliability of the pixel circuit 14.

[0171] It should be noted that the specific value of the spacing d2 between the first connecting line 13 and the first via 35 can be set according to actual needs, and the embodiment of the present invention is not limited to this. It can be understood that the larger the spacing d2 between the first connecting line 13 and the first via 35, the smaller the mutual interference between the first connecting line 13 and the first via 35; but the smaller the spacing d2 between the first connecting line 13 and the first via 35, the more conducive it is to compress the size of the pixel circuit 14, thereby helping to improve the pixel density of the display panel.

[0172] It should be noted that if Fig. 9As shown, due to the limitation of the manufacturing process, the size of the first via hole 35 is usually large to ensure the reliability of the connection between the data signal writing transistor 27 and the second signal line 15. In order to ensure that the spacing d2 between the first connecting line 13 and the first via hole 35 is greater than 0, the first connecting line 13 can be set as a broken line to avoid the first via hole 35. Those skilled in the art can make settings according to actual needs, and the embodiment of the present invention is not limited to this.

[0173] like Figure 1-Figure 10 As shown, optionally, the first display area 10 further includes a second sub-display area 102 , and the second sub-display area 102 includes a fifth signal line 36 extending along the second direction Y, and the fifth signal line 36 is used to provide the first type of signal to the pixel circuit 14 of the second sub-display area 102 .

[0174] Fig.18 A partial structural diagram of another display panel provided by an embodiment of the present invention is shown. Fig.19 A partial structural diagram of another display panel provided by an embodiment of the present invention is shown. Fig. 20 A partial structural diagram of another display panel provided by an embodiment of the present invention is shown. Fig.21 A partial structural diagram of another display panel provided by an embodiment of the present invention is shown in FIG. Figure 18-Figure 21 As shown, the display panel provided by the embodiment of the present invention further includes a virtual signal line 37 extending along the second direction Y, the virtual signal line 37 includes a first virtual signal line 371 located in the second sub-display area 102, and in the same pixel circuit 14 of the second sub-display area 102, the fifth signal line 36 and the first virtual signal line 371 are located on the same side of the fourth signal line 17. The virtual signal line 37 further includes a second virtual signal line 372 located in the first sub-display area 101, the second virtual signal line 372 and the third signal line 16 are arranged along the second direction Y, and the second virtual signal line 372 and the third signal line 16 are insulated. The virtual signal line further includes a third virtual signal line 373 located in the second display area 11, and in the same pixel circuit 14 of the second display area 11, the first signal line 13 and the third virtual signal line 373 are located on the same side of the fourth signal line 17.

[0175] Specifically, Figure 1-8 As shown, since the third signal line 16 extending along the second direction Y is added to the first sub-display area 101, the density of the wiring along the second direction Y in the first sub-display area 101 is greater than the density of the wiring along the second direction Y in other display areas. Since the wiring density along the second direction Y in different areas of the display area is different, the reflected light is different, which affects the overall visual effect of the display panel.

[0176] Continue to refer Figure 18-Figure 21In this embodiment, a first virtual signal line 371 extending along the second direction Y is set in the second sub-display area 102, and in the same pixel circuit 14 of the second sub-display area 102, the fifth signal line 36 and the first virtual signal line 371 are located on the same side of the fourth signal line 17, wherein the first virtual signal line 371 is used to compensate for the wiring density of the second sub-display area 102 in the second direction Y, so that the wiring density of the second sub-display area 102 and the first sub-display area 101 in the second direction Y tends to be consistent, thereby improving the problem of different reflections and ensuring the overall visual effect of the display panel.

[0177] Among them, the positional relationship between the first virtual signal line 371 and the corresponding pixel circuit 14 can be set with reference to the positional relationship between the third signal line 16 and the corresponding pixel circuit 14, so that the routing of the second sub-display area 102 and the first sub-display area 101 in the second direction Y is evenly distributed, thereby further improving the problem of different reflections between the second sub-display area 102 and the first sub-display area 101.

[0178] Further, continue to refer to Figure 18-Figure 21 , a second virtual signal line 372 extending along the second direction Y is arranged in the first sub-display area 101, the second virtual signal line 372 and the third signal line 16 are arranged along the second direction Y, and the second virtual signal line 372 and the third signal line 16 are insulated to prevent the second virtual signal line 372 from affecting the signal transmission of the third signal line 16. The second virtual signal line 372 is used to compensate for the wiring density of the area in the first sub-display area 101 where the third signal line 16 is not arranged, so that the wiring density of the area in the first sub-display area 101 where the third signal line 16 is not arranged and the area in the first sub-display area 101 where the third signal line 16 is arranged tend to be consistent in the second direction Y, thereby improving the problem of different reflections.

[0179] Among them, the positional relationship between the second virtual signal line 372 and the pixel circuit 14 corresponding thereto can be set with reference to the positional relationship between the third signal line 16 and the pixel circuit 14 corresponding thereto. For example, the second virtual signal line 372 and the third signal line 16 are located on the same straight line, so that the area in the first sub-display area 101 where the third signal line 16 is not set and the area in the first sub-display area 101 where the third signal line 16 is set are evenly distributed in the second direction Y, thereby further improving the problem of different reflections in the first sub-display area 101. At the same time, the second virtual signal line 372 and the third signal line 16 are disconnected from each other to ensure insulation between the second virtual signal line 372 and the third signal line 16.

[0180] Further, continue to refer to Figure 18-Figure 21A third virtual signal line 373 extending along the second direction Y is set in the second display area 11, and in the same pixel circuit 14 of the second display area 11, the first signal line 13 and the third virtual signal line 373 are located on the same side of the fourth signal line 17, wherein the third virtual signal line 373 is used to compensate for the wiring density of the second display area 11 in the second direction Y, so that the wiring density of the second display area 11 and the first sub-display area 101 in the second direction Y tends to be consistent, thereby improving the problem of different reflections.

[0181] Among them, the positional relationship between the third virtual signal line 373 and the corresponding pixel circuit 14 can be set with reference to the positional relationship between the third signal line 16 and the corresponding pixel circuit 14, so that the routing of the second display area 11 and the first sub-display area 101 in the second direction Y is evenly distributed, thereby further improving the problem of different reflections between the second display area 11 and the first sub-display area 101.

[0182] It should be noted that the positional relationship between the virtual signal line 37 and the corresponding pixel circuit 14 can be set with reference to the positional relationship between the third signal line 16 and the corresponding pixel circuit 14. For example, Fig.18 and Fig.19 As shown in FIG. 1 , when the third signal line 16 overlaps with the pixel circuit 14, the virtual signal line 37 also overlaps with the pixel circuit 14. For another example, Fig. 20 and Fig.21 As shown, when the third signal line 16 is located between two adjacent pixel circuits 14, the virtual signal line 37 is also located between two adjacent pixel circuits 14, so that the wiring density of the entire display area in the second direction Y can be made consistent, thereby improving the problem of different reflections.

[0183] Optionally, a third type of signal is applied to the virtual signal line 37, and the third type of signal is a fixed voltage signal.

[0184] Among them, a fixed voltage signal is applied to the virtual signal line 37 so that the voltage on the virtual signal line 37 is a constant voltage. Such a setting can reduce the influence of the virtual signal line 37 on the pixel circuit 14.

[0185] At the same time, since the voltage on the virtual signal line 37 is a constant voltage, the virtual signal line 37 can shield the signal lines and signal nodes that have overlapping areas with it, thereby helping to reduce mutual interference between the signal lines and signal nodes in the pixel circuit 14 and improve the driving performance of the pixel circuit 14.

[0186] Continue to refer Figure 18-Figure 21Optionally, the display panel provided in the embodiment of the present invention further includes a first power signal line 18, and the first power signal line 18 is used to transmit a first power signal, and the fixed voltage signal and the first power signal are the same signal.

[0187] Specifically, Figure 18-Figure 21 As shown, the virtual signal line 37 can be electrically connected to the first power signal line 18. Since the first power signal is a DC signal rather than an AC signal, the first power signal line 18 can provide a constant fixed voltage for the virtual signal line 37. On the one hand, the impact of the virtual signal line 37 on the pixel circuit 14 can be reduced. On the other hand, the voltage on the virtual signal line 37 is a constant voltage. The virtual signal line 37 can shield the signal lines and signal nodes that have overlapping areas with it, thereby helping to reduce mutual interference between the signal lines and signal nodes in the pixel circuit 14 and improve the driving performance of the pixel circuit 14.

[0188] In addition, after the first power signal line 18 is electrically connected to the virtual signal line 37, the routing area of ​​the first power signal line 18 is increased, thereby reducing the resistance of the first power signal line 18, and further reducing the voltage drop (IR drop) of the first power signal on the first power signal line 18, which helps to improve display uniformity.

[0189] like Fig.13 As shown, optionally, the display panel provided by the embodiment of the present invention also includes a first power signal line 18 and a second power signal line 38, the first power signal line 18 is used to transmit a first power signal, the second power signal line 38 is used to transmit a second power signal, and the voltage of the second power signal is less than the voltage of the first power signal, and the fixed voltage signal and the second power signal are the same signal.

[0190] Specifically, Fig.13 As shown, the driving transistor 28 and the light emitting element 30 are connected in series between the first power signal line 18 and the second power signal line 38. In the light emitting stage, a current path is formed from the first power signal line 18, the driving transistor 28, the light emitting element 30 to the second power signal line 38, so that the driving current generated by the driving transistor 28 can be transmitted to the light emitting element 30, thereby driving the light emitting element 30 to emit light.

[0191] The first power signal line 18 is used to provide a first power signal for the pixel circuit 14, and the second power signal line 38 is used to provide a second power signal for the pixel circuit 14. Both the first power signal and the second power signal are DC signals, not AC signals. Therefore, both the first power signal line 18 and the second power signal line 38 can provide a constant voltage for the pixel circuit 14. The voltage of the second power signal is lower than the voltage of the first power signal. The first power signal line 18 can be, for example, a PVDD signal line, and the second power signal line 38 can be, for example, a PVEE signal line, which is not limited in the embodiment of the present invention.

[0192] Furthermore, the virtual signal line 37 can be electrically connected to the second power signal line 38. Since the second power signal is a DC signal rather than an AC signal, the second power signal line 38 can provide a constant fixed voltage for the virtual signal line 37. On the one hand, the impact of the virtual signal line 37 on the pixel circuit 14 can be reduced. On the other hand, the voltage on the virtual signal line 37 is a constant voltage. The virtual signal line 37 can shield the signal lines and signal nodes that have overlapping areas with it, thereby helping to reduce mutual interference between the signal lines and signal nodes in the pixel circuit 14 and improve the driving performance of the pixel circuit 14.

[0193] In addition, after the second power signal line 38 is electrically connected to the virtual signal line 37, the routing area of ​​the second power signal line 38 is increased, thereby reducing the resistance of the second power signal line 38, and further reducing the voltage drop (IR drop) of the first power signal on the second power signal line 38, which helps to improve display uniformity.

[0194] It should be noted that the second power signal line 38 can be arranged in the non-display area surrounding the display area, and the virtual signal line 37 can extend into the non-display area and connect with the second power signal line 38, but it is not limited to this. In other embodiments, the second power signal line 38 can also be located in the display area, and its specific setting method can be set according to actual needs, and the embodiment of the present invention is not limited to this.

[0195] Continue to refer Figure 18-Figure 21 Optionally, in the same pixel circuit 14 of the first sub-display area 101, along the first direction X, the spacing between the second signal line 15 and the third signal line 16 is d1, and in the same pixel circuit 14 of the second sub-display area 102, the spacing between the fifth signal line 36 and the first virtual signal line 37 is d3, wherein d1≥d3.

[0196] Specifically, Figure 18-Figure 21As shown, the spacing d1 between the second signal line 15 and the third signal line 16 can be equal to the spacing d3 between the fifth signal line 36 and the first virtual signal line 37, so that the routing of the first sub-display area 101 and the second sub-display area 102 in the second direction Y is evenly distributed, thereby improving the problem of different reflections between the first sub-display area 101 and the second sub-display area 102.

[0197] In addition, since the third signal line 16 is used to transmit the first type of signal, and the first virtual signal line 37 does not need to transmit a signal with a changing voltage, in another embodiment, the spacing d1 between the second signal line 15 and the third signal line 16 can be set to be greater than the spacing d3 between the fifth signal line 36 and the first virtual signal line 37, so that the distance between the second signal line 15 and the third signal line 16 is farther, reducing the signal interference between the second signal line 15 and the third signal line 16, so that the first type of signal transmitted on the second signal line 15 and the third signal line 16 is more accurate and stable, thereby helping to improve the driving performance of the pixel circuit 14.

[0198] Optionally, the line width of the third signal line is W1, and the line width of the virtual signal line is W2, wherein W1≤W2.

[0199] Specifically, the line width W1 of the third signal line can be equal to the line width W2 of the virtual signal line, so that the routing of the first sub-display area 101 and the second sub-display area 102 in the second direction Y is evenly distributed, thereby improving the problem of different reflections between the first sub-display area 101 and the second sub-display area 102.

[0200] In addition, since the third signal line 16 is used to transmit the first type of signal, and the first virtual signal line 37 does not need to transmit a signal with a voltage change, in another embodiment, the line width W1 of the third signal line can be set to be smaller than the line width W2 of the virtual signal line, so that the third signal line 16 is thinner and its projection area on the plane where the display panel is located is smaller, which helps to reduce the overlapping area between the third signal line 16 and other signal lines in the pixel circuit 14, thereby reducing the parasitic capacitance between the third signal line 16 and other signal lines in the pixel circuit 14, reducing the signal interference between the third signal line 16 and other signal lines in the pixel circuit 14, making the first type of signal transmitted on the third signal line 16 more accurate and stable, thereby helping to improve the driving performance of the pixel circuit 14. At the same time, reducing the parasitic capacitance between the third signal line 16 and other signal lines in the pixel circuit 14 also helps to reduce the loss of the first type of signal on the third signal line 16, thereby helping to reduce the power consumption of the display panel.

[0201] Fig. 22 A partial structural diagram of another display panel provided by an embodiment of the present invention is shown. Fig.23 A partial structural diagram of another display panel provided by an embodiment of the present invention is shown in FIG. Fig. 22 and Fig.23 For example, optionally, the display panel provided by an embodiment of the present invention also includes a second connecting line 39 extending along the first direction X, and the second connecting line 39 is used to connect the first virtual signal line 371 with the second virtual signal line 372, and / or, the second connecting line 39 is used to connect the second virtual signal line 372 with the third virtual signal line 373.

[0202] Specifically, Fig. 22 and Fig.23 As shown, by setting a second connecting line 39 extending along the first direction X, the first virtual signal line 371 of the second sub-display area 102 and the second virtual signal line 372 of the first sub-display area 101 are electrically connected through the second connecting line 39, so that the fixed voltages on the first virtual signal line 371 of the second sub-display area 102 and the second virtual signal line 372 of the first sub-display area 101 are consistent, and then the effects of the first virtual signal line 371 and the second virtual signal line 372 on the corresponding pixel circuits 14 tend to be consistent, thereby helping to improve the display uniformity of the first sub-display area 101 and the second sub-display area 102.

[0203] In addition, when a power signal (such as a first power signal or a second power signal) is applied to the first virtual signal line 371 and the second virtual signal line 372, the first virtual signal line 371 and the second virtual signal line 372 are connected by a second connecting line 39, which can further increase the routing area for transmitting the power signal, thereby reducing the transmission loss of the power signal and helping to improve display uniformity.

[0204] Furthermore, if Fig. 22 and Fig.23 As shown, by setting a second connecting line 39 extending along the first direction X, the second virtual signal line 372 of the first sub-display area 101 and the third virtual signal line 373 of the second display area 11 are electrically connected through the second connecting line 39, so that the fixed voltages on the second virtual signal line 372 of the first sub-display area 101 and the third virtual signal line 373 of the second display area 11 are consistent, and then the effects of the second virtual signal line 372 and the third virtual signal line 373 on the corresponding pixel circuits 14 tend to be consistent, thereby helping to improve the display uniformity of the first sub-display area 101 and the second display area 11.

[0205] In addition, when a power signal (such as a first power signal or a second power signal) is applied to the second virtual signal line 372 and the third virtual signal line 373, the second virtual signal line 372 and the third virtual signal line 373 are connected by a second connecting line 39, which can further increase the routing area for transmitting the power signal, thereby reducing the transmission loss of the power signal and helping to improve display uniformity.

[0206] Fig.24 A partial cross-sectional structural diagram of another display panel provided by an embodiment of the present invention is shown in FIG. Fig.24 As shown, optionally, the first virtual signal line 371 , the second virtual signal line 372 and the third virtual signal line 373 are located in the same film layer, and the second connecting line 39 and the virtual signal line 37 are located in different film layers.

[0207] Specifically, Fig.24 As shown, the first virtual signal line 371 of the second sub-display area 102, the second virtual signal line 372 of the first sub-display area 101 and the third virtual signal line 373 of the second display area 11 are arranged in the same layer, and along the thickness direction of the display panel, the vertical distances between the first virtual signal line 371, the second virtual signal line 372 and the third virtual signal line 373 and other metal film layers in the pixel circuit 14 are basically consistent, so that the parasitic capacitance between the first virtual signal line 371, the second virtual signal line 372 and the third virtual signal line 373 and other metal film layers in the pixel circuit 14 can be at a similar level, thereby making the effects of the first virtual signal line 371, the second virtual signal line 372 and the third virtual signal line 373 on the corresponding pixel circuits 14 tend to be consistent, thereby helping to improve the display uniformity of the display panel.

[0208] At the same time, by setting the first virtual signal line 371, the second virtual signal line 372 and the third virtual signal line 373 in the same film layer, there is no need to set a separate metal layer for each virtual signal line, and the setting of the metal layer can be reduced, thereby achieving the purpose of reducing production costs and reducing the thickness of the display panel. In addition, the first virtual signal line 371, the second virtual signal line 372 and the third virtual signal line 373 can be made of the same material, so that the first virtual signal line 371, the second virtual signal line 372 and the third virtual signal line 373 can be prepared in the same process, thereby shortening the process time.

[0209] Furthermore, if Fig.24 As shown, the second connection line 39 and the virtual signal line 37 are located in different film layers.

[0210] Specifically, Fig.24 As shown, the second connection line 39 and the virtual signal line 37 are located in different film layers, and the second connection line 39 and the virtual signal line 37 to be connected thereto can be connected by punching.

[0211] It can be understood that the second connecting line 39 extends along the first direction X, and the virtual signal lines 37 extend along the second direction Y. Therefore, the second connecting line 39 will overlap with part of the virtual signal line 37. In this embodiment, by arranging the second connecting line 39 and the virtual signal line 37 in different layers, when the second connecting line 39 needs to be connected to the virtual signal line 37, the connection is made by punching; when the second connecting line 39 does not need to be connected to the virtual signal line 37, no punching is required, and the second connecting line 39 does not need to avoid the virtual signal line 37 by crossing the line, so that the structure is simpler and easier to implement.

[0212] For example, Fig.24 As shown, the virtual signal line 37 can be arranged on the side of the first source-drain electrode layer 26 away from the base substrate 23, wherein the virtual signal line 37 can be formed by a Ti / Al / Ti metal stack. Since Al has a smaller resistance, the resistance of the virtual signal line 37 can be reduced, and the line loss of the fixed voltage signal on the virtual signal line 37 can be reduced, thereby reducing the voltage drop of the fixed voltage signal on the virtual signal line 37, which helps to improve display uniformity.

[0213] At the same time, the second connecting line 39 can be set in the same layer as the first source-drain electrode layer 26, wherein the metal film layer where the first source-drain electrode layer 26 is located is usually formed by a Ti / Al / Ti metal stack. Setting the second connecting line 39 in the film layer where the first source-drain electrode layer 26 is located can reduce the line loss of the fixed voltage signal on the second connecting line 39, thereby reducing the voltage drop of the fixed voltage signal on the second connecting line 39, which helps to improve display uniformity.

[0214] Furthermore, if Fig.24 As shown, the second connection line 39 and the dummy signal line 37 are located in adjacent metal film layers. Along the thickness direction of the display panel, the distance between the second connection line 39 and the dummy signal line 37 can be relatively close, thereby facilitating punching connection.

[0215] It should be noted that the specific film layer positions of the second connecting line 39 and the virtual signal line 37 are not limited to the above-mentioned embodiments. In other embodiments, the second connecting line 39 and the virtual signal line 37 may also be arranged in the same layer as any metal film layer such as the first gate layer 25, the first source-drain electrode layer 26, the first electrode 401, the second electrode 402 or the shading metal layer 41, and the embodiments of the present invention are not limited to this.

[0216] It should be noted that in order to reduce the length of the attached drawings, Fig.24 Only the related structures of the first virtual signal line 371, the second virtual signal line 372 and the third virtual signal line 373 are shown, which does not represent the actual structure of the display panel and does not constitute a limitation on the protection scope of the present invention.

[0217] Fig.25 A partial structural diagram of another display panel provided by an embodiment of the present invention is shown. Fig.26 A partial structural diagram of another display panel provided by an embodiment of the present invention is shown. Fig. 27 A partial structural diagram of another display panel provided by an embodiment of the present invention is shown. Fig.28 A partial structural diagram of another display panel provided by an embodiment of the present invention is shown in FIG. Figure 25-28 As shown, optionally, the display panel provided by the embodiment of the present invention also includes a first connecting line 31 extending along the first direction X, and the first connecting line 31 is used to connect the first signal line 13 in the second display area 11 to the third signal line 16 in the first sub-display area 101. The display panel also includes a virtual connecting line 42 extending along the first direction X, and the virtual connecting line 42 and the first connecting line 31 are arranged along the first direction X, and the virtual connecting line 42 and the first connecting line 31 are insulated.

[0218] Specifically, Figure 25-28 As shown, by setting a first connecting line 31 extending along the first direction X, the first sub-portion 131 and the second sub-portion 132 of the third signal line 16 are led out to the first sub-display area 101 to achieve connection between the first sub-portion 131 and the second sub-portion 132 and the third signal line 16.

[0219] like Fig.25 and Fig.26 As shown, optionally, along the thickness direction of the display panel, the first connecting line 31 overlaps with the pixel circuit 14, that is, the vertical projection of the first connecting line 31 on the plane where the display panel is located overlaps with the vertical projection of the pixel circuit 14 on the plane where the display panel is located, so that the first connecting line 31 does not need to occupy additional space, which is beneficial to improve the pixel density of the display panel.

[0220] like Fig. 27 and Fig.28 As shown, optionally, the first connection line 31 may also be located between two adjacent pixel circuits 14 , thereby avoiding the formation of parasitic capacitance between the first connection line 31 and each metal film layer in the pixel circuit 14 , thereby reducing the impact of the first connection line 31 on the performance of the pixel circuit 14 .

[0221] It should be noted that the first connecting line 31 is located in the display area (specifically in the first sub-display area 101 and the second display area 11), which can reduce the number of connecting lines set in the border of the light-transmitting area, or even eliminate the need to set connecting lines in the border of the light-transmitting area. Therefore, the border area of ​​the light-transmitting area can be reduced, thereby increasing the screen-to-body ratio of the array substrate.

[0222] Among them, Figure 1-8As shown, since a first connecting line 31 extending along the first direction X is added in the display area, the density of the lines along the first direction X in the area where the first connecting line 31 is located is greater than the density of the lines along the first direction X in other display areas. Since the density of the lines along the first direction X in different areas of the display area is different, problems such as different reflections may occur.

[0223] Continue to refer Figure 25-28 In this embodiment, the display panel is provided with a virtual connection line 42 extending along the first direction X, the virtual connection line 42 and the first connection line 31 are arranged along the first direction X, and the virtual connection line 42 and the first connection line 31 are insulated to prevent the virtual connection line 42 from affecting the signal transmission of the first connection line 31. The virtual connection line 42 is used to compensate for the wiring density of the area where the first connection line 31 is not provided in the first direction X, so that the wiring density of the area where the first connection line 31 is not provided and the area where the first connection line 31 is located in the first direction X tends to be consistent, thereby improving the problem of different reflections.

[0224] Among them, the positional relationship between the virtual connection line 42 and the corresponding pixel circuit 14 can be set with reference to the positional relationship between the first connection line 31 and the corresponding pixel circuit 14. For example, the virtual connection line 42 and the first connection line 31 are located on the same straight line, and the virtual connection line 42 and the first connection line 31 are disconnected from each other to ensure insulation between the virtual connection line 42 and the first connection line 31, so that the area where the first connection line 31 is not set and the area where the first connection line 31 is located are evenly distributed in the first direction X, thereby further improving the problem of different reflections.

[0225] In other embodiments, for example, Fig.25 and Fig.26 As shown in FIG. 1 , when the first connection line 31 overlaps with the pixel circuit 14, the virtual connection line 42 also overlaps with the pixel circuit 14. Fig. 27 and Fig.28 As shown, when the first connection line 31 is located between two adjacent pixel circuits 14, the virtual connection line 42 is also located between two adjacent pixel circuits 14, so that the wiring density of the entire display area in the first direction X can be made consistent, thereby improving the problem of different reflections.

[0226] Continue to refer Fig. 9 and Fig.13Optionally, the display panel provided in the embodiment of the present invention further includes a first scan line 43, a second scan line 44, a third scan line 45, a light-emitting control signal line 46, a first power signal line 18, a second power signal line 38, a first reference voltage signal line 321, and a second reference voltage signal line 322, wherein the first power signal line 18 is used to transmit a first power signal, and the second power signal line 38 is used to transmit a second power signal, and the voltage of the second power signal is less than the voltage of the first power signal. The pixel circuit 14 includes a first light-emitting control transistor 47, a data signal writing transistor 27, a driving transistor 28, a compensation transistor 29, a first reset transistor 33, a second light-emitting control transistor 48, a light-emitting reset transistor 34, a storage capacitor 40, and a light-emitting element 30. The gate G5 of the first reset transistor 33 is electrically connected to the first scan line 43, the first electrode S5 of the first reset transistor 33 is electrically connected to the second electrode S4 of the compensation transistor 29, the gate G3 of the driving transistor 28 and the second electrode plate 402 of the storage capacitor 40 at the first node N1 respectively; the second electrode D5 of the first reset transistor 33 is electrically connected to the first reference voltage signal line 321. The first electrode D4 of the compensation transistor 29 is electrically connected to the second electrode S3 of the driving transistor 28 and the first electrode D6 of the second light-emitting control transistor 48 respectively, and the gate G4 of the compensation transistor 29 is electrically connected to the second scan line 44. The gate G1 of the first light-emitting control transistor 47 and the gate G6 of the second light-emitting control transistor 48 are both electrically connected to the light-emitting control signal line 46, the first electrode D1 of the first light-emitting control transistor 47 is electrically connected to the first power supply signal line 18, and the second electrode S1 of the first light-emitting control transistor 47 is electrically connected to the first electrode D3 of the driving transistor 28 and the first electrode S2 of the data signal writing transistor 27 respectively. The second electrode S6 of the second light emitting control transistor 48 is electrically connected to the anode of the light emitting element 30 and the first electrode S7 of the light emitting reset transistor 34, respectively. The second electrode D7 of the light emitting reset transistor 34 is electrically connected to the second reference voltage signal line 322, and the gate G7 of the light emitting reset transistor 34 is electrically connected to the third scan line 45. The gate G2 of the data signal writing transistor 27 is electrically connected to the third scan line 45. The first electrode plate 401 of the storage capacitor 40 is electrically connected to the first power signal line 18. The cathode of the light emitting element 30 is electrically connected to the second power signal line 38. In the pixel circuit 14 of the first sub-display area 101, the second electrode D2 of the data signal writing transistor 27 is electrically connected to the second signal line 15. In the pixel circuit of the second display area 11, the second electrode D2 of the data signal writing transistor 27 is electrically connected to the first signal line 13.

[0227] Specifically, Fig. 9 and Fig.13 The driving process of the pixel circuit 14 shown in FIG. 1 is, for example:

[0228] In the initialization stage, the first scanning signal on the first scanning line 43 turns on the first reset transistor 33, and the first reference voltage on the first reference voltage signal line 321 is applied to one end of the storage capacitor 40 through the first reset transistor 33, that is, the potential of the first node N1 is the first reference voltage, so as to reset the first node N1. At this time, the potential of the gate G3 of the driving transistor 28 is also the first reference voltage.

[0229] In the data signal voltage writing stage, the third scanning signal on the third scanning line 45 causes the data writing transistor 27 and the compensation transistor 29 to be turned on. At this time, the potential of the gate G3 of the driving transistor 28 is the first reference voltage, and the driving transistor 28 is also turned on. The data signal voltage on the data signal line is applied to the first node N1 through the data writing transistor 27, the driving transistor 28 and the compensation transistor 29, thereby writing the data signal voltage into the storage capacitor 40.

[0230] At the same time, in the data signal voltage writing stage, the second scanning signal on the third scanning line 45 causes the light-emitting reset transistor 34 to also be turned on. The light-emitting reset transistor 34 writes the second reference voltage on the second reference voltage signal line 322 into the anode of the light-emitting element 30, and resets the anode potential of the light-emitting element 30. This can reduce the influence of the anode voltage of the light-emitting element 30 in the previous frame on the anode voltage of the light-emitting element 30 in the next frame, thereby improving display uniformity.

[0231] In the light-emitting stage, the light-emitting control signal on the light-emitting control signal line 46 turns on the first light-emitting control transistor 47 and the second light-emitting control transistor 48, thereby driving the light-emitting element 30 to emit light through the driving transistor 28, thereby realizing the light-emitting and display functions of the display panel.

[0232] Fig.29 A partial cross-sectional structural diagram of another display panel provided by an embodiment of the present invention is shown in FIG. Fig. 9 , Fig.13 and Fig.29 As shown, optionally, the compensation transistor 29 and the first reset transistor 33 are oxide semiconductor transistors 49 .

[0233] The driving transistor 28 controls the magnitude of the driving current according to its gate voltage, and the magnitude of the driving current is used to adjust the luminance of the light-emitting element 30, thereby controlling the grayscale. The compensation transistor 29 and the first reset transistor 33 are both electrically connected to the gate of the driving transistor 28, and the performance of the compensation transistor 29 and the first reset transistor 33 directly affects the potential of the gate of the driving transistor 28, thereby affecting the luminance of the light-emitting element 30.

[0234] In this embodiment, the first reset transistor 33 can be set as an oxide semiconductor transistor 49, such as an N-type indium gallium zinc oxide (IGZO) transistor. When the first scan signal on the first scan line 43 is a high-level signal, the source and drain of the N-type oxide semiconductor transistor 49 are turned on to realize the conduction of the first reset transistor 33. Since the mobility of the IGZO transistor is low and the leakage current is small, the first reset transistor 33 uses an oxide semiconductor transistor 49, which can prevent the charge of the gate of the driving transistor 28 from leaking through the first reset transistor 33 during low-frequency driving, and can effectively solve the leakage current problem during low-frequency driving, so that the pixel circuit 14 is suitable for realizing low-frequency driving, which is conducive to reducing the power consumption of the display panel.

[0235] Furthermore, the compensation transistor 29 may also be an oxide semiconductor transistor 49, such as an N-type indium gallium zinc oxide (IGZO) transistor. When the second scan signal on the second scan line 44 is a high-level signal, the source and drain of the N-type oxide semiconductor transistor 49 are turned on to realize the conduction of the compensation transistor 29. Since the IGZO transistor has a low mobility and a small leakage current, the compensation transistor 29 is an oxide semiconductor transistor 49, which can prevent the charge of the gate of the driving transistor 28 from leaking through the compensation transistor 29 during low-frequency driving, effectively reduce the influence of the leakage current on the stability of the gate potential of the driving transistor 28, and is conducive to improving the stability of the low-frequency driving of the pixel circuit 14.

[0236] Optionally, the first light emission control transistor 47, the data signal writing transistor 27, the driving transistor 28, the second light emission control transistor 48 and the light emission reset transistor 34 can be P-type low temperature polysilicon (LTPS) thin film transistors (P-type transistors). LTPS transistors have the advantages of small size and good stability.

[0237] Continue to refer Fig. 9 , Fig.13 and Fig.29 Optionally, the compensation transistor 29 and the first reset transistor 33 are dual-gate transistors.

[0238] Among them, the leakage current of the dual-gate transistor is small, and the compensation transistor 29 and the first reset transistor 33 use dual-gate transistors, which can prevent the charge of the gate of the driving transistor 28 from leaking through the compensation transistor 29 and the first reset transistor 33 during low-frequency driving, and can effectively solve the leakage current problem during low-frequency driving, so that the pixel circuit 14 is suitable for low-frequency driving, which is beneficial to reducing the power consumption of the display panel.

[0239] Meanwhile, when the compensation transistor 29 and the first reset transistor 33 are oxide semiconductor transistors 49 , since the size of the oxide semiconductor transistor 49 is generally large, setting it as a dual-gate transistor helps reduce the size of the compensation transistor 29 and the first reset transistor 33 .

[0240] Continue to refer Fig.29 , exemplarily, the pixel circuit 14 may include a first thin film transistor 22 and an oxide semiconductor transistor 49 at the same time. Among them, the first thin film transistor 22 is an LTPS transistor, and the first thin film transistor 22 includes a first active layer 24, a first gate layer 25 and a first source-drain electrode layer 26 stacked on one side of the substrate 23, and the first gate layer 25 may be located above the first active layer 24. That is, the LTPS transistor is usually a top-gate structure. The oxide semiconductor transistor 49 includes a second gate layer 50, a second active layer 51, a third gate layer 52 and a second source-drain electrode layer 53 stacked on one side of the substrate 23, the third gate layer 52 is located above the second active layer 51, and the second gate layer 50 is located below the second active layer 51. That is, the oxide semiconductor transistor 49 is usually a top-bottom double-gate structure, in which the third gate layer 52 is a top gate and the second gate layer 50 is a bottom gate.

[0241] Among them, the second gate layer 50 can be located in the same film layer as the first electrode 401, and the second source-drain electrode layer 53 can be located in the same film layer as the first source-drain electrode layer 26, which can reduce the setting of the metal layer and achieve the purpose of reducing production costs and reducing the thickness of the display panel, but is not limited to this.

[0242] Continue to refer Fig. 9 Optionally, along the thickness direction of the display panel, the first power signal line 18 covers the compensation transistor 29 and the first reset transistor 33.

[0243] The first power signal line 18 is used to provide a first power signal to the pixel circuit 14. The first power signal is a DC signal, not an AC signal. Therefore, the voltage on the first power signal line 18 is a constant voltage. Fig. 9 As shown, in the present embodiment, the first power signal line 18 covers the compensation transistor 29 and the first reset transistor 33, so that the first power signal line 18 can shield the compensation transistor 29 and the first reset transistor 33, thereby reducing the influence of the signal line in the pixel circuit 14 on the compensation transistor 29 and the first reset transistor 33, thereby stabilizing the gate potential of the driving transistor 28, helping to improve the control accuracy of the pixel circuit 14 on the driving current, and further improving the display effect.

[0244] Continue to refer Fig. 9 and Fig.13Optionally, along the thickness direction of the display panel, the first power signal line 18 covers the first node N1.

[0245] Specifically, Fig.13 As shown, the potential at the first node N1 is the gate potential of the driving transistor 28. Therefore, the first power signal line 18 covers the first node N1, so that the first power signal line 18 can shield the first node N1, reducing the influence of the signal line in the pixel circuit 14 on the potential of the first node N1, thereby stabilizing the gate potential of the driving transistor 28, which helps to improve the control accuracy of the pixel circuit 14 on the driving current, thereby improving the display effect.

[0246] Continue to refer Fig. 9 Optionally, the line width of the first power signal line 18 is greater than the line widths of the second signal line 15 and the third signal line 16. By setting the line widths of the second signal line 15 and the third signal line 16 smaller, so that the second signal line 15 and the third signal line 16 are thinner, the projection area thereof on the plane where the display panel is located is smaller, which helps to reduce the overlapping area between the second signal line 15 and the third signal line 16 and other signal lines in the pixel circuit 14, thereby reducing the parasitic capacitance between the second signal line 15 and the third signal line 16 and other signal lines in the pixel circuit 14, reducing the signal interference between the second signal line 15 and the third signal line 16 and other signal lines in the pixel circuit 14, making the first type of signal transmitted on the second signal line 15 and the third signal line 16 more accurate and stable, thereby helping to improve the driving performance of the pixel circuit 14. At the same time, reducing the parasitic capacitance between the second signal line 15 and the third signal line 16 and other signal lines in the pixel circuit 14 also helps to reduce the loss of the first type of signal on the second signal line 15 and the third signal line 16, thereby helping to reduce the power consumption of the display panel.

[0247] At the same time, the line width of the first power signal line 18 is relatively large, that is, the first power signal line 18 is relatively wide, which can reduce the resistance on the first power signal line 18, thereby reducing the line loss of the first power signal on the first power signal line 18, which helps to improve display uniformity.

[0248] Continue to refer Fig.11 , Fig.12 , Figure 14-17 , Fig.24 and Fig.29 Optionally, the substrate 23 can be set to a three-layer structure, including a first substrate 231, a first inorganic layer 232 and a first substrate 233 arranged in sequence, wherein the first inorganic layer 232 can block moisture and oxygen from entering the pixel circuit 14, thereby ensuring the driving performance of the pixel circuit 14.

[0249] Continue to refer Fig.11 , Fig.12 , Figure 14-17 , Fig.24 and Fig.29 Optionally, a buffer layer 54 is provided between the light-shielding metal layer 41 and the first active layer 24 , and the buffer layer 54 can play the role of shockproof, buffering and isolation.

[0250] Continue to refer Fig.11 , Fig.12 , Figure 14-17 , Fig.24 and Fig.29 Optionally, a gate insulating layer 55, a capacitor insulating layer 56, an interlayer insulating layer 57, a planarizing layer 58 and a passivation layer 59 are sequentially stacked on the side of the buffer layer 54 away from the base substrate 23. The gate insulating layer 55 is located between the first active layer 24 and the first gate layer 25, the capacitor insulating layer 56 is located between the first electrode plate 401 and the second electrode plate 402, the interlayer insulating layer 57 is located between the first electrode plate 401 and the first source-drain electrode layer 26, the planarizing layer 58 is located between the first source-drain electrode layer 26 and the second signal line 15, and the passivation layer 59 is located on the side of the second signal line 15 away from the base substrate 23.

[0251] The gate insulating layer 55 , the capacitor insulating layer 56 and the interlayer insulating layer 57 may be inorganic film layers, and the planarization layer 58 and the passivation layer 59 may be organic film layers.

[0252] Furthermore, the interlayer insulating layer 57 may include a single insulating layer or multiple insulating layers, for example, Fig.29 As shown, the interlayer insulating layer 57 may also include a first interlayer insulating layer 571, a second interlayer insulating layer 572 and a third interlayer insulating layer 573 which are stacked, wherein the first interlayer insulating layer 571 is located between the second gate layer 50 and the second active layer 51, the second interlayer insulating layer 572 is located between the second active layer 51 and the third gate layer 52, and the third interlayer insulating layer 573 is located between the third gate layer 52 and the second source-drain electrode layer 53, but is not limited thereto.

[0253] It should be noted that the specific structure of the pixel circuit 14 is not limited to the above structure, and those skilled in the art can set the specific structure of the pixel circuit 14 according to actual needs.

[0254] Based on the same inventive concept, an embodiment of the present invention further provides a display device, Fig.30 A schematic diagram of a display device according to an embodiment of the present invention is shown in FIG. Fig.30As shown, the display device 70 includes the display panel 71 described in any embodiment of the present invention. Therefore, the display device 70 provided in the embodiment of the present invention has the technical effect of the technical solution in any of the above embodiments, and the structures that are the same or corresponding to the above embodiments and the explanation of terms are no longer repeated here.

[0255] Among them, Fig.30 As shown, the display panel 71 includes a first functional area 12, and the display device 70 includes an optical electronic component (not shown in the figure) arranged in the first functional area 12. The optical electronic component may include one or more of a camera module, a light sensor and an ultrasonic distance sensor, and those skilled in the art may make settings according to actual needs.

[0256] The display device 70 provided in the embodiment of the present invention can be Fig.30 The mobile phone shown can also be any electronic product with a display function, including but not limited to the following categories: televisions, laptops, desktop displays, tablet computers, digital cameras, smart bracelets, smart glasses, car displays, medical equipment, industrial control equipment, touch interactive terminals, etc. The embodiments of the present invention do not specifically limit this.

[0257] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A display panel, characterized in that: include: A first display area, a second display area and a first functional area, wherein in a first direction, the first display area is adjacent to the first functional area, and in a second direction, the second display area is adjacent to the first functional area, and the first direction intersects with the second direction; The second display area includes a first signal line extending along the second direction, the first signal line is used to provide a first type of signal to the pixel circuit of the second display area, and the first signal line includes a first sub-section and a second sub-section separated by the first functional area; The first display area includes a first sub-display area; The first sub-display area includes a second signal line and a third signal line extending along the second direction; the second signal line is used to provide the first type of signal to the pixel circuit of the first sub-display area, and the third signal line is electrically connected to the first sub-section and the second sub-section respectively; The display panel further includes a fourth signal line extending along the second direction, and the fourth signal line is used to transmit a second type of signal; The display panel further includes a first connecting line extending along the first direction, the first connecting line connecting the first signal line and the third signal line; The display panel further includes a first power signal line, wherein the first power signal line is used to transmit a first power signal; The pixel circuit includes a data signal writing transistor and a driving transistor; The driving transistor is connected in series between the first power signal line and the light emitting element; The first electrode of the driving transistor is electrically connected to the first electrode of the data signal writing transistor; In the pixel circuit of the first sub-display area, the second electrode of the data signal writing transistor is electrically connected to the second signal line at least through a first via hole; Along the second direction, the distance between the first connecting line and the first via hole is d2; wherein d2>0.

2. The display panel according to claim 1, characterized in that: The fourth signal line is a first power signal line, and / or the second type of signal is a first power signal line, and / or the first type of signal is a data signal.

3. The display panel according to claim 1, characterized in that: In the same pixel circuit of the first sub-display area, the second signal line and the third signal line are located on the same side of the fourth signal line.

4. The display panel according to claim 1, characterized in that: The display panel includes a pixel circuit group, and the pixel circuit group includes a first pixel circuit and a second pixel circuit that are adjacently arranged along the first direction, and the first pixel circuit and the second pixel circuit are arranged in a mirror image.

5. The display panel according to claim 4, characterized in that: In the same pixel circuit group of the first sub-display area, along the first direction, the second signal line is located between two third signal lines; or, the third signal line is located between two second signal lines.

6. The display panel according to claim 1, characterized in that: The second signal line and the third signal line are located in the same film layer.

7. The display panel according to claim 1, characterized in that: Along the first direction, a distance between the second signal line and the third signal line is d1; wherein d1≥2.5 μm.

8. The display panel according to claim 1, characterized in that: The second signal line and the third signal line are located in different film layers; Along a thickness direction of the display panel, the second signal line and the third signal line at least partially overlap.

9. The display panel according to claim 1, characterized in that: The first connecting line and the third signal line are located in different film layers.

10. The display panel according to claim 1, characterized in that: The first connection line and the reference voltage signal line are located in the same film layer.

11. The display panel according to claim 1, characterized in that: The display panel further comprises a reference voltage signal line extending along the first direction, wherein the reference voltage signal line is used to provide a reference voltage signal for the pixel circuit; The first connection line is insulated from the reference voltage signal line, and along a thickness direction of the display panel, the first connection line at least partially overlaps with the reference voltage signal line.

12. The display panel according to claim 11, characterized in that: The display panel further includes a first power signal line, wherein the first power signal line is used to transmit a first power signal; The reference voltage signal line includes a first reference voltage signal line; The pixel circuit includes a driving transistor and a first reset transistor; The driving transistor is connected in series between the first power signal line and the light emitting element; The gate of the driving transistor is electrically connected to the first electrode of the first reset transistor, and the second electrode of the first reset transistor is electrically connected to the first reference voltage signal line; The first connection line and the first reference voltage signal line are located in different film layers, and along the thickness direction of the display panel, the first connection line and the first reference voltage signal line at least partially overlap.

13. The display panel according to claim 11, characterized in that: The display panel further includes a first power signal line, wherein the first power signal line is used to transmit a first power signal; The reference voltage signal line includes a second reference voltage signal line; The pixel circuit includes a driving transistor and a light emitting reset transistor; The driving transistor is connected in series between the first power signal line and the light emitting element; The anode of the light emitting element is electrically connected to the first electrode of the light emitting reset transistor, and the second electrode of the light emitting reset transistor is electrically connected to the second reference voltage signal line; The first connection line and the second reference voltage signal line are located in different film layers, and along the thickness direction of the display panel, the first connection line and the second reference voltage signal line at least partially overlap.

14. The display panel according to claim 1, characterized in that: The first display area also includes a second sub-display area; The second sub-display area comprises a fifth signal line extending along the second direction, and the fifth signal line is used to provide the first type of signal to the pixel circuit of the second sub-display area; The display panel further includes a virtual signal line extending along the second direction; The virtual signal line includes a first virtual signal line located in the second sub-display area, and in the same pixel circuit in the second sub-display area, the fifth signal line and the first virtual signal line are located on the same side of the fourth signal line; The virtual signal line further includes a second virtual signal line located in the first sub-display area. The second virtual signal line and the third signal line are arranged along the second direction, and the second virtual signal line and the third signal line are insulated from each other.

15. The display panel according to claim 14, characterized in that: The virtual signal lines further include a third virtual signal line located in the second display area. In the same pixel circuit in the second display area, the first signal line and the third virtual signal line are located on the same side of the fourth signal line.

16. The display panel according to claim 14, characterized in that: A third type of signal is applied to the virtual signal line, and the third type of signal is a fixed voltage signal.

17. The display panel according to claim 16, characterized in that: The display panel further includes a first power signal line, wherein the first power signal line is used to transmit a first power signal; The fixed voltage signal and the first power signal are the same signal.

18. The display panel according to claim 16, characterized in that: The display panel further includes a first power signal line and a second power signal line, wherein the first power signal line is used to transmit a first power signal, and the second power signal line is used to transmit a second power signal, and a voltage of the second power signal is lower than a voltage of the first power signal; The fixed voltage signal and the second power signal are the same signal.

19. The display panel according to claim 14, characterized in that: In the same pixel circuit of the first sub-display area, along the first direction, the distance between the second signal line and the third signal line is d1; In the same pixel circuit of the second sub-display area, the distance between the fifth signal line and the first virtual signal line is d3; Among them, d1≥d3.

20. The display panel according to claim 14, characterized in that: The line width of the third signal line is W1, and the line width of the dummy signal line is W2; wherein W1≤W2.

21. The display panel according to claim 14, characterized in that: The display panel further includes a second connection line extending along the first direction, the second connection line connecting the first virtual signal line and the second virtual signal line, and / or the second connection line connecting the second virtual signal line and the third virtual signal line.

22. The display panel according to claim 21, characterized in that: The first virtual signal line, the second virtual signal line and the third virtual signal line are located in the same film layer; The second connecting line and the dummy signal line are located in different film layers.

23. The display panel according to claim 14, characterized in that: The display panel further includes a first connection line extending along the first direction, the first connection line being used to connect the first signal line in the second display area to the third signal line in the first sub-display area; The display panel further includes a virtual connection line extending along the first direction, the virtual connection line and the first connection line are arranged along the first direction, and the virtual connection line and the first connection line are insulated from each other.

24. The display panel according to claim 1, characterized in that: In the same pixel circuit, the third signal line is located on a side of the second signal line close to the fourth signal line, or the third signal line is located on a side of the second signal line far from the fourth signal line.

25. A display device, characterized in that: A display panel comprising any one of claims 1-24.

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